Semiconductor device

Abstract

The objective is to provide a semiconductor device comprising a low-resistance source region and drain electrode without relying on silicon nitride included in a protective insulating layer. The semiconductor device comprises an oxide insulating layer, an oxide semiconductor layer above the oxide insulating layer, a gate insulating layer above the oxide semiconductor layer that contacts the oxide semiconductor layer, and a gate electrode above the gate insulating layer. The oxide semiconductor layer comprises a channel region that overlaps with the gate electrode, and a source region and drain region that do not overlap with the gate electrode. At the interface between the source region and drain region and the gate insulating layer, the concentration of impurities on the surface of the source region and drain region is 1 × 10¹⁹ cm⁻³ or more.

Description

Technology Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel. Background Technology

[0002] In recent years, semiconductor devices using oxide semiconductors as channels have been developed as alternatives to silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon (see, for example, Patent Documents 1 to 6). Semiconductor devices containing such oxide semiconductors have a simple structure and can be formed by a low-temperature process, just like semiconductor devices containing amorphous silicon. Furthermore, it is known that semiconductor devices containing oxide semiconductors have higher field-effect mobility than semiconductor devices containing amorphous silicon. Prior art literature

[0003] Japanese Patent Publication No. 2021-141338 Japanese Patent Publication No. 2014-099601 Japanese Patent Publication No. 2021-153196 Japanese Patent Publication No. 2018-006730 Japanese Patent Publication No. 2016-184771 Japanese Patent Publication No. 2021-108405 The problem to be solved

[0004] In oxide semiconductors, carriers are generated when hydrogen is trapped in oxygen defects. If this mechanism is utilized in a semiconductor device containing an oxide semiconductor layer—that is, by forming oxygen defects in the oxide semiconductor layer and supplying hydrogen to the formed oxygen defects—source and drain regions can be formed in the oxide semiconductor layer with a carrier concentration higher than that of the channel region. Silicon nitride contains a large amount of hydrogen. Therefore, by depositing silicon nitride as a protective insulating layer in the semiconductor device and supplying the hydrogen contained in the silicon nitride to the oxide semiconductor layer, low-resistance source and drain regions can be formed. In other words, a protective insulating layer containing silicon nitride was required to make the source and drain regions low-resistance.

[0005] One embodiment of the present invention has the objective of providing a semiconductor device comprising a low-resistance source region and a drain region, without relying on silicon nitride included in a protective insulating layer. means of solving the problem

[0006] A semiconductor device according to one embodiment of the present invention comprises an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on the oxide semiconductor layer that contacts the oxide semiconductor layer, and a gate electrode on the gate insulating layer, wherein the oxide semiconductor layer comprises a channel region that overlaps with the gate electrode, and a source region and a drain region that do not overlap with the gate electrode, and wherein, at the interface between the source region and the drain region and the gate insulating layer, the concentration of impurities on the surface of the source region and the drain region is 1×10 19 cm -3 That is all. Brief explanation of the drawing

[0007] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a schematic plan view showing the configuration of a semiconductor device according to one embodiment of the present invention. FIG. 3 is a schematic partial enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 5 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 7 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 8 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 11 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 12 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 13 is a graph showing the correlation between the concentration of boron and the sheet resistance on the surface of the source region and the drain region in the example sample and the comparative example sample. FIG. 14 is a schematic cross-sectional view illustrating a hydrogen trap region that traps hydrogen supplied from a protective insulating layer. FIG. 15a is a graph showing the electrical characteristics of Example Sample 1-1. FIG. 15b is a graph showing the electrical characteristics of Example Sample 1-2. FIG. 15c is a graph showing the electrical characteristics of Example Samples 1-3. FIG. 15d is a graph showing the electrical characteristics of Example Samples 1-4. Figure 16a is a graph showing the electrical characteristics of Example Sample 2-1. FIG. 16b is a graph showing the electrical characteristics of Example Sample 2-2. FIG. 16c is a graph showing the electrical characteristics of Example Sample 2-3. FIG. 16d is a graph showing the electrical characteristics of Example Samples 2-4. Specific details for implementing the invention

[0008] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Any configuration that can be easily conceived by a person skilled in the art by appropriately modifying the configuration of the embodiment while maintaining the well-known knowledge of the invention is naturally included within the scope of the present invention. To make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and in each drawing, components identical to those described above in the previously published drawings are given the same reference numerals, and detailed descriptions may be appropriately omitted.

[0009] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward," etc. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward," etc. Thus, for convenience of explanation, the terms "upward" or "downward" are used in the description; however, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a direction different from that illustrated. In the following description, for example, the expression "oxide semiconductor layer above the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be placed between the substrate and the oxide semiconductor layer. "Upward" or "downward" refers to the stacking order in a structure in which multiple layers are stacked; when expressed as "pixel electrode above the semiconductor device," the positional relationship may be such that the semiconductor device and the pixel electrode do not overlap when viewed in a planar view. On the other hand, when expressed as "pixel electrode vertically above the semiconductor device," it refers to a positional relationship in which the semiconductor device and the pixel electrode overlap when viewed in a planar view.

[0010] In this specification, the terms “film” and “layer” may be interchanged depending on the case.

[0011] In this specification, the term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical elements (e.g., polarizing elements, backlights, touch panels, etc.) are mounted on a display cell. Unless there is a technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electroluminescence (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Accordingly, regarding the embodiments described below, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are described as examples of display devices, but the structure in this embodiment may be applied to other display devices including electro-optical layers described above.

[0012] In the present specification, expressions such as “α includes A, B, or C,” “α includes any one of A, B, and C,” and “α includes one selected from the group consisting of A, B, and C” do not exclude cases where α includes multiple combinations of A to C unless specifically stated otherwise. Furthermore, these expressions do not exclude cases where α includes other components.

[0013] With reference to FIGS. 1 to 12, a semiconductor device (10) according to one embodiment of the present invention will be described. The semiconductor device (10) can be used, for example, in an integrated circuit (IC) such as a display device, a microprocessing unit (MPU), or a memory circuit.

[0014] [1. Configuration of the semiconductor device (10)]

[0015] With reference to FIGS. 1 and 2, the configuration of a semiconductor device (10) according to an embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device (10) according to an embodiment of the present invention. FIG. 2 is a schematic plan view showing the configuration of a semiconductor device (10) according to an embodiment of the present invention. Specifically, FIG. 1 is a cross-sectional view cut along the line A-A' of FIG. 2.

[0016] As illustrated in FIG. 1, the semiconductor device (10) comprises a substrate (100), a light-blocking layer (105), a nitride insulating layer (110), a first oxide insulating layer (120), a second oxide insulating layer (130), an oxide semiconductor layer (140), a gate insulating layer (150), a gate electrode (160), a source electrode (201), and a drain electrode (203). The light-blocking layer (105) is provided on the substrate (100). The nitride insulating layer (110) covers the upper surface and cross-section of the light-blocking layer (105) and is provided on the substrate (100). The first oxide insulating layer (120) is provided on the nitride insulating layer (110). The second oxide insulating layer (130) has a predetermined pattern and is provided on the first oxide insulating layer (120). The oxide semiconductor layer (140) has a pattern similar to that of the second oxide insulating layer (130) and is provided on top of the second oxide insulating layer (130). The gate insulating layer (150) covers the upper surface of the oxide semiconductor layer (140) and the respective cross-sections of the second oxide insulating layer (130) and the oxide semiconductor layer (140), and is provided on top of the first oxide insulating layer (120). The gate electrode (160) overlaps with the oxide semiconductor layer (140) and is provided on top of the gate insulating layer (150). The gate insulating layer (150) is provided with openings (171 and 173) through which a portion of the upper surface of the oxide semiconductor layer (140) is exposed. The source electrode (201) is provided on top of the gate insulating layer (150) and inside the openings (171) and is in contact with the oxide semiconductor layer (140). Likewise, the drain electrode (203) is provided above the gate insulating layer (150) and inside the opening (173), and is in contact with the oxide semiconductor layer (140). The source electrode (201) and the drain electrode (203) are in contact with the surface of the gate insulating layer (150) that is in contact with the gate electrode (160). Furthermore, below, if the source electrode (201) and the drain electrode (203) are not specifically distinguished, they may be collectively referred to as the source and drain electrode (200).

[0017] The oxide semiconductor layer (140) is divided into a source region S, a drain region D, and a channel region CH based on the gate electrode (160). That is, the oxide semiconductor layer (140) includes a channel region CH that overlaps with the gate electrode (160), and source region S and drain region D that do not overlap with the gate electrode (160). In the film thickness direction of the oxide semiconductor layer (140), the end of the channel region CH approximately coincides with the end of the gate electrode (160). The channel region CH has semiconductor properties. The source region S and the drain region D each have conductor properties. Therefore, the carrier concentration of the source region S and the drain region D is greater than the carrier concentration of the channel region CH. The source electrode (201) and the drain electrode (203) are each in contact with the source region S and the drain region D, and are electrically connected to the oxide semiconductor layer (140). In addition, the oxide semiconductor layer (140) may be a single layer structure or a stacked structure.

[0018] As illustrated in FIG. 2, each of the light-blocking layer (105) and the gate electrode (160) has a constant width in the D1 direction and extends in the D2 direction, which is orthogonal to the D1 direction. In the D1 direction, the width of the light-blocking layer (105) is greater than the width of the gate electrode (160). The channel region CH completely overlaps with the light-blocking layer (105). In the semiconductor device (10), the D1 direction corresponds to the direction in which current flows from the source electrode (201) to the drain electrode (203) through the oxide semiconductor layer (140). Accordingly, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0019] A substrate (100) can support each layer constituting a semiconductor device (10). As the substrate (100), a rigid substrate having light transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate, may be used. Additionally, as the substrate (100), a rigid substrate not having light transparency, such as a silicon substrate, may be used. Additionally, as the substrate (100), a flexible substrate having light transparency, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluoropolymer substrate, may be used. To improve the heat resistance of the substrate (100), impurities may be introduced into the resin substrate. Furthermore, a substrate having a silicon oxide film or a silicon nitride film formed on the aforementioned rigid substrate or flexible substrate may be used as the substrate (100).

[0020] The light-blocking layer (105) can reflect or absorb external light. As described above, since the light-blocking layer (105) is provided with an area larger than the channel region CH of the oxide semiconductor layer (140), it can block external light incident on the channel region CH. As the light-blocking layer (105), for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys thereof or compounds thereof, etc., may be used. Also, as the light-blocking layer (105), if conductivity is not required, it does not necessarily have to contain metal. For example, as the light-blocking layer (105), a black matrix made of black resin may be used. Also, the light-blocking layer (105) may be a single-layer structure or a stacked structure. For example, the light-blocking layer (105) may be a stacked structure of a red color filter, a green color filter, and a blue color filter.

[0021] The nitride insulating layer (110) can prevent impurities (e.g., sodium, etc.) contained in the substrate (100) or impurities (e.g., water, etc.) entering from the outside from diffusing into the oxide semiconductor layer (140). As the nitride insulating layer (110), a nitride including, for example, silicon or aluminum may be used. Specifically, as the nitride insulating layer (110), silicon nitride (SiN x ), silicon nitride (SiN x O y ), aluminum nitride (AlN x ), or aluminum nitride (AlN x O y ) etc. can be used. The nitride insulating layer (110) may be a single layer structure or a multilayer structure.

[0022] Each of the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150) can suppress the diffusion of hydrogen into the channel region CH. In particular, if a hydrogen trap region described later is formed in at least one of the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150), the effect of suppressing hydrogen diffusion is high. As each of the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150), an oxide containing, for example, silicon or aluminum may be used. Specifically, as each of the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150), silicon oxide (SiO₂) x ), silicon nitride (SiO₂) x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y...etc. can be used. The oxide included in the second oxide insulating layer (130) is different from the oxide included in the first oxide insulating layer (120). Since a predetermined pattern of the second oxide insulating layer (130) is formed by etching, it is preferable that the first oxide insulating layer (120) and the second oxide insulating layer (130) are oxides with different etching rates. It is preferable to use aluminum oxide as the second oxide insulating layer (130). Each of the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150) may have a single-layer structure or a stacked structure.

[0023] In addition, in this embodiment, it is also possible to apply a configuration in which the second oxide insulating layer (130) is not provided.

[0024] Here, silicon nitride (SiO₂) x N y ) and aluminum oxide nitride (AlO x N y ) are oxides containing nitrogen (N) in a proportion (x>y) smaller than that of oxygen (O), respectively. Also, silicon nitride oxide (SiN x O y ) and aluminum nitride (AlN x O y ) is a nitride containing oxygen in a smaller proportion (x>y) than nitrogen.

[0025] The gate electrode (160), source electrode (201), and drain electrode (203) are conductive. As each of the gate electrode (160), source electrode (201), and drain electrode (203), for example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys thereof or compounds thereof may be used. Each of the gate electrode (160), source electrode (201), and drain electrode (203) may have a single-layer structure or a stacked structure.

[0026] As an oxide semiconductor layer (140), an oxide semiconductor containing two or more metal elements including indium (In) is used. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides are used. The oxide semiconductor layer (140) may have an amorphous structure or a polycrystalline structure. However, in order to improve electrical properties, it is preferable that the oxide semiconductor layer (140) have a polycrystalline structure. In particular, it is preferable that the crystal structure of the source region S and the drain region D be the same as the crystal structure of the channel region CH.

[0027] When the oxide semiconductor layer (140) has a polycrystalline structure, it is preferable to use an oxide semiconductor as the oxide semiconductor layer (140) in which the ratio of indium to the total metal elements is 50% or more in atomic proportion. As the ratio of indium increases, the oxide semiconductor layer (140) becomes easier to crystallize. In addition, it is preferable to include gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer (140) is not hindered by gallium, and the oxide semiconductor layer (140) has a polycrystalline structure.

[0028] A detailed method for manufacturing the oxide semiconductor layer (140) will be described in the method for manufacturing the semiconductor device (10) described later, but the oxide semiconductor layer (140) can be formed using a sputtering method. The composition of the oxide semiconductor layer (140) formed by sputtering depends on the composition of the sputtering target. When the oxide semiconductor layer (140) has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer (140) are approximately identical. In this case, the metal element composition of the oxide semiconductor layer (140) can be determined based on the metal element composition of the sputtering target. Additionally, when the oxide semiconductor layer (140) has a polycrystalline structure, the composition of the oxide semiconductor layer (140) may be determined using X-ray diffraction (XRD) methods. Specifically, the metal element composition of the oxide semiconductor layer (140) can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer (140) obtained from the XRD method. Additionally, the metal element composition of the oxide semiconductor layer (140) can be determined using fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. Furthermore, the oxygen contained in the oxide semiconductor layer (140) is not limited to this, as it varies depending on the sputtering process conditions.

[0029] As described above, the oxide semiconductor layer (140) may have an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be fabricated using Poly-OS (Poly-crystalline Oxide Semiconductor) technology. In the following, when distinguishing from an oxide semiconductor having an amorphous structure, an oxide semiconductor having a polycrystalline structure may be described as Poly-OS.

[0030] [2. Configuration of the Hydrogen Trap Region]

[0031] FIG. 3 is a schematic partial enlarged cross-sectional view showing the configuration of a semiconductor device (10) according to one embodiment of the present invention. Specifically, FIG. 3 is an enlarged cross-sectional view of region P in FIG. 1. In addition, region P shown in FIG. 3 is a region near the drain region D, but the region near the source region S has the same configuration as region P.

[0032] Although details will be described later, the source region S and drain region D of the oxide semiconductor layer (140) are formed by ion implantation of impurities using the gate electrode (160) as a mask. As impurities, for example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are used. By ion implantation, oxygen defects are formed in the source region S and drain region D of the oxide semiconductor layer (140). Then, as hydrogen is trapped in the formed oxygen defects, the source region S and drain region D become low-resistance.

[0033] Ion implantation is performed through the gate insulating layer (150). At this time, dangling bond defect DB (marked X in FIG. 3) is formed in the gate insulating layer (150) by ion implantation. In addition, during ion implantation, there is a distribution of impurities in the depth direction, and impurities are implanted not only in the gate insulating layer (150) but also in the first oxide insulating layer (120) and the second oxide insulating layer (130). Therefore, dangling bond defect DB is formed in the first oxide insulating layer (120) and the second oxide insulating layer (130). Furthermore, as described above, since the ion implantation of impurities is performed using the gate electrode (160) as a mask, impurities are not implanted in the region overlapping with the gate electrode (160), and dangling bond defect DB is not formed.

[0034] If the amount of dangling bond defect DB in a certain region exceeds a predetermined value, that region functions as a hydrogen trap region that traps hydrogen. That is, if dangling bond defect DB exceeding a predetermined amount is formed in the gate insulating layer (150), a hydrogen trap region is formed in the gate insulating layer (150). Since the hydrogen trap region is formed by ion implantation, the hydrogen trap region does not overlap with the gate electrode (160). Although details will be described later, at the interface between the gate insulating layer (150) and the oxide semiconductor layer (140) (specifically, the source region S and drain region D of the oxide semiconductor layer (140)), the concentration of impurities on the surface of the source region S and drain region D is 2×10 17 cm -3 When this is the case, a hydrogen trap region is formed in the gate insulating layer (150). In addition, for the semiconductor device (10) to obtain good electrical characteristics, the concentration of impurities on the surfaces of the source region S and the drain region D is 2×10 19 cm -3 It is desirable to be ideal.

[0035] Here, "concentration of impurities at the surface" refers to the concentration of impurities near the surface. Additionally, "near the surface" refers to a region extending from the interface between the gate insulating layer (150) and the oxide semiconductor layer (140) (or the upper surface of the oxide semiconductor layer (140)) to a depth of 4 nm in the film thickness direction of the oxide semiconductor layer (140). However, the depth near the surface is not limited to 4 nm. For example, the depth near the surface may be 1 / 5 of the film thickness of the oxide semiconductor layer (140) based on the film thickness of the oxide semiconductor layer (140). Additionally, the concentration of impurities may be a value calculated from the dose amount of ion implantation, or a value measured by analysis such as Secondary Ion Mass Spectroscopy (SIMS).

[0036] As described above, dangling bond defect DB is formed not only in the gate insulating layer (150) but also in the first oxide insulating layer (120) and the second oxide insulating layer (130). Therefore, hydrogen trap regions that do not overlap with the gate electrode (160) may also be formed in the first oxide insulating layer (120) and the second oxide insulating layer (130). Each hydrogen trap region of the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer can significantly suppress the diffusion of hydrogen into the channel region CH.

[0037] When silicon oxide is used as the first oxide insulating layer (120), silicon dangling bond defect DB is formed in the first oxide insulating layer (120). When aluminum oxide is used as the second oxide insulating layer (130), aluminum dangling bond defect DB is formed in the second oxide insulating layer (130). In this way, different types of dangling bond defect DB are formed in the first oxide insulating layer (120) and the second oxide insulating layer (130), and a difference in hydrogen trapping performance in the hydrogen trap region may be made.

[0038] Additionally, since hydrogen is trapped in the hydrogen trap region, the hydrogen trap region that does not overlap with the gate electrode (160) has a higher concentration of hydrogen than the region that overlaps with the gate electrode (160).

[0039] Although the configuration of the semiconductor device (10) has been described above, the semiconductor device (10) described above is a so-called top-gate type transistor. The semiconductor device (10) can be modified in various ways. For example, if the light-blocking layer (105) is conductive, the semiconductor device (10) may be configured such that the light-blocking layer (105) functions as a gate electrode, and the nitride insulating layer (110), the first oxide insulating layer (120), and the second oxide insulating layer (130) function as gate insulating layers. In this case, the semiconductor device (10) is a so-called dual-gate type transistor. Also, if the light-blocking layer (105) is conductive, the light-blocking layer (105) may be a floating electrode and may be connected to the source electrode (201). Additionally, the semiconductor device (10) may be a so-called bottom-gate type transistor in which the light-blocking layer (105) functions as the main gate electrode.

[0040] [3. Method of manufacturing a semiconductor device (10)]

[0041] Referring to FIGS. 4 to 12, a method for manufacturing a semiconductor device (10) according to an embodiment of the present invention will be described. FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor device (10) according to an embodiment of the present invention. FIGS. 5 to 12 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device (10) according to an embodiment of the present invention.

[0042] As illustrated in FIG. 4, the method for manufacturing a semiconductor device (10) includes steps S1010 to S1110. Hereinafter, steps S1010 to S1110 are described in order, but the order of steps in the method for manufacturing a semiconductor device (10) may be changed. Additionally, the method for manufacturing a semiconductor device (10) may include additional steps.

[0043] In step S1010, a light-blocking layer (105) having a predetermined pattern is formed on a substrate (100) (see FIG. 5). The patterning of the light-blocking layer (105) is performed using a photolithography method.

[0044] In step S1020, a nitride insulating layer (110) and a first oxide insulating layer (120) are formed sequentially on the light-blocking layer (105) (see FIG. 6). The nitride insulating layer (110) and the first oxide insulating layer (120) are formed using a CVD method. For example, as the nitride insulating layer (110) and the first oxide insulating layer (120), a silicon nitride film and a silicon oxide film are formed, respectively. The silicon nitride film and the silicon oxide film may be formed continuously by changing the reactive gas within the same chamber.

[0045] In the step described below, a dangling bond defect having a hydrogen trap function is formed in a predetermined region of the first oxide insulating layer (120). Therefore, the first oxide insulating layer (120) does not have to be a film containing excess oxygen that becomes a hydrogen trap, and it is preferable that it be a dense film with few defects formed at 350°C or higher. If the first oxide insulating layer (120) is a film containing excess oxygen, the reliability of the semiconductor device (10) is reduced, but by making the first oxide insulating layer (120) a dense film, the reliability of the semiconductor device (10) can be improved.

[0046] The thickness of the nitride insulating layer (110) is, for example, 50 nm or more and 500 nm or less, preferably 150 nm or more and 300 nm or less. In addition, the thickness of the first oxide insulating layer (120) is, for example, 50 nm or more and 500 nm or less, preferably 150 nm or more and 300 nm or less.

[0047] In step S1030, a second oxide insulating film (135) and an oxide semiconductor film (145) are formed on the first oxide insulating layer (120) (see FIG. 7). The second oxide insulating film (135) and the oxide semiconductor film (145) are formed by a sputtering method. As the second oxide insulating film (135), an aluminum oxide film is formed. The thickness of the second oxide insulating film (135) is, for example, 1 nm or more and 30 nm or less, preferably 1 nm or more and 20 nm or less, and more preferably 1 nm or more and 10 nm or less. The thickness of the oxide semiconductor film (145) is, for example, 10 nm or more and 100 nm or less, preferably 15 nm or more and 70 nm or less, and more preferably 15 nm or more and 40 nm or less.

[0048] The oxide semiconductor film (145) in step S1030 is amorphous. In Poly-OS technology, in order for the oxide semiconductor layer (140) to have a uniform polycrystalline structure within the substrate surface, it is desirable that the oxide semiconductor film (145) be amorphous after deposition and before heat treatment. Therefore, the deposition conditions of the oxide semiconductor film (145) are preferably such that the oxide semiconductor layer (140) immediately after deposition does not crystallize as much as possible. When the oxide semiconductor film (145) is deposited by the sputtering method, the oxide semiconductor film (145) is deposited while controlling the temperature of the object to be deposited (substrate (100) and the layer formed on the substrate (100)) to 100°C or lower, preferably 80°C or lower, and more preferably 50°C or lower. Additionally, the oxide semiconductor film (145) is deposited under conditions of low oxygen partial pressure. The oxygen partial pressure is 2% or more and 20% or less, preferably 3% or more and 15% or less, and more preferably 3% or more and 10% or less.

[0049] In step S1040, patterning of the second oxide insulating film (135) and the oxide semiconductor film (145) is performed (see FIG. 8). Patterning of the second oxide insulating film (135) and the oxide semiconductor film (145) is performed using photolithography. As for etching the second oxide insulating film (135) and the oxide semiconductor film (145), wet etching may be used or dry etching may be used. In wet etching, etching may be performed using an acidic etchant. Examples of etchants may be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid. Since the oxide semiconductor film (145) in step S1040 is amorphous, the oxide semiconductor film (145) can be easily patterned into a predetermined shape by wet etching. In addition, the second oxide insulating film (135) can also be patterned into a predetermined shape using the oxide semiconductor film (145) as a mask. By doing so, the second oxide insulating layer (130) is formed.

[0050] In step S1050, heat treatment is performed on the oxide semiconductor film (145). Hereinafter, the heat treatment performed in step S1050 is referred to as "OS annealing." In OS annealing, the oxide semiconductor film (145) is maintained at a predetermined temperature for a predetermined time. The predetermined temperature is 300°C or higher and 500°C or lower, and preferably 350°C or higher and 450°C or lower. In addition, the maintenance time at the temperature is 15 minutes or higher and 120 minutes or lower, and preferably 30 minutes or higher and 60 minutes or lower. Through OS annealing, the oxide semiconductor film (145) is crystallized, and an oxide semiconductor layer (140) having a polycrystalline structure (i.e., an oxide semiconductor layer (140) including Poly-OS) is formed.

[0051] In step S1060, a gate insulating layer (150) is deposited on the second oxide insulating layer (130) and the oxide semiconductor layer (140) (see FIG. 9). The gate insulating layer (150) is deposited using a CVD method. For example, silicon oxide is deposited as the gate insulating layer (150). To reduce defects in the gate insulating layer (150), the gate insulating layer (150) may be deposited at a deposition temperature of 350°C or higher. The thickness of the gate insulating layer (150) is 50 nm or more and 300 nm or less, preferably 60 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less.

[0052] In step S1070, heat treatment is performed on the oxide semiconductor layer (140). Hereinafter, the heat treatment performed in step S1070 is referred to as "oxidation annealing." When a gate insulating layer (150) is formed on the oxide semiconductor layer (140), many oxygen defects are formed on the upper surface and side surface of the oxide semiconductor layer (140). When oxidation annealing is performed while the oxide semiconductor layer (140) is surrounded by the second oxide insulating layer (130) and the gate insulating layer (150), oxygen is supplied to the oxide semiconductor layer (140) through the second oxide insulating layer (130) and the gate insulating layer (150), and the oxygen defects of the oxide semiconductor layer (140) are repaired.

[0053] In step S1080, a gate electrode (160) having a predetermined pattern is formed on the gate insulating layer (150) (see FIG. 10). The gate electrode (160) is formed by sputtering or atomic layer deposition, and the patterning of the gate electrode (160) is performed using photolithography.

[0054] In step S1090, a source region S and a drain region D are formed within the oxide semiconductor layer (140) (see FIG. 11). The source region S and the drain region D are formed by ion implantation. Ion implantation can be performed using an ion doping device or an ion implantation device. Specifically, using the gate electrode (160) as a mask, impurities are implanted into the oxide semiconductor layer (140) through the gate insulating layer (150). Examples of implanted impurities include boron (B), phosphorus (P), argon (Ar), or nitrogen (N). In the source region S and the drain region D that do not overlap with the gate electrode (160), oxygen defects are formed by ion implantation, and hydrogen is trapped in the formed oxygen defects. As a result, the resistance of the source region S and the drain region D is reduced. Meanwhile, in the channel region CH that overlaps with the gate electrode (160), since impurities are not implanted, oxygen defects are not formed, and the resistance of the channel region CH is not reduced.

[0055] Additionally, in step S1090, impurities are implanted into the gate insulating layer (150), the second oxide insulating layer (130), and the first oxide insulating layer (120). In the gate insulating layer (150), the second oxide insulating layer (130), and the first oxide insulating layer (120), dangling bond defect DBs are formed by ion implantation. That is, hydrogen trap regions caused by dangling bond defect DBs are formed in each of the gate insulating layer (150), the second oxide insulating layer (130), and the first oxide insulating layer (120). Since hydrogen trap regions are formed by ion implantation, the hydrogen trap regions contain impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N).

[0056] In the ion implantation of step S1090, at the interface between the gate insulating layer (150) and the oxide semiconductor layer (140) (specifically, the source region S and drain region D of the oxide semiconductor layer (140)), the concentration of impurities on the surfaces of the source region S and drain region D is 1×10 19 cm -3 To achieve this, the process parameters of ion implantation (e.g., dose amount, acceleration voltage, plasma power, etc.) are controlled. For example, the dose amount is 1×10⁻⁶ 14 cm -2 The above and the acceleration voltage are 20 keV or higher, but the process parameters are not limited to these.

[0057] The concentration of impurities on the surface of the oxide semiconductor layer (140) is 1×10 19 cm -3 If the above, sufficient oxygen defects are formed in the source region S and drain region D. Additionally, hydrogen is generated along with the formation of dangling bond defect DB in the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150). In this case, even without providing a protective insulating layer containing silicon nitride on the gate insulating layer (150), hydrogen generated in the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150) is supplied to the oxygen defects formed in the source region S and drain region D. Therefore, the source region S and drain region D are sufficiently reduced in resistance.

[0058] In step S1100, openings (171 and 173) are formed in the gate insulating layer (150) (see FIG. 12). By forming the openings (171 and 173), the source region S and drain region D of the oxide semiconductor layer (140) are exposed.

[0059] In step S1110, a source electrode (201) is formed on the gate insulating layer (150) and inside the opening (171), and a drain electrode (203) is formed on the gate insulating layer (150) and inside the opening (173). The source electrode (201) and the drain electrode (203) are formed as the same layer. Specifically, the source electrode (201) and the drain electrode (203) are formed by patterning a single conductive film formed. By the above steps, the semiconductor device (10) shown in FIG. 1 is manufactured.

[0060] The method for manufacturing the semiconductor device (10) is not limited to the steps described above. For example, a step of forming a protective insulating layer may be included after step S1110. In this embodiment, since the source region S and drain region D are sufficiently low resistance in step S1090, a configuration that does not include silicon nitride in the protective insulating layer is also possible. For example, a planarization film such as polyimide resin may be used as the protective insulating layer.

[0061] As described above, in a semiconductor device (10) according to one embodiment of the present invention, a hydrogen trap region is formed in the gate insulating layer (150), and oxygen defects are formed in the source region S and drain region D. Additionally, hydrogen is generated in the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150) by ion implantation. The concentration of impurities on the surface of the source region S and drain region D is 1×10 19 cm -3If the above, sufficient oxygen defects are formed in the source region S and drain region D. In this case, hydrogen generated from the first oxide insulating layer (120), the second oxide insulating layer (130), and the gate insulating layer (150) is supplied to the oxygen defects formed in the source region S and drain region D. Accordingly, the semiconductor device (10) includes a low-resistance source region S and drain region D, regardless of whether a protective insulating layer containing silicon nitride is formed, and has electrical characteristics in which depletion is suppressed.

[0062] Examples

[0063] Based on the sample produced, the semiconductor device (10) is described in more detail.

[0064] [1. Preparation of Example Samples]

[0065] As Example 1, the acceleration voltage and dose amount are controlled using the manufacturing method described above, and the concentration of impurities (boron) on the surfaces of the source region and drain region is 1×10 19 cm -3 Four semiconductor devices (Example Samples 1-1 to 1-4) were fabricated. In addition, as Example 2, a protective insulating layer containing silicon nitride was provided, and the concentration of impurities (boron) on the surfaces of the source region and drain region was 1×10 19 cm -3 Four semiconductor devices (Example Samples 2-1 to 2-4) were fabricated. Specifically, in Example 2, after step S1090, a protective insulating layer containing silicon nitride was formed. Then, similar to steps S1100 and S1110, the protective insulating layer and the gate insulating layer were opened, and a source electrode and a drain electrode were formed so as to be electrically connected to the source region and the drain region, respectively, through the opening.

[0066] [2. Preparation of Comparative Sample]

[0067] As Comparative Example 1, the acceleration voltage and dose amount were controlled using the same manufacturing method as in Example 1, and the concentration of impurities (boron) on the surfaces of the source and drain regions was 1×10 19 cm -3 Nine semiconductor devices (Comparative Example Samples 1-1 to 1-9) with a value of less than [value] were fabricated. Additionally, as Comparative Example 2, a protective insulating layer containing silicon nitride was provided using the same manufacturing method as in Example 2, and the concentration of impurities (boron) on the surfaces of the source region and drain region was 1×10⁻⁶ 19 cm -3 Nine semiconductor devices (Comparative Example Samples 2-1 to 2-9) with fewer than [number] were fabricated.

[0068] In addition, for both the example sample and the comparative example sample, the oxide semiconductor layer contained indium, and the atomic ratio of indium to the total metal elements was 50% or more. Furthermore, the oxide semiconductor layer had an amorphous structure before OS annealing, but the oxide semiconductor layer was crystallized by OS annealing and had a polycrystalline structure. That is, the oxide semiconductor layer of both the example sample and the comparative example sample contained Poly-OS.

[0069] The surface boron concentrations in the source and drain regions of the example samples are as shown in Table 1. In addition, the surface boron concentrations in the source and drain regions of the comparative example samples are as shown in Table 2. The boron concentration was converted into the dose amount in ion implantation.

[0070]

[0071]

[0072] [3. Measurement of Sheet Resistance]

[0073] FIG. 13 is a graph showing the correlation between the boron concentration and sheet resistance on the surfaces of the source and drain regions in the example samples and comparative example samples. Additionally, in the graph of FIG. 13, for convenience of explanation, the boron concentration for comparative example sample 1-1 and comparative example sample 2-1 is 2×10 15 cm -3 It is plotting as if it were

[0074] The graph shown in FIG. 13 is divided into three ranges based on the boron concentration on the surfaces of the source and drain regions. The first range is 2×10 17 cm -3 It is a range of less than, and the second range is 2×10 17 cm -3 At least 1×10 19 cm -3 The range is less than, and the third range is 1×10 19 cm -3 The above ranges are. Comparative Example Samples 1-1 to 1-6 and Comparative Example Samples 2-1 to 2-6 fall within the first range. Comparative Example Samples 1-7 to 1-9 and Comparative Example Samples 2-7 to 2-9 fall within the second range. Example Samples 1-1 to 1-4 and Example Samples 2-1 to 2-4 fall within the third range.

[0075] In the first range, the sheet resistance of the source region and drain region of Comparative Example Samples 1-1 to 1-6 is greater than the sheet resistance of the source region and drain region of Comparative Example Samples 2-1 to 2-6. In Comparative Example Samples 2-1 to 2-6, a protective insulating layer containing silicon nitride is provided, so sufficient hydrogen is supplied from the protective insulating layer to the source region and drain region. Therefore, the source region and drain region of Comparative Example Samples 2-1 to 2-5 become low resistance. On the other hand, in Comparative Example Samples 1-1 to 1-6, a protective insulating layer containing silicon nitride is not provided. Therefore, hydrogen is not supplied to the source region and drain region of Comparative Example Samples 1-1 to 1-6, and the source region and drain region do not become low resistance.

[0076] The first range is a range in which the source region and drain region become low-resistance due to the supply of hydrogen from a protective insulating layer containing silicon nitride. However, in the first range, sufficient oxygen defects are not formed in the source region and drain region. Therefore, the hydrogen supplied to the source region and drain region is not trapped in the source region and drain region but diffuses into the channel region. Consequently, in the first range, it is difficult to obtain electrical characteristics that exhibit switching performance.

[0077] In the second range, as understood from the trends of Comparative Examples 2-7 to 2-9, the sheet resistance of the source region and drain region increases. Similarly, in Comparative Samples 1-7 to 1-9, although there is a tendency for the sheet resistance of the source region and drain region to decrease overall, the sheet resistance of the source region and drain region increases. Here, with reference to FIG. 14, the reason for the increase in the sheet resistance of the source region and drain region is explained.

[0078] FIG. 14 is a schematic cross-sectional view illustrating a hydrogen trap region that traps hydrogen supplied from a protective insulating layer (170).

[0079] As illustrated in FIG. 14, when a sufficient number of dangling bond defect DBs are formed in the gate insulating layer (150) to form a hydrogen trap region, the supply of hydrogen from the protective insulating layer (170) containing silicon nitride to the source region S and drain region D is suppressed by the hydrogen trap region. Consequently, the source region S and drain region D have oxygen defects, but since hydrogen is not supplied to the oxygen defects, the sheet resistance of the source region S and drain region D increases.

[0080] The second range is a range in which a hydrogen trap region is formed within the gate insulating layer by ion implantation. In the second range, since hydrogen is preferentially trapped in the hydrogen trap region, the supply of hydrogen to the source region and drain region is suppressed. Consequently, in the second range, the contact resistance between the source region and the source electrode and between the drain region and the drain electrode increases, and the current flowing through the channel region is suppressed. As a result, electrical characteristics with reduced on-current are obtained.

[0081] In the third range, the sheet resistance of the source and drain regions of Example Samples 1-1 to 1-4 is 1×10 2 The resistance is reduced to kΩ / sq. or less, and is of the same degree as the sheet resistance of the source and drain regions of Example Samples 2-1 to 2-4. That is, in Example Samples 1-1 to 1-4, the source and drain regions are sufficiently reduced to low resistance even without the supply of hydrogen from the protective insulating layer.

[0082] In the third range, since sufficient oxygen defects are formed in the source and drain regions by ion implantation, hydrogen is supplied from the first oxide insulating layer and the second oxide insulating layer to the oxygen defects in the source and drain regions. That is, since the amount of hydrogen supplied to the source and drain regions is controlled according to the oxygen defects, the diffusion of hydrogen into the channel region is suppressed. Therefore, electrical characteristics are obtained that exhibit switching performance and suppress depletion.

[0083] [4. Measurement of Electrical Characteristics]

[0084] FIGS. 15a to 15d are graphs showing the electrical characteristics of Example Samples 1-1 to 1-4, respectively. FIGS. 16a to 16d are graphs showing the electrical characteristics of Example Samples 2-1 to 2-4, respectively. Each of the graphs shown in FIGS. 15a to 15d and FIGS. 16a to 16d displays the electrical characteristics of 26 samples having a channel width W / channel length L = 4.5 μm / 3.0 μm. The drain current Id is plotted on the vertical axis of the graphs showing the electrical characteristics, and the gate voltage Vg is plotted on the horizontal axis. The measurement conditions for the electrical characteristics of each sample are as shown in Table 3.

[0085]

[0086] As illustrated in FIGS. 15a to 15d and FIGS. 16a to 16d, in any of the example samples 1-1 to 1-4 in which a protective insulating layer including silicon nitride is not provided and example samples 2-1 to 2-4 in which a protective insulating layer including silicon nitride is provided, switching performance is exhibited and electrical characteristics with suppressed depletion are obtained.

[0087] Each of the embodiments described above as embodiments of the present invention may be implemented in appropriate combinations as long as they are not contradictory to one another. Furthermore, based on each embodiment, any addition, deletion, or design modification of components, or any addition, omission, or modification of processes, or any changes to conditions made by a person skilled in the art are also included within the scope of the present invention, provided that they possess the essence of the present invention.

[0088] Even if there are other effects different from those resulting from the modes of each embodiment described above, those that are obvious from the description in this specification or can be easily predicted by those skilled in the art shall be interpreted as naturally resulting from the present invention. Explanation of the symbols

[0089] 10: Semiconductor device 100: Substrate 105: Shading layer 110: Nitride insulating layer 120: First oxide insulating layer 130: Second oxide insulating layer 135: Second oxide insulating film 140: Oxide semiconductor layer 145: Oxide semiconductor film 150: Gate insulation layer 160: Gate electrode 171: Opening 173: Opening 200: Source and drain electrodes 201: Source electrode 203: Drain electrode

Claims

Claim 1 The apparatus comprises a first oxide insulating layer, a second oxide insulating layer above the first oxide insulating layer, an oxide semiconductor layer above the second oxide insulating layer, a gate insulating layer above the oxide semiconductor layer that contacts the oxide semiconductor layer, and a gate electrode above the gate insulating layer, wherein the first oxide insulating layer comprises silicon oxide, the second oxide insulating layer comprises aluminum oxide, the second oxide insulating layer has the same pattern as the oxide semiconductor layer, the oxide semiconductor layer comprises a channel region that overlaps with the gate electrode, and a source region and a drain region that do not overlap with the gate electrode, and at the interface between the source region and the drain region and the gate insulating layer, the concentration of impurities on at least one surface of the source region and the drain region is 1×10⁻⁶ 19 cm -3 A semiconductor device having the above, wherein the above impurities are also included in the region overlapping with the oxide semiconductor layer within the first oxide insulating layer. Claim 2 A semiconductor device according to claim 1, wherein the impurity is one selected from the group consisting of boron, phosphorus, argon, and nitrogen. Claim 3 ◈Claim 3 was abandoned upon payment of the registration fee.◈ A semiconductor device according to Claim 1, wherein the oxide semiconductor layer comprises a plurality of metal elements, one of the plurality of metal elements is indium, and the atomic ratio of indium to the plurality of metal elements is 50% or more. Claim 4 A semiconductor device according to claim 1, wherein the oxide semiconductor layer has a polycrystalline structure. Claim 5 ◈Claim 5 was abandoned upon payment of the registration fee.◈ A semiconductor device according to Claim 4, wherein the at least one crystal structure of the source region and the drain region is identical to the crystal structure of the channel region. Claim 6 In claim 1, the at least one sheet resistance of the source region and drain region is 1×10 2 Semiconductor device with a kΩ / sq. or less. Claim 7 delete Claim 8 A semiconductor device according to claim 1, further comprising a source electrode and a drain electrode electrically connected to each of the source region and the drain region, wherein the source electrode and the drain electrode are in contact with the surface of the gate insulating layer in contact with the gate electrode. Claim 9 A semiconductor device according to claim 1, wherein the gate insulating layer includes a hydrogen trap region for trapping hydrogen. Claim 10 In claim 9, the semiconductor device wherein the hydrogen trap region is formed by the impurity injected using the gate electrode as a mask. Claim 11 A semiconductor device according to claim 10, wherein the impurity is one selected from the group consisting of boron, phosphorus, argon, and nitrogen.

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