Semiconductor device

Abstract

A semiconductor device according to one embodiment includes a plurality of sampler circuits that receive a plurality of offset clock signals or a plurality of divided clock signals and sample a data signal in response to each of the plurality of divided clock signals, and a calibration circuit that applies a first offset clock signal among the plurality of offset clock signals to a first sampler circuit among the plurality of sampler circuits and applies a second offset clock signal having a phase opposite to the first offset clock signal among the plurality of offset clock signals to a second sampler circuit among the plurality of sampler circuits, and generates a first offset adjustment signal that adjusts the offset of the first sampler circuit based on the output of the first sampler circuit that is output in response to the first offset clock signal.

Description

Technology Field

[0001] The disclosure relates to a semiconductor device. Background Technology

[0002] Since semiconductor devices are designed to operate at low power, the receiving circuit of the semiconductor device must accurately process input data signals with small amplitudes. The receiving circuit includes a sampler circuit that amplifies the input data signals. However, the sampler circuit has difficulty detecting minute signals due to offsets caused by process skew, mismatches, etc., between the transistors of the sampler circuit. Therefore, the sampler circuit includes an offset control circuit that compensates for the offset of the sampler circuit. The technology forming the background of the present invention is disclosed in U.S. Patent Publication US20150358005. The problem to be solved

[0003] One embodiment aims to provide a semiconductor device capable of canceling kickback noise in the offset calibration operation of a sampler circuit.

[0004] One embodiment aims to provide a semiconductor device capable of applying an accurate offset voltage to a sampler circuit. means of solving the problem

[0005] A semiconductor device according to one embodiment for solving such technical problems includes a plurality of offset clock signals or a plurality of divided clock signals, a plurality of sampler circuits that receive a plurality of offset clock signals and sample a data signal in response to each of the plurality of divided clock signals, and a calibration circuit that applies a first offset clock signal among the plurality of offset clock signals to a first sampler circuit among the plurality of sampler circuits, applies a second offset clock signal having a phase opposite to the first offset clock signal among the plurality of offset clock signals to a second sampler circuit among the plurality of sampler circuits, and generates a first offset adjustment signal that adjusts the offset of the first sampler circuit based on the output of the first sampler circuit that is output in response to the first offset clock signal.

[0006] The calibration circuit may include a clock generator that generates a first offset clock signal and a second offset clock signal.

[0007] It may further include a phase splitter that generates multiple divided clock signals by dividing a data clock signal received in synchronization with a data signal.

[0008] The calibration circuit includes a clock generator that generates a first internal clock signal and a second internal clock signal, and the phase splitter can buffer the first internal clock signal to generate a first clock signal and buffer the second internal clock signal to generate a second clock signal.

[0009] A phase splitter may include a divider that divides a clock signal input to an input terminal by a constant phase difference to generate a plurality of first clock signals and outputs the plurality of first clock signals to an output terminal, and a buffer that buffers the plurality of first clock signals input to an input terminal and outputs them to an output terminal.

[0010] The phase splitter further includes a compensation circuit that applies a degradation compensation signal to the gate of at least one of the transistors included in the divider, and the compensation circuit can buffer a first internal clock signal and a second internal clock signal and apply them to the output terminal of the divider as a first offset clock signal and a second offset clock signal.

[0011] The phase splitter further includes a compensation circuit that applies a degradation compensation signal to the gate of at least one of the transistors included in the buffer, and the compensation circuit can buffer a first internal clock signal and a second internal clock signal and apply them to the output terminal of the buffer as a first offset clock signal and a second offset clock signal.

[0012] The calibration circuit includes a clock generator that generates an internal clock signal, and a phase splitter can divide the internal clock signal to generate a first offset clock signal and a second offset clock signal.

[0013] Each of the plurality of sampler circuits may include an amplifier that amplifies and outputs the voltage difference between a data signal and a reference signal, and an offset control circuit that applies a voltage to the output terminal of the amplifier to control the offset of the amplifier according to an offset control signal when the data signal is input to the amplifier.

[0014] The reference signal can be applied in common to the amplifier of the first sampler circuit and the amplifier of the second sampler circuit.

[0015] When a first offset clock signal is applied to the amplifier of the first sampler circuit and a second offset clock signal is applied to the amplifier of the second sampler circuit, the calibration circuit can generate a first offset adjustment signal.

[0016] When a first offset clock signal is applied to the amplifier of the first sampler circuit and a second offset clock signal is applied to the amplifier of the second sampler circuit, the calibration circuit can generate a second offset adjustment signal that adjusts the offset of the amplifier of the second sampler circuit at a different period from the first offset adjustment signal.

[0017] The calibration circuit, after generating a first offset adjustment signal, applies a third offset clock signal among a plurality of offset clock signals to a third sampler circuit among a plurality of sampler circuits, generates a third offset adjustment signal that adjusts the offset of the third sampler circuit based on the output of the third sampler circuit that is output in response to the third offset clock signal, and the sum of the phase difference between the third offset clock signal and the first offset clock signal and the phase difference between the second offset clock signal and the third offset clock signal may be 180 degrees.

[0018] If there are n sampler circuits, the multiple offset clock signals have a phase difference of 360 / n degrees from each other, and n is a natural number, and the calibration circuit can sequentially perform offset calibration for the multiple sampler circuits in the order of the phase difference of each of the multiple offset clock signals applied to each of the multiple sampler circuits.

[0019] A semiconductor memory device according to one embodiment includes a memory cell array comprising a plurality of memory cells, a clock control circuit that receives a data clock signal and divides the data clock signal to generate a plurality of divided clock signals, a plurality of sampler circuits that receive a data signal and samples the data signal in synchronization with the plurality of divided clock signals, a sense amplifier that writes the sampled data signal to a plurality of memory cells, and a calibration circuit that applies a plurality of offset clock signals having opposite phases to the plurality of sampler circuits and performs offset calibration of the plurality of sampler circuits based on the output of the plurality of sampler circuits generated in synchronization with the plurality of offset clock signals.

[0020] The clock control circuit receives a system clock signal, buffers the system clock signal, and provides it to the calibration circuit, and the calibration circuit can generate multiple offset clock signals based on the buffered system clock signal.

[0021] The output terminal of the clock control circuit is connected to the clock input terminal of a plurality of sampler circuits, and the calibration circuit can apply a plurality of offset clock signals to the clock input terminal of a plurality of sampler circuits through the output terminal of the clock control circuit.

[0022] The clock control circuit receives a system clock signal further, buffers the system clock signal, and provides it to the calibration circuit. The calibration circuit can provide the buffered system clock signal to the clock control circuit so that the clock control circuit outputs a plurality of offset clock signals to the output terminal of the clock control circuit.

[0023] The calibration circuit can sequentially perform offset calibration of the first sampler circuit and the second sampler circuit while applying a first offset clock signal among a plurality of offset clock signals to the first sampler circuit among a plurality of sampler circuits and applying a second offset clock signal having a phase opposite to the first offset clock signal among a plurality of offset clock signals to the second sampler circuit.

[0024] If there are n sampler circuits, the multiple offset clock signals have a phase difference of 360 / n degrees from each other, and n is a natural number, and the calibration circuit can sequentially perform offset calibration for the multiple sampler circuits in the order of the phase difference of each of the multiple offset clock signals applied to each of the multiple sampler circuits.

[0025] An offset calibration method according to one embodiment includes the steps of: applying a first voltage and a second voltage to two input terminals of a first amplifier and two input terminals of a second amplifier different from the first amplifier; applying a first clock signal to a clock input terminal of the first amplifier and applying a second clock signal having an opposite phase to the first clock signal to a clock input terminal of the second amplifier; and generating a first offset adjustment signal that adjusts the offset of the first amplifier by performing offset calibration of the first amplifier using a voltage output from an output terminal of the first amplifier while applying the first clock signal and the second clock signal.

[0026] While applying the first clock signal and the second clock signal, the method may further include the step of generating a second offset adjustment signal that adjusts the offset of the second amplifier by performing offset calibration of the second amplifier using the voltage output from the output terminal of the second amplifier.

[0027] It may further include the step of applying a first offset adjustment signal to a first offset adjustment circuit connected to two output terminals of the first amplifier to adjust the offset of the first amplifier.

[0028] A receiver according to one embodiment includes a plurality of sampler circuits, each comprising an offset adjustment circuit that receives an offset adjustment signal and outputs an offset voltage, and an amplifier that senses and amplifies a data signal input to an input terminal and outputs it to an output terminal to which an offset voltage is applied; and a calibration circuit that applies a first clock signal to an amplifier of a first sampler circuit among the plurality of sampler circuits, applies a second clock signal having a phase opposite to the first clock signal to an amplifier of a second sampler circuit among the plurality of sampler circuits, and generates an offset adjustment signal of the first sampler circuit based on the output at the output terminal of the amplifier of the first sampler circuit. Brief explanation of the drawing

[0029] FIG. 1 is an example block diagram of a memory system according to one embodiment. FIG. 2 is a block diagram showing a semiconductor memory device according to one embodiment. FIG. 3 is a block diagram showing a clock control circuit, a receiver, and a calibration circuit of a semiconductor memory device according to one embodiment. Figure 4 is a schematic circuit diagram of the sense amplifier of Figure 3. Figure 5 is a graph showing the waveforms of signals input to the amplifier of Figure 4. FIG. 6 is a timing diagram showing a clock signal applied to a sense amplifier according to one embodiment. FIG. 7 is a diagram showing a clock signal applied during the offset calibration period of a sense amplifier according to one embodiment. FIG. 8 is a block diagram showing a clock control circuit, a receiver, and a calibration circuit of a semiconductor memory device according to another embodiment. FIG. 9 is a block diagram showing an example of a phase splitter according to another embodiment. FIG. 10 is a diagram illustrating the connection state of a compensation circuit of a buffer that outputs a clock signal during the offset calibration period of a sense amplifier according to another embodiment. FIG. 11 is a diagram illustrating the connection state of a compensation circuit of a CMOS divider that outputs a clock signal during the offset calibration period of a sense amplifier according to another embodiment. FIG. 12 is a diagram illustrating a phase splitter that outputs a clock signal during the offset calibration period of a sense amplifier according to another embodiment. FIG. 13 is an exemplary block diagram showing a computer system according to one embodiment. Specific details for implementing the invention

[0030] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0031] In addition, to clearly explain the invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals. In the flowcharts described with reference to the drawings, the order of operations may be changed, multiple operations may be merged or divided, and certain operations may not be performed.

[0032] Additionally, expressions written in the singular form may be interpreted as singular or plural unless explicit expressions such as "one" or "singular" are used. Terms including ordinal numbers, such as the first, the second, etc., may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

[0033] FIG. 1 is an example block diagram of a memory system according to one embodiment.

[0034] Referring to FIG. 1, the memory system (100) includes a memory device (110) and a memory controller (120). In some embodiments, the memory device (110) and the memory controller (120) are connected through a memory interface and can exchange signals through the memory interface.

[0035] A memory device (110) includes a memory cell array (111) and a data input / output (I / O) circuit (112). The memory cell array (111) includes a plurality of memory cells connected in a plurality of rows and a plurality of columns. In some embodiments, a row may be defined by a word line and a column may be defined by a bit line. The data I / O circuit (112) may store data (DATA) transmitted from the outside in the memory cell array (111) or output data (DATA) stored in the memory cell array (111) to the outside of the memory device (110) (i.e., a memory controller (120), etc.).

[0036] In one embodiment, the data I / O circuit (112) can amplify data (DATA) using a sampler circuit (113). The data I / O circuit (112) can perform offset calibration so that the data (DATA) can be accurately amplified. The data I / O circuit (112) can perform offset calibration by simultaneously providing clock signals of opposite phases to the sampler circuit (113). In some embodiments, the data I / O circuit (112) can generate clock signals of opposite phases using an internal clock signal of a memory device (110). For example, the data I / O circuit (112) can generate a first internal clock signal and a second internal clock signal having opposite phases and provide them to the sampler circuit (113). As another example, the data I / O circuit (112) can divide the internal clock signal and provide it to the sampler circuit (113) as clock signals of opposite phases.

[0037] The memory controller (120) provides a signal to the memory device (110) to control the memory operation of the memory device (110). The signal may include a command (CMD) and an address (ADDR). In some embodiments, the memory controller (120) provides the command (CMD) and the address (ADDR) to the memory device (110) to access the memory cell array (111) and control memory operations such as reading or writing. Data may be transferred from the memory cell array (111) to the memory controller (120) according to a read operation, and data may be transferred from the memory controller (120) to the memory cell array (111) according to a write operation.

[0038] The command (CMD) may include an activate command, a read / write command, and a refresh command. In some embodiments, the command (CMD) may further include a precharge command. The activate command may be a command to switch a target row of the memory cell array (111) to an active state in order to write data to the memory cell array (111) or to read data from the memory cell array (111). In response to the activate command, the memory cells of the target row may be activated (e.g., driven). The read / write command may be a command to perform a read or write operation on the target memory cells of the row that has been switched to an active state. In some embodiments, the read command may be a command to enable an emphasis drive. The refresh command may be a command to perform a refresh operation on the memory cell array (111).

[0039] The memory controller (120) applies a system clock (CK) and a data clock (WCK) to the memory device (110) to control data input / output. The system clock (CK) may be provided in the form of differential signals having phases complementary to each other. Additionally, the data clock (WCK) may also be provided in the form of differential signals having phases complementary to each other. The system clock (CK) is a clock related to the transmission rate of a command (CMD) or address (ADDR) applied to perform data input / output operations. Meanwhile, the data clock (WCK) is a clock related to the input / output rate of data (DATA). In some embodiments, the command (CMD) and address signal (ADDR) are transmitted based on the system clock signal (CK, CKB). The data (DATA) is transmitted based on the data clock signal (WCK).

[0040] In some embodiments, the memory controller (120) may access the memory device (110) in response to a request from a host outside the memory system (100). The memory controller (120) may communicate with the host using various protocols.

[0041] The memory device (110) may be a storage device based on a semiconductor device. In some embodiments, the memory device (110) may include a Dynamic Random Access Memory (DRAM) device. In some embodiments, the memory device (110) may include other volatile or non-volatile memory devices in which a sense amplifier (113) is used.

[0042] FIG. 2 is a block diagram showing a semiconductor memory device according to one embodiment.

[0043] Referring to FIG. 2, the memory device (200) includes a memory cell array (210), a sense amplifier (211), a control logic circuit (220), an address buffer (230), a row decoder (250), a column decoder (260), an I / O gating circuit (270), a clock control circuit (280), and a data I / O circuit (290).

[0044] A memory cell array (210) includes a plurality of memory cells (MC). In some embodiments, the memory cell array (210) may include a plurality of memory banks (210a to 210h). Although eight memory banks (BANK0 to BANK7) (210a to 210h) are shown in FIG. 2, the number of memory banks is not limited thereto. Each memory bank (210a to 210h) may include a plurality of rows, a plurality of columns, and a plurality of memory cells (MC) arranged at the intersections of the plurality of rows and the plurality of columns. In some embodiments, the plurality of rows may be defined by a plurality of word lines (WL), and the plurality of columns may be defined by a plurality of bit lines (BL).

[0045] The control logic circuit (220) controls the operation of the memory device (200). For example, the control logic circuit (220) can generate a control signal to enable the memory device (200) to perform a read operation, a write operation, an offset calibration operation, etc. In some embodiments, the control logic circuit (220) may include a command decoder (221). The command decoder (221) can generate a control signal by decoding a command (CMD) received from a memory controller (e.g., 120 in FIG. 1). In some embodiments, the control logic circuit (220) may further include a mode register (222) for setting the operation mode of the memory device (200).

[0046] The address buffer (230) receives an address (ADDR) provided by the memory controller (120). The address (ADDR) includes a row address (RA) indicating a row of the memory cell array (210) and a column address (CA) indicating a column. The row address (RA) is provided to the row decoder (250), and the column address (CA) is provided to the column decoder (260). The row address (RA) may also be provided to the refresh control circuit (290). In some embodiments, the row address (RA) may be provided to the row decoder (250) through a row address multiplexer (251). In some embodiments, the address (ADDR) may further include a bank address (BA) indicating a memory bank. The bank address (BA) may be provided to the bank control logic (240).

[0047] In some embodiments, the memory device (200) may further include bank control logic (240) that generates a bank control signal in response to a bank address (BA). In response to the bank control signal, the bank control logic (240) may activate a row decoder (250) corresponding to the bank address (BA) among a plurality of row decoders (250) and activate a column decoder (260) corresponding to the bank address (BA) among a plurality of column decoders (260).

[0048] In some embodiments, the memory device (200) may further include a row address multiplexer (251). The row address multiplexer (251) may receive a row address (RA) from an address buffer (230) and receive a row address to be refreshed (REF_RA) from a refresh control circuit (290). The row address multiplexer (251) may optionally output the row address (RA) received from the address buffer (230) and the row address (REF_RA) received from the refresh control circuit (290) to a row decoder (250).

[0049] The row decoder (250) selects a row to be activated among a plurality of rows of the memory cell array (210) based on the row address. To do this, the row decoder (250) may apply a driving voltage to the word line corresponding to the row to be activated. In some embodiments, a plurality of row decoders (250a to 250h) corresponding to a plurality of memory banks (210a to 210h) may be provided.

[0050] The column decoder (260) selects a column to be activated from among a plurality of columns of the memory cell array (210) based on a column address. To do this, the column decoder (260) can activate a sense amplifier (211) corresponding to the column address (CA) through an I / O gating circuit (270). In some embodiments, a plurality of column decoders (260a to 260h) corresponding to a plurality of memory banks (210a to 210h) may be provided. In some embodiments, the I / O gating circuit (270) gates input / output data and may include a data latch for storing data read from the memory cell array (210) and a write driver for writing data to the memory cell array (210). Data read from the memory cell array (210) is detected by the sense amplifier (211) and may be stored in the I / O gating circuit (270) (e.g., the data latch). In some embodiments, a plurality of sense amplifiers (211a to 211h) corresponding to each of a plurality of memory banks (210a to 210h) may be provided.

[0051] In some embodiments, data read from the memory cell array (210) (e.g., data stored in a data latch) may be provided to the memory controller (120) through the data I / O circuit (290). Data to be written to the memory cell array (210) is provided from the memory controller (120) to the data I / O circuit (290), and the data provided to the data I / O circuit (290) may be provided to the I / O gating circuit (270).

[0052] The clock control circuit (280) can receive a system clock (CK) and a data clock (WCK). The clock control circuit (280) can generate divided clock signals (DCKa, …, DCKh) having multiple phases using the system clock (CK) and the data clock (WCK). In some embodiments, the clock control circuit (280) can generate divided clock signals (DCKa, …, DCKh) by dividing the data clock (WCK) using the system clock (CK). Additionally, the clock control circuit (280) can generate an internal clock signal using the system clock (CK).

[0053] The data I / O circuit (290) includes a receiver (291) and a calibration circuit (294). The receiver (291) can sample data (DATA). The receiver (291) may include a plurality of sampler circuits (292a, …, 292h) and a plurality of latches (293a, …, 293h). Each of the plurality of sampler circuits (292a, …, 292h) is provided with clock divider signals (DCKa, …, DCKh), and the plurality of sampler circuits (292a, …, 292h) can sample data (DATA) in synchronization with the provided clock divider signals (DCKa, …, DCKh). The latch (293) can latch the sampled data (DATA) and output it.

[0054] The calibration circuit (294) can perform offset calibration to compensate for the offset of the sampler circuit (292). Specifically, the calibration circuit (294) can perform offset calibration to generate an offset adjustment signal used to compensate for the offset of the sampler circuit (292). The offset calibration can be performed using the voltage difference between the voltages output from the two output terminals of the sampler circuit (292) when an input signal and a reference signal are applied to the sampler circuit (292). In some embodiments, the calibration circuit (294) can generate an offset adjustment signal such that the voltage difference between the voltages output from the two output terminals is minimized. The calibration circuit (294) can generate an offset adjustment signal that compensates for the offset voltage so that the voltages output from the two output terminals have a voltage difference within a predetermined range. When offset calibration is performed for the sampler circuit (292a), kick-back noise may occur in which the clock signal applied to the sampler circuit (292a) by the parasitic capacitor of the sampler circuit (292a) affects other signals input to the sampler circuit (292a). Kick-back noise caused by the clock signal may affect the reference signal applied to the sampler circuit (292a). During normal operation of receiving data, clock signals (DCKa, …, DCKh) having phase differences are simultaneously applied to a plurality of sampler circuits (292a, …, 292h), so that kick-back noise generated by clock signals of opposite phases can cancel each other out, thus reducing the impact of the clock signal's kick-back noise on the reference signal. However, when offset calibration is performed, if a clock signal is applied to each of the sampler circuits (292a, …, 292h), the reference signal may be affected by the kickback noise of one clock signal.An offset adjustment signal generated using a reference signal affected by kickback noise has difficulty accurately compensating for the offset voltage during normal operation of receiving data (DATA). A calibration circuit (294) according to one embodiment may provide two clock signals having opposite phases to a sampler circuit (292) during the offset calibration period. Since two clock signals having opposite phases are provided to the sampler circuit (292), the kickback noise can cancel each other out. That is, since the calibration circuit (294) generates an offset adjustment signal using a reference signal that is less affected by kickback noise, it can accurately compensate for the offset voltage occurring during normal operation of receiving data (DATA).

[0055] FIG. 3 is a block diagram showing a clock control circuit, a receiver, and a calibration circuit of a semiconductor memory device according to one embodiment.

[0056] Referring to FIG. 3, the clock control circuit (300) may include clock buffers (301, 302) and a phase splitter (310), the calibration circuit (310) may include an internal clock generator (311) and an offset calibration circuit (312), and the receiver (320) may include a plurality of sampler circuits (321_1, …, 321_n) and a plurality of latches (332_1, … 332_n).

[0057] The clock buffer (301) receives data clock signals (WCK, WCKB) transmitted through the data clock pads (WCK_T, WCK_C). The clock buffer (301) can buffer the received data clock signals (WCK, WCKB) and provide them to the phase splitter (310).

[0058] The clock buffer (302) receives system clock signals (CK, CKB) transmitted through clock pads (CK_T, CK_C). The clock buffer (302) can buffer the received system clock signals (CK, CKB) and provide them to the phase splitter (310). The clock buffer (302) can also provide the buffered system clock signals (ICK, OCKB) to the internal clock generator (311) and other circuits.

[0059] The phase splitter (310) receives clock signals (ICK, ICKB) and data clock signals (WCK, WCKB) buffered in the clock buffer (301) and can generate divided clock signals (DCK1, …, DCKn). The phase splitter (310) can generate n divided clock signals (DCK1, …, DCKn). The phases of the divided clock signals (DCK1, …, DCKn) may be different from each other. For example, the phase of each of the n divided clock signals (DCK1, …, DCKn) may be 360 / n*0, …, 360 / n*(n-1). The divided clock signals (DCK1, …, DCKn) may be applied to the clock input terminals (PH1, …, PHn) of the sampler circuit (321). The phase splitter (310) can match the phase of the first divided clock signal (DCK1) among the divided clock signals (DCK1, …, DCKn) to the clock signal (ICK).

[0060] The internal clock generator (311) receives clock signals (ICK, ICKB) during the offset calibration period and can generate offset clock signals (OCK1, …, OCKn) for performing offset calibration. The offset clock signals (OCK1, …, OCKn) can be applied to the clock input terminals (PH1, …, PHn) of the sampler circuit (321).

[0061] A plurality of sampler circuits (321_1, …, 321_n) can receive data (DATA). A plurality of sampler circuits (321_1, …, 321_n) can each sample data (DATA) in synchronization with an applied divided clock signal (DCK1, …, DCKn). A plurality of sampler circuits (321_1, …, 321_n) can output the sampled signal (SAD1, …, SADn) to a plurality of latches (322_1, … 322_n).

[0062] Multiple latches (322_1, … 322_n) can latch the output signal (SAD1, …, SADn) of the sampler circuit (321) and output it as sampling data (SPD1, …, SPDn).

[0063] When performing offset calibration, the offset calibration circuit (312) can receive output signals (SAD1, …, SADn) of the sampler circuit (321) and generate offset adjustment signals (CAL1, …, CALn). The offset adjustment signals (CAL1, …, CALn) can each be used to adjust the offset voltage of the sampler circuits (321_1, …, 321_n). In some embodiments, when offset calibration is performed by the offset calibration circuit (312), the internal clock generator (311) can generate a plurality of offset clock signals (OCK, …, OCKn) and output them to a plurality of sampler circuits (321_1, …, 321_n). If there are n sampler circuits (321_1, …, 321_n), the multiple offset clock signals (OCK, …, OCKn) have a phase difference of 360 / n degrees, and n can be a natural number. The internal clock generator (311) can output offset clock signals having opposite phases to the multiple sampler circuits (321_1, …, 321_n). The internal clock generator (311) can apply a first offset clock signal to a first sampler circuit where offset calibration is performed, and apply a second offset clock signal having a phase opposite to the first offset clock signal to a second sampler circuit. For example, the internal clock generator (311) can apply an offset clock signal with a phase of 0 degrees to the first sampler circuit while applying an offset clock signal with a phase of 180 degrees to the second sampler circuit. The offset calibration circuit (312) can perform offset calibration using a signal output from the first sampler circuit. The offset calibration circuit (312) can sequentially perform offset calibration for the plurality of sampler circuits (321_1, …, 321_n) in the order of the phase difference of each of the plurality of offset clock signals (OCK, …, OCKn) applied to each of the plurality of sampler circuits (321_1, …, 321_n).

[0064] Figure 4 is a schematic circuit diagram showing the sampler circuit of Figure 3.

[0065] Referring to FIG. 4, the sampler circuit (400) includes an amplifier (410) and an offset control circuit (420). The amplifier (410) can compare input signals (DATA, VREF) with each other and amplify the voltage difference between the signals (DATA, VREF). The amplifier (410) can output output signals (SAD1, SAD2) at nodes (N1, N2), respectively. The amplifier (410) can determine the voltage level of the output signals (SAD1, SAD2) based on the result of comparing the data (DATA) and the reference signal (VREF). In some embodiments, the reference signal (VREF) may be generated internally within the integrated circuit in which the sampler circuit (400) is implemented or provided from an external device (such as the integrated circuit in which the sampler circuit (400) is implemented or a separate electronic device, such as a memory controller).

[0066] The amplifier (410) may include transistors (P1, P2, P3, M1, M2). Data (DATA) may be input to the gate of transistor (P2). A reference signal (VREF) may be input to the gate of transistor (P3). A divided clock signal (DCK1) may be input to the gates of transistors (P1, M1, M2). A first operating voltage (VDDL) is applied to one end of transistor (P1), and the other end is connected to one end of transistors (P2, P3) at node (N0). Transistors (P2, M1) are connected in series between node (N0) and a power supply terminal where voltage (VSSL) is supplied, and the node to which transistors (P2, M1) are connected is the output node (N2). The transistors (P3, M2) are connected in series between the node (N0) and the power terminal where the voltage (VSSL) is supplied, and the node to which the transistors (P3, M2) are connected is the output node (N1).

[0067] When a divided clock signal (DCK1) is applied to transistors (P1, M1, M2), kickback noise may occur due to the parasitic capacitance of transistors (P1, M2, P3). Kickback noise affects the reference signal (VREF). Refer to Fig. 5 in this regard.

[0068] Figure 5 is a graph showing the waveforms of signals input to the amplifier of Figure 4.

[0069] At time t1, the divided clock signal (DCLK1) transitions from a low level (L) to a high level (H). Then, transistor (P1) is turned off and transistor (M2) is turned on. The drain voltage of the turned-off transistor (P1) (i.e., the source voltage of transistor (P3)) decreases. The drain voltage of the turned-on transistor (M2) (i.e., the drain voltage of the third transistor (P3)) decreases. When the source voltage of transistor (P3) decreases, the voltage of the reference signal (VREF) input to the gate of transistor (P3) decreases due to the parasitic capacitance between the gate and source of transistor (P3). Also, when the drain voltage of transistor (P3) decreases, the voltage of the reference signal (VREF) input to the gate of transistor (P3) decreases due to the parasitic capacitance between the gate and drain of transistor (P3). Due to this kickback noise, a voltage change of voltage (Vd1) may occur in the reference signal (VREF).

[0070] At time t2, the divided clock signal (DCLK1) transitions from a low level (H) to a high level (L). Then, transistor (P1) is turned on and transistor (M2) is turned off. The drain voltage of the turned-on transistor (P1) (i.e., the source voltage of transistor (P3)) increases. The drain voltage of the turned-off transistor (M2) (i.e., the drain voltage of the third transistor (P3)) increases. When the source voltage of transistor (P3) increases, the voltage of the reference signal (VREF) input to the gate of transistor (P3) increases due to the parasitic capacitance between the gate and source of transistor (P3). Also, when the drain voltage of transistor (P3) increases, the voltage of the reference signal (VREF) input to the gate of transistor (P3) increases due to the parasitic capacitance between the gate and drain of transistor (P3). Due to this kickback noise, a voltage change of voltage (Vd2) may occur in the reference signal (VREF).

[0071] Referring again to FIG. 4, the offset control circuit (420) can apply an offset control voltage according to the offset control signal (CAL1_L[1], CAL1_R[1], CAL1_L[0], CAL1_R[0]) to the output nodes (N1, N2) of the amplifier (410). The offset control voltage can be used, for example, to eliminate an offset voltage at the input of the individual amplifier caused by transistor mismatch and / or other causes within the individual amplifier.

[0072] The offset control circuit (420) may include transistors (P4, …, P11). Transistors (P4, P6) are connected in series between node (N0) and output node (N2). Transistors (P5, P7) are connected in series between node (N0) and output node (N1). Transistors (P8, P10) are connected in series between node (N0) and output node (N2). Transistors (P9, P11) are connected in series between node (N0) and output node (N1).

[0073] A reference signal (VREF) can be applied to the gates of transistors (P4, P5, P8, P9). An offset control signal (CAL1_L[1], CAL1_R[1], CAL1_L[0], CAL1_R[0]) can be applied to the gates of transistors (P4, P5, P8, P9), respectively. The current of transistors (P4, P5, P8, P9) is controlled differently by the offset control signals (CAL1_L[1], CAL1_R[1], CAL1_L[0], CAL1_R[0]), and this controlled current is combined with the current flowing through transistors (P2, P3) according to input signals (DATA, VREF) to control the voltage of nodes (N1, N2). Accordingly, when the offset voltage of the output nodes (N1, N2) of the amplifier (410) is adjusted by the offset adjustment circuit (420), and signal amplification is performed in the amplifier (410), an accurately amplified output signal (SAD1, SAD1B) can be output from the output nodes (N1, N2).

[0074] FIG. 6 is a timing diagram showing a clock signal applied to a sampler circuit according to one embodiment, and FIG. 7 is a diagram showing a clock signal applied during an offset calibration period of a sampler circuit according to one embodiment.

[0075] FIGS. 6 and 7 illustrate four offset clock signals (OCK1, …, OCK4) applied to four sampler circuits during the offset calibration period. The phase of each of the four offset clock signals (OCK1, …, OCK4) can be 360 / 4*0, …, 360 / 4*(3) (i.e., 0, 90, 180, 270). Although FIGS. 6 and 7 describe four sampler circuits, in the case of n sampler circuits, the phase of each of the n offset clock signals (OCK1, …, OCKn) can be 360 / n*0, …, 360 / n*(n-1), and the following description can be applied in the same way.

[0076] Referring to FIG. 6(a), the divided clock signals (DCK1, …, DCK4) applied to the sampler circuits while receiving data (DATA) can all toggle with a constant phase difference from each other. When the divided clock signal (DCK1) transitions from a high level (H) to a low level (L) at time t01, the data (DATA) can be sampled by the sampler circuit to which the divided clock signal (DCK1) is applied. As the divided clock signal (DCK1) transitions from a high level (H) to a low level (L) at time t01, kickback noise is generated, and a divided clock signal (DCK3) having an opposite phase can transition from a low level (L) to a high level (H) to generate kickback noise that cancels out the kickback noise caused by the divided clock signal (DCK1). At time t02, kickback noise is generated as the divided clock signal (DCK2) transitions from a high level (H) to a low level (L), and kickback noise can be generated by the divided clock signal (DCK4), which has an opposite phase, transitioning from a low level (L) to a high level (H) to cancel out the kickback noise caused by the divided clock signal (DCK2). At time t03, kickback noise is generated as the divided clock signal (DCK3) transitions from a high level (H) to a low level (L), and kickback noise can be generated by the divided clock signal (DCK1), which has an opposite phase, transitioning from a low level (L) to a high level (H) to cancel out the kickback noise caused by the divided clock signal (DCK3). At time t04, kickback noise is generated as the divided clock signal (DCK4) transitions from a high level (H) to a low level (L). However, kickback noise can be generated by the divided clock signal (DCK2), which has an opposite phase, transitioning from a low level (L) to a high level (H) to cancel out the kickback noise caused by the divided clock signal (DCK4). Therefore, while the sampler circuits are sampling data, the influence of kickback noise generated by the divided clock signals (DCK1, …, DCK4) on the reference signal is very small.

[0077] Referring to FIG. 6(b), during the offset calibration period, the offset clock signal (OCK1) input to the sampler circuit where offset calibration is performed toggles, while the offset clock signals (OCK2, …, OCK4) input to the remaining sampler circuits do not toggle and remain at a high level (H). As the offset clock signal (OCK1) transitions from a high level (H) to a low level (L) at time t11, kickback noise may occur. Since this kickback noise can affect the reference signal applied to the sampler circuit, it may cause the generation of an inaccurate offset adjustment signal.

[0078] Referring to FIG. 6(c), during the offset calibration period, the offset clock signal (OCK1) input to the sampler circuit where offset calibration is performed toggles, the offset clock signal (OCK3) input to another sampler circuit toggles, and the remaining offset clock signals (OCK2, OCK4) are not toggled and remain at a high level (H). At time t21, as the offset clock signal (OCK1) transitions from a high level (H) to a low level (L), kickback noise is generated. However, as the offset clock signal (OCK3), which has an opposite phase, transitions from a low level (L) to a high level (H), kickback noise can be generated to cancel out the kickback noise caused by the offset clock signal (OCK1). A receiver according to one embodiment can cancel out kickback noise caused by the offset clock signal (OCK1) by applying an offset clock signal (OCK3) having an opposite phase to the offset clock signal (OCK1) applied to a sampler circuit where an offset calibration operation is performed, to another sampler circuit. Therefore, just as when sampler circuits sample data, the influence of kickback noise generated by the offset clock signals (OCK1, …, OCK4) on the reference signal is very small. Accordingly, an offset adjustment signal that compensates for the offset voltage in the operation of receiving data (DATA) can be generated.

[0079] In some embodiments, as shown in FIG. 6(a), the offset clock signal (OCK1) input to the sampler circuit where offset calibration is performed during the offset calibration period toggles, and the remaining offset clock signals (OCK2, OCK3, OCK4) can also all toggle. Even in this case, just as when the sampler circuits sample data, the influence of kickback noise generated by the offset clock signals (OCK1, …, OCK4) on the reference signal is very small. Therefore, an offset adjustment signal that compensates for the offset voltage in the operation of receiving data (DATA) can be generated.

[0080] Referring to FIG. 7(a), offset calibration for sampler circuits (SA1), (SA2), (SA3), and (SA4) can be performed sequentially. For example, after offset calibration for sampler circuit (SA1) is performed, offset calibration for sampler circuit (SA2) can be performed by receiving an offset calibration clock signal (OCK2) that has a predetermined phase difference (e.g., 90 degrees) with respect to the offset calibration clock signal (OCK1) applied to sampler circuit (SA1). After offset calibration for sampler circuit (SA2) is performed, offset calibration for sampler circuit (SA3) can be performed by receiving an offset calibration clock signal (OCK3) that has a predetermined phase difference (e.g., 90 degrees) with respect to the offset calibration clock signal (OCK2) applied to sampler circuit (SA2). The sum of the phase difference between the offset calibration clock signal (OCK2) and the offset calibration clock signal (OCK1) and the phase difference between the offset calibration clock signal (OCK3) and the offset calibration clock signal (OCK2) can be 180 degrees. That is, offset calibration can be performed sequentially for a plurality of sampler circuits (SA1, …, SA4).

[0081] During the offset calibration period for the sampler circuit (SA1), the offset calibration clock (OCK1) applied to the sampler circuit (SA1) and the offset calibration clock (OCK3) with opposite phase to the offset calibration clock (OCK1) are toggled. Likewise, during the offset calibration period for the sampler circuit (SA2), the offset calibration clock (OCK2) applied to the sampler circuit (SA2) and the offset calibration clock (OCK4) with opposite phase to the offset calibration clock (OCK2) are toggled. During the offset calibration period for the sampler circuit (SA3), the offset calibration clock (OCK3) applied to the sampler circuit (SA3) and the offset calibration clock (OCK1) with opposite phase to the offset calibration clock (OCK3) are toggled. Likewise, during the offset calibration period for the sampler circuit (SA4), the offset calibration clock (OCK4) applied to the sampler circuit (SA4) and the offset calibration clock (OCK2) having a phase opposite to that of the offset calibration clock (OCK4) are toggled.

[0082] Referring to FIG. 7(b), when a pair of offset calibration clock signals (OCK1, OCK3 / OCK2, OCK4) with opposite phases are applied, offset calibration can be performed on a pair of sampler circuits (SA1, SA3 / SA2, SA4) to which the pair of offset calibration clock signals are applied. When a pair of offset calibration clock signals (OCK1, OCK3) is applied, offset calibration can be performed on the sampler circuit (SA1) and offset calibration can be performed on the sampler circuit (SA3). When a pair of offset calibration clock signals (OCK2, OCK4) is applied, offset calibration can be performed on the sampler circuit (SA2) and offset calibration can be performed on the sampler circuit (SA4).

[0083] That is, in FIG. 7(a), the offset calibration period for the sampler circuit (SA1), the offset calibration period for the sampler circuit (SA2), the offset calibration period for the sampler circuit (SA3), and the offset calibration period for the sampler circuit (SA4) are described as sequential; however, as in FIG. 7(b), offset calibration can be performed in the order of the offset calibration period for the sampler circuit (SA1), the offset calibration period for the sampler circuit (SA3), the offset calibration period for the sampler circuit (SA2), and the offset calibration period for the sampler circuit (SA4).

[0084] Although it was explained above that an offset calibration clock (OCK1) is applied to the sampler circuit (SA1) and an offset calibration clock (OCK3) with a phase opposite to that of the offset calibration clock (OCK1) is applied to the sampler circuit (SA3), the offset calibration clock (OCK3) may be applied to at least one of the other sampler circuits (SA2, SA3, SA4).

[0085] FIG. 8 is a block diagram showing a clock control circuit, a receiver, and a calibration circuit of a semiconductor memory device according to another embodiment.

[0086] Referring to FIG. 8, the clock control circuit (801) may include clock buffers (802, 802) and a phase splitter (803), the calibration circuit (810) may include an internal clock generator (811) and an offset calibration circuit (812), and the receiver (820) may include a plurality of sampler circuits (821_1, …, 821_n) and a plurality of latches (822_1, … 822_n).

[0087] The description of the clock buffers (801, 802), the plurality of sampler circuits (821_1, …, 821_n), the plurality of latches (822_1, …, 822_n), and the calibration circuit (810) is omitted as they are identical or similar to the description in FIG. 3.

[0088] The internal clock generator (811) can generate internal clock signals (SCK1, …, SCKn) during the offset calibration period and provide them to the phase splitter (803).

[0089] During the period of receiving data (DATA), the phase splitter (803) receives clock signals (ICK, ICKB) and data clock signals (WCK, WCKB) buffered in the clock buffer (801), and can generate divided clock signals (DCK1, …, DCKn). During the offset calibration period, the phase splitter (803) can generate offset clock signals (OCK1, …, OCKn) using internal clock signals (SCK1, …, SCKn). In some embodiments, during offset calibration, the phase splitter (803) can receive pairs of internal clock signals having opposite phases from an internal clock generator (811) on the signal path inside the phase splitter (803) and output offset clock signals (OCK1, …, OCKn). This will be described later with reference to FIGS. 10 and FIGS. 11. In some embodiments, the phase splitter (803) may apply offset clock signals (OCK1, …, OCKn) to the clock input terminals (PH1, …, PHn) of the sampler circuit (821). In some embodiments, during offset calibration, the phase splitter (803) may receive a pair of internal clock signals having opposite phases from the internal clock generator (811) at the input terminal of the phase splitter (803) and output offset clock signals (OCK1, …, OCKn). This will be described later with reference to FIG. 12.

[0090] FIG. 9 is a block diagram showing an example of a phase splitter according to another embodiment.

[0091] Referring to FIG. 9, the phase splitter (900) may include buffers (910, 920), a first divider (911), a second divider (921), and converters (930, 940).

[0092] The buffer (910) receives a data clock signal (WCK) and a complementary data clock signal (WCKB) and can differentially amplify the data clock signal (WCK) and the complementary data clock signal (WCKB). The first divider (911) can divide the output of the buffer (910) to generate a plurality of first clock signals (W01, …, W04) having different phases. For example, the first divider (911) can generate the first clock signals (W01, …, W04) by dividing the frequency of the output of the buffer (910) by 4. The output terminal of the first divider (911) can be connected to the input terminal of the first buffer (931). For example, each of the first clock signals (W01, …, W04) can be applied to each of the first buffers (931_1, …, 931_4).

[0093] The buffer (920) receives a data clock signal (WCK) and a complementary data clock signal (WCKB), and can differentially amplify the data clock signal (WCK) and the complementary data clock signal (WCKB).

[0094] The second divider (921) can divide the output of the buffer (920) to generate a plurality of second clock signals (W11, …, W14) having different phases. For example, the second divider (921) can generate the second clock signals (W11, …, W14) by dividing the frequency of the output of the second clock signals (W11, …, W14) by 4. The output terminal of the second divider (921) can be connected to the input terminal of the second buffer (932). For example, the second clock signal (W11) can be applied to the second buffer (931_1). The second clock signal (W12) can be applied to the second buffer (931_2). The second clock signal (W13) can be applied to the second buffer (931_3). The second clock signal (W14) can be applied to the second buffer (931_4).

[0095] In some embodiments, the buffer (910) and the first divider (911) may operate when a high-frequency data clock signal (WCK, WCKB) is applied, and the buffer (920) and the second divider (921) may operate when a low-frequency data clock signal (WCK, WCKB) is applied. The receiver may operate by activating the buffer (910) when the frequency of the data clock signal (WCK) is relatively high, so that the buffer (910) differentially amplifies the data clock signal (WCK) and the complementary data clock signal (WCKB) to receive the data clock signal (WCK) and the complementary data clock signal (WCKB). The buffer (910) may include a Current Mode Logic (CML) amplifier for amplifying a clock signal having a high frequency. The buffer (920) may include a Complementary Metal-Oxide Semiconductor (CMOS) amplifier for amplifying an accurate signal, although the operating speed is relatively slow.

[0096] The compensation circuit (922) can provide compensation signals (CP1, CP1B) to the second divider (921). If the voltage applied to the gate of some of the transistors included in the second divider (921), which can operate in a high voltage level region, remains at a constant voltage level, degradation due to the Bias Temperature Instability (BTI) phenomenon may occur. The compensation circuit (922) can prevent the degradation of the transistors and increase the chip life time and reliability of operation by changing the voltage level of the gate of some transistors using the compensation signals (CP1, CP1B).

[0097] The converter (930) may include a plurality of first buffers (931_1, …, 931_4) and a plurality of second buffers (932_1, …, 932_4). The converter (930) may amplify a first clock signal (W01, …, W04) and output it as divided clock signals (DCK1, …, DCK4). For example, a pair of first buffers (931_1) and second buffers (932_1) may detect and amplify the phase of the first clock signal (W01) relative to the phase of the first clock signal (W03) to generate a divided clock signal (DCK1). The pair of first buffer (931_1) and second buffer (932_1) can generate a divided clock signal (DCK1) that is substantially identical in phase to the first clock signal (W01) and has a larger amplitude than the first clock signal (W01).

[0098] A plurality of first buffers (931_1, …, 931_4) can each receive two first clock signals (W01, …, W04) swinging at a CML level and output them as a single signal (BCK1, …, BCK4) swinging at a CML level. Each of the plurality of first buffers (931_1, …, 931_4) can receive two of the first clock signals (W01, …, W04) output from the first divider (911), buffer them, and output them as a single signal (BCK1, …, BCK4). For example, the first buffer (931_1) can receive first clock signals (W01, W03) having opposite phases and output a single signal (BCK1) swinging at a CML level. The first buffer (931_2) can receive first clock signals (W02, W04) having opposite phases and output a single signal (BCK2) that swings to a CML level. The first buffer (931_3) can also receive first clock signals (W03, W01) having opposite phases and output a single signal (BCK3) that swings to a CML level. The first buffer (931_4) can also receive first clock signals (W04, W02) having opposite phases and output a single signal (BCK4) that swings to a CML level. Each of the multiple second buffers (932_1, …, 932_4) can amplify and output a single signal (BCK1, …, BCK4) swinging at a CML level output from the multiple first buffers (931_1, …, 931_4) into a single divided clock signal (DCK1, …, DCK4) swinging at a CMOS level.

[0099] The compensation circuit (933) can provide compensation signals (CP2, CP2B) to the second buffer (932). If the voltage applied to the gate of some of the transistors included in the second buffer (932), which can operate in a high voltage level region, remains at a constant voltage level, degradation due to the BTI phenomenon may occur. The compensation circuit (933) can change the voltage level of the gate of some transistors using the compensation signals (CP2, CP2B).

[0100] In some embodiments, the compensation circuit (933) may apply an offset clock signal to the output terminal of the converter (930), i.e., the clock input terminal (PH1, …, PH4) of the sampler circuit, during offset calibration. This will be explained together with reference to FIG. 10.

[0101] FIG. 10 is a diagram illustrating the connection state of a compensation circuit of a buffer that outputs a clock signal during the offset calibration period of a sampler circuit according to another embodiment.

[0102] Referring to FIG. 10, the output terminal of the second buffer (1010_1) can be connected to the clock input terminal (PH1) of the sampler circuit through a path having zero or more inverters (1030). The output terminal of the compensation circuit (1020) can also be connected to the clock input terminal (PH1) of the sampler circuit through a path having zero or more inverters (1030). The compensation circuit (1020) can receive an internal clock signal (SCK1), buffer it, and output a compensation signal (CP). The compensation signal (CP) can be provided to the output terminal of the second buffer (1010_1) and output to the clock input terminal (PH1) of the sampler circuit as an offset clock signal (OCK1). Likewise, the compensation circuit (1021) can receive an internal clock signal (SCK3), buffer it, and output a compensation signal (CPB). The compensation signal (CPB) is provided to the output terminal of the second buffer (1010_3) and can be output to the clock input terminal (PH3) of the sampler circuit as an offset clock signal (OCK3). Since the internal clock signal (SCK1) and the internal clock signal (SCK3) have opposite phases to each other, the offset clock signal (OCK1) and the offset clock signal (OCK3) can also have opposite phases to each other. According to this embodiment, an offset clock signal (OCK1, OCK3) with opposite phases can be provided by using a signal path between the second buffer (1010_1, 1010_3) and the clock input terminal (PH1, PH3) of the sampler circuit, which are connected to each other to provide a divided clock signal (DCK1, DCK3).

[0103] In some embodiments, the compensation circuit (922) may output an offset clock signal by applying compensation signals (CP1, CP1B) to the output terminal of the second divider (921) during offset calibration. This will be explained together with reference to FIG. 11.

[0104] FIG. 11 is a diagram illustrating the connection state of a compensation circuit of a CMOS divider that outputs a clock signal during the offset calibration period of a sampler circuit according to another embodiment.

[0105] Referring to FIG. 11, the output terminal of the second divider (1110) can be connected to the input terminal of the second buffers (1140_1, 1140_3) through a path having zero or more inverters (1130, 1131). The output terminal of the second buffer (1140_1) can be connected to the clock input terminal (PH1) of the sampler circuit through a path having zero or more inverters (1150). The output terminal of the second buffer (1140_3) can be connected to the clock input terminal (PH3) of the sampler circuit through a path having zero or more inverters (1151). The output terminal of the compensation circuit (1120) can also be connected to the input terminal of the second buffer (1140_1) through a path having zero or more inverters (1130). The compensation circuit (1120) receives an internal clock signal (SCK1), buffers it, and outputs a compensation signal (CP) to the input terminal of the second buffer (1140_1). The second buffer (1140_1) amplifies the input compensation signal (CP) and outputs it as an offset clock signal (OCK1) to the clock input terminal (PH1) of the sampler circuit.

[0106] Likewise, the compensation circuit (1121) can receive the internal clock signal (SCK3), buffer it, and output a compensation signal (CPB) to the input terminal of the second buffer (1140_3). The second buffer (1140_3) can amplify the input compensation signal (CPB) and output it as an offset clock signal (OCK3) to the clock input terminal (PH3) of the sampler circuit. Since the internal clock signal (SCK1) and the internal clock signal (SCK3) have opposite phases, the offset clock signal (OCK1) and the offset clock signal (OCK3) can also have opposite phases. According to this embodiment, an offset clock signal of opposite phase (OCK1, OCK3) can be provided by using a signal path between a second divider (1110), a second buffer (1140_1, 1140_3) and a clock input terminal (PH1, PH3) of a sampler circuit that are connected to each other to provide a divided clock signal (DCK1, DCK3).

[0107] FIG. 12 is a diagram illustrating a phase splitter that outputs a clock signal during the offset calibration period of a sampler circuit according to another embodiment.

[0108] Referring to FIG. 12, the input terminal of the buffer (1220) may receive internal clock signals (SCK, SCKB). The internal clock signals (SCK, SCKB) may have opposite phases. Then, the output signal of the buffer (1220) may be provided to the second divider (1221) to be divided and output as an offset clock signal (OCK1, …, OCK4) through the second buffer (1232). Among the offset clock signals (OCK1, …, OCK4), a pair of offset clock signals (OCK1, OCK3 / OCK2, OCK4) having opposite phases may be applied to the clock input terminal (PH1, PH3 / PH2, PH4) of the sampler circuit. According to this embodiment, an offset clock signal of opposite phase (OCK1, OCK3 / OCK2, OCK4) can be provided by using the signal path of a phase splitter (1200) connected to each other to provide a divided clock signal (DCK1, DCK3).

[0109] FIG. 13 is an exemplary block diagram showing a computer system according to one embodiment.

[0110] Referring to FIG. 13, the computing system (1300) includes a processor (1310), memory (1320), memory controller (1330), storage device (1340), communication interface (1350), and bus (1360). The computing system (1300) may further include other general-purpose components.

[0111] The processor (1310) controls the overall operation of each component of the computing system (1300). The processor (1310) may be implemented as at least one of various processing units, such as a CPU (central processing unit), an AP (application processor), and a GPU (graphic processing unit).

[0112] The memory (1320) stores various data and commands. The memory (1320) may be implemented as a memory device described with reference to FIGS. 1 through 12. The memory controller (1330) controls the transfer of data or commands to and from the memory (1320). The memory controller (1330) may be implemented as a memory controller described with reference to FIGS. 1 through 12. In some embodiments, the memory controller (1330) may be provided as a separate chip from the processor (1310). In some embodiments, the memory controller (1330) may be provided as an internal component of the processor (1310).

[0113] The storage device (1340) stores programs and data non-temporarily. In some embodiments, the storage device (1340) may be implemented as non-volatile memory. The communication interface (1350) supports wired and wireless internet communication of the computing system (1300). Additionally, the communication interface (1350) may support various communication methods other than internet communication. The bus (1360) provides communication functions between components of the computing system (1300). The bus (1360) may include at least one type of bus according to the communication protocol between components.

[0114] In some embodiments, each component or combination of two or more components described with reference to FIGS. 1 to 12 may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application-specific integrated circuit (ASIC), etc.

[0115] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims

Claim 1 A semiconductor device comprising: a plurality of sampler circuits that receive a plurality of offset clock signals or a plurality of divided clock signals and sample a data signal in response to each of the plurality of divided clock signals; and a calibration circuit that applies a first offset clock signal among the plurality of offset clock signals to a first sampler circuit among the plurality of sampler circuits and applies a second offset clock signal having a phase opposite to the first offset clock signal among the plurality of offset clock signals to a second sampler circuit among the plurality of sampler circuits, and generates a first offset adjustment signal that adjusts the offset of the first sampler circuit based on the output of the first sampler circuit output in response to the first offset clock signal. Claim 2 A semiconductor device according to claim 1, wherein the calibration circuit comprises a clock generator that generates the first offset clock signal and the second offset clock signal. Claim 3 A semiconductor device according to claim 1, further comprising a phase splitter that divides a data clock signal received in synchronization with the data signal to generate the plurality of divided clock signals. Claim 4 A semiconductor device according to paragraph 3, wherein the calibration circuit includes a clock generator that generates a first internal clock signal and a second internal clock signal, and the phase splitter buffers the first internal clock signal to generate a first clock signal and buffers the second internal clock signal to generate a second clock signal. Claim 5 In claim 4, the phase splitter comprises a divider that divides the data clock signal input to an input terminal by a constant phase difference to generate a plurality of first clock signals and outputs the plurality of first clock signals to an output terminal, and a buffer that buffers the plurality of first clock signals input to an input terminal and outputs them to an output terminal. Claim 6 A semiconductor device according to claim 5, wherein the phase splitter further comprises a compensation circuit that applies a degradation compensation signal to the gate of at least one of the transistors included in the divider, and the compensation circuit buffers the first internal clock signal and the second internal clock signal and applies them to the output terminal of the divider as the first offset clock signal and the second offset clock signal. Claim 7 A semiconductor device according to claim 5, wherein the phase splitter further comprises a compensation circuit that applies a degradation compensation signal to the gate of at least one of the transistors included in the buffer, and the compensation circuit buffers the first internal clock signal and the second internal clock signal and applies them to the output terminal of the buffer as the first offset clock signal and the second offset clock signal. Claim 8 A semiconductor device according to paragraph 3, wherein the calibration circuit includes a clock generator that generates an internal clock signal, and the phase splitter divides the internal clock signal to generate the first offset clock signal and the second offset clock signal. Claim 9 A semiconductor device according to claim 1, wherein each of the plurality of sampler circuits comprises an amplifier that amplifies and outputs the voltage difference between the data signal and the reference signal, and an offset control circuit that applies a voltage to the output terminal of the amplifier to control the offset of the amplifier according to an offset control signal when the data signal is input to the amplifier. Claim 10 A semiconductor device according to claim 9, wherein the reference signal is applied in common to the amplifier of the first sampler circuit and the amplifier of the second sampler circuit. Claim 11 A semiconductor device according to claim 9, wherein when the first offset clock signal is applied to the amplifier of the first sampler circuit and the second offset clock signal is applied to the amplifier of the second sampler circuit, the calibration circuit generates the first offset adjustment signal. Claim 12 A semiconductor device according to claim 11, wherein when the first offset clock signal is applied to the amplifier of the first sampler circuit and the second offset clock signal is applied to the amplifier of the second sampler circuit, the calibration circuit generates a second offset adjustment signal for adjusting the offset of the amplifier of the second sampler circuit at a different period from the first offset adjustment signal. Claim 13 A semiconductor device according to claim 1, wherein the calibration circuit, after generating the first offset adjustment signal, applies a third offset clock signal among the plurality of offset clock signals to a third sampler circuit among the plurality of sampler circuits, generates a third offset adjustment signal that adjusts the offset of the third sampler circuit based on the output of the third sampler circuit output in response to the third offset clock signal, and the sum of the phase difference between the third offset clock signal and the first offset clock signal and the phase difference between the second offset clock signal and the third offset clock signal is 180 degrees. Claim 14 A semiconductor device according to claim 1, wherein if the plurality of sampler circuits are n, the plurality of offset clock signals have a phase difference of 360 / n degrees relative to each other, and n is a natural number, and the calibration circuit sequentially performs offset calibration for the plurality of sampler circuits in the order of the phase difference of each of the plurality of offset clock signals applied to each of the plurality of sampler circuits. Claim 15 A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a clock control circuit that receives a data clock signal and divides the data clock signal to generate a plurality of divided clock signals; a plurality of sampler circuits that receive a data signal and sample the data signal in synchronization with the plurality of divided clock signals; a sense amplifier that writes the sampled data signal to the plurality of memory cells; and a calibration circuit that applies a plurality of offset clock signals having opposite phases to the plurality of sampler circuits and performs offset calibration of the plurality of sampler circuits based on the output of the plurality of sampler circuits generated in synchronization with the plurality of offset clock signals. Claim 16 A semiconductor memory device according to claim 15, wherein the clock control circuit further receives a system clock signal, buffers the system clock signal and provides it to the calibration circuit, and the calibration circuit generates the plurality of offset clock signals based on the buffered system clock signal. Claim 17 A semiconductor memory device according to claim 15, wherein the output terminal of the clock control circuit is connected to the clock input terminal of the plurality of sampler circuits, and the calibration circuit applies the plurality of offset clock signals to the clock input terminal of the plurality of sampler circuits through the output terminal of the clock control circuit. Claim 18 A semiconductor memory device according to claim 17, wherein the clock control circuit further receives a system clock signal, buffers the system clock signal and provides it to the calibration circuit, and the calibration circuit provides the buffered system clock signal to the clock control circuit so that the clock control circuit outputs the plurality of offset clock signals to the output terminal of the clock control circuit. Claim 19 A semiconductor memory device according to claim 15, wherein the calibration circuit sequentially performs offset calibration of the first sampler circuit and the second sampler circuit while applying a first offset clock signal among the plurality of offset clock signals to the first sampler circuit among the plurality of sampler circuits and applying a second offset clock signal having a phase opposite to the first offset clock signal among the plurality of offset clock signals to the second sampler circuit. Claim 20 A semiconductor memory device according to claim 15, wherein if the plurality of sampler circuits are n, the plurality of offset clock signals have a phase difference of 360 / n degrees relative to each other, and n is a natural number, and the calibration circuit sequentially performs offset calibration for the plurality of sampler circuits in the order of the phase difference of each of the plurality of offset clock signals applied to each of the plurality of sampler circuits. Claim 21 An offset calibration method comprising: applying a first voltage and a second voltage to two input terminals of a first amplifier and two input terminals of a second amplifier different from the first amplifier; applying a first clock signal to a clock input terminal of the first amplifier and applying a second clock signal having an opposite phase to the first clock signal to a clock input terminal of the second amplifier; and generating a first offset adjustment signal that adjusts the offset of the first amplifier by performing offset calibration of the first amplifier using a voltage output from an output terminal of the first amplifier while applying the first clock signal and the second clock signal. Claim 22 An offset calibration method according to claim 21, further comprising the step of generating a second offset adjustment signal that adjusts the offset of the second amplifier by performing offset calibration of the second amplifier using a voltage output from the output terminal of the second amplifier while applying the first clock signal and the second clock signal. Claim 23 An offset calibration method according to claim 21, further comprising the step of applying the first offset adjustment signal to a first offset adjustment circuit connected to two output terminals of the first amplifier to adjust the offset of the first amplifier.

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