Memory system and operating method thereof

Abstract

The memory system includes a non-volatile memory device; and a lightsame manager configured to perform a lightsame operation on the non-volatile memory device, wherein the lightsame manager merges the first lightsame operation and the second lightsame operation by comparing first operation information of the first lightsame operation and second operation information of the second lightsame operation.

Description

Technology Field

[0001] The present invention relates to a memory system, and more specifically, to a memory system including a non-volatile memory device. Background Technology

[0002] The memory system may be configured to store data provided by the host device in response to a write request from the host device. Additionally, the memory system may be configured to provide the stored data to the host device in response to a read request from the host device. The host device is an electronic device capable of processing data and may include a computer, a digital camera, or a mobile phone. The memory system may operate by being embedded in the host device or by being manufactured in a detachable form and connected to the host device. The problem to be solved

[0003] An embodiment of the present invention is to provide a memory system that efficiently performs a light-same operation and a method of operating the same. means of solving the problem

[0004] A memory system according to an embodiment of the present invention includes a non-volatile memory device; and a lightsame manager configured to perform a lightsame operation on the non-volatile memory device, wherein the lightsame manager can merge the first lightsame operation and the second lightsame operation by comparing first operation information of a first lightsame operation and second operation information of a second lightsame operation.

[0005] A method of operating a memory system according to an embodiment of the present invention may include a step of comparing first operation information of a first light-same operation and second operation information of a second light-same operation; and a step of determining whether the first light-same operation and the second light-same operation can be merged according to the comparison result.

[0006] A memory system according to an embodiment of the present invention may include a non-volatile memory device; a LightSame manager configured to perform a LightSame operation on the non-volatile memory device; and an encryption unit configured to encrypt duplicate patterns corresponding to consecutive logical addresses into encrypted patterns at once when the LightSame operation is performed. Effects of the invention

[0007] A memory system and a method of operation according to an embodiment of the present invention can efficiently perform light-same operations. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram illustrating a memory system according to an embodiment of the present invention. FIG. 2 is a drawing illustrating a method of performing a lightsame operation according to an embodiment of the present invention. FIG. 3 is a diagram illustrating the encryption operation of the encryption unit according to an embodiment of the present invention. FIGS. 4a to 4c are drawings illustrating a method for a Lightsame Manager to merge Lightsame actions according to an embodiment of the present invention, FIGS. 5a to 5c are drawings illustrating cases in which a Lightsame Manager cannot merge Lightsame actions according to an embodiment of the present invention, FIG. 6 is a flowchart illustrating a method for a lightsame manager to perform a lightsame operation according to an embodiment of the present invention. FIG. 7 is a flowchart illustrating a method for a Lightsame Manager to merge Lightsame actions according to an embodiment of the present invention. FIG. 8 is a drawing exemplarily illustrating a data processing system including a solid-state drive (SSD) according to an embodiment of the present invention, FIG. 9 is a drawing exemplarily illustrating a data processing system including a memory system according to an embodiment of the present invention, FIG. 10 is a drawing exemplarily illustrating a data processing system including a memory system according to an embodiment of the present invention, FIG. 11 is a drawing exemplarily illustrating a network system including a memory system according to an embodiment of the present invention, FIG. 12 is a block diagram exemplarily illustrating a non-volatile memory device included in a memory system according to an embodiment of the present invention. Specific details for implementing the invention

[0009] The advantages and features of the present invention and the methods for achieving them will be explained in detail through the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. These embodiments are provided merely to explain in detail enough to enable those skilled in the art to easily implement the technical concept of the present invention.

[0010] In the drawings, embodiments of the invention are not limited to the specific forms depicted and are exaggerated for clarity. Specific terms have been used herein, but are used for the purpose of describing the invention and are not intended to limit the meaning or the scope of the invention as defined in the claims.

[0011] In this specification, the expression "and / or" is used to mean including at least one of the components listed before and after it. Additionally, the expression "connected / combined" is used to mean being directly connected to another component or being indirectly connected through another component. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Furthermore, components, steps, actions, and elements referred to as "include" or "comprising" in this specification signify the presence or addition of one or more other components, steps, actions, and elements.

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0013] FIG. 1 is a block diagram illustrating a memory system (100) according to an embodiment of the present invention.

[0014] The memory system (100) may be configured to store data provided from a host device in response to a write request from an external host device. Additionally, the memory system (100) may be configured to provide the stored data to the host device in response to a read request from the host device.

[0015] The memory system (100) may be composed of PCMCIA (Personal Computer Memory Card International Association) cards, CF (Compact Flash) cards, smart media cards, memory sticks, various multimedia cards (MMC, eMMC, RS-MMC, MMC-micro), SD (Secure Digital) cards (SD, Mini-SD, Micro-SD), UFS (Universal Flash Storage), or SSD (Solid State Drive).

[0016] The memory system (100) may include a controller (110) and a non-volatile memory device (120).

[0017] The controller (110) can control the general operations of the memory system (100). The controller (110) can control the non-volatile memory device (120) to perform foreground operations according to instructions from the host device. Foreground operations may include writing data to the non-volatile memory device (120) and reading data from the non-volatile memory device (120) according to instructions from the host device, namely, write requests and read requests.

[0018] Additionally, the controller (110) can control the non-volatile memory device (120) to perform necessary background operations internally independently of the host device. Background operations may include wear leveling operations, garbage collection operations, erase operations, read reclaim operations, and refresh operations for the non-volatile memory device (120). Background operations may include writing data to the non-volatile memory device (120) and reading data from the non-volatile memory device (120), similar to foreground operations.

[0019] The controller (110) can perform a lightsame operation. For example, the controller (110) can perform a lightsame operation in response to a lightsame command transmitted from a host device. The lightsame command may be a command in which the host device instructs the controller (110) to redundantly store a specific pattern for consecutive logical addresses. The pattern may be a unit of data corresponding to a single logical address.

[0020] The controller (110) may include a light signature manager (111), an encryption unit (112), and a light unit (113).

[0021] The lightsame manager (111) can generate operation information in response to a lightsame command. The operation information may include pattern data and information about consecutive logical addresses for which a lightsame operation is to be performed. For example, the operation information may include pattern data, a starting logical address of consecutive logical addresses, and the number of consecutive logical addresses.

[0022] The Lightsame Manager (111) may include an Action Information Memory (INFM) in which action information is stored. The Action Information Memory (INFM) may store action information for one or more Lightsame actions that have not yet been performed. The Action Information Memory (INFM) may be managed in a queue structure.

[0023] The lightsame manager (111) can merge the first lightsame operation and the second lightsame operation by comparing the first operation information of the first lightsame operation and the second operation information of the second lightsame operation by referring to the operation information memory (INFM).

[0024] According to an embodiment, the lightsame manager (111) can merge the first lightsame operation and the second lightsame operation when the pattern data of the first operation information and the pattern data of the second operation information are identical and the logical addresses formed by merging the logical addresses of the first operation information and the logical addresses of the second operation information are consecutive. On the other hand, the lightsame manager (111) can determine that the first lightsame operation and the second lightsame operation cannot be merged when the pattern data of the first operation information and the pattern data of the second operation information are not identical or when the logical addresses formed by merging the logical addresses of the first operation information and the logical addresses of the second operation information are not consecutive.

[0025] The lightsame manager (111) can generate updated action information when merging the first lightsame action and the second lightsame action. The lightsame manager (111) can update the faster of the first action information of the first lightsame action and the second action information of the second lightsame action in the action information memory (INFM) with the updated action information and remove the other slower one.

[0026] According to an embodiment, the lightsame manager (111) stores operation information in the operation information memory (INFM) in response to a lightsame command, and then transmits the response to the lightsame command to the host device even before the corresponding lightsame operation is completed.

[0027] The light-same manager (111) can control the encryption unit (112) and the light unit (113) to perform light-same operations.

[0028] The encryption unit (112) can encrypt a pattern corresponding to a logical address based on the logical address and generate an encrypted pattern. The encrypted pattern may include error check data such as parity data and CRC.

[0029] In particular, the encryption unit (112) can encrypt duplicate patterns corresponding to consecutive logical addresses into patterns encrypted based on those logical addresses all at once.

[0030] The encryption unit (112) may include, for example, an AES (Advanced Encryption Standard) engine.

[0031] The light unit (113) can store patterns encrypted by the encryption unit (112) in a non-volatile memory device (120).

[0032] According to an embodiment, the light-same manager (111) can control the encryption operation of the encryption unit (112) and the writing operation of the writing unit (113) to be performed in parallel. Specifically, the light-same manager (111) can control the encryption unit (112) to generate subsequent encrypted patterns while the writing unit (113) stores the encrypted pattern in a non-volatile memory device (120).

[0033] The non-volatile memory device (120) can store data transmitted from the controller (110) under the control of the controller (110), and read the stored data to transmit it to the controller (110).

[0034] The non-volatile memory device (120) may include a flash memory device such as NAND Flash or NOR Flash, FeRAM (Ferroelectrics Random Access Memory), PCRAM (Phase-Change Random Access Memory), MRAM (Magnetic Random Access Memory), or ReRAM (Resistive Random Access Memory).

[0035] The non-volatile memory device (120) may include one or more planes, one or more memory chips, one or more memory dies, or one or more memory packages.

[0036] FIG. 2 is a diagram illustrating a method in which a lightsame operation is performed according to an embodiment of the present invention.

[0037] Referring to FIG. 2, the controller (110) can receive a lightsame command (WSCMD) from the host device (10). The lightsame command (WSCMD) may include pattern data (PTD), a start logical address, and a count.

[0038] The Lightsame Manager (111) can store operation information (INF) in operation information memory (INFM) in response to a Lightsame Command (WSCMD). The operation information (INF) may include pattern data (PTD), a start logical address (SLA), and a count (CNT). After storing the operation information (INF) in the operation information memory (INFM), the Lightsame Manager (111) can immediately send a response (RSP) to the host device (10) even before the Lightsame operation is completed. The host device (10) can determine that the Lightsame operation is completed based on the response (RSP) sent from the Lightsame Manager (111). That is, by sending a fast response (RSP) to the host device (10) when the reliability of the Lightsame operation is guaranteed, the response speed of the Lightsame operation to the host device (10) can be improved.

[0039] The operation information (INF) stored in the operation information memory (INFM) can be protected even if a sudden power off occurs. For example, when a sudden power off occurs, the Lightsame Manager (111) can transfer the operation information (INF) stored in the operation information memory (INFM) to a non-volatile memory device (120) using backup power. As another example, the operation information memory (INFM) can be composed of non-volatile memory.

[0040] The light-same manager (111) can perform a light-same operation corresponding to the operation information (INF) immediately after storing the operation information (INF). Alternatively, the light-same manager (111) can perform a light-same operation as a background operation during idle time. Alternatively, the light-same manager (111) can perform a light-same operation according to various conditions, such as a waiting time and the number of operation information (INF) stored in the operation information memory (INFM).

[0041] The LightSame Manager (111) can control the encryption unit (112) and the light unit (113) to perform a LightSame operation based on operation information (INF). Specifically, the LightSame Manager (111) can generate a pattern (PT) having a predetermined size based on pattern data (PTD). The predetermined size of the pattern (PT) may be, for example, 512 bytes. The predetermined size may be, for example, the size of data corresponding to a single logical address recognized by the host device (10). When the pattern data (PTD) is transmitted with a predetermined size, the LightSame Manager (111) can use the pattern data (PTD) immediately as a pattern (PT). When the pattern data (PTD) is smaller than the predetermined size, the LightSame Manager (111) can generate a pattern (PT) of the predetermined size by duplicating the pattern data (PTD).

[0042] The light signature manager (111) can control the encryption unit (112) to generate encrypted data (ENDT) based on a number (CNT) of consecutive logical addresses starting from a pattern (PT) and a starting logical address (SLA).

[0043] And, the LightSame manager (111) can control the write unit (113) to store encrypted data (ENDT) in a memory area (MR1) of a non-volatile memory device (120). The physical address of the memory area (MR1) can be mapped to a number (CNT) of consecutive logical addresses starting from the start logical address (SLA). When the encrypted data (ENDT) is stored in the memory area (MR1), the LightSame operation can be terminated.

[0044] Meanwhile, the LightSame Manager (111) can control the encryption unit (112) and the light unit (113) to operate in parallel. Specifically, the LightSame Manager (111) can control the encryption unit (112) to generate subsequent encrypted data (ENDT) while the light unit (113) stores the encrypted data (ENDT) in the non-volatile memory device (120). That is, the LightSame Manager (111) can further improve the performance of the LightSame operation by controlling the encryption unit (112) and the light unit (113) asynchronously.

[0045] According to an embodiment, the light-same manager (111) can store a pattern (PT) instead of pattern data (PTD) as operation information (INF).

[0046] FIG. 3 is a diagram illustrating the encryption operation of the encryption unit (112) according to an embodiment of the present invention.

[0047] Referring to FIG. 3, the encryption unit (112) can generate encrypted data (ENDT) by performing an encryption operation on duplicate patterns (PT).

[0048] The encryption unit (112) may receive a pattern (PT), a starting logical address (SLA), and a count (CNT) from the light signature manager (111) to generate encrypted data (ENDT). The count (CNT) may be the number of times the pattern (PT) must be duplicated. In other words, the count (CNT) may be the number of consecutive logical addresses (LA) starting from the starting logical address (SLA).

[0049] Accordingly, when the LightSame Manager (111) receives a start logic address (SLA) "1" and a count (CNT) "10", it can determine a series of logic addresses (LA) from "1" to "10". The logic addresses (LA) can each correspond to duplicate patterns (PT).

[0050] According to an embodiment, the encryption unit (112) may receive a pattern (PT) and consecutive logical addresses (LA) from the light signature manager (111).

[0051] The encryption unit (112) can generate encrypted patterns (EPT1~EPT10) by encrypting each of the duplicate patterns (PT) using logical addresses (LA). The encryption unit (112) can encrypt each pattern (PT) using a corresponding logical address (LA). For example, the encryption unit (112) can generate an encrypted pattern (EPT1) by encrypting the pattern (PT) using a starting logical address (SLA) "1". At this time, the encryption unit (112) can generate different encrypted patterns even if the pattern (PT) is the same, if the logical address (LA) is different. That is, the encrypted patterns (EPT1~EPT10) can have different values.

[0052] Each of the encrypted patterns (EPT1 to EPT10) may include parity data and error check data such as CRC.

[0053] Meanwhile, the encryption unit (112) may show better performance when encrypting data at once than when dividing large-sized data and encrypting it multiple times. Specifically, a method of performing encryption operations on consecutive logical addresses and outputting encrypted patterns together may show better performance than a method of performing an encryption operation on one logical address and outputting an encrypted pattern, and then performing an encryption operation on the next logical address and outputting an encrypted pattern.

[0054] Meanwhile, the encryption unit (112) can perform encryption operations only on consecutive logical addresses at once due to the characteristics of the hardware.

[0055] According to an embodiment, the encryption unit (112) can perform encryption operations on up to a predetermined maximum number of logical addresses at once. Accordingly, when the light-same operation is for more than a predetermined maximum number of logical addresses, the encryption unit (112) can repeatedly perform encryption operations by dividing consecutive logical addresses into a predetermined maximum number.

[0056] Accordingly, by utilizing the characteristics of the encryption unit (112), the Lightsame manager (111) can perform Lightsame operations more efficiently by merging different Lightsame operations as described below.

[0057] FIGS. 4a to 4c are drawings illustrating a method in which a Lightsame Manager (111) merges Lightsame actions according to an embodiment of the present invention. FIGS. 4a to 4c illustrate examples in which different new action information (NINF1 to NINF3) are merged for the same standby action information (WINF).

[0058] Referring to FIG. 4a, the standby operation information (WINF) is stored in the operation information memory (INFM) prior to the standby operation and may be for a lightsame operation that has not yet been performed (hereinafter, standby lightsame operation).

[0059] The lightsame manager (111) can store new action information (NINF1) for a new lightsame action in the action information memory (INFM) in response to a lightsame command. The lightsame manager (111) can compare the new action information (NINF1) with the standby action information (WINF) to determine that the new lightsame action can be merged into the standby lightsame action.

[0060] Specifically, the wait operation information (WINF) may include a pattern (PT1), a start logical address (SLA) "1", and a count (CNT) "2". Thus, the wait operation information (WINF) may be for the logical addresses (LA) of "1" and "2".

[0061] New operation information (NINF1) may include a pattern (PT1), a start logical address (SLA) "3", and a count (CNT) "3". Thus, new operation information (NINF1) may be for logical addresses (LA) from "3" to "5".

[0062] The Lightsame Manager (111) can determine that the pattern (PT1) of the standby operation information (WINF) and the new operation information (NINF1) is identical. Additionally, the Lightsame Manager (111) can determine that the logical addresses (LA) of the standby operation information (WINF) and the logical addresses (LA) of the new operation information (NINF1) are merged into logical addresses (LA) from "1" to "5" (i.e., elements of the union of the logical addresses of the standby operation information (WINF) and the logical addresses (LA) of the new operation information (NINF1)).

[0063] Accordingly, the Lightsame Manager (111) can determine that the standby Lightsame operation and the new Lightsame operation are mergeable and can update the standby operation information (WINF). The updated standby operation information (UINF1) may include the same pattern (PT1), include the first logical address (LA) "1" among the merged logical addresses as the starting logical address (SLA), and include the number of merged logical addresses "5" as the count (CNT).

[0064] Referring to FIG. 4b, while standby action information (WINF) is stored in the action information memory (INFM), the lightsame manager (111) can store new action information (NINF2) for a new lightsame action in the action information memory (INFM) in response to a lightsame command. The lightsame manager (111) can compare the new action information (NINF2) with the standby action information (WINF) to determine that the new lightsame action can be merged into the standby lightsame action.

[0065] Specifically, the new operation information (NINF2) may include a pattern (PT1), a start logical address (SLA) "2", and a count (CNT) "3". Thus, the new operation information (NINF2) may be for logical addresses (LA) from "2" to "4".

[0066] The Lightsame Manager (111) can determine that the pattern (PT1) of the standby operation information (WINF) and the new operation information (NINF2) is identical. Additionally, the Lightsame Manager (111) can determine that the logical addresses (LA) from "1" to "4" formed by merging the logical addresses (LA) of the standby operation information (WINF) and the logical addresses (LA) of the new operation information (NINF2) are continuous. That is, the Lightsame Manager (111) can determine that the merged logical addresses are continuous even when at least some of the logical addresses (LA) of the standby operation information (WINF) and the logical addresses (LA) of the new operation information (NINF2) overlap.

[0067] Accordingly, the Lightsame Manager (111) can determine that the standby Lightsame operation and the new Lightsame operation are mergeable and can update the standby operation information (WINF). The updated standby operation information (UINF2) may include the same pattern (PT1), include the leading logical address (LA) "1" among the merged logical addresses as the starting logical address (SLA), and include the number of merged logical addresses "4" as the count (CNT).

[0068] Referring to FIG. 4c, while standby action information (WINF) is stored in the action information memory (INFM), the lightsame manager (111) can store new action information (NINF3) for a new lightsame action in the action information memory (INFM) in response to a lightsame command. The lightsame manager (111) can compare the new action information (NINF3) with the standby action information (WINF) to determine that the new lightsame action can be merged into the standby lightsame action.

[0069] Specifically, the new operation information (NINF3) may include a pattern (PT1), a start logical address (SLA) "0", and a count (CNT) "3". Thus, the new operation information (NINF3) may be for logical addresses (LA) from "0" to "2".

[0070] The LightSame Manager (111) can determine that the pattern (PT1) of the standby operation information (WINF) and the new operation information (NINF3) is identical. Additionally, the LightSame Manager (111) can determine that the logical addresses (LA) from "0" to "2" formed by merging the logical addresses (LA) of the standby operation information (WINF) and the logical addresses (LA) of the new operation information (NINF3) are consecutive.

[0071] Accordingly, the Lightsame Manager (111) can determine that the standby Lightsame operation and the new Lightsame operation are mergeable and can update the standby operation information (WINF). The updated standby operation information (UINF3) may include the same pattern (PT1), include the leading logical address (LA) "0" among the merged logical addresses as the starting logical address (SLA), and include the number of merged logical addresses "3" as the count (CNT).

[0072] FIGS. 5a to 5c are drawings illustrating cases in which the Lightsame Manager (111) cannot merge Lightsame operations according to an embodiment of the present invention.

[0073] Referring to FIG. 5a, while standby operation information (WINF) is stored in the operation information memory (INFM), the lightsame manager (111) can store new operation information (NINF4) for a new lightsame operation in the operation information memory (INFM). The lightsame manager (111) can compare the new operation information (NINF4) with the standby operation information (WINF) and determine that the new lightsame operation cannot be merged into the standby lightsame operation.

[0074] Specifically, the new operation information (NINF4) may include a pattern (PT2), a start logical address (SLA) "3", and a count (CNT) "3". Thus, the new operation information (NINF4) may be for logical addresses (LA) from "3" to "5".

[0075] The lightsame manager (111) can determine that the patterns (PT1, PT2) of the standby operation information (WINF) and the new operation information (NINF4) are different. Therefore, even if the logical addresses (LA) of the standby operation information (WINF) and the logical addresses (LA) of the new operation information (NINF4) are consecutive, the lightsame manager (111) can determine that the standby lightsame operation and the new lightsame operation are non-mergeable. In this case, the standby operation information (WINF) and the new operation information (NINF4) can be retained in the operation information memory (INFM) as they are.

[0076] Referring to FIG. 5b, while standby operation information (WINF) is stored in the operation information memory (INFM), the lightsame manager (111) can store new operation information (NINF5) for a new lightsame operation in the operation information memory (INFM). The lightsame manager (111) can compare the new operation information (NINF5) with the standby operation information (WINF) and determine that the new lightsame operation cannot be merged into the standby lightsame operation.

[0077] Specifically, the new operation information (NINF5) may include a pattern (PT1), a start logical address (SLA) "4", and a count (CNT) "2". Thus, the new operation information (NINF5) may be for the logical addresses (LA) of "4" and "5".

[0078] The LightSame Manager (111) can determine that the pattern (PT1) of the standby operation information (WINF) and the new operation information (NINF5) is identical. Additionally, the LightSame Manager (111) can determine that the logical addresses (LA) formed by merging the logical addresses (LA) of the standby operation information (WINF) and the logical addresses (LA) of the new operation information (NINF5) are discontinuous.

[0079] Therefore, the lightsame manager (111) may determine that the standby lightsame operation and the new lightsame operation cannot be merged. In this case, the standby operation information (WINF) and the new operation information (NINF5) may be retained in the operation information memory (INFM) as they are.

[0080] According to an embodiment, the standby operation information (WINF) of FIGS. 4a to 5b may not be limited to the last one stored in the operation information memory (INFM). That is, when there are multiple standby lightsame operations, the lightsame manager (111) can determine whether to merge each of the standby lightsame operations with a new lightsame operation.

[0081] FIG. 6 is a flowchart illustrating a method in which a lightsame manager (111) performs a lightsame operation according to an embodiment of the present invention.

[0082] Referring to FIG. 6, in step (S110), the lightsame manager (111) can receive a lightsame command from the host device.

[0083] In step (S120), the lightsame manager (111) can store new operation information in the operation information memory (INFM) in response to a lightsame command.

[0084] In step (S130), the lightsame manager (111) can send a response to a lightsame command to the host device even before completing a new lightsame operation.

[0085] In step (S130), the light-same manager (111) can perform a light-same operation on the non-volatile memory device (120) based on operation information stored in the operation information memory (INFM). Specifically, the light-same manager (111) can control the encryption unit (112) to generate encrypted data based on patterns and consecutive logical addresses. Then, the light-same manager (111) can control the write unit (113) to store the encrypted data in the non-volatile memory device (120).

[0086] FIG. 7 is a flowchart illustrating a method for a Lightsame manager (111) to merge Lightsame actions according to an embodiment of the present invention.

[0087] Referring to FIG. 7, in step (S210), the Lightsame Manager (111) can determine whether the pattern data of the standby operation information and the pattern data of the new operation information are identical. When a pattern is generated from the pattern data and stored as operation information, the Lightsame Manager (111) can determine whether the pattern of the standby operation information and the pattern of the new operation information are identical. When the pattern data of the standby operation information and the pattern data of the new operation information are different, the procedure can proceed to step (S250). When the pattern data of the standby operation information and the pattern data of the new operation information are identical, the procedure can proceed to step (S220).

[0088] In step (S220), the LightSame Manager (111) can determine whether the logical addresses formed by merging the logical addresses of the standby operation information and the logical addresses of the new operation information are consecutive. If the merged logical addresses are not consecutive, the procedure can proceed to step (S250). If the merged logical addresses are consecutive, the procedure can proceed to step (S230).

[0089] In step (S230), the lightsaim manager (111) may determine that a new lightsaim action can be merged into a standby lightsaim action.

[0090] In step (S240), the light-same manager (111) can update the standby operation information and remove the new operation information.

[0091] In step (S250), the lightsame manager (111) may determine that a new lightsame action cannot be merged into a standby lightsame action.

[0092] FIG. 8 is a diagram illustrating an exemplary data processing system including a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 8, the data processing system (1000) may include a host device (1100) and a solid state drive (1200) (hereinafter referred to as SSD).

[0093] The SSD (1200) may include a controller (1210), a buffer memory device (1220), non-volatile memory devices (1231 to 123n), a power supply (1240), a signal connector (1250), and a power connector (1260).

[0094] The controller (1210) can control the general operation of the SSD (1200). The controller (1210) may include a host interface unit (1211), a control unit (1212), a random access memory (1213), an error correction code (ECC) unit (1214), and a memory interface unit (1215).

[0095] The host interface unit (1211) can exchange signals (SGL) with the host device (1100) through the signal connector (1250). Here, the signal (SGL) may include commands, addresses, data, etc. The host interface unit (1211) can interface the host device (1100) with the SSD (1200) according to the protocol of the host device (1100). For example, the host interface unit (1211) can communicate with the host device (1100) through any one of the standard interface protocols such as secure digital, USB (universal serial bus), MMC (multi-media card), eMMC (embedded MMC), PCMCIA (personal computer memory card international association), PATA (parallel advanced technology attachment), SATA (serial advanced technology attachment), SCSI (small computer system interface), SAS (serial attached SCSI), PCI (peripheral component interconnection), PCI-E (PCI Expresss), and UFS (universal flash storage).

[0096] The control unit (1212) can analyze and process a signal (SGL) input from the host device (1100). The control unit (1212) can control the operation of background function blocks according to firmware or software for driving the SSD (1200). Random access memory (1213) can be used as an operating memory for driving such firmware or software.

[0097] The control unit (1212) may include the lightsame manager (111), encryption unit (112), and light unit (113) of FIG. 1.

[0098] The error correction code (ECC) unit (1214) can generate parity data for data to be transmitted to non-volatile memory devices (1231–123n). The generated parity data can be stored in the non-volatile memory devices (1231–123n) along with the data. The error correction code (ECC) unit (1214) can detect errors in the data read from the non-volatile memory devices (1231–123n) based on the parity data. If the detected error is within the correction range, the error correction code (ECC) unit (1214) can correct the detected error.

[0099] The memory interface unit (1215) can provide control signals, such as commands and addresses, to non-volatile memory devices (1231 to 123n) under the control of the control unit (1212). The memory interface unit (1215) can also exchange data with the non-volatile memory devices (1231 to 123n) under the control of the control unit (1212). For example, the memory interface unit (1215) can provide data stored in the buffer memory device (1220) to the non-volatile memory devices (1231 to 123n), or provide data read from the non-volatile memory devices (1231 to 123n) to the buffer memory device (1220).

[0100] The buffer memory device (1220) can temporarily store data to be stored in the non-volatile memory devices (1231–123n). Additionally, the buffer memory device (1220) can temporarily store data read from the non-volatile memory devices (1231–123n). Data temporarily stored in the buffer memory device (1220) can be transferred to the host device (1100) or the non-volatile memory devices (1231–123n) under the control of the controller (1210).

[0101] Non-volatile memory devices (1231–123n) can be used as storage media for the SSD (1200). Each of the non-volatile memory devices (1231–123n) can be connected to the controller (1210) through multiple channels (CH1–CHn). One or more non-volatile memory devices can be connected to a single channel. Non-volatile memory devices connected to a single channel can be connected to the same signal bus and data bus.

[0102] The power supply (1240) can provide power (PWR) input through the power connector (1260) to the SSD (1200) background. The power supply (1240) may include an auxiliary power supply (1241). The auxiliary power supply (1241) can supply power so that the SSD (1200) can shut down normally in the event of a sudden power off. The auxiliary power supply (1241) may include large capacitors.

[0103] The signal connector (1250) can be configured with various types of connectors depending on the interface method between the host device (1100) and the SSD (1200).

[0104] The power connector (1260) can be configured with various types of connectors depending on the power supply method of the host device (1100).

[0105] FIG. 9 is a diagram illustrating an exemplary data processing system including a memory system according to an embodiment of the present invention. Referring to FIG. 9, the data processing system (2000) may include a host device (2100) and a memory system (2200).

[0106] The host device (2100) may be configured in the form of a board, such as a printed circuit board. Although not illustrated, the host device (2100) may include background function blocks to perform the functions of the host device.

[0107] The host device (2100) may include a connection terminal (2110), such as a socket, slot, or connector. The memory system (2200) may be mounted to the connection terminal (2110).

[0108] The memory system (2200) may be configured in the form of a substrate such as a printed circuit board. The memory system (2200) may be referred to as a memory module or a memory card. The memory system (2200) may include a controller (2210), a buffer memory device (2220), non-volatile memory devices (2231–2232), a power management integrated circuit (PMIC) (2240), and a connection terminal (2250).

[0109] The controller (2210) can control the general operations of the memory system (2200). The controller (2210) can be configured in the same way as the controller (1210) shown in FIG. 8.

[0110] The buffer memory device (2220) can temporarily store data to be stored in the non-volatile memory devices (2231–2232). Additionally, the buffer memory device (2220) can temporarily store data read from the non-volatile memory devices (2231–2232). Data temporarily stored in the buffer memory device (2220) can be transferred to the host device (2100) or the non-volatile memory devices (2231–2232) under the control of the controller (2210).

[0111] Non-volatile memory devices (2231–2232) can be used as storage media for the memory system (2200).

[0112] The PMIC (2240) can provide power input through the connection terminal (2250) to the background of the memory system (2200). The PMIC (2240) can manage the power of the memory system (2200) under the control of the controller (2210).

[0113] The connection terminal (2250) can be connected to the connection terminal (2110) of the host device. Through the connection terminal (2250), signals such as commands, addresses, data, and power can be transmitted between the host device (2100) and the memory system (2200). The connection terminal (2250) can be configured in various forms depending on the interface method between the host device (2100) and the memory system (2200). The connection terminal (2250) can be placed on one side of the memory system (2200).

[0114] FIG. 10 is a drawing illustrating an exemplary data processing system including a memory system according to an embodiment of the present invention. Referring to FIG. 10, the data processing system (3000) may include a host device (3100) and a memory system (3200).

[0115] The host device (3100) may be configured in the form of a board, such as a printed circuit board. Although not illustrated, the host device (3100) may include background function blocks to perform the functions of the host device.

[0116] The memory system (3200) may be configured in the form of a surface-mount package. The memory system (3200) may be mounted to a host device (3100) via a solder ball (3250). The memory system (3200) may include a controller (3210), a buffer memory device (3220), and a non-volatile memory device (3230).

[0117] The controller (3210) can control the general operations of the memory system (3200). The controller (3210) can be configured in the same way as the controller (1210) shown in FIG. 8.

[0118] The buffer memory device (3220) can temporarily store data to be stored in the non-volatile memory device (3230). Additionally, the buffer memory device (3220) can temporarily store data read from the non-volatile memory devices (3230). Data temporarily stored in the buffer memory device (3220) can be transferred to the host device (3100) or the non-volatile memory device (3230) under the control of the controller (3210).

[0119] A non-volatile memory device (3230) can be used as a storage medium for a memory system (3200).

[0120] FIG. 11 is a diagram illustrating an exemplary network system including a memory system according to an embodiment of the present invention. Referring to FIG. 11, the network system (4000) may include a server system (4300) and a plurality of client systems (4410 to 4430) connected through a network (4500).

[0121] The server system (4300) can provide data in response to requests from multiple client systems (4410 to 4430). For example, the server system (4300) can store data provided by multiple client systems (4410 to 4430). As another example, the server system (4300) can provide data to multiple client systems (4410 to 4430).

[0122] The server system (4300) may include a host device (4100) and a memory system (4200). The memory system (4200) may be composed of the memory system (100) of FIG. 1, the SSD (1200) of FIG. 8, the memory system (2200) of FIG. 9, and the memory system (3200) of FIG. 10.

[0123] FIG. 12 is a block diagram illustrating, by way of example, a non-volatile memory device included in a memory system according to an embodiment of the present invention. Referring to FIG. 12, the non-volatile memory device (300) may include a memory cell array (310), a row decoder (320), a data read / write block (330), a column decoder (340), a voltage generator (350), and control logic (360).

[0124] The memory cell array (310) may include memory cells (MC) arranged in areas where word lines (WL1~WLm) and bit lines (BL1~BLn) intersect each other.

[0125] The row decoder (320) can be connected to the memory cell array (310) through the word lines (WL1–WLm). The row decoder (320) can operate under the control of the control logic (360). The row decoder (320) can decode an address provided from an external device (not shown). The row decoder (320) can select and drive the word lines (WL1–WLm) based on the decoding result. For example, the row decoder (320) can provide a word line voltage provided from the voltage generator (350) to the word lines (WL1–WLm).

[0126] The data read / write block (330) can be connected to the memory cell array (310) through bit lines (BL1 to BLn). The data read / write block (330) may include read / write circuits (RW1 to RWn) corresponding to each of the bit lines (BL1 to BLn). The data read / write block (330) can operate under the control of the control logic (360). Depending on the operation mode, the data read / write block (330) can operate as a write driver or as a sense amplifier. For example, the data read / write block (330) can operate as a write driver that stores data provided from an external device in the memory cell array (310) during a write operation. As another example, the data read / write block (330) can operate as a sense amplifier that reads data from the memory cell array (310) during a read operation.

[0127] The column decoder (340) can operate under the control of the control logic (360). The column decoder (340) can decode an address provided from an external device. Based on the decoding result, the column decoder (340) can connect the read / write circuits (RW1~RWn) of the data read / write block (330) corresponding to each of the bit lines (BL1~BLn) with the data input / output line (or data input / output buffer).

[0128] The voltage generator (350) can generate a voltage used for background operation of the non-volatile memory device (300). The voltages generated by the voltage generator (350) can be applied to the memory cells of the memory cell array (310). For example, a program voltage generated during a program operation can be applied to the word lines of the memory cells where the program operation is to be performed. As another example, an erase voltage generated during an erase operation can be applied to the well regions of the memory cells where the erase operation is to be performed. As another example, a read voltage generated during a read operation can be applied to the word lines of the memory cells where the read operation is to be performed.

[0129] The control logic (360) can control the general operations of the non-volatile memory device (300) based on a control signal provided from an external device. For example, the control logic (360) can control the read, write, and erase operations of the non-volatile memory device (300).

[0130] A person skilled in the art to which the present invention pertains should understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features, and therefore the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0131] 100: Memory System 110: Controller 111: Lightsame Manager INFM: Operation Information Memory 112: Encryption section 113: Light Department 120: Non-volatile memory device

Claims

Claim 1 A memory system comprising: a non-volatile memory device; and a light-same manager configured to perform a light-same operation on the non-volatile memory device, wherein the light-same manager stores operation information in the operation information memory in response to a light-same command transmitted from a host device, and transmits a response to the light-same command to the host device even before the light-same operation corresponding to the operation information is completed. Claim 2 In claim 1, the light-same manager is a memory system that merges the first light-same operation and the second light-same operation when the pattern data of the first operation information of the first light-same operation and the pattern data of the second operation information of the second light-same operation are identical and the logical addresses of the first operation information and the logical addresses of the second operation information are consecutive. Claim 3 In paragraph 2, the light-same manager generates updated operation information to merge the first light-same operation and the second light-same operation, and the updated operation information includes the pattern data, the leading logical address among the logical addresses formed by merging the logical addresses of the first operation information and the logical addresses of the second operation information, and the number of the merged logical addresses. Claim 4 In paragraph 3, the light-same manager stores the first operation information and the second operation information in the operation information memory, updates whichever of the first operation information and the second operation information is created first with the updated operation information, and removes the other one created subsequently. Claim 5 A memory system according to claim 1, wherein the light-same manager determines that the first light-same operation and the second light-same operation are non-mergeable when the pattern data of the first operation information of the first light-same operation and the pattern data of the second operation information of the second light-same operation are not identical, or when the logical addresses of the first operation information and the logical addresses of the second operation information are not consecutive. Claim 6 A memory system according to claim 1, further comprising an encryption unit configured to collectively encrypt duplicate patterns corresponding to consecutive logical addresses into encrypted patterns when the light signature operation is performed. Claim 7 A memory system according to claim 6, further comprising a light unit configured to store the encrypted patterns in the non-volatile memory device when the light-same operation is performed, wherein the light-same manager controls the encryption unit to generate subsequent encrypted patterns while the light unit stores the encrypted patterns in the non-volatile memory device. Claim 8 delete Claim 9 A method of operation of a memory system comprising: a step of comparing first operation information of a first light-same operation and second operation information of a second light-same operation; and a step of determining whether the first light-same operation and the second light-same operation can be merged according to the comparison result, wherein the step of comparing the first operation information and the second operation information includes a step of determining whether the pattern data of the first operation information and the pattern data of the second operation information are identical, and whether the logical addresses formed by merging the logical addresses of the first operation information and the logical addresses of the second operation information are consecutive. Claim 10 delete Claim 11 A method of operation of a memory system according to claim 9, further comprising the step of generating updated operation information to merge the first lightsame operation and the second lightsame operation, wherein the updated operation information includes the pattern data, the leading logical address among the merged logical addresses, and the number of the merged logical addresses. Claim 12 In claim 11, the step of generating the updated operation information comprises updating either of the first operation information and the second operation information, which is generated first, with the updated operation information, and removing the other one subsequently generated. Claim 13 A method of operation of a memory system according to claim 9, wherein when the first light-same operation and the second light-same operation are mergeable, the method further comprises the step of performing a merged light-same operation, wherein the step of performing the merged light-same operation includes: the step of encrypting duplicate patterns corresponding to the merged logical addresses into encrypted patterns in bulk; and the step of storing the encrypted patterns in a non-volatile memory device, wherein subsequent encrypted patterns are generated while the encrypted patterns are stored in the non-volatile memory device. Claim 14 A method of operation of a memory system according to claim 9, further comprising: a step of storing operation information in an operation information memory in response to a lightsame command transmitted from a host device; and a step of transmitting a response to the lightsame command to the host device even before the lightsame operation corresponding to the operation information is completed. Claim 15 A memory system comprising: a non-volatile memory device; a LightSame manager configured to perform a LightSame operation on the non-volatile memory device; and an encryption unit configured to encrypt duplicate patterns corresponding to consecutive logical addresses into encrypted patterns in batches when the LightSame operation is performed. Claim 16 In paragraph 15, the above-mentioned lightsame manager is a memory system that merges two or more lightsame actions for the same pattern. Claim 17 In paragraph 16, the above lightsame manager is a memory system that merges the lightsame operations when the logical addresses corresponding to the lightsame operations are consecutive. Claim 18 In paragraph 17, the above lightsame manager generates operation information of a merged lightsame operation, and the operation information is a memory system including the pattern, the leading logical address among the merged logical addresses, and the number of the merged logical addresses. Claim 19 A memory system according to claim 15, further comprising a light unit configured to store the encrypted patterns in the non-volatile memory device when the light-same operation is performed, wherein the light-same manager controls the encryption unit to generate subsequent encrypted patterns while the light unit stores the encrypted patterns in the non-volatile memory device. Claim 20 In paragraph 15, the above-mentioned lightsame manager stores operation information in an operation information memory in response to a lightsame command transmitted from a host device, and transmits a response to the lightsame command to the host device even before the lightsame operation corresponding to the operation information is completed.

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