Nitride semiconductor devices and methods of manufacturing nitride semiconductor devices formed on diamond substrates

Abstract

The present invention relates to a nitride semiconductor device formed on a diamond substrate and a method for manufacturing a nitride semiconductor device, and more specifically, to a method for manufacturing a nitride semiconductor device formed on a diamond substrate in which twinning defects in a diamond layer formed on the substrate are prevented depending on the type of substrate and the orientation of the crystal plane, and by forming a single-crystal nitride semiconductor device alone on the diamond layer or forming a single-crystal nitride semiconductor device and a diamond semiconductor device simultaneously, the nitride semiconductor device and the nitride semiconductor device have high voltage, high frequency, and radiation resistance characteristics and improved heat dissipation performance.

Description

Technology Field

[0001] The present invention relates to a nitride semiconductor device formed on a diamond substrate and a method for manufacturing a nitride semiconductor device, and more specifically, to a method for manufacturing a nitride semiconductor device formed on a diamond substrate in which twinning defects in a diamond layer formed on the substrate are prevented depending on the type of substrate and the orientation of the crystal plane, and by forming a single-crystal nitride semiconductor device alone on the diamond layer or forming a single-crystal nitride semiconductor device and a diamond semiconductor device simultaneously, the nitride semiconductor device and the nitride semiconductor device have high voltage, high frequency, and radiation resistance characteristics and improved heat dissipation performance. Background Technology

[0003] As technologies such as 5G, radar systems, and power converters advance, the demand for power semiconductors capable of operating at high power and high frequency is surging. However, conventional power semiconductor devices using silicon (Si) and silicon carbide (SiC) as substrates have a problem in that the lifespan of the device is shortened due to heat generated during operation.

[0004] To address this, diamond, which has high thermal conductivity and insulation properties, has been proposed as a substrate for power semiconductor devices. In particular, single-crystal diamonds with (111) and (113) planes, known as thermodynamically stable planes, are attracting attention. However, in the case of conventional technology for epitaxially growing a diamond substrate on a substrate, the occurrence rate of twin defects is high, and it is difficult to grow a single-crystal diamond substrate having crystal planes with (111) to (113) orientations. Furthermore, a problem has arisen in which the quality of the semiconductor device formed on the diamond substrate is also degraded due to the degradation of the quality of the single-crystal diamond substrate.

[0005] That is, there is a need for a method to improve the quality of a single-crystal diamond substrate having a crystal plane of orientation (111) or (113) and to manufacture a power semiconductor device with improved heat dissipation performance. The problem to be solved

[0007] The present invention aims to provide a nitride semiconductor device formed on a diamond substrate and a method for manufacturing a nitride semiconductor device, wherein twinning defects in the diamond layer formed on the substrate are prevented depending on the type of substrate and the orientation of the crystal plane, and a single-crystal nitride semiconductor device is formed alone on the diamond layer, or a single-crystal nitride semiconductor device and a diamond semiconductor device are formed simultaneously, thereby providing high voltage, high frequency, and radiation resistance characteristics and improved heat dissipation performance. means of solving the problem

[0009] To solve the above problems, one embodiment of the present invention provides a semiconductor integrated device comprising: a substrate layer; a buffer layer disposed on the substrate layer; a diamond layer disposed on the buffer layer; and a nitride semiconductor layer disposed on the diamond layer, wherein the diamond layer comprises a single crystal diamond having a crystal plane having an orientation of either (111) or (113).

[0010] In some embodiments of the present invention, the substrate layer comprises any one of a sapphire substrate (Al2O3), a silicon (Si) substrate, a silicon carbide (SiC) substrate, a nitride substrate, and a diamond substrate, and may have an off angle of -10 to 10°.

[0011] In some embodiments of the present invention, the buffer layer comprises one or more of iridium (Ir), ruthenium (Ru), and oxide materials, and may comprise one or more layers.

[0012] In some embodiments of the present invention, the diamond layer has a thickness of 5 to 500 μm and has a crystal plane having an orientation of either (111) or (113), and may have an off-angle of -10 to 10° with respect to an axis perpendicular to the upper surface of the substrate layer.

[0013] In some embodiments of the present invention, the nitride semiconductor layer comprises: a buffer nitride layer comprising aluminum nitride (AlN) having an orientation of (0001); and aluminum gallium nitride (Al) disposed on the buffer nitride layer. x Ga 1-x It includes a nitride element layer comprising N); and the nitride element layer may be a multilayer structure comprising two or more layers.

[0014] In some embodiments of the present invention, the nitride semiconductor layer is aluminum gallium nitride (Al x Ga 1-x A nitride element layer having a multilayer structure including N; wherein the nitride element layer may each include an undoped layer; and a doped layer doped with either n-type or p-type.

[0015] In some embodiments of the present invention, the nitride semiconductor layer comprises a nitride device layer having a multilayer structure including two or more layers; and the nitride device layer comprises a plurality of layers, wherein each of the plurality of layers has a different x value and is composed of aluminum gallium nitride (Al x Ga 1-x It may be a Field Effect Transistor (FET) structure that includes N) and has either a 2-dimensional electron gas (2DEG) or a 2-dimensional hole gas (2DHG) formed on the inside.

[0016] In some embodiments of the present invention, the nitride element layer may have a structure of either a transistor structure or a diode structure.

[0017] In some embodiments of the present invention, the nitride semiconductor layer is partially disposed in a portion of the upper surface of the diamond layer, and the semiconductor integrated element may further include a diamond semiconductor layer partially disposed in another portion of the upper surface of the diamond layer where the nitride semiconductor layer is not disposed, and spaced apart from the nitride semiconductor layer.

[0018] In some embodiments of the present invention, the thickness of the buffer nitride layer may be 1 to 1000 nm.

[0019] In some embodiments of the present invention, the nitride semiconductor layer may be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0020] In some embodiments of the present invention, the diamond layer is formed by chemical vapor deposition (CVD) on the buffer layer and 0.5 W / mm 2 Up to 5W / mm 2 It can be formed at a growth rate of 0.01 to 100 μm / hr under plasma power, pressure of 0 to 1000 torr, and temperature of 100 to 1300°C.

[0021] In some embodiments of the present invention, the semiconductor integrated device may be able to operate even when the substrate layer and the buffer layer are each removed.

[0022] In some embodiments of the present invention, the nitride semiconductor layer further comprises a first electrode disposed on the nitride element layer, and the first electrode may include a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from each of the first source and the first gate.

[0023] To solve the above problems, one embodiment of the present invention provides a method for manufacturing a semiconductor integrated device, comprising: a substrate preparation step of preparing a substrate layer; a buffer placement step of placing a buffer layer on the substrate layer; a diamond placement step of placing a diamond layer on the buffer layer; and a nitride semiconductor placement step of placing a nitride semiconductor layer on the diamond layer, wherein the diamond layer comprises a single-crystal diamond having a crystal plane orientation of either (111) or (113).

[0024] In some embodiments of the present invention, the semiconductor integrated device can use the remaining diamond layer and nitride semiconductor after removing each of the substrate layer and buffer layer, and the method for manufacturing the semiconductor integrated device may further include a lower layer removal step of removing each of the substrate layer and buffer layer and leaving only the diamond layer and nitride semiconductor layer.

[0025] In some embodiments of the present invention, the nitride semiconductor placement step comprises: a buffer nitride placement step for placing a buffer nitride layer comprising aluminum nitride (AlN) having an orientation of (0001); and aluminum gallium nitride (Al x Ga 1-x The method further includes a detailed step of a nitride element placement step in which a nitride element layer comprising N) is placed on the buffer nitride layer, and the nitride element layer may be a multilayer structure comprising two or more layers.

[0026] In some embodiments of the present invention, the nitride semiconductor placement step further comprises a detailed step of a first electrode placement step of placing a first electrode on the nitride element layer, wherein the first electrode may include a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from each of the first source and the first gate. Effects of the invention

[0028] According to one embodiment of the present invention, a semiconductor integrated device includes a high-quality single-crystal diamond layer that functions as a heat dissipation layer, thereby preventing heat generation of the device and improving the lifespan of the device.

[0029] According to one embodiment of the present invention, a semiconductor integrated device can reduce the defect rate caused by defects by minimizing the occurrence of defects in a nitride semiconductor layer formed on a diamond layer, and can improve economic efficiency by increasing the yield of the semiconductor integrated device manufacturing process.

[0030] According to one embodiment of the present invention, the substrate layer can improve the crystallinity and quality of the diamond layer and increase the heat dissipation and insulation characteristics of the diamond layer by having the crystal planes deviated.

[0031] According to one embodiment of the present invention, the diamond layer is formed to have a high-quality single-crystal thin film structure by the angle of the substrate layer, thereby exhibiting the effect of improving thermal conductivity, charge mobility, and dielectric strength.

[0032] According to one embodiment of the present invention, the nitride element layer is a gallium aluminum nitride (Al) having a crystal plane of the (0001) orientation on a diamond layer having a crystal plane of either the (111) or (113) orientation. x Ga 1-x By being formed to include N), it can be grown in the form of a single crystal, thereby exhibiting the effect of improving the crystallinity and durability of the semiconductor integrated device.

[0033] According to one embodiment of the present invention, the nitride semiconductor layer is formed on a diamond layer having one of the crystal planes of orientations (111) and (113), thereby improving interfacial adhesion with the diamond layer and preventing peeling and breakage.

[0034] According to one embodiment of the present invention, a semiconductor integrated device can improve the heat dissipation performance of the diamond layer and improve the reliability and lifespan of the device by performing a lower layer removal step. Brief explanation of the drawing

[0036] FIG. 1 schematically illustrates a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 2 schematically illustrates the off-angle of a substrate layer according to one embodiment of the present invention. FIG. 3 schematically illustrates a perspective view of a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 4 schematically illustrates the manufacturing steps of a semiconductor integrated device according to one embodiment of the present invention. FIG. 5 schematically illustrates the detailed steps of the nitride semiconductor placement step according to one embodiment of the present invention. FIG. 6 schematically illustrates a perspective view of a semiconductor integrated circuit having a two-dimensional electron gas formed therein according to one embodiment of the present invention. FIG. 7 schematically illustrates a perspective view of a semiconductor integrated circuit comprising a p-type or n-type doped nitride element layer according to one embodiment of the present invention. FIG. 8 schematically illustrates a semiconductor integrated device including a dia semiconductor layer according to one embodiment of the present invention. FIG. 9 schematically illustrates a semiconductor integrated circuit with the substrate layer and buffer layer removed according to one embodiment of the present invention. FIG. 10 schematically illustrates the SEM measurement results of a semiconductor integrated device according to one embodiment of the present invention. Specific details for implementing the invention

[0037] Hereinafter, various embodiments and / or aspects are disclosed with reference to the drawings. For illustrative purposes, numerous specific details are disclosed in the following description to aid in a general understanding of one or more aspects. However, it will also be recognized by those skilled in the art that these aspects may be practiced without such specific details. The following description and the accompanying drawings describe specific exemplary aspects of one or more aspects in detail. However, these aspects are exemplary, and some of the various methods in the principles of the various aspects may be used, and the description is intended to include all such aspects and their equivalents.

[0038] In addition, various aspects and features will be presented by a system that may include multiple devices, components and / or modules, etc. It should also be understood and recognized that various systems may include additional devices, components and / or modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in relation to the drawings.

[0039] As used herein, terms such as "examples," "examples," "aspects," "examples," etc., may not be interpreted as implying that any aspect or design described is better or more advantageous than other aspects or designs.

[0040] Additionally, the terms “comprising” and / or “comprising” should be understood to mean that the relevant feature and / or component is present, but not to exclude the presence or addition of one or more other features, components and / or groups thereof.

[0041] Additionally, terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0042] Furthermore, in the embodiments of the present invention, all terms used herein, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the embodiments of the present invention.

[0044] Although the demand for power semiconductors capable of high-power, high-frequency operation is surging, conventional power semiconductor devices using silicon (Si) and silicon carbide (SiC) as substrates have a problem in that their lifespan is shortened due to heat generation. Accordingly, diamond, which has high thermal conductivity, has been proposed as a new substrate; however, it is difficult to grow high-quality substrates from single-crystal diamonds on the (111) and (113) planes, which are the most thermodynamically stable planes. Consequently, a problem has arisen in which the quality of semiconductor devices formed on the diamond substrate is also degraded.

[0045] To solve this, the present invention proposes a nitride semiconductor device formed on a diamond substrate and a method for manufacturing the nitride semiconductor device, which improves the quality of the semiconductor device formed on the diamond layer (3000).

[0046] More specifically, in the present invention, a high-quality single-crystal diamond layer (3000) can be formed by depositing a single-crystal diamond having one of the crystal planes of the (111) orientation and the (113) orientation on a substrate layer (1000) having an off-angle of -10 to 10°. In addition, by forming a nitride semiconductor layer (4000) on the diamond layer (3000), a single-crystal aluminum gallium nitride (Al) can be formed. x Ga 1-x A semiconductor integrated device (1) including N) can be manufactured.

[0047] With this configuration, the semiconductor integrated device (1) has high heat dissipation characteristics due to the diamond layer (3000), so heat generated during device operation can be easily discharged and problems of performance degradation caused by crystal defects can be prevented.

[0049] That is, according to one embodiment of the present invention, the semiconductor integrated device (1) includes a high-quality single-crystal diamond layer (3000) that acts as a heat dissipation layer, thereby preventing heat generation of the device and improving the lifespan of the device.

[0050] In addition, according to one embodiment of the present invention, the semiconductor integrated device (1) can reduce the defect rate caused by defects by minimizing the occurrence of defects in the nitride semiconductor layer (4000) formed on the diamond layer (3000), and can improve economic efficiency by increasing the yield of the semiconductor integrated device (1) manufacturing process.

[0052] Hereinafter, a nitride semiconductor device formed on a diamond substrate according to one embodiment of the present invention and a method for manufacturing the nitride semiconductor device will be described in detail.

[0054] FIG. 1 schematically illustrates a semiconductor integrated element (1) according to one embodiment of the present invention.

[0056] According to one embodiment of the present invention, a semiconductor integrated device (1) may be provided, comprising: a substrate layer (1000); a buffer layer (2000) disposed on the substrate layer (1000); a diamond layer (3000) disposed on the buffer layer (2000); and a nitride semiconductor layer (4000) disposed on the diamond layer (3000); wherein the diamond layer (3000) comprises a single crystal diamond having a crystal plane orientation of either (111) or (113).

[0057] According to one embodiment of the present invention, the substrate layer (1000) may include any one of a sapphire substrate (Al2O3), a silicon (Si) substrate, a silicon carbide (SiC) substrate, a nitride substrate, and a diamond substrate.

[0058] According to one embodiment of the present invention, the buffer layer (2000) comprises one or more of iridium (Ir), ruthenium (Ru), and oxide materials, and may comprise one or more layers.

[0059] According to one embodiment of the present invention, the diamond layer (3000) may have a thickness of 5 to 500 μm.

[0060] According to one embodiment of the present invention, the nitride semiconductor layer (4000) comprises: a buffer nitride layer (4100) comprising aluminum nitride (AlN) having an orientation of (0001); and aluminum gallium nitride (Al) disposed on the buffer nitride layer (4100). x Ga 1-x It includes a nitride element layer (4200) including N); and the nitride element layer (4200) may be a multilayer structure including two or more layers.

[0061] According to one embodiment of the present invention, the thickness of the buffer nitride layer (4100) may be 1 to 1000 nm.

[0063] As illustrated in FIG. 1, a semiconductor integrated device (1) according to one embodiment of the present invention may include a substrate layer (1000), a buffer layer (2000), a diamond layer (3000), and a nitride semiconductor layer (4000). Additionally, the diamond layer (3000) may include a single-crystal diamond having an orientation of either (111) or (113).

[0064] Specifically, the substrate layer (1000) may include any one of a sapphire substrate (Al2O3), a silicon (Si) substrate, a silicon carbide (SiC) substrate, a nitride substrate, and a diamond substrate. According to one embodiment of the present invention, the substrate layer (1000) may have a crystal plane grown in a specific orientation that is predetermined. For example, the crystal plane of the substrate layer (1000) may be an orientation in which a single-crystal diamond can grow having a crystal plane of either orientation (111) or (113). A more detailed description of the substrate layer (1000) will be provided in the drawings described later.

[0065] The buffer layer (2000) may be disposed on the substrate layer (1000). According to one embodiment of the present invention, the buffer layer (2000) may include one or more layers. In other words, the buffer layer (2000) may be a single-layer structure consisting of one layer or a multi-layer structure including two or more layers.

[0066] Additionally, one or more layers included in the buffer layer (2000) may each include one or more of a metal material or an oxide material. According to one embodiment of the present invention, the buffer layer (2000) may include one or more of iridium (Ir), ruthenium (Ru), aluminum oxide (Al2O3), YSZ (Yttria-stabilized zirconia), and STO (SrTiO3). For example, if the buffer layer (2000) is a multilayer structure including two layers, one layer included in the buffer layer (2000) may include iridium, and the other layer included in the buffer layer (2000) may be aluminum oxide. On the other hand, if the buffer layer (2000) according to one embodiment of the present invention is a single-layer structure including only one layer, the buffer layer (2000) may include only iridium.

[0067] The diamond layer (3000) may be disposed on top of the buffer layer (2000). According to one embodiment of the present invention, the buffer layer (2000) is disposed between the substrate layer (1000) and the diamond layer (3000) so as to perform a buffer function that mitigates lattice mismatch that occurs when the diamond layer (3000) grows on the substrate layer (1000).

[0068] According to one embodiment of the present invention, the buffer layer (2000) may be either crystalline or amorphous. When the buffer layer (2000) is crystalline, the buffer layer (2000) may serve as a transition buffer that gradually connects the substrate layer (1000) and the diamond layer (3000) by having a value between the values ​​corresponding to the lattice constants of the substrate layer (1000) and the diamond layer (3000), respectively. Meanwhile, when the buffer layer (2000) is amorphous, the buffer layer (2000) may serve to block lattice mismatch between the substrate layer (1000) and the diamond layer (3000) by not having a lattice constant.

[0069] By placing the buffer layer (2000) on top of the substrate layer (1000), the stress caused by lattice mismatch between the diamond layer (3000) and the substrate layer (1000) can be reduced. Accordingly, the probability of defects occurring due to lattice mismatch between the diamond layer (3000) and the substrate layer (1000) is lowered, thereby improving crystallinity and enabling the formation of a high-quality single-crystal thin film.

[0071] According to one embodiment of the present invention, the semiconductor integrated device (1) can mitigate defects occurring in the diamond layer (3000) and improve the quality of the diamond layer (3000) by including the buffer layer (2000).

[0073] Meanwhile, the diamond layer (3000) may be disposed on top of the buffer layer (2000). As previously mentioned, the diamond layer (3000) may include a single-crystal diamond having an orientation of either (111) or (113). Additionally, according to one embodiment of the present invention, the thickness of the diamond layer (3000) may be 5 to 500 μm. Preferably, the thickness of the diamond layer (3000) is 10 to 300 μm. More preferably, the thickness of the diamond layer (3000) is 20 to 150 μm.

[0074] According to one embodiment of the present invention, the diamond layer (3000) may comprise a single-crystal diamond having one of the (111) and (113) orientations by being disposed on the upper side of the substrate layer (1000) and the buffer layer (2000). A more detailed description of the diamond layer (3000) will be provided in the drawings described below.

[0076] The nitride semiconductor layer (4000) may be disposed on the diamond layer (3000). According to one embodiment of the present invention, the nitride semiconductor layer (4000) may each include a buffer nitride layer (4100) and a nitride element layer (4200). Specifically, the buffer nitride layer (4100) may be disposed on the diamond layer (3000), and the nitride element layer (4200) may be disposed on the buffer nitride layer (4100).

[0077] According to one embodiment of the present invention, the buffer nitride layer (4100) may include aluminum nitride (AlN) having a crystal plane with an orientation of (0001). That is, the buffer nitride layer (4100) according to one embodiment of the present invention may include single-crystal aluminum nitride.

[0078] Generally, when a material is grown as a single crystal on a substrate having a specific crystal plane, the material can be grown to have a crystal plane of a specific orientation that has a small difference in lattice constant with the substrate and can form a thermodynamically stable bond with the substrate in order to minimize lattice mismatch with the substrate.

[0079] Accordingly, when the diamond layer (3000) comprises a single-crystal diamond having a crystal plane having either (111) or (113) orientations, the crystal plane of the single-crystal material grown heterogeneously on the diamond layer (3000) may have a predetermined orientation. According to one embodiment of the present invention, aluminum nitride may be grown heterogeneously on the diamond layer (3000) where the crystal plane has an orientation of (111) or (113) when the crystal plane has an orientation of (0001). That is, the buffer nitride layer (4100) may include aluminum nitride having a crystal plane of the (0001) orientation to grow heterogeneously in the form of a single crystal on the diamond layer (3000).

[0081] According to one embodiment of the present invention, the thickness of the buffer nitride layer (4100) may be 1 to 1000 nm. Preferably, the thickness of the buffer nitride layer (4100) is 10 to 500 nm. More preferably, the thickness of the buffer nitride layer (4100) is 20 to 300 nm.

[0082] The buffer nitride layer (4100) can perform the role of a buffer by being placed between the diamond layer (3000) and the nitride element layer (4200), respectively. In other words, the buffer nitride layer (4100) can perform a role similar to that of the buffer layer (2000). That is, the buffer nitride layer (4100) can alleviate lattice mismatch between the nitride element layer (4200) and the diamond layer (3000).

[0084] According to one embodiment of the present invention, the buffer nitride layer (4100) acts as a buffer to prevent defects caused by lattice mismatch with the diamond layer (3000) from occurring in the nitride element layer (4200), thereby improving the crystallinity of the nitride element layer (4200) and improving the performance of the semiconductor integrated device (1).

[0086] The nitride element layer (4200) may be disposed on top of the buffer nitride layer (4100). According to one embodiment of the present invention, the nitride element layer (4200) is aluminum gallium nitride (Al x Ga 1-x It may include N). Additionally, the nitride element layer (4200) may be a multilayer structure comprising two or more layers. Specifically, each of the two or more layers included in the nitride element layer (4200) is aluminum gallium nitride (Al x Ga 1-x It may include N). A more detailed description of the multilayer structure of the nitride element layer (4200) will be provided in the drawings described later.

[0087] Meanwhile, aluminum gallium nitride (Al) included in the nitride element layer (4200) x Ga 1-x N) may have a single-crystal structure. According to one embodiment of the present invention, a single-crystal aluminum gallium nitride (Al) included in the nitride element layer (4200) x Ga 1-x N) may have a crystal plane orientation of (0001). In other words, the nitride element layer (4200) according to one embodiment of the present invention is aluminum gallium nitride (Al) having a crystal plane orientation corresponding to that of aluminum nitride included in the buffer nitride layer (4100). x Ga 1-x It may include N).

[0088] According to one embodiment of the present invention, the aluminum gallium nitride included in the nitride element layer (4200) is Al x Ga 1-x It can be expressed by the chemical formula of N, and x can have a value greater than or equal to 0 and less than 1. A more specific description of the nitride element layer (4200) will be described in the drawings to be described later.

[0090] FIG. 2 schematically illustrates the off-angle of a substrate layer (1000) according to one embodiment of the present invention.

[0092] According to one embodiment of the present invention, the substrate layer (1000) may have an off angle of -10 to 10°.

[0093] According to one embodiment of the present invention, the diamond layer (3000) may have a crystal plane having an orientation of either (111) or (113), and may have an off-angle of -10 to 10° with respect to an axis perpendicular to the upper surface of the substrate layer (1000).

[0095] As described above, the substrate layer (1000) may include any one of a sapphire substrate (Al2O3), a silicon (Si) substrate, a silicon carbide (SiC) substrate, a nitride substrate, and a diamond substrate. Additionally, the substrate layer (1000) may be grown with a crystal plane in a predetermined specific orientation. The predetermined specific orientation may be an orientation in which the diamond layer (3000) can be grown to include a single-crystal diamond having a crystal plane of either orientation (111) or (113).

[0096] According to one embodiment of the present invention, the substrate layer (1000) may be formed to have an off-angle so that the crystal plane of the diamond layer (3000) grows to have an orientation of either (111) or (113). Generally, an off-angle may mean that when a substrate has a crystal plane of a specific orientation, the crystal plane of the specific orientation is not positioned perpendicular to an axis perpendicular to the ground, but is positioned to have a specific angle.

[0097] In addition, 'decline' may refer to the specific angle itself when the crystal plane of the specific orientation is not positioned perpendicular to an axis perpendicular to the ground, but is positioned to have a specific angle. Accordingly, both the expression 'the crystal plane is deviated' and the expression 'the crystal plane has a deviated angle' may be used in this specification.

[0099] FIG. 2(a) illustrates a case where the substrate layer (1000) is not angled, FIG. 2(b) illustrates a process of arranging the substrate layer (1000) to have an angle, and FIG. 2(c) illustrates a case where the substrate layer (1000) is angled.

[0100] Specifically, as illustrated in FIG. 2(a), the substrate layer (1000) may have a crystal plane of a specific orientation, and the crystal plane of the specific orientation may be positioned perpendicular to an axis perpendicular to the ground. When the crystal plane of the specific orientation is perpendicular to an axis perpendicular to the ground, the crystal plane of the specific orientation may have an angle of 0°. That is, the crystal plane of the specific orientation of the substrate layer (1000) illustrated in FIG. 2(a) may be in a state of not being angled.

[0101] Hereinafter, a specific orientational crystal plane of the substrate layer (1000) will be referred to as the (hlk) plane. In other words, when the substrate layer (1000) in which the (hlk) plane is not deviated is placed on the ground as in FIG. 2(a), the upper surface and the (hlk) plane of the substrate layer (1000) can each be placed horizontally with respect to the ground.

[0103] Meanwhile, as shown in FIG. 2(b), the substrate layer (1000) may be positioned so that the (hlk) plane is not horizontal to the ground and forms a specific angle. According to one embodiment of the present invention, the specific angle formed by the (hlk) plane of the substrate layer (1000) with the ground may be θ. That is, the (hlk) plane may be deflected by θ. Accordingly, the (hlk) plane may have a deflection angle of θ with respect to an axis horizontal to the ground.

[0104] According to one embodiment of the present invention, when the (hlk) plane is positioned such that it is angled by θ, the substrate layer (1000) may have all parts corresponding to the area outside the dotted line removed, leaving only the area A indicated by the dotted line in FIG. 2(b). Accordingly, as shown in FIG. 2(c), the substrate layer (1000) may have a structure in which the upper surface and the lower surface are each positioned horizontally with respect to the ground, while the (hlk) plane is angled by θ.

[0105] According to one embodiment of the present invention, the substrate layer (1000) may have a (hlk) plane with an angle of deviation of -10 to 10°. That is, θ may satisfy the inequality -10° ≤ θ ≤ 10°. Preferably, the substrate layer (1000) may have a (hlk) plane with an angle of deviation of -8 to 8°. More preferably, the substrate layer (1000) may have a (hlk) plane with an angle of deviation of -5 to 5°.

[0107] As previously described, the (hlk) plane of the substrate layer (1000) may be a crystal plane that can be heterogeneously grown so that the diamond layer (3000) has one of the (111) and (113) orientations. According to one embodiment of the present invention, when the substrate layer (1000) of the semiconductor integrated device (1) has an angle of -10 to 10°, the twin defects formed in the diamond layer (3000) may be relatively reduced compared to when the substrate layer (1000) is not angled.

[0108] Meanwhile, according to one embodiment of the present invention, when the substrate layer (1000) is deviated, the diamond layer (3000) is a single crystal having one of the crystal planes of orientations (111) and (113), and the crystal plane of orientations (111) and (113) may be formed to have a deviation angle of -10 to 10° with respect to an axis perpendicular to the upper surface of the substrate layer (1000). That is, the crystal plane of the diamond layer (3000) may be deviated in correspondence with the crystal plane of the substrate layer (1000).

[0109] Preferably, any one of the crystal planes of orientations (111) and (113) included in the diamond layer (3000) has an angle of deviation of -8 to 8°. More preferably, any one of the crystal planes of orientations (111) and (113) included in the diamond layer (3000) has an angle of deviation of -5 to 5°.

[0110] According to one embodiment of the present invention, as shown in FIG. 2(c), the upper surface and lower surface of the substrate layer (1000) are each horizontal with respect to the ground, but only the (hlk) surface may be deflected by θ with respect to an axis perpendicular to the ground. Accordingly, the diamond layer (3000) is positioned such that its upper surface and lower surface are each horizontal with respect to the upper surface of the substrate layer (1000), just like the substrate layer (1000), but only one of the crystal planes of orientations (111) and (113) may be deflected by α with respect to an axis perpendicular to the upper surface of the substrate layer (1000) (= axis perpendicular to the ground).

[0111] However, according to one embodiment of the present invention, when the crystal plane of the substrate layer (1000) is deviated by θ, the crystal plane of the diamond layer (3000) may be deviated by α, and θ and α may correspond to each other. At this time, the fact that θ and α correspond to each other may mean that the error rate of θ and α is 20% or less. In other words, θ and α may correspond to each other within a range having an error of 20% or less, satisfying each of the inequalities -10° ≤ θ ≤ 10° and -10° ≤ α ≤ 10°.

[0113] According to one embodiment of the present invention, the substrate layer (1000) can have the effect of improving the quality of the diamond layer (3000) by having the crystal planes deviated.

[0114] In addition, the substrate layer (1000) according to one embodiment of the present invention can improve the crystallinity and quality of the diamond layer (3000) by having a crystal plane angled, thereby having the effect of increasing the heat dissipation and insulation characteristics of the diamond layer (3000).

[0115] The semiconductor integrated device (1) according to one embodiment of the present invention can have improved electrical characteristics and extended lifespan by improving the heat dissipation and insulation characteristics of the diamond layer (3000).

[0117] FIG. 3 schematically illustrates a perspective view of a semiconductor integrated element (1) according to one embodiment of the present invention.

[0119] According to one embodiment of the present invention, the nitride semiconductor layer (4000) further comprises a first electrode (4300) disposed on the nitride element layer (4200), and the first electrode (4300) may include a first source (4310), a first gate (4320) formed spaced apart from the first source (4310), and a first drain (4330) formed spaced apart from each of the first source (4310) and the first gate (4320).

[0121] As illustrated in FIG. 3, the semiconductor integrated device (1) according to one embodiment of the present invention may include the substrate layer (1000), the buffer layer (2000), the diamond layer (3000), and the nitride semiconductor layer (4000) as described above. Additionally, the semiconductor integrated device (1) may further include a first electrode (4300) disposed on the nitride semiconductor layer (4000).

[0122] Specifically, the nitride semiconductor layer (4000) may include the buffer nitride layer (4100) and the nitride element layer (4200), and the first electrode (4300) may be disposed on the nitride element layer (4200). The first electrode (4300) may each include a first source (4310), a first gate (4320), and a first drain (4330). The first electrode (4300) may be disposed on a portion of the upper surface of the nitride element layer (4200).

[0123] Meanwhile, the first gate (4320) may be placed in a portion of the upper surface of the nitride element layer (4200) where the first source (4310) is not placed, and may be formed spaced apart from the first source (4310). The first drain (4330) may be placed in a portion of the upper surface of the nitride element layer (4200) where the first source (4310) and the first gate (4320) are not placed, and may be formed spaced apart from the first source (4310) and the first gate (4320), respectively.

[0124] According to one embodiment of the present invention, the semiconductor integrated element (1) can be connected to an external circuit by including the first electrode (4300). Specifically, the semiconductor integrated element (1) can apply voltage or current to the nitride semiconductor layer (4000) through the first electrode (4300). Additionally, an electrical signal generated in the semiconductor integrated element (1) can be transmitted to an external circuit through the first electrode (4300).

[0126] FIG. 4 schematically illustrates the manufacturing steps of a semiconductor integrated device (1) according to one embodiment of the present invention, and FIG. 5 schematically illustrates the detailed steps of a nitride semiconductor placement step (S40) according to one embodiment of the present invention.

[0128] According to one embodiment of the present invention, a method for manufacturing a semiconductor integrated device (1) comprises: a substrate preparation step (S10) for preparing a substrate layer (1000); a buffer placement step (S20) for placing a buffer layer (2000) on the substrate layer (1000); a diamond placement step (S30) for placing a diamond layer (3000) on the buffer layer (2000); and a nitride semiconductor placement step (S40) for placing a nitride semiconductor layer (4000) on the diamond layer (3000); wherein the diamond layer (3000) comprises a single-crystal diamond having a crystal plane orientation of either (111) or (113).

[0129] According to one embodiment of the present invention, the semiconductor integrated device (1) can use the remaining diamond layer (3000) and nitride semiconductor after removing the substrate layer (1000) and buffer layer (2000) respectively as the semiconductor integrated device (1), and the method for manufacturing the semiconductor integrated device (1) may further include a lower layer removal step (S50) in which the substrate layer (1000) and buffer layer (2000) respectively are removed and only the diamond layer (3000) and nitride semiconductor layer (4000) are left.

[0130] According to one embodiment of the present invention, the diamond layer (3000) is formed on the buffer layer (2000) by chemical vapor deposition (CVD) and 0.5 W / mm 2 Up to 5W / mm 2 It can be formed at a growth rate of 0.01 to 100 μm / hr under plasma power, pressure of 0 to 1000 torr, and temperature of 100 to 1300°C.

[0132] As illustrated in FIG. 4, according to one embodiment of the present invention, the semiconductor integrated device (1) can be manufactured by performing a substrate preparation step (S10), a buffer placement step (S20), a diamond placement step (S30), and a nitride semiconductor placement step (S40). In the case of the lower layer removal step (S50) illustrated in FIG. 4, it may be performed optionally, unlike the substrate preparation step (S10), the buffer placement step (S20), the diamond placement step (S30), and the nitride semiconductor placement step (S40). A more specific description of the lower layer removal step (S50) will be provided in the drawings described later.

[0134] Specifically, in the substrate preparation step (S10), the substrate layer (1000) can be prepared. As described above, the substrate layer (1000) according to one embodiment of the present invention may include any one of a sapphire substrate (Al2O3), a silicon (Si) substrate, a silicon carbide (SiC) substrate, a nitride substrate, and a diamond substrate.

[0135] Additionally, the substrate layer (1000) may have a crystal plane of a specific orientation. According to one embodiment of the present invention, the crystal plane of the specific orientation may be a crystal plane capable of growing into a single-crystal diamond having either a crystal plane of orientations (111) and (113). Meanwhile, the substrate layer (1000) may perform a role of assisting the diamond layer (3000) to grow into a single-crystal diamond having either a crystal plane of orientations (111) and (113) by being formed such that the crystal plane of the specific orientation has an angle of deviation of -10 to 10° with respect to an axis perpendicular to the ground.

[0136] When the above substrate preparation step (S10) is completed, the above buffer placement step (S20) may be performed. When the above buffer placement step (S20) is performed, the above buffer layer (2000) may be placed on the above substrate layer (1000). As described above, the above buffer layer (2000) may be either a single layer or a multilayer structure including one or more layers. In addition, each of the one or more layers included in the above buffer layer (2000) may include one or more of a metal material and an oxide material.

[0137] Meanwhile, the buffer layer (2000) acts as a buffer to mitigate the lattice mismatch between the substrate layer (1000) and the diamond layer (3000), thereby preventing the formation of defects in the diamond layer (3000) due to the lattice mismatch with the substrate layer (1000).

[0139] That is, each of the substrate layer (1000) and the buffer layer (2000) according to one embodiment of the present invention performs the role of preventing defects in the diamond layer (3000), thereby forming the diamond layer (3000) with high quality and thereby having the effect of improving the performance of the semiconductor integrated device (1).

[0141] When the buffer placement step (S20) is completed, the diamond placement step (S30) may be performed. When the diamond placement step (S30) is performed, the diamond layer (3000) may be placed on top of the buffer layer (2000). As described above, the diamond layer (3000) may include a single-crystal diamond having an orientation of either (111) or (113) and may be formed to have a thickness of 5 to 500 μm.

[0142] According to one embodiment of the present invention, when the crystal plane of the substrate layer (1000) has an angle of deviation of -10 to 10°, the crystal plane having an orientation of either (111) or (113) of the diamond layer (3000) may be formed to have an angle of deviation of -10 to 10° with respect to an axis perpendicular to the upper surface of the substrate layer (1000). At this time, the angles of the crystal plane of the substrate layer (1000) and the crystal plane of the diamond layer (3000), respectively, may have corresponding angles within the range of -10 to 10°. As described above, having corresponding angles may mean that the error rate of the two angles is 20% or less.

[0143] According to one embodiment of the present invention, the diamond layer (3000) is formed on the substrate layer (1000) in which the crystal plane is angled, so that it can be grown to have one of the crystal planes of orientations (111) and (113), and defect formation can be relatively prevented.

[0145] That is, the diamond layer (3000) according to one embodiment of the present invention is formed to have a high-quality single-crystal thin film structure by the angle of the substrate layer (1000), and can exhibit the effect of improving thermal conductivity, charge mobility, and voltage resistance.

[0146] In addition, the semiconductor integrated device (1) according to one embodiment of the present invention can exhibit the effect of improving economic efficiency and usability by preventing failure and shortening of lifespan due to heat generation, as the heat dissipation performance is enhanced by improving the thermal conductivity, charge mobility, and voltage resistance of the diamond layer (3000).

[0148] According to one embodiment of the present invention, in the diamond placement step (S30), the diamond layer (3000) may be formed by a chemical vapor deposition (CVD) method. Specifically, the diamond layer (3000) is 0.5 W / mm 2 Up to 5W / mm 2 It can be formed on the buffer layer (2000) at a growth rate of 0.01 to 100 μm / hr under plasma power, pressure of 0 to 1000 torr, and temperature of 100 to 1300°C.

[0149] Preferably, the diamond layer (3000) is 1 to 4 W / mm 2 It is preferable that the diamond layer (3000) be formed at a growth rate of 0.1 to 80 μm / hr under plasma power, a pressure of 10 to 800 torr, and a temperature of 300 to 1200°C. More preferably, the diamond layer (3000) is formed at a growth rate of 2 to 3 W / mm 2 It is preferable that the buffer layer (2000) be formed at a growth rate of 1 to 50 μm / hr under plasma power, a pressure of 100 to 500 torr, and a temperature of 500 to 1000°C.

[0151] When the above diamond placement step (S30) is completed, the above nitride semiconductor placement step (S40) may be performed. When the above nitride semiconductor placement step (S40) is performed, the above nitride semiconductor layer (4000) may be placed on the diamond layer (3000). As described above, the above nitride semiconductor layer (4000) may each include a buffer nitride layer (4100) placed on the diamond layer (3000), a nitride element layer (4200) placed on the buffer nitride layer (4100), and a first electrode (4300) placed on the nitride element layer (4200).

[0152] Accordingly, the nitride semiconductor placement step (S40) according to one embodiment of the present invention may further include detailed steps of a buffer nitride placement step (S41), a nitride device placement step (S42), and a first electrode placement step (S43) as illustrated in FIG. 5.

[0154] According to one embodiment of the present invention, the nitride semiconductor placement step (S40) comprises: a buffer nitride placement step (S41) for placing a buffer nitride layer (4100) comprising aluminum nitride (AlN) having an orientation of (0001); and aluminum gallium nitride (Al x Ga 1-x The method further includes a detailed step of a nitride element placement step (S42) of placing a nitride element layer (4200) containing N on the buffer nitride layer (4100), and the nitride element layer (4200) may be a multilayer structure including two or more layers.

[0155] According to one embodiment of the present invention, the nitride semiconductor placement step (S40) further includes a detailed step of a first electrode placement step (S43) of placing a first electrode (4300) on the nitride element layer (4200), and the first electrode (4300) may include a first source (4310), a first gate (4320) formed spaced apart from the first source (4310), and a first drain (4330) formed spaced apart from each of the first source (4310) and the first gate (4320).

[0156] According to one embodiment of the present invention, the nitride semiconductor layer (4000) can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0158] Specifically, when the diamond placement step (S30) is completed, the buffer nitride placement step (S41) included in the nitride semiconductor placement step (S40) may be performed. When the buffer nitride placement step (S41) is performed, the buffer nitride layer (4100) may be placed on top of the diamond layer (3000).

[0159] As described above, the buffer nitride layer (4100) according to one embodiment of the present invention may include aluminum nitride (AlN) having a crystal plane with an orientation of (0001). Additionally, the thickness of the buffer nitride layer (4100) may be 1 to 1000 nm. Preferably, the thickness of the buffer nitride layer (4100) is 10 to 500 nm. More preferably, the thickness of the buffer nitride layer (4100) is 20 to 300 nm.

[0160] According to one embodiment of the present invention, the buffer nitride layer (4100) can induce a lattice match between the diamond layer (3000) and the nitride element layer (4200). Specifically, the diamond layer (3000) comprises a single-crystal diamond having a crystal plane of either the (111) orientation or the (113) orientation, and the nitride element layer (4200) comprises a single-crystal aluminum gallium nitride (Al) having a crystal plane of the (0001) orientation. x Ga 1-x It may include N). Meanwhile, the buffer nitride layer (4100) may include aluminum nitride having a crystal plane of (0001) orientation.

[0161] According to one embodiment of the present invention, the lattice parameter of the buffer nitride layer (4100) may have a value smaller than the lattice parameter of the diamond layer (3000) and larger than the lattice parameter of the nitride element layer (4200). In other words, the buffer nitride layer (4100) is formed to have a value corresponding to the intermediate range of the lattice parameters of the diamond layer (3000) and the nitride element layer (4200), respectively, thereby serving as a buffer to mitigate the lattice mismatch between the diamond layer (3000) and the nitride element layer (4200).

[0163] Meanwhile, the nitride element layer (4200) may be placed on top of the buffer nitride layer (4100) when the nitride element placement step (S42) is performed after the buffer nitride placement step (S41) is completed. As described above, the nitride element layer (4200) is aluminum gallium nitride (Al x Ga 1-x It may include N), and may be a multilayer structure including two or more layers. Each of the two or more layers included in the nitride element layer (4200) is aluminum gallium nitride (Al x Ga 1-x It may include N).

[0164] According to one embodiment of the present invention, aluminum gallium nitride (Al) included in the nitride element layer (4200) x Ga 1-x N) can have a crystal plane of (0001) orientation and can be formed as a single crystal. In other words, the aluminum gallium nitride (Al) included in the nitride element layer (4200) x Ga 1-x N) is a single crystal aluminum gallium nitride (Al) formed to have an orientation (0001) corresponding to the crystal plane of aluminum nitride included in the buffer nitride layer (4100). x Ga 1-x N) It ​​can be.

[0165] Generally, when a material is formed in the form of a single crystal, the durability and electrical characteristics of the device can be improved by preventing the formation of grain boundaries, a type of crystal defect, within the material.

[0167] That is, according to one embodiment of the present invention, the nitride element layer (4200) is a gallium aluminum nitride (Al) having a crystal plane of orientation (0001) on a diamond layer (3000) having a crystal plane of orientation (0001) on which a crystal plane has an orientation of either (111) or (113). x Ga 1-x By being formed to include N), it can grow into the form of a single crystal, thereby producing an effect that improves the crystallinity and durability of the semiconductor integrated device (1).

[0168] In addition, according to one embodiment of the present invention, the nitride element layer (4200) is formed on the diamond layer (3000) to prevent the occurrence of defects in the nitride element layer (4200) and to improve the electrical performance of the nitride semiconductor layer (4000).

[0169] According to one embodiment of the present invention, the nitride semiconductor layer (4000) is formed on a diamond layer (3000) having a crystal plane having an orientation of either (111) or (113), thereby improving interfacial adhesion with the diamond layer (3000) and enabling the effect of preventing peeling and breakage.

[0171] Meanwhile, according to one embodiment of the present invention, aluminum gallium nitride (Al) included in the nitride element layer (4200) x Ga 1-x x of N) can satisfy the inequality 0 ≤ x < 1. In addition, each of the two or more layers included in the nitride element layer (4200) is aluminum gallium nitride (Al x Ga 1-xIt includes N), but may have different x values. A more detailed description of the multilayer structure and composition of the nitride element layer (4200) will be provided in the drawings described later.

[0173] According to one embodiment of the present invention, the nitride semiconductor layer (4000) formed in the nitride semiconductor placement step (S40) can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C. Specifically, the buffer nitride layer (4100) formed in the buffer nitride placement step (S41) and the nitride device placement step (S42) formed in the nitride device placement step (S42) can each be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0174] Preferably, the nitride semiconductor layer (4000) is formed at a growth rate of 0.1 to 800 μm / hr under conditions of a pressure of 10 to 800 torr and a temperature of 500 to 1300°C. More preferably, the nitride semiconductor layer (4000) is formed at a growth rate of 1 to 500 μm / hr under conditions of a pressure of 50 to 500 torr and a temperature of 600 to 1000°C.

[0176] When the above nitride element placement step (S42) is completed, the above first electrode placement step (S43) may be performed. According to one embodiment of the present invention, when the above first electrode placement step (S43) is performed, the above first electrode (4300) may be placed on the upper surface of the above nitride element layer (4200).

[0177] Specifically, as described above, the first electrode (4300) may include a first source (4310), a first gate (4320), and a first drain (4330). That is, in the first electrode placement step (S43), each of the first source (4310), the first gate (4320), and the first drain (4330) may be formed.

[0178] At this time, the first source (4310) may be placed in a portion of the upper surface of the nitride element layer (4200). The first gate (4320) may be formed in a portion of the upper surface of the nitride element layer (4200) where the first source (4310) is not placed, and may be spaced apart from the first source (4310). Additionally, the first drain (4330) may be placed in a portion of the upper surface of the nitride element layer (4200) where the first source (4310) and the first gate (4320) are not placed, and may be spaced apart from the first source (4310) and the first gate (4320), respectively.

[0180] According to one embodiment of the present invention, the semiconductor integrated device (1) can be completed when the nitride semiconductor placement step (S40) is terminated by performing each of the buffer nitride placement step (S41), the nitride device placement step (S42), and the first electrode placement step (S43). However, according to one embodiment of the present invention, the manufacturing process of the semiconductor integrated device (1) may additionally perform the lower layer removal step (S50). As described above, the lower layer removal step (S50) may be performed optionally.

[0181] Specifically, when the lower layer removal step (S50) is performed, the substrate layer (1000) and the buffer layer (2000) can each be removed from the semiconductor integrated device (1). That is, the semiconductor integrated device (1) in which the lower layer removal step (S50) is performed may include only the diamond layer (3000) and the nitride semiconductor layer (4000), respectively. According to one embodiment of the present invention, the semiconductor integrated device (1) can operate even when the substrate layer (1000) and the buffer layer (2000) are each removed.

[0182] In other words, if the lower layer removal step (S50) is not performed, the semiconductor integrated device (1) may include the substrate layer (1000), the buffer layer (2000), the diamond layer (3000), and the nitride semiconductor layer (4000), respectively. Meanwhile, if the lower layer removal step (S50) is performed, the semiconductor integrated device (1) may include only the diamond layer (3000) and the nitride semiconductor, respectively. A more detailed description of the semiconductor integrated device (1) in which the lower layer removal step (S50) is performed will be provided in the drawings described later.

[0184] FIG. 6 schematically illustrates a perspective view of a semiconductor integrated device (1) having a two-dimensional electron gas (E) formed therein according to one embodiment of the present invention.

[0186] According to one embodiment of the present invention, the nitride semiconductor layer (4000) comprises a nitride device layer (4200) having a multilayer structure including two or more layers; and the nitride device layer (4200) is composed of a plurality of layers, wherein each of the plurality of layers has a different x value and is made of aluminum gallium nitride (Al). x Ga 1-x It may be a Field Effect Transistor (FET) structure that includes N) and has either a 2-dimensional electron gas (E) (2DEG) or a 2-dimensional hole gas (2DHG) formed on the inside.

[0188] As illustrated in FIG. 6, the semiconductor integrated device (1) according to one embodiment of the present invention comprises a substrate layer (1000), a buffer layer (2000), a diamond layer (3000), and a nitride semiconductor layer (4000), wherein the nitride semiconductor layer (4000) has a multilayer structure comprising two or more layers, and a two-dimensional electron gas (E) (2DEG) may be formed in any one of the two or more layers.

[0190] Specifically, according to one embodiment of the present invention, the nitride element layer (4200) may be a multilayer structure including a channel layer (4210-1) and a barrier layer (4210-2). As shown in FIG. 6, according to one embodiment of the present invention, the channel layer (4210-1) may be placed on top of the buffer nitride layer (4100), and the barrier layer (4210-2) may be placed on top of the channel layer (4210-1).

[0192] As described above, when the nitride element layer (4200) is a multilayer structure comprising two or more layers, each of the two or more layers included in the nitride element layer (4200) is aluminum gallium nitride (Al x Ga 1-x It may include N). In this case, gallium aluminum nitride is Al x Ga 1-x It is expressed by the chemical formula of N, and x in the said chemical formula may be 0 or greater and less than 1. In addition, aluminum gallium nitride (Al) included in each of the two or more layers included in the nitride element layer (4200) x Ga 1-x N) can have different x values. In addition, aluminum gallium nitride (Al) included in the nitride element layer (4200) x Ga 1-x N) may be a single crystal having a crystal plane of (0001) orientation.

[0193] In other words, according to one embodiment of the present invention, each of the channel layer (4210-1) and the barrier layer (4210-2) is a single-crystal structure of aluminum gallium nitride (Al) having a crystal plane of (0001) orientation. x Ga 1-x It may include N). In addition, aluminum gallium nitride (Al nitride) included in the channel layer (4210-1) x Ga 1-x aluminum gallium nitride (Al N) contained in x and the barrier layer (4210-2) x Ga 1-x Each x of N) can have different values ​​within a range satisfying the condition 0 ≤ x < 1. That is, each of the channel layer (4210-1) and the barrier layer (4210-2) is made of gallium aluminum nitride (Al x Ga 1-x It includes N), but the detailed composition may differ.

[0195] According to one embodiment of the present invention, aluminum gallium nitride (Al) included in the channel layer (4210-1) x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) contained in the barrier layer (4210-2). x Ga 1-x It may be smaller than the x value of N). For example, aluminum gallium nitride (Al) included in the channel layer (4210-1). x Ga 1-x The x value of N) is referred to as x1, and the aluminum gallium nitride (Al) included in the barrier layer (4210-2) is x Ga 1-x The x value of N) can be referred to as x2. In this case, x1 and x2 each have 0 ≤ x1 <x2<1의 부등식을 만족할 수 있다.

[0196] Meanwhile, the channel layer (4210-1) according to one embodiment of the present invention may include a two-dimensional electron gas (E) inside. The two-dimensional electron gas (E) may be a single layer in which electrons are arranged at a high density within a specific area range. In addition, high-speed movement of electrons may be possible within the region of the two-dimensional electron gas (E). According to one embodiment of the present invention, the two-dimensional electron gas (E) may be arranged inside the channel layer (4210-1) parallel to the ground, and may be arranged adjacent to the interface between the channel layer (4210-1) and the barrier layer (4210-2).

[0198] According to one embodiment of the present invention, the barrier layer (4210-2) is aluminum gallium nitride (Al) with an x ​​value greater than that of the channel layer (4210-1). x Ga 1-x It includes N) and is positioned on the channel layer (4210-1) to induce the formation of a two-dimensional electron gas (E) inside the channel layer (4210-1).

[0199] Specifically, according to one embodiment of the present invention, aluminum gallium nitride (Al) included in each of the channel layer (4210-1) and the barrier layer (4210-2) x Ga 1-x Because the detailed composition of N) is different, the Fermi energy level (E) of each of the channel layer (4210-1) and barrier layer (4210-2) f ) can be placed at different locations. For example, when two materials having different Fermi energy levels come into contact, the Fermi energy levels have a tendency to align at corresponding locations. Therefore, band bending, in which the band bends at the interface, may occur in each of the two materials.

[0200] Accordingly, when the barrier layer (4210-2) is placed on the channel layer (4210-1), a band bending phenomenon occurs at the interface between the channel layer (4210-1) and the barrier layer (4210-2), thereby forming a quantum well. A plurality of electrons that have crossed over to the interface between the barrier layer (4210-2) and the channel layer (4210-1) along the bent band are trapped in the quantum well, thereby forming the two-dimensional electron gas (E).

[0201] That is, according to one embodiment of the present invention, the two-dimensional electron gas (E) may be disposed inside the interface of the channel layer (4210-1) bonded with the barrier layer (4210-2) and may exist in the form of a layer in which electrons move in a direction horizontal to the surface of the channel layer (4210-1). The two-dimensional electron gas (E) may operate as a channel for electron movement and thus may play a role in inducing current to flow in the channel layer (4210-1). According to one embodiment of the present invention, the two-dimensional electron gas (E) may be formed inside the channel layer (4210-1) even when no voltage is applied to the first electrode (4300).

[0203] Meanwhile, the semiconductor integrated circuit (1) can operate as a field-effect transistor (FET) by including a first electrode (4300) comprising a first source (4310), a first gate (4320), and a first drain (4330), each spaced apart from each other and disposed on the upper side of the nitride semiconductor layer (4000). Generally, the FET may be a device that controls the current flowing through the first source (4310) and the first drain (4330) by controlling the voltage applied to the first gate (4320). The FET may include a channel, and the channel may be disposed between the first source (4310) and the first drain (4330). Additionally, the current flow in the channel may be controlled by the voltage applied to the first gate (4320).

[0204] As previously described, the two-dimensional electron gas (E) formed inside the channel layer (4210-1) can operate as a channel through which electrons move, and may be formed inside the channel layer (4210-1) even when no voltage is applied to the first electrode (4300). Accordingly, the semiconductor integrated device (1) according to one embodiment of the present invention can function as a D-mode FET that maintains an always-on state by including a channel through which electrons can move even when no voltage is applied to the first electrode (4300).

[0206] Although not illustrated in FIG. 6, according to one embodiment of the present invention, the nitride element layer (4200) may further include a capping layer disposed on top of the barrier layer (4210-2). In other words, the nitride element layer (4200) according to one embodiment of the present invention may be a multilayer structure that further includes other layers in addition to the channel layer (4210-1) and the barrier layer (4210-2). However, even if the nitride element layer (4200) has a multilayer structure that includes three or more layers by including other layers, the barrier layer (4210-2) may be disposed on top of the channel layer (4210-1).

[0208] Additionally, although not illustrated in FIG. 6, the semiconductor integrated device (1) according to one embodiment of the present invention comprises a substrate layer (1000), a buffer layer (2000), a diamond layer (3000), and a nitride semiconductor layer (4000), wherein the nitride semiconductor layer (4000) has a multilayer structure comprising two or more layers, and a two-dimensional hole gas (2DHG) may be formed in any one of the two or more layers. When the two-dimensional hole gas is formed, the two-dimensional hole gas may operate as a channel for holes to move within any one of the two or more layers of the nitride semiconductor layer (4000).

[0210] According to one embodiment of the present invention, the nitride element layer (4200) is aluminum gallium nitride (Al) having different detailed compositions. x Ga 1-x By having a multilayer structure composed of a channel layer (4210-1) and a barrier layer (4210-2) including N), one of the two-dimensional electron gas (E) and two-dimensional hole gas is formed inside the channel layer (4210-1), thereby enabling the effect of improving the performance of the semiconductor integrated device (1).

[0211] In addition, the semiconductor integrated device (1) according to one embodiment of the present invention can exhibit the effect of improving electrical performance by improving electron mobility and reducing switching loss through the two-dimensional electron gas (E).

[0212] Meanwhile, the semiconductor integrated device (1) according to one embodiment of the present invention can exhibit the effect of improving electrical performance by improving hole mobility through the two-dimensional hole gas.

[0214] FIG. 7 schematically illustrates a perspective view of a semiconductor integrated device (1) including a nitride element layer (4200) doped with p-type or n-type according to one embodiment of the present invention.

[0216] According to one embodiment of the present invention, the nitride semiconductor layer (4000) is aluminum gallium nitride (Al x Ga 1-x A nitride element layer (4200) having a multilayer structure including N); wherein the nitride element layer (4200) may each include an undoped layer (4220-1); and a doped layer (4220-2) doped with either n-type or p-type.

[0217] According to one embodiment of the present invention, the nitride element layer (4200) may have a structure of either a transistor structure or a diode structure.

[0219] As illustrated in FIG. 7, the semiconductor integrated device (1) according to one embodiment of the present invention comprises a substrate layer (1000), a buffer layer (2000), a diamond layer (3000), and a nitride semiconductor layer (4000), wherein the nitride semiconductor layer (4000) may comprise a nitride element layer (4200) having a multilayer structure comprising two or more layers. Additionally, the nitride element layer (4200) may be aluminum gallium nitride (Al x Ga 1-x It may include N).

[0220] As described above, each of the two or more layers included in the nitride element layer (4200) is all aluminum gallium nitride (Al x Ga 1-x It may include N). Aluminum gallium nitride (Al) included in the nitride element layer (4200). x Ga 1-x N) is a single-crystal aluminum gallium (Al) having a crystal plane of (0001) orientation. x Ga 1-x It can be N). In this case, gallium aluminum nitride (Al x Ga 1-x The x value of N) can be 0 or greater and less than 1.

[0222] Specifically, as illustrated in FIG. 7, the nitride element layer (4200) may be a multilayer structure comprising a non-doped layer (4220-1) and a doped layer (4220-2), respectively. According to one embodiment of the present invention, the non-doped layer (4220-1) is aluminum gallium nitride (Al x Ga 1-x It may be a layer that includes N) but is not doped. Meanwhile, the doping layer (4220-2) according to one embodiment of the present invention is aluminum gallium nitride (Al x Ga 1-x It may be a layer containing N) and doped with n-type or p-type. In other words, the doping layer (4220-2) may further include either an n-type dopant or a p-type dopant.

[0223] FIG. 7 illustrates a nitride element layer (4200) having a total of two layers, each comprising one layer of a non-doped layer (4220-1) and one layer of a doped layer (4220-2). However, according to one embodiment of the present invention, the nitride element layer (4200) may have a multilayer structure comprising two or more layers. That is, the nitride element layer (4200) according to one embodiment of the present invention may include one or more non-doped layers (4220-1) and one or more doped layers (4220-2).

[0224] According to one embodiment of the present invention, the nitride element layer (4200) may have the doping layer (4220-2) disposed on the non-doping layer (4220-1), or the non-doping layer (4220-1) disposed on the doping layer (4220-2). Additionally, when the nitride element layer (4200) includes each of a plurality of non-doping layers (4220-1) and a plurality of doping layers (4220-2), each of the plurality of non-doping layers (4220-1) and the plurality of doping layers (4220-2) may be arranged intersectingly with one another, each of the plurality of doping layers (4220-2) may be arranged adjacently to one another, and the plurality of non-doping layers (4220-1) may be disposed on one or more of the lower and upper sides of the plurality of doping layers (4220-2). That is, the arrangement of the non-doping layer (4220-1) and the doping layer (4220-2) according to one embodiment of the present invention can be freely changed during the manufacturing step of the semiconductor integrated device (1).

[0226] According to one embodiment of the present invention, when the nitride element layer (4200) includes two or more doping layers (4220-2), one of the two or more doping layers (4220-2) may be doped with n-type, and the remaining doping layer (4220-2) that is not doped with n-type may be doped with p-type. At this time, the doping layer (4220-2) doped with n-type and the doping layer (4220-2) doped with p-type may each be arranged adjacent to each other to form a pn junction in the nitride element layer (4200).

[0227] According to one embodiment of the present invention, the nitride element layer (4200) may have a diode structure by including a pn junction. That is, the semiconductor integrated device (1) may operate as a diode device that moves charge through doping by doping, as the doping layer (4220-2) is doped as n-type or p-type.

[0228] According to one embodiment of the present invention, when the semiconductor integrated device (1) has a diode structure including a pn junction, the semiconductor integrated device (1) can perform rectification and amplification operations for charge.

[0230] Meanwhile, according to one embodiment of the present invention, the semiconductor integrated element (1) may operate as a transistor by including a first electrode (4300) comprising a first source (4310), a first gate (4320), and a first drain (4330), each spaced apart from each other and disposed on the upper side of the nitride semiconductor layer (4000).

[0232] According to one embodiment of the present invention, when the semiconductor integrated device (1) includes a doping layer (4220-2) doped with p-type or n-type, it can operate as a transistor or diode device, thereby enabling the device to have an effect of improving usability.

[0234] FIG. 8 schematically illustrates a semiconductor integrated device (1) including a diamond semiconductor layer (5000) according to one embodiment of the present invention.

[0236] According to one embodiment of the present invention, the nitride semiconductor layer (4000) is partially disposed in a portion of the upper surface of the diamond layer (3000), and the semiconductor integrated element (1) may further include a diamond semiconductor layer (5000) which is partially disposed in another portion of the upper surface of the diamond layer (3000) where the nitride semiconductor layer (4000) is not disposed, and which is spaced apart from the nitride semiconductor layer (4000).

[0237] According to one embodiment of the present invention, the dia semiconductor layer (5000) further includes a second electrode (5100) disposed on the upper surface, and the second electrode (5100) may include a second source (5110), a second gate (5120) formed spaced apart from the second source (5110), and a second drain (5130) formed spaced apart from each of the second source (5110) and the second gate (5120).

[0238] According to one embodiment of the present invention, the first electrode (4300) and the second electrode (5100) can each be electrically connected to each other to form an integrated circuit.

[0240] FIG. 8(a) schematically illustrates a front view of a semiconductor integrated device (1) including a diamond semiconductor layer (5000) according to one embodiment of the present invention, and FIG. 8(b) schematically illustrates a perspective view of a semiconductor integrated device (1) including a diamond semiconductor layer (5000) according to one embodiment of the present invention.

[0242] As illustrated in FIGS. 8(a) and FIGS. 8(b), a semiconductor integrated device (1) according to one embodiment of the present invention may include a substrate layer (1000), a buffer layer (2000), a diamond layer (3000), a nitride semiconductor layer (4000), and a diamond semiconductor layer (5000). Each of the substrate layer (1000), the buffer layer (2000), and the diamond layer (3000) may have the buffer layer (2000) disposed on the substrate layer (1000) and the diamond layer (3000) disposed on the buffer layer (2000), as described above in FIGS. 1 to 7.

[0243] Meanwhile, the nitride semiconductor layer (4000) according to one embodiment of the present invention may be disposed on the diamond layer (3000), and may be partially disposed in a portion of the upper surface of the diamond layer (3000). Additionally, the diamond semiconductor layer (5000) may be disposed on the upper surface of the diamond layer (3000), and may be partially disposed in another portion of the upper surface of the diamond layer (3000) where the nitride semiconductor layer (4000) is not disposed. The nitride semiconductor layer (4000) and the diamond semiconductor layer (5000) may each be disposed spaced apart from each other.

[0245] Specifically, the nitride semiconductor layer (4000) may include the buffer nitride layer (4100) and the nitride element layer (4200) as described above. According to one embodiment of the present invention, the buffer nitride layer (4100) may include aluminum nitride (AlN) having a crystal plane with an orientation of (0001), and the nitride element layer (4200) may include single-crystal aluminum gallium nitride (AlN) having a crystal plane with an orientation of (0001). x Ga 1-x It may include N). Aluminum gallium nitride (Al) included in the nitride element layer (4200). x Ga 1-x The x value of N) may be 0 or greater and less than 1. Additionally, the nitride element layer (4200) may be a multilayer structure including two or more layers, and each of the two or more layers is aluminum gallium nitride (Al x Ga 1-x It may include N).

[0246] According to one embodiment of the present invention, the nitride element layer (4200) included in the semiconductor integrated device (1) may have a multilayer structure including a channel layer (4210-1) and a barrier layer (4210-2), as described above in FIG. 6, and including either a two-dimensional electron gas (E) or a two-dimensional hole gas inside the channel layer (4210-1). Alternatively, according to one embodiment of the present invention, the nitride element layer (4200) may have a transistor structure or a diode structure, as described above in FIG. 7, including a non-doping layer (4220-1) and a doping layer (4220-2).

[0248] Meanwhile, the diamond semiconductor layer (5000) according to one embodiment of the present invention may be disposed on the diamond layer (3000) and spaced apart from the nitride semiconductor layer (4000). According to one embodiment of the present invention, the diamond semiconductor layer (5000) may include a single crystal diamond having a crystal plane orientation of either (111) or (113) corresponding to the diamond layer (3000).

[0249] According to one embodiment of the present invention, the dia semiconductor layer (5000) may operate as a transistor or a diode. Additionally, although not shown in the drawings, the dia semiconductor layer (5000) according to one embodiment of the present invention may further include a 2-dimensional hole gas (2DHG) inside.

[0250] According to one embodiment of the present invention, when the dia semiconductor layer (5000) further includes the two-dimensional hole gas, the two-dimensional hole gas can operate as a channel through which holes can move within the dia semiconductor layer (5000). The two-dimensional hole gas may be formed inside the dia semiconductor layer (5000) even when no voltage is applied to the dia semiconductor layer (5000).

[0251] A second electrode (5100) may be disposed on the upper surface of the above-described diamond semiconductor layer (5000). According to one embodiment of the present invention, the second electrode (5100) may include a second source (5110), a second gate (5120), and a second drain (5130). The second source (5110) may be disposed in a portion of the upper surface of the above-described diamond semiconductor layer (5000). The second gate (5120) may be disposed in another portion of the upper surface of the above-described diamond semiconductor layer (5000) where the second source (5110) is not disposed, and may be disposed spaced apart from the second source (5110). Meanwhile, the second drain (5130) may be placed in a portion of the upper surface of the diamond semiconductor layer (5000) where the second source (5110) and the second gate (5120) are not placed, and may be placed spaced apart from each of the second source (5110) and the second gate (5120).

[0253] According to one embodiment of the present invention, the first electrode (4300) disposed on the nitride semiconductor layer (4000) and the second electrode (5100) disposed on the dia semiconductor layer (5000) can each be electrically connected to each other. When the first electrode (4300) and the second electrode (5100) are each electrically connected to each other, the nitride semiconductor layer (4000) and the dia semiconductor layer (5000) can form an integrated circuit.

[0254] According to one embodiment of the present invention, when the semiconductor integrated device (1) further includes the diamond semiconductor layer (5000) and the first electrode (4300) and the second electrode (5100) are connected to each other to form an integrated circuit, the semiconductor integrated device (1) can operate as a CMOS (complementary metal-oxide semiconductor).

[0256] That is, the semiconductor integrated device (1) according to one embodiment of the present invention can form an integrated circuit by including each of the nitride semiconductor layer (4000) and the diamond semiconductor layer (5000), thereby having the effect of expanding the usability of the device.

[0258] Hereinafter, the semiconductor integrated device (1) including the substrate layer (1000), buffer layer (2000), diamond layer (3000), and nitride semiconductor layer (4000) shown in FIGS. 3, 6, and 7 will be referred to as Example 1. Additionally, the semiconductor integrated device (1) including the substrate layer (1000), buffer layer (2000), diamond layer (3000), nitride semiconductor layer (4000), and diamond semiconductor layer (5000) shown in FIG. 8 will be referred to as Example 2.

[0260] FIG. 9 schematically illustrates a semiconductor integrated device (1) with the substrate layer (1000) and buffer layer (2000) removed according to one embodiment of the present invention.

[0262] According to one embodiment of the present invention, the semiconductor integrated element (1) may be able to operate even when the substrate layer (1000) and the buffer layer (2000) are each removed.

[0264] FIG. 9(a) schematically illustrates the case in which the substrate layer (1000) and the buffer layer (2000) are removed from the semiconductor integrated device (1) of Example 1, and FIG. 9(b) schematically illustrates the case in which the substrate layer (1000) and the buffer layer (2000) are removed from the semiconductor integrated device (1) of Example 2.

[0265] Hereinafter, the semiconductor integrated device (1) in which the substrate layer (1000) and the buffer layer (2000) are removed in Example 1 shown in FIG. 9(a) will be referred to as Example 3, and the semiconductor integrated device (1) in which the substrate layer (1000) and the buffer layer (2000) are removed in Example 2 shown in FIG. 9(b) will be referred to as Example 4.

[0267] As illustrated in FIG. 9(a), Example 3 may include only the diamond layer (3000) and the nitride semiconductor layer (4000). Additionally, as illustrated in FIG. 9(b), Example 4 may include only the diamond layer (3000), the nitride semiconductor layer (4000), and the diamond semiconductor layer (5000).

[0268] According to one embodiment of the present invention, the nitride semiconductor layer (4000) included in Examples 3 and 4 may include the buffer nitride layer (4100), the nitride element layer (4200), and the first electrode (4300). Additionally, the nitride element layer (4200) according to one embodiment of the present invention may be a multilayer structure including two or more layers, and may include a non-doped layer (4220-1) and a doped layer (4220-2), or may be a structure including either a two-dimensional electron gas (E) and a two-dimensional hole gas inside.

[0270] As described above, the semiconductor integrated device (1) according to one embodiment of the present invention can be completed when the first electrode placement step (S43), which is a detailed step of the nitride semiconductor placement step (S40), is performed. At this time, the completed semiconductor integrated device (1) may optionally perform a lower layer removal step (S50). When the lower layer removal step (S50) is performed, the semiconductor integrated device (1) may include only the diamond layer (3000) and the nitride semiconductor layer (4000) respectively, as the substrate layer (1000) and the buffer layer (2000) are each removed as in Example 3.

[0271] Although not illustrated in the drawings above, in the case of Example 4, similar to Example 3, the semiconductor integrated device (1) can be completed after the nitride semiconductor placement step (S40) is completed and the formation of the diamond semiconductor layer (5000) is completed, and thereafter, a lower layer removal step (S50) can be further performed. Accordingly, the semiconductor integrated device (1) may include only the diamond layer (3000), the nitride semiconductor layer (4000), and the diamond semiconductor layer (5000) respectively, as the substrate layer (1000) and the buffer layer (2000) are each removed as in Example 4.

[0273] According to one embodiment of the present invention, the semiconductor integrated device (1) may be able to operate even when the substrate layer (1000) and the buffer layer (2000) are each removed by performing a lower layer removal step (S50). In other words, Example 3 can operate as a semiconductor integrated device (1) in the same way as Example 1. In addition, Example 4 can operate as a semiconductor integrated device (1) in the same way as Example 2.

[0274] Specifically, according to one embodiment of the present invention, the substrate layer (1000) and the buffer layer (2000) may each be used to grow the diamond layer (3000) to include a single-crystal diamond having one of the (111) and (113) orientations. As previously mentioned, the diamond layer (3000) can be grown into a single-crystal diamond having one of the (111) and (113) orientations by angulating the substrate layer (1000). Additionally, the buffer layer (2000) can serve as a buffer to mitigate lattice mismatch between the substrate layer (1000) and the diamond layer (3000) by being placed between the substrate layer (1000) and the diamond layer (3000).

[0275] Meanwhile, the nitride semiconductor layer (4000) and the diamond semiconductor layer (5000) may perform the role of an electrical element by having a transistor structure or a diode structure within the semiconductor integrated device (1). That is, the substrate layer (1000) and the buffer layer (2000) may each not perform the role of an electrical element in the semiconductor integrated device (1) but may be included as a material for the growth of the diamond layer (3000).

[0276] Accordingly, since each of Example 3 and Example 4 may include the nitride semiconductor layer (4000) or the diamond semiconductor layer (5000) which performs the role of an electrical element even when the substrate layer (1000) and the buffer layer (2000) are removed respectively, it can operate normally as a semiconductor integrated device (1) just like Example 1 and Example 2.

[0278] As previously described, the substrate layer (1000) according to one embodiment of the present invention may include any one of a sapphire substrate (Al2O3), a silicon (Si) substrate, a silicon carbide (SiC) substrate, a nitride (Nitride) substrate, and a diamond substrate. Generally, the thermal conductivity of a single-crystal diamond having a crystal plane having either (111) or (113) orientation may be higher than the thermal conductivity of each of the sapphire substrate (Al2O3), silicon (Si) substrate, silicon carbide (SiC) substrate, and nitride (Nitride) substrate included in the substrate layer (1000). Additionally, even when the substrate layer (1000) includes a diamond substrate, the crystallinity of the diamond layer (3000) may be higher than the crystallinity of the substrate layer (1000).

[0279] That is, the thermal conductivity of the diamond layer (3000) may be higher than the thermal conductivity of the substrate layer (1000). According to one embodiment of the present invention, when the lower layer removal step (S50) is performed, the lower surface of the diamond layer (3000) may be exposed to the outside. In other words, the diamond layer (3000) included in each of Example 3 and Example 4 may have a larger external exposure area than the diamond layer (3000) in each of Example 1 and Example 2, in which the substrate layer (1000) and buffer layer (2000) are disposed on the lower side, as the lower surface of the diamond layer (3000) included in Example 3 and Example 4 is exposed to the outside.

[0280] Accordingly, the semiconductor integrated device (1) according to one embodiment of the present invention can increase the external exposure area of ​​the diamond layer (3000) by performing the lower layer removal step (S50), thereby allowing heat generated during operation to be released more efficiently to the outside.

[0282] The semiconductor integrated device (1) according to one embodiment of the present invention can improve the heat dissipation performance of the diamond layer (3000) and improve the reliability and lifespan of the device by performing a lower layer removal step (S50).

[0284] FIG. 10 schematically illustrates the SEM measurement results of a semiconductor integrated device (1) according to one embodiment of the present invention.

[0286] FIG. 10(a) is an SEM view of the upper surface of a nitride element layer (4200) included in the semiconductor integrated device (1), FIG. 10(b) is an SEM view of the upper surface of a buffer nitride layer (4100) included in the semiconductor integrated device (1), and FIG. 10(c) is an SEM view of the upper surface of a diamond layer (3000) included in the semiconductor integrated device (1).

[0288] As illustrated in FIGS. 10(a), 10(b), and 10(c), each of the nitride element layer (4200), buffer nitride layer (4100), and diamond layer (3000) according to one embodiment of the present invention may be formed to have a uniform shape without any defects that are visually observable on the upper surface.

[0289] That is, the nitride element layer (4200) according to one embodiment of the present invention is a gallium aluminum nitride (Al) having a crystal plane of (0001) orientation grown with a uniform density, without containing defects. x Ga 1-x It may include N). In addition, the buffer nitride layer (4100) according to one embodiment of the present invention may include aluminum nitride having a crystal plane of (0001) orientation grown at a uniform density without defects.

[0290] Meanwhile, the diamond layer (3000) according to one embodiment of the present invention may have equilateral triangle-shaped structures distributed at high density on its upper surface. The equilateral triangle-shaped structures formed on the upper surface of the diamond layer (3000) may be due to 3-fold symmetry, which is an inherent characteristic of a single-crystal diamond that includes a crystal plane of either (111) or (113) orientation. That is, the diamond layer (3000) according to one embodiment of the present invention may include a single-crystal diamond having a crystal plane of either (111) or (113) orientation.

[0292] According to one embodiment of the present invention, a semiconductor integrated device includes a high-quality single-crystal diamond layer that functions as a heat dissipation layer, thereby preventing heat generation of the device and improving the lifespan of the device.

[0293] According to one embodiment of the present invention, a semiconductor integrated device can reduce the defect rate caused by defects by minimizing the occurrence of defects in a nitride semiconductor layer formed on a diamond layer, and can improve economic efficiency by increasing the yield of the semiconductor integrated device manufacturing process.

[0294] According to one embodiment of the present invention, a semiconductor integrated device can mitigate defects occurring in a diamond layer and improve the quality of the diamond layer by including a buffer layer.

[0295] According to one embodiment of the present invention, the buffer nitride layer performs the role of a buffer to prevent defects caused by lattice mismatch between the nitride element layer and the diamond layer, thereby improving the crystallinity of the nitride element layer and the effect of improving the performance of the semiconductor integrated device.

[0296] According to one embodiment of the present invention, the substrate layer can have the effect of improving the quality of the diamond layer by having the crystal planes deviated.

[0297] According to one embodiment of the present invention, the substrate layer can improve the crystallinity and quality of the diamond layer by having the crystal planes deviated, thereby exhibiting the effect of increasing the heat dissipation and insulation characteristics of the diamond layer.

[0298] According to one embodiment of the present invention, the semiconductor integrated device can have improved electrical characteristics and extended lifespan by improving the heat dissipation and insulation characteristics of the diamond layer.

[0299] According to one embodiment of the present invention, the substrate layer and the buffer layer each perform the role of preventing defects in the diamond layer, thereby forming a high-quality diamond layer and thereby exhibiting the effect of improving the performance of the semiconductor integrated device.

[0300] According to one embodiment of the present invention, the diamond layer is formed to have a high-quality single-crystal thin film structure by the angle of the substrate layer, thereby exhibiting the effect of improving thermal conductivity, charge mobility, and dielectric strength.

[0301] According to one embodiment of the present invention, the semiconductor integrated device can exhibit improved economic efficiency and usability by enhancing heat dissipation performance through improved thermal conductivity, charge mobility, and dielectric strength of the diamond layer, thereby preventing failure and shortened lifespan caused by heat generation.

[0302] According to one embodiment of the present invention, the nitride element layer is a gallium aluminum nitride (Al) having a crystal plane of the (0001) orientation on a diamond layer having a crystal plane of either the (111) or (113) orientation. x Ga 1-x By being formed to include N), it can be grown in the form of a single crystal, thereby exhibiting the effect of improving the crystallinity and durability of the semiconductor integrated device.

[0303] According to one embodiment of the present invention, the nitride element layer is formed on the diamond layer, thereby preventing the occurrence of defects in the nitride element layer and improving the electrical performance of the nitride semiconductor layer.

[0304] According to one embodiment of the present invention, the nitride semiconductor layer is formed on a diamond layer having one of the crystal planes of orientations (111) and (113), thereby improving interfacial adhesion with the diamond layer and preventing peeling and breakage.

[0305] According to one embodiment of the present invention, the nitride element layer is aluminum gallium nitride (Al) having different detailed compositions. x Ga 1-x By having a multilayer structure composed of a channel layer and a barrier layer including N), either a two-dimensional electron gas or a two-dimensional hole gas is formed inside the channel layer, thereby enabling the effect of improving the performance of the semiconductor integrated device.

[0306] According to one embodiment of the present invention, a semiconductor integrated circuit can exhibit the effect of improving electrical performance by enhancing electron mobility and reducing switching losses through a two-dimensional electron gas.

[0307] According to one embodiment of the present invention, when a semiconductor integrated device includes a doping layer doped with p-type or n-type, it can operate as a transistor or diode device, thereby enabling the device to exhibit an effect of improving usability.

[0308] According to one embodiment of the present invention, a semiconductor integrated device can form an integrated circuit by including a nitride semiconductor layer and a dia semiconductor layer, respectively, thereby enabling the effect of expanding the usability of the device.

[0309] According to one embodiment of the present invention, a semiconductor integrated device can improve the heat dissipation performance of the diamond layer and improve the reliability and lifespan of the device by performing a lower layer removal step.

[0311] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims. Explanation of the symbols

[0313] 1 : Semiconductor integrated circuit 1000 : Substrate layer 2000: Buffer layer 3000: Diamond layer 4000: Nitride semiconductor layer 4100: Buffer nitride layer 4200: Nitride element layer 4210-1: Channel layer 4210-2 : Barrier layer 4220-1 : Non-doping layer 4220-2 : Doping layer 4300 : First electrode 4310: 1st Source 4320: 1st Gate 4330 : 1st drain 5000 : Dia semiconductor layer 5100 : Second electrode 5110 : Second source 5120 : 2nd Gate 5130 : 2nd Drain E : 2D electron gas S10 : Substrate preparation step S20: Buffer placement stage S30: Diamond placement stage S40: Nitride semiconductor placement step S41: Buffer nitride placement step S42: Nitride element placement step S43: First electrode placement step S50: Lower layer removal stage

Claims

Claim 1 A semiconductor integrated device comprising: a substrate layer; a buffer layer disposed on the substrate layer; a diamond layer disposed on the buffer layer; and a nitride semiconductor layer disposed on the diamond layer; wherein the diamond layer comprises a single crystal diamond having a crystal plane having an orientation of either (111) or (113); and wherein, when the nitride semiconductor layer is partially disposed in a portion of the upper surface of the diamond layer, the semiconductor integrated device further comprises a diamond semiconductor layer disposed partially in another portion of the upper surface of the diamond layer where the nitride semiconductor layer is not disposed, and disposed spaced apart from the nitride semiconductor layer. Claim 2 A semiconductor integrated device according to claim 1, wherein the substrate layer comprises any one of a sapphire substrate (Al2O3), a silicon (Si) substrate, a silicon carbide (SiC) substrate, a nitride substrate, and a diamond substrate, and has an off angle of -10 to 10°. Claim 3 A semiconductor integrated device according to claim 1, wherein the buffer layer comprises one or more of iridium (Ir), ruthenium (Ru), and oxide materials, and comprises one or more layers. Claim 4 A semiconductor integrated device according to claim 1, wherein the diamond layer has a thickness of 5 to 500 μm and a crystal plane has an orientation of either (111) or (113), and has an off-angle of -10 to 10° with respect to an axis perpendicular to the upper surface of the substrate layer. Claim 5 In claim 1, the nitride semiconductor layer comprises: a buffer nitride layer comprising aluminum nitride (AlN) having an orientation of (0001); and aluminum gallium nitride (Al) disposed on the buffer nitride layer. x Ga 1-x A semiconductor integrated device comprising a nitride element layer including N; wherein the nitride element layer has a multilayer structure including two or more layers. Claim 6 In claim 1, the nitride semiconductor layer is aluminum gallium nitride (Al x Ga 1-x A semiconductor integrated device comprising a nitride element layer having a multilayer structure including N; wherein the nitride element layer comprises an undoped layer; and a doped layer doped with either n-type or p-type; each comprising a semiconductor integrated device. Claim 7 In claim 1, the nitride semiconductor layer comprises a nitride device layer having a multilayer structure including two or more layers; and the nitride device layer comprises a plurality of layers, wherein each of the plurality of layers has a different x value and is made of aluminum gallium nitride (Al x Ga 1-x A semiconductor integrated device having a Field Effect Transistor (FET) structure comprising N) and having either a 2-dimensional electron gas (2DEG) or a 2-dimensional hole gas (2DHG) formed on the inside. Claim 8 A semiconductor integrated device according to claim 6, wherein the nitride element layer has a structure among a transistor structure and a diode structure. Claim 9 delete Claim 10 A semiconductor integrated device according to claim 5, wherein the thickness of the buffer nitride layer is 1 to 1000 nm. Claim 11 A semiconductor integrated device according to claim 1, wherein the nitride semiconductor layer is formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C. Claim 12 In claim 1, the diamond layer is formed on the buffer layer by chemical vapor deposition (CVD) and 0.5 W / mm 2 Up to 5W / mm 2 A semiconductor integrated device formed at a growth rate of 0.01 to 100 μm / hr under plasma power, a pressure of 0 to 1000 torr, and a temperature of 100 to 1300°C. Claim 13 In claim 1, the semiconductor integrated device is capable of operation even when each of the substrate layer and the buffer layer is removed. Claim 14 A semiconductor integrated device according to claim 5, wherein the nitride semiconductor layer further comprises a first electrode disposed on the nitride element layer, and the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from each of the first source and the first gate. Claim 15 A method for manufacturing a semiconductor integrated device, comprising: a substrate preparation step for preparing a substrate layer; a buffer placement step for placing a buffer layer on the substrate layer; a diamond placement step for placing a diamond layer on the buffer layer; and a nitride semiconductor placement step for placing a nitride semiconductor layer on the diamond layer; wherein the diamond layer comprises a single crystal diamond having a crystal plane orientation of either (111) or (113); and when the nitride semiconductor layer is partially placed in a portion of the upper surface of the diamond layer, the semiconductor integrated device further comprises a diamond semiconductor layer that is partially placed in another portion of the upper surface of the diamond layer where the nitride semiconductor layer is not placed, and is spaced apart from the nitride semiconductor layer. Claim 16 In claim 15, the semiconductor integrated device can use the diamond layer and nitride semiconductor remaining after removing each of the substrate layer and buffer layer as a semiconductor integrated device, and the method of manufacturing the semiconductor integrated device further comprises a lower layer removal step of removing each of the substrate layer and buffer layer and leaving only the diamond layer and nitride semiconductor layer. Claim 17 In claim 15, the nitride semiconductor placement step comprises: a buffer nitride placement step of placing a buffer nitride layer comprising aluminum nitride (AlN) having an orientation of (0001); and aluminum gallium nitride (Al x Ga 1-x A method for manufacturing a semiconductor integrated device, further comprising a detailed step of a nitride element placement step in which a nitride element layer including N) is placed on the buffer nitride layer, wherein the nitride element layer is a multilayer structure including two or more layers. Claim 18 A method for manufacturing a semiconductor integrated device according to claim 17, wherein the nitride semiconductor placement step further comprises a detailed step of a first electrode placement step of placing a first electrode on the nitride element layer, and wherein the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from each of the first source and the first gate.

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