Display apparatus having thin film transistor

Abstract

A display device including a thin-film transistor according to one example of the present invention comprises: an active pattern located on a substrate and including a channel region, a source region located between the channel region, and a drain region; a gate electrode located on the active pattern; a gate insulating film located between the gate electrode and the channel region; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region, wherein the source region and the drain region each include a conductive region and a conductive diffusion region, and the gate electrode overlaps with the channel region but does not overlap with the conductive diffusion region.

Description

Technology Field

[0001] This specification relates to a display device comprising a thin-film transistor capable of securing an effective channel length through a lead-forming process. Background Technology

[0002] Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. To this end, research is continuously being conducted to develop thinner, lighter, and lower power consumption display devices.

[0003] Examples of display devices include Liquid Crystal Display (LCD), Plasma Display Panel (PDP), or Organic Light Emitting Display Device (OLED). Among these, an Organic Light Emitting Display Device (OLED) comprises a plurality of pixel regions arranged in a display area where an image is displayed, and a plurality of organic light-emitting elements corresponding to the pixel regions. Since organic light-emitting elements are self-luminous devices that emit light on their own, OLEDs have the advantages of faster response speed, higher luminous efficiency, brightness, and viewing angle compared to LCDs, as well as superior contrast ratio and color reproduction rate.

[0004] An organic light-emitting display includes a light-emitting unit, thin-film transistors for driving the unit, and storage capacitors. For thin-film transistors to drive the unit and maintain the light-emitting state, mobility and leakage current characteristics, as well as durability and electrical reliability, are critical. Accordingly, research is continuously being conducted to enhance the reliability of thin-film transistors while improving their electrical characteristics. The problem to be solved

[0005] The problem solved according to the embodiments of the present specification is to provide a display device including a thin-film transistor that can improve the electrical characteristics of the thin-film transistor while increasing reliability.

[0006] In addition, the purpose is to provide a display device including a thin-film transistor that can prevent off-current from occurring due to a short channel by preventing the reduction of the effective channel length.

[0007] In addition, it is intended to prevent simultaneous etching of the gate insulating film and the gate electrode.

[0008] In addition, the invention according to the embodiments of the present specification aims to reduce the consumption of current for achieving the same brightness in individual pixels by preventing the reduction of the channel width of the gate electrode and maintaining the amount of driving current.

[0009] In addition, the gate insulating film is used as the dielectric of the storage capacitor, and the purpose is to increase the capacitance of the storage capacitor.

[0010] In addition, the invention aims to provide a display device capable of increasing the total capacitance of the storage capacitor while increasing the area of ​​the light-emitting region by reducing the area occupied by the storage capacitor.

[0011] The problems solved according to one embodiment of this specification are not limited to the purposes mentioned above, and other unmentioned purposes and advantages of the present invention may be understood from the following description and will be more clearly understood by the embodiments of this specification. Furthermore, it will be readily apparent that the purposes and advantages of this specification can be realized by the means and combinations thereof set forth in the claims. means of solving the problem

[0012] A thin-film transistor according to one embodiment of the present specification comprises: an active pattern located on a substrate and including a channel region, a source region located between the channel region, and a drain region; a gate electrode located on the active pattern; a gate insulating film located between the gate electrode and the channel region; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region, wherein the source region and the drain region each include a conductive region and a conductive diffusion region, and the gate electrode overlaps with the channel region but does not overlap with the conductive diffusion region.

[0013] Herein, the gate electrode is characterized by including a plurality of recesses located overlapping with the conductive diffusion region when viewed from a planar perspective; and a protrusion located not overlapping with the conductive diffusion region. Effects of the invention

[0014] According to an embodiment of the present specification, by including a plurality of recesses and protrusions on the gate electrode so that the gate electrode is positioned so as not to overlap with the conductive diffusion region, the effective channel length is reduced, thereby preventing off-current from occurring due to the short channel.

[0015] In addition, by preventing the simultaneous etching of the gate insulating film and the gate electrode, it provides the advantage of preventing short circuits between the gate electrode and the active pattern and preventing the loss of the buffer layer.

[0016] In addition, by preventing the reduction of the channel width of the gate electrode, there is an effect of reducing current consumption required to achieve the same brightness in individual pixels.

[0017] In addition, according to the embodiments of this specification, the gate insulating film is used as the dielectric of the storage capacitor, and by reducing the area occupied by the storage capacitor and increasing the area of ​​the light-emitting region, the aperture ratio can be improved.

[0018] In addition, it offers the advantage of increasing the capacitance of the storage capacitor by using a gate insulating film as a dielectric while reducing the area occupied by the storage capacitor.

[0019] The effects of this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0020] FIG. 1 is a plan view of a thin-film transistor according to one embodiment of the present specification. FIG. 2a is a cross-sectional view of FIG. 1 taken by cutting along the I-I' direction. FIG. 2b is a cross-sectional view of FIG. 1 taken by cutting along the II-II' direction. FIGS. 3 to 13 are cross-sectional views shown to explain a method for manufacturing a display device according to one embodiment of the present specification. FIG. 14 is a cross-sectional view showing the case where the gate electrode is formed to have a straight line shape. Figure 15 is a graph showing the threshold voltage according to the channel length. Figures 16 and 17 are drawings shown to illustrate the change in channel width due to misalignment of the gate electrode. Figure 18 is a diagram illustrating the case where the gate insulating film and the gate electrode are etched simultaneously. Specific details for implementing the invention

[0021] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0022] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0023] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0024] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0025] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0026] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0027] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0028] Hereinafter, a display device including a thin-film transistor according to an embodiment of the present invention will be described with reference to the attached drawings.

[0029] FIG. 1 is a plan view of a thin-film transistor according to one embodiment of the present specification. FIG. 2a is a cross-sectional view of FIG. 1 taken along the I-I' direction. FIG. 2b is a cross-sectional view of FIG. 1 taken along the II-II' direction.

[0030] Referring to FIGS. 1 to 2b, a thin film transistor according to one embodiment of the present specification may include a buffer layer (120) located on a substrate (100), an active pattern (130) located on the buffer layer (120), a gate electrode (164) located on the active pattern (130), a gate insulating film (140) located between the gate electrode (164) and the active pattern (130), a source electrode (166), and a drain electrode (168).

[0031] The substrate (100) may be made of a flat insulating material. For example, the substrate (100) may be a transparent substrate. The buffer layer (120) located on the substrate (100) may be formed in a single layer or multilayer structure including an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0032] The active pattern (130) located on the buffer layer (120) comprises at least one of amorphous silicon, polycrystalline silicon, or oxide semiconductor. For example, the active layer pattern (130) may comprise at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO).

[0033] The active pattern (130) includes a source region (130b) and a drain region (130a) facing each other with the channel region (CH) in between. The channel region (CH) is positioned to overlap with the gate electrode (164) with the gate insulating film (140) in between. In one example, the active pattern (130) may be positioned in the horizontal direction of the substrate (100), and the gate electrode (164) may be positioned in the vertical direction of the substrate (100) across the active pattern (130). Each of the source region (130b) and the drain region (130a) provided in the active layer (125) includes a conductive region (130-1) and a conductive diffusion region (130-2). The conductive diffusion region (130-2) may be located between the channel region (CH) and the conductive region (130-1). As illustrated in FIG. 1, the conductive diffusion region (130-1) may include a first region (P1) disposed at each corner portion of the boundary surface between the channel region (CH) and the conductive region (130-1) in the active pattern (130), and a second region (P2) disposed in a rod shape between adjacent first regions (P1). The second region (P2) is disposed between the first regions (P1) along the vertical direction of the substrate (100) on which the gate electrode (164) is disposed, and may have a relatively narrower width than the first region (P1).

[0034] Here, as the gate electrode (164) is positioned so as not to overlap with the conductive region (130-1) or the conductive diffusion region (130-2), the effective channel length (L1, L2) of the gate electrode (164) can have the same length as the target effective channel length (Lt1, Lt2) to be implemented.

[0035] In one example, the upper surface of the conductive region (130-1) of each of the drain region (130a) and source region (130b) may have the same level as the upper surface of the channel region (CH). In another example, the upper surface of the conductive region (130-1) of each of the drain region (130a) and source region (130b) may be located at a lower level than the upper surface of the channel region (CH). Here, the conductive diffusion region (130-2) of each of the drain region (130a) and source region (130b) may have the same level as the upper surface of the channel region (CH).

[0036] The gate electrode (164) is positioned overlapping the channel region (CH) of the active pattern (130). A gate insulating film (140) is disposed between the gate electrode (164) and the channel region (CH) of the active pattern (130). The gate electrode (164), source electrode (166), and drain electrode (168) can be configured in a stacked structure of a first gate metal (160) and a second gate metal (162). The first gate metal (160) or the second gate metal (162) may be made of any one of the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof.

[0037] The gate electrode (164) can be formed to include a plurality of recesses (164r) when viewed from a planar perspective. The recesses (164r) have a concave shape that is inwardly inward from one side portion (164s) of the gate electrode (164). Here, at least two recesses (164r) can be arranged based on one side portion (164s) of the gate electrode (164). These recesses (164r) are positioned to correspond to the conductive diffusion region (130-2) so that the gate electrode (164) does not overlap with the conductive diffusion region (130-2).

[0038] A protrusion (164t) may be disposed between multiple recesses (164r). Accordingly, the gate electrode (164) may have a shape in which the recesses (164r) and the protrusion (164t) are continuously connected. The protrusion (164t) of the gate electrode (164) is disposed so as not to overlap with the conductive diffusion region (130-2).

[0039] When viewed from a planar perspective, the gate electrode (164) has a recess (164r) located corresponding to the first region (P1) of the conductive diffusion region (130-2), and a protrusion (164t) located corresponding to the second region (P2) of the conductive diffusion region (130-2).

[0040] The gate electrode (164) can be formed to have a 'Wang' shape when viewed from a plane by including the recess (164r) and the protrusion (164t). In other words, the gate electrode (164) can have a shape in which a '-' shape crosses the center of the 'I' when viewed from a plane.

[0041] The gate electrode (164) can be formed with different widths in the portion where the recess (164r) is formed and the portion where the protrusion (164t) is formed. In one example, the width (gw1) of the portion where the recess (164r) is formed, as shown in FIG. 2a, may have a relatively smaller size than the width (gw2) of the portion where the protrusion (164t) is formed, as shown in FIG. 2b.

[0042] The source electrode (166) is electrically connected to the source region (130b) of the active pattern (130) through a source contact hole (154) formed on the gate insulating film (140), and the drain electrode (168) is electrically connected to the drain region (130a) of the active pattern (130) through a drain contact hole (152) formed on the gate insulating film (140). The source electrode (166) and the drain electrode (168) can be formed in a full-contact manner that fills the source contact hole (154) and the drain contact hole (152), respectively, contacts the exposed surface of the source region (130b), and extends to the upper surface of the gate insulating film (140). Accordingly, the area of ​​the contact holes can be reduced while reducing contact resistance compared to a method of partially filling the source contact hole and the drain contact hole.

[0043] The source electrode (166) and drain electrode (168) are made of the same material as the gate electrode (164) and can be positioned on the same plane (layer) as the gate electrode (164) through an etching process using the same mask.

[0044] According to one embodiment of the present specification, the gate electrode may be formed to include a plurality of recesses and protrusions. These recesses may be positioned to correspond to a conductive diffusion region so that the gate electrode is positioned so as not to overlap with the conductive diffusion region. Accordingly, the effective channel length is reduced by the overlap between the conductive diffusion region and the gate electrode, thereby preventing the occurrence of off-current due to a short channel.

[0045] Hereinafter, a thin-film transistor of FIGS. 1 to 2b and a method for manufacturing a display device including the same will be described with reference to the drawings.

[0046] FIGS. 3 to 13 are cross-sectional views shown to explain a method for manufacturing a display device according to an embodiment of the present specification. FIG. 14 is a cross-sectional view showing a case where the gate electrode is formed to have a straight line shape. FIG. 15 is a graph showing the threshold voltage according to the channel length. FIGS. 16 and 17 are drawings shown to explain the change in gate width due to misalignment of the gate electrode. FIG. 18 is a drawing shown to explain the case where the gate insulating film and the gate electrode are etched simultaneously.

[0047] Referring to FIG. 3, a light-blocking layer (105), a first storage electrode (110), and a wiring electrode (115) are formed on a substrate (100). Specifically, a first metal layer (102) and a second metal layer (104) are formed on the substrate (100). Next, a photolithography process using a mask and an etching process are performed on the first metal layer (102) and the second metal layer (104) to form a light-blocking layer (105), a first storage electrode (110), and a wiring electrode (115). Here, it is preferable that the light-blocking layer (105) be formed at a position that overlaps with the active layer of the thin-film transistor to be formed later. The light-blocking layer (105) serves to protect the thin-film transistor from light incident from the outside. In one example, the wiring electrode (115) may be any one of a data line (DL), a driving power supply line (VDD), or a reference power supply line (Vref).

[0048] The substrate (100) may be made of a flat insulating material. For example, the substrate (100) may be a transparent substrate. The substrate (100) may be made of a hard material such as glass or reinforced glass, or may be made of a flexible material such as plastic, but is not limited thereto.

[0049] The light-blocking layer (105), the first storage electrode (110), and the wiring electrode (115) can be formed using the same material. In one example, the first metal layer (102) and the second metal layer (104) may be formed as a single layer or a laminated structure of any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti), or copper (Cu), or an alloy thereof.

[0050] A buffer layer (120) is subsequently formed on the substrate (100). The buffer layer (120) is formed to cover the light-blocking layer (105), the first storage electrode (110), and the wiring electrode (115). The buffer layer (120) prevents moisture or oxygen from penetrating from the substrate (100) toward the organic light-emitting diode to be formed on top, and serves to protect the thin-film transistor formed in the subsequent process from impurities such as hydrogen leaking from the substrate (100). Additionally, the buffer layer (120) serves to mutually insulate the light-blocking layer (105), the first storage electrode (110), and the wiring electrode (115).

[0051] The buffer layer (120) may include a structure in which a first buffer layer (117) and a second buffer layer (119) are stacked. The buffer layer (120) may be composed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). In one example, the first buffer layer (117) may be formed of silicon nitride (SiNx) of a first thickness, and the second buffer layer (119) may be formed of silicon oxide (SiOx) of a second thickness thicker than the first buffer layer (117), but is not limited thereto.

[0052] Referring to FIG. 4, an active layer (125) is formed on a buffer layer (120). The active layer (125) may be formed by including at least one of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the active layer (125) may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO). Additionally, the active layer (125) may be formed with other oxide semiconductor materials known in the art.

[0053] Next, a photoresist pattern (127) is formed on the active layer (125). Specifically, a photoresist film is applied on the buffer layer (120). Subsequently, an exposure process in which light is selectively irradiated onto the photoresist film through a halftone mask and a development process in which the photoresist film modified by the exposure process are removed are performed to form the photoresist pattern (127). The photoresist pattern (127) may include an opening formed at a location overlapping with the region where the thin-film transistor is to be formed and the region where the storage capacitor is to be formed, which blocks the active layer (125) and exposes the surface of the active layer (125) in the remaining region. The photoresist pattern (127) may be formed to have the thickest thickness in the region where the thin-film transistor is to be formed.

[0054] Referring to FIG. 5, a patterning process is performed to etch the exposed surface of the active layer (125) using a photoresist pattern (127) formed on the active layer (125) as an etching mask. The patterning process can be performed using a wet etching method. Then, as the exposed surface of the active layer (125) is etched, the surface of the buffer layer (120) is exposed, and an active pattern (130) and a second storage electrode (135) can be formed below the photoresist pattern (127). The process of etching the active layer (125) can be performed using a wet etching method.

[0055] Referring to FIGS. 6a and 6b, an ashing process is performed to remove the thickness and width of the photoresist pattern (127) to form a photoresist residual pattern (127R). FIG. 6b is a planar view of the 'X' region of FIG. 6a. Further explanation regarding this is omitted. The ashing process can be performed using oxygen (O2) plasma. When the ashing process is performed, the photoresist pattern (127) can be completely removed during the ashing process in the remaining regions, excluding the region where a thin-film transistor is to be formed with the thickest thickness of the photoresist pattern (127, see FIG. 5).

[0056] Accordingly, in the region where the thin-film transistor is to be formed, the thickness and width are reduced, leaving a photoresist residual pattern (127R) that partially covers the surface of the active pattern (130). Additionally, in the region where the storage capacitor is to be formed, the photoresist pattern (127, see FIG. 5) is completely removed, so that the second storage electrode (135) can be exposed. Referring again to FIG. 6b, the photoresist residual pattern (127R) can be formed to have a shape that crosses the width (W) direction of the active pattern (130).

[0057] Referring to FIGS. 7a to 7d, a conductive process is performed on a substrate (100) to form a drain region (130a) and a source region (130b) on an active pattern (130).

[0058] The conductorization process can be carried out using plasma treatment or an ion implantation process method that supplies impurity ions. Here, FIG. 7c is a diagram showing an enlarged view of the 'X' region to explain the drain region (130a) and source region (130b) formed on the active pattern (130) when plasma treatment is used. Also, FIG. 7d is a diagram showing an enlarged view of the 'X' region to explain the drain region (130a) and source region (130b) formed on the active pattern (130) when an ion implantation process method that supplies impurity ions is used.

[0059] In one example, a conductive process through plasma treatment can form a conductive region (130-1) by supplying a plasma-treated reaction gas to an exposed portion of an active pattern (130) to make this portion conductive. Plasma treatment can be performed by generating a plasma discharge in helium (He), hydrogen (H2), fluorine (F), or argon (Ar) gas. For example, when the active pattern (130) is formed as an oxide semiconductor, the conductivity characteristics vary depending on the oxygen content, and if plasma treatment is performed, the oxygen content in the oxide semiconductor is reduced, thereby lowering the resistance of the oxide semiconductor and making it conductive.

[0060] In another example, an ion implantation process supplying impurity ions can form a conductive region (130-1) by implanting boron ions or phosphorus ions into an exposed portion of the active pattern (130) to make this portion conductive. Here, the surface resistance (sheet resistance) of the conductive region (130-1) formed through the conductive process is 10 -2 to 10 -3 Plasma treatment and ion implantation processes are performed to improve electron mobility while maintaining the Ω·cm range.

[0061] Meanwhile, although plasma-activated reaction gas is not directly supplied or impurity ions are injected onto the active pattern (130), plasma-activated reaction gas or impurity ions supplied during the conductive process to form the conductive region (130-1) can be diffused from the conductive region (130-1) toward the active pattern (130) through the interface between the photoresist residual pattern (127R) and the active pattern (130), as indicated by the arrow in FIG. 7B, to form a conductive diffusion region (130-2).

[0062] In particular, the conductive diffusion region (130-2) can be formed by diffusing in the direction of the active pattern (130) through the interface of the active pattern (130) at the 'A' portion that overlaps with the corner portion of the photoresist residual pattern (127R) in the active pattern (130) covered by the photoresist residual pattern (127R), and the interface of the side portion between the corner portions of the photoresist residual pattern (127R).

[0063] Except for the conductive region (130-1) and conductive diffusion region (130-2) on the active pattern (130), the portion covered by the photoresist residual pattern (127R) is not conductive in the conductive process.

[0064] Referring to FIG. 7c, which illustrates a case where a conductive process using plasma treatment is performed, the active pattern (130) can be lowered by a predetermined thickness from the surface by the plasma-activated reaction gas supplied to form a conductive region (130-1). Accordingly, the upper surface (S2) of the conductive region (130-1) of the drain region (130a) and source region (130b) can be located at a lower level than the upper surface (S1) of the active pattern (130) in the unconducted portion, as it is covered with a photoresist residual pattern (127R). Here, the conductive diffusion region (130-2) of the drain region (130a) and source region (130b) can have the same level as the upper surface (S1) of the active pattern (130) in the unconducted portion, since it is not formed by directly supplying the plasma-activated reaction gas.

[0065] Additionally, referring to FIG. 7d which shows a case where a conductive process is performed using an ion implantation process that supplies impurity ions, the upper surface of the conductive region (130-1) of the drain region (130a) and source region (130b) may have the same level as the upper surface (S1) of the active pattern (130) that is not conductive.

[0066] Meanwhile, during the process of conducting the conductive process, the second storage electrode (135) with its surface exposed can also be conductive and function as a storage electrode.

[0067] Referring to FIGS. 8a and 8b, the photoresist residual pattern (127R) is removed to expose an active pattern (130) comprising a drain region (130a) and a source region (130b). Here, the drain region (130a) may include a conductive region (130-1) and a conductive diffusion region (130-2), and the source region (130b) may include a conductive region (130-1) and a conductive diffusion region (130-2).

[0068] The conductive diffusion region (130-2) may be located between the channel region (CH) and the conductive region (130-1). As illustrated in FIG. 1, the conductive diffusion region (130-1) may include a first region (P1) disposed at each corner portion of the boundary surface between the channel region (CH) and the conductive region (130-1) in the active pattern (130), and a second region (P2) disposed in a rod shape between adjacent first regions (P1). The second region (P2) is disposed between the first regions (P1) along the vertical direction of the substrate (100) on which the gate electrode (164) is disposed, and may have a relatively narrower width than the first region (P1).

[0069] Referring to FIGS. 9a and 9b, a gate insulating film (140) including a plurality of GI holes (150, 152, 154, 156) is formed on a substrate (100). To this end, the gate insulating film (140) is formed on the front surface of a buffer layer (120) including an active pattern (130). The gate insulating film (140) may be formed by including silicon oxide (SiO2). Next, a photoresist film is formed on the gate insulating film (140), and an exposure process and a development process are performed to remove the photoresist film modified by the exposure process. Then, a photoresist pattern (145) is formed including a plurality of open regions from which the photoresist film has been completely removed to expose the surface of the gate insulating film (140).

[0070] A etching process is performed to remove the gate insulating film (140) exposed by the open region. The etching process can be performed using a dry etching method. During the dry etching process, the gate insulating film (140) exposed by the open region of the photoresist pattern (145) can be removed. Additionally, in some regions, the gate insulating film (140), the second buffer layer (119) and the first buffer layer (117) below the gate insulating film (140) can be etched and removed together. Then, a plurality of GI holes (150, 152, 154, 156) are formed within the gate insulating film (140).

[0071] Here, a plurality of GI holes (150, 152, 154, 156) may include a light-blocking contact hole (150) formed by exposing the surface of the light-blocking layer (105). Additionally, a plurality of GI holes (150, 152, 154, 156) may include a source contact hole (154) and a drain contact hole (152) that expose a portion of the surface of the active pattern (130). Here, referring to FIG. 9b, the source contact hole (154) and the drain contact hole (152) each expose a conductive region (130-1) of the active pattern (130). Then, a strip process is performed to remove the photoresist pattern (145).

[0072] Referring to FIGS. 10a to 10d, a gate electrode (164), a source electrode (166), a drain electrode (168), a third storage electrode (168), and a pad electrode (170) are formed on a substrate (100).

[0073] To this end, a gate metal layer (160, 162) is formed on a substrate (100) having a gate insulating film (140) formed thereon, the gate metal layer (160, 162) having a plurality of GI holes (150, 152, 154, 156). The gate metal layer (160, 162) can be formed in a stacked structure of a first gate metal layer (160) and a second gate metal layer (162). In one example, the first gate metal layer (160) and the second gate metal layer (162) may be composed of a single layer or a multilayer made of any one of the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof, but are not limited thereto.

[0074] Next, the gate metal layer (160, 162) and the gate insulating film (140) are patterned through a photolithography process using a photomask and an etching process to form the gate electrode (164), source electrode (166), drain electrode (168), third storage electrode (168), and pad electrode (170). Here, the etching process can be performed using a dry etching method. Since the gate electrode (164), source electrode (166), drain electrode (168), third storage electrode (168), and pad electrode (170) are formed by patterning the same gate metal layer (160, 162), they are made of the same material and can be formed on the same plane (layer).

[0075] The gate electrode (164) is positioned overlapping the channel region (CH) and does not overlap with the conductive region (130-1) and the conductive diffusion region (130-2). The source electrode (166) is electrically connected to the source region (130b) of the active pattern (130) through a source contact hole (154) formed within the gate insulating film (140). The drain electrode (168) is connected to the drain region (130a) of the active pattern (130) through a drain contact hole (152) formed within the gate insulating film (140). The source electrode (166) and the drain electrode (168) can be formed in a full-contact manner that fills the exposed surfaces of the source contact hole (154) and the drain contact hole (152), respectively. Accordingly, compared to a method of partially filling the source contact hole and drain contact hole, the contact resistance can be reduced while the contact hole area can be reduced.

[0076] In the storage capacitor region, a storage capacitor (Cst) is formed in which the first storage electrode (110) and the second storage electrode (135) overlap with the buffer film (120) in between, and the third storage electrode (168) and the second storage electrode (135) overlap with the gate insulating film (140) in between.

[0077] When a conductive process is performed on an active pattern after forming a gate electrode, it is difficult to perform a conductive process on the second storage electrode (135) made of an oxide semiconductor material, and thus it is difficult to form a storage capacitor with a stacked structure, which limits the ability to improve capacitance.

[0078] On the other hand, in the embodiment of the present specification, a conductive process is performed on the active pattern (130) before forming the gate electrode (164) to form conductive regions (130a, 130b), and a patterning process is performed to form the gate electrode (164). Then, a stacked storage capacitor (Cst) can be formed, including a structure in which a gate insulating film (140) is applied as a dielectric between the third storage electrode (168) and the second storage electrode (135). Since a stacked storage capacitor (Cst) can be formed, the capacitance can be improved, allowing the light emission of the organic light-emitting device to be maintained for a relatively long time. Therefore, the area occupied by the storage capacitor can be reduced, and the light-emitting region can be increased by the amount of the reduced storage capacitor area, thereby increasing the aperture ratio.

[0079] Referring to FIG. 10b, the gate electrode (164) may be formed to include a plurality of recesses (164r). The recesses (164r) have a concave shape extending inward from one side portion (164s) of the gate electrode (164). Here, at least two recesses (164r) may be arranged based on one side portion of the gate electrode (164). These recesses (164r) correspond to the conductive diffusion region (130-2) so that the gate electrode (164) does not overlap with the conductive diffusion region (130-2). Between the plurality of recesses (164r), a protrusion (164t) may be arranged to have the same width as one side portion (164s) of the gate electrode (164). The protrusion (164t) of the gate electrode (164) is arranged so as not to overlap with the conductive diffusion region (130-2).

[0080] When viewed from a planar perspective, the gate electrode (164) has a recess (164r) located corresponding to the first region (P1) of the conductive diffusion region (130-2), and a protrusion (164t) located corresponding to the second region (P2) of the conductive diffusion region (130-2).

[0081] By forming the gate electrode (164) including such a recess (164r), the gate electrode (164) can be formed to have a 'Wang' shape when viewed from a plane. In other words, the gate electrode (164) can have a shape in which a '-' shape crosses the center of the 'I' when viewed from a plane. Meanwhile, in FIG. 10b, the conductive region (130-1) and the conductive diffusion region (130-2) below the gate insulating film (140) are exposed and described for easy explanation of the embodiment.

[0082] The gate electrode (164) can be formed with different widths at the portion where the recess (164r) is formed and at the portion where the protrusion (164t) is formed. This will be explained below with reference to the drawings.

[0083] FIGS. 10c and FIGS. 10d are cross-sectional views showing the portion of FIG. 10b where the gate electrode (164) is formed, cut along the II' and II-II' directions. FIG. 10c shows the gate electrode (164) in the portion where the recess (164r) is formed, and FIG. 10d shows the gate electrode (164) in the portion where the protrusion (164t) is formed.

[0084] Referring to FIGS. 10c and FIGS. 10d, the gate electrode (164) is positioned overlapping the channel region (CH) of the active pattern (130). A drain region (130a) and a source region (130b) may be positioned with the channel region (CH) in between. The drain region (130a) and the source region (130b) may each include a conductive region (130-1) and a conductive diffusion region (130-2).

[0085] The width (gw1) of the gate electrode (164) in the portion where the recess (164r) of FIG. 10c is formed may have a relatively smaller size than the width (gw2) of the gate electrode (164) in the portion where the protrusion (164t) of FIG. 10d is formed.

[0086] Referring to FIGS. 10b and 10c, the recess portion (164r) is positioned to correspond to the conductive diffusion region (130-2), so that the gate electrode (164) does not overlap with the conductive diffusion region (130-2). Accordingly, the effective channel length (L1) of the gate electrode (164) in the portion where the recess portion (164r) is formed is not affected by the conductive diffusion region (130-2) and can be formed to have the same length as the target effective channel length (Lt1) to be implemented.

[0087] Additionally, referring to FIG. 10b and FIG. 10d, the gate electrode (164) in the portion where the protrusion (164t) is formed is also formed so as not to overlap with the conductive diffusion region (130-2), so the effective channel length (L2) of the gate electrode (164) in the portion where the protrusion (164t) is formed is not affected by the conductive diffusion region (130-2) and can be formed to have the same length as the target effective channel length (Lt2) to be implemented.

[0088] The width of the region in the channel region (CH) that can function as a channel without being conductive can be defined as the effective channel length (Leff). An increase or decrease in the effective channel length (Leff) can affect the device characteristics of the thin-film transistor. For example, if the effective channel length (Leff) is reduced below the target effective channel length to be achieved, the threshold voltage (Vth) of the thin-film transistor decreases, as shown in Fig. 15. A decrease in the threshold voltage (Vth) induces a short channel phenomenon, which can lead to off-current and cause device degradation.

[0089] Accordingly, it is important to have a method that can match the effective channel length of the actual channel region (CH) formed with the target effective channel length to be implemented.

[0090] FIG. 14 illustrates a case where the gate electrode is formed to have a straight line shape. As shown in FIG. 14, when the gate electrode (GE) is patterned into a straight line shape, the gate electrode (GE) is placed overlapping with the conductive diffusion region (130-2).

[0091] The width of the channel region overlapping with the gate electrode (GE) in the center of the active pattern (130) of FIG. 14 is the target effective channel length (Lt3). The target effective channel length (Lt3) can be understood as the effective channel length that the thin-film transistor intends to implement to perform a switching function. Additionally, the width of the conductive diffusion region (130-2) formed by diffusion from the conductive region (130-1) can be indicated as '△L'. Here, as the conductive diffusion region (130-2) is formed in both directions, it has a value of '2△L'.

[0092] Meanwhile, the conductive regions of the active pattern (130) formed by performing the conductive process do not function as channels as their resistivity decreases. That is, the conductive diffusion region (130-2) also does not function as a channel because its resistivity is lower than that of the channel region.

[0093] Accordingly, only the portion obtained by subtracting the width (2△L) of the diffusion region (130-2) from the target effective channel length (Lt3) can effectively function as the actual channel as the actual formed effective channel length (L3). In other words, the actual formed effective channel length (L3) is reduced by the width of '2△L' compared to the target effective channel length (Lt3). As the actual formed effective channel length (L3) decreases compared to the target effective channel length (Lt3), a short channel phenomenon can be induced in which the threshold voltage (Vth) of the thin-film transistor decreases. Then, due to the short channel phenomenon, the off-current increases, and leakage current may occur.

[0094] In this regard, according to an embodiment of the present specification, by introducing a gate electrode (164) including a recess portion (164r) positioned corresponding to a conductive diffusion region (130-2), the conductive diffusion region (130-2) and the gate electrode (164) do not overlap. Accordingly, the effective channel length (L1) of the gate electrode (164) in the portion where the recess portion (164r) is formed is not affected by the conductive diffusion region (130-2) and can be formed to have the same length as the target effective channel length (Lt1) to be implemented. In other words, the target effective channel lengths (L1, L2) can be effectively maintained as actual channels without being reduced. Accordingly, the occurrence of short channels can be prevented, thereby preventing the occurrence of off-current.

[0095] FIG. 16 illustrates a case where the shape of the active pattern is modified. Referring to FIG. 16, the active pattern (ACT) can be patterned to have a concave portion (R) so that no conductive diffusion region occurs on the active pattern (ACT). However, if misalignment (M / A) occurs during the process of placing the gate electrode (GE) on the active pattern (ACT), a phenomenon may occur in which the channel width of the gate electrode (GE) is reduced.

[0096] For example, FIG. 16(a) illustrates a case where the gate electrode (GE) is placed on the active pattern (ACT) at a normal alignment position (a1), and FIG. 16(b) illustrates a case where the gate electrode (GE) is placed on the active pattern (ACT) at a position moved from the normal alignment position (a1) to a misalignment position (a2). In this case, at the normal alignment position (a1), the gate electrode (GE) overlaps with the active pattern (ACT) to form a first channel width (W A1 While having ), the gate electrode (GE) located at the misaligned position (a2) overlaps with the portion where the concave (R) of the active pattern (ACT) is placed, so the first width (W A1 A second channel width (W) that is relatively narrower than )A2 ) will have.

[0097] An organic light-emitting diode emits light at a desired brightness during the emission period in the emission region by controlling the driving current (Ion; on current) supplied to the thin-film transistor. This driving current (Ion) is influenced by the channel width (W) and channel length (L), as shown in [Equation 1] below.

[0098] [Equation 1]

[0099] Ion = W / L (W; channel width, L; channel length)

[0100] Referring to [Equation 1], the driving current (Ion) is proportional to the value of the channel width (W). In other words, if the channel width (W) increases, the amount of driving current (Ion) increases, and if the channel width (W) decreases, the amount of driving current (Ion) decreases. If the amount of driving current (Ion) decreases, a phenomenon occurs where the desired brightness cannot be achieved in the light-emitting region. Then, an additional compensation circuit is required to achieve the desired brightness in the light-emitting region, and consequently, power consumption increases.

[0101] As described above, when the shape of the active pattern is modified to prevent the effective channel length from being reduced by the conductive diffusion region, a phenomenon may occur in which the amount of driving current decreases as the channel width (W) where the gate electrode (GE) and the active pattern (ACT) overlap is reduced.

[0102] In this regard, according to an embodiment of the present specification, the shape of the active pattern is not deformed, and by placing a recess portion (164r) on the gate electrode (164), the channel width (W) can be prevented from being reduced.

[0103] Specifically, FIG. 17(a) illustrates a case where the gate electrode (164) is placed on the active pattern (130) at a normal alignment position (a1), and FIG. 17(b) illustrates a case where the gate electrode (164) is placed on the active pattern (130) at a position moved from the normal alignment position (a1) to a misalignment position (a2). In this case, the gate electrode (164) located at the normal alignment position (a1) or the misalignment position (a2) all have a channel width (W) of the same size. g1 , W g2 It can be confirmed that it has ). Accordingly, the channel width (W to be implemented g1 , W g2 It is possible to secure the driving current (Ion), thereby maintaining the amount of driving current and achieving the desired brightness in the light-emitting region for the duration of the light-emitting period. Accordingly, it is possible to prevent an increase in power consumption.

[0104] FIG. 18 illustrates a case where the gate insulating film and the gate electrode are etched simultaneously. Referring to FIG. 18, when the gate insulating film (GI) and the gate electrode (GE) are etched simultaneously, a dry etching method can be performed using a photoresist film pattern (PR) as an etching mask. However, if the dry etching method is performed, the conductive region (MRA) may be excessively lost from the dry etching reaction gas, and the thickness of the conductive region (MRA) may be excessively reduced (e1). In addition, when the gate insulating film (GI) and the gate electrode (GE) are etched simultaneously, the photoresist film pattern (PR) becomes narrower than the target photoresist film pattern (PRt), and a taper phenomenon may occur in which the slope of the gate electrode (GE) increases toward the top (e2).

[0105] In addition, metallic foreign matter generated from the conductive region (MRA) during the dry etching process may remain at the edge of the gate insulating film (GI), which degrades the insulation between the gate electrode (GE) and the active pattern (ACT), potentially causing a short circuit. Furthermore, the buffer layer (BF) may be lost due to the dry etching reaction gas (e4). Additionally, metallic foreign matter generated from the conductive region (MRA) during the dry etching process may be redeposited (rd) on the side of the gate insulating film (GI), causing the gate electrode (GE) and the active pattern (ACT) to be connected by the metallic foreign matter, which may cause a short circuit (e5).

[0106] On the other hand, in the embodiment of the present specification, before forming a plurality of GI holes on the gate insulating film (140) by a dry etching method, a conductive process is performed on the active pattern (130) to form conductive regions (130a, 130b), and a patterning process is performed to form the gate electrode (164).

[0107] Accordingly, the gate insulating film (140) remains unremoved during the patterning process for forming the gate electrode (164). The gate insulating film (140) covers both the exposed surfaces of the conductive region (130-1) and the conductive diffusion region (130-2). Since the gate insulating film (140) is not removed, even if the conductive region (130-1) is lowered by a certain thickness from the surface during the conductive process using plasma treatment, the gate insulating film (140) covers both the exposed surfaces of the conductive region (130-1) and the conductive diffusion region (130-2), thereby preventing an increase in contact resistance and improving the reliability of the device.

[0108] In addition, as the conductive regions (130a, 130b) are covered by the gate insulating film (140) during the process of patterning the gate electrode (164), it is possible to prevent metallic foreign matter from being generated from the conductive regions and to prevent a short circuit between the gate electrode and the active pattern, and to prevent the buffer layer from being lost. In addition, it is possible to prevent metallic foreign matter from remaining at the edges of the gate insulating film (140).

[0109] Referring to FIG. 11, an interlayer insulating film (180) is formed on a substrate (100) on which a gate electrode (164), a source electrode (166), a drain electrode (168), and a third storage electrode (168) are formed. The interlayer insulating film (180) is formed with a sufficient thickness to cover the surfaces of the gate electrode (164), the source electrode (166), the drain electrode (168), and the third storage electrode (168). Here, the interlayer insulating film (180) may not be formed on the pad electrode (170). The interlayer insulating film (180) may be formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0110] Next, a color filter (185) is formed on the interlayer insulating film (180). To do this, red (R), green (G), and blue (B) pigments are applied on the interlayer insulating film (180), and a mask process is performed to form a color filter (185) at a position corresponding to the light-emitting region. If the color filter (185) consists of red (R), green (G), and blue (B), the mask process may require three mask processes.

[0111] Referring to FIG. 12, a flattening film (190) is formed on an interlayer insulating film (180) on which a color filter (185) is placed.

[0112] The flattening film (190) can be formed with a sufficient thickness to flatten the surface on the substrate (100) while serving to protect the lower elements. The flattening film (190) can be formed by applying an organic insulating material such as acrylic resin, but is not limited thereto. Subsequently, the flattening film (190) and the interlayer insulating film (180) are patterned to form a pixel contact hole (192) that exposes a portion of the surface of the drain region (130a).

[0113] A first electrode (195) is formed on the flattening film (190), and a bank (200) is formed having a bank hole (205) that exposes a portion of the surface of the first electrode (195).

[0114] The first electrode (195) can be electrically connected to the gate electrode (164) through a drain region (130a) exposed by the pixel contact hole (192). The first electrode (195) may be composed of a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The first electrode (195) may also be referred to as an anode electrode or a pixel electrode. The first electrode (195) may be formed as a pad cover electrode (197) that covers the exposed surface of the pad electrode (170) to prevent corrosion.

[0115] A bank (200) having a bank hole (205) is disposed on a planarization film (190) on which a first electrode (195) is formed. The bank (200) serves to separate each sub-pixel by defining a boundary area that defines the light-emitting area of ​​the region where pixels are to be formed. Additionally, the bank (200) serves as a barrier to prevent light of different colors from adjacent pixels from mixing and being output. The bank (200) can be formed using an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as polyimide.

[0116] Referring to FIG. 13, an organic light-emitting layer (210) and a second electrode (215) are formed on a light-emitting region defined by a bank (200). Accordingly, an organic light-emitting device (OLED) composed of a first electrode (195), an organic light-emitting layer (210), and a second electrode (215) can be formed.

[0117] The organic light-emitting layer (210) is formed to be directly connected to the first electrode (195) exposed by the bank hole (205). In one example, the organic light-emitting layer (210) may be formed to extend along the exposed surface of the first electrode (195) to the upper surface of the bank (200). In one example, the organic light-emitting layer (210) is made of an organic material that emits white light and may display a color by means of a color filter (185).

[0118] Although not shown in the drawing, the organic light-emitting layer (210) may include a stacked structure of a hole transport layer (HTL), a light-emitting layer (EML), and an electron transport layer (ETL). The organic light-emitting layer may also be configured to further include a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL), and an electron injection layer (EIL) together with the hole transport layer (HTL), the light-emitting layer (EML), and the electron transport layer (ETL).

[0119] The second electrode (215) can be formed to cover the entire exposed surface of the organic light-emitting layer (210). The second electrode (215) can be formed as a common electrode that applies voltage by making common contact with adjacent pixels on the display area. The second electrode (215) may also be referred to as a cathode electrode.

[0120] In one example, the second electrode (215) may be composed of a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Alternatively, the second electrode (215) may be formed of a semipermeable metal material composed of molybdenum (Mo), tungsten (W), silver (Ag) or aluminum (Al) and an alloy containing at least one of these.

[0121] And, an encapsulation layer (220) can be formed on the second electrode (215). The encapsulation layer (220) serves to protect the organic light-emitting layer by preventing moisture or oxygen from penetrating into the organic light-emitting layer (210), and can be formed by including an insulating material.

[0122] As described above, a display device including a thin-film transistor according to an embodiment of the present specification can be configured such that the gate electrode is not overlapped with the conductive diffusion region by forming the gate electrode to include a plurality of recesses and protrusions. Accordingly, the effective channel length is reduced by the overlap between the conductive diffusion region and the gate electrode, thereby preventing the occurrence of off-current due to the short channel. Explanation of the symbols

[0124] 100: Substrate 105: Light-blocking layer 117: 1st buffer layer 119: 2nd buffer layer 130: Active Pattern 130-1: Conducting Region 130-2: Conducting diffusion region 130a: Drain conducting region 130b: Source conducting region 140: Gate insulating film 164: Gate electrode 166: Source electrode 168: Drain electrode 180: Interlayer insulation film 185: Color filter 190: Planarization film 195: First electrode 200: Bank 210: Organic light-emitting layer 215: Second electrode 220: Bag layer

Claims

Claim 1 A display device comprising a thin-film transistor, wherein the active pattern is located on a substrate and includes a channel region, a source region located between the channel region, and a drain region; a gate electrode located on the active pattern; a gate insulating film located between the gate electrode and the channel region; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region, wherein the source region and the drain region each include a conductive region and a conductive diffusion region, the gate electrode overlaps with the channel region but does not overlap with the conductive diffusion region, and the gate electrode includes a plurality of recesses located corresponding to the conductive diffusion region when viewed from a planar view, and a protrusion located not overlapping with the conductive diffusion region. Claim 2 delete Claim 3 A display device according to claim 1, wherein the recess portion comprises a thin-film transistor having a concave shape inwardly inwardly from one side portion of the gate electrode. Claim 4 A display device according to claim 1, wherein the gate electrode has a 'Wang' shape when viewed from a plane or a '—' shape crossing the center of I, comprising a thin-film transistor. Claim 5 A display device according to claim 1, wherein the gate electrode comprises a thin-film transistor having different widths from each other in the portion where the plurality of recesses are formed and the portion where the protrusions are formed. Claim 6 A display device comprising a thin-film transistor, wherein, in claim 5, the width of the portion in which a recess is formed at the gate electrode is relatively smaller than the width of the portion in which a protrusion is formed. Claim 7 A display device according to claim 1, wherein the gate insulating film covers both the exposed surfaces of the conductive region and the conductive diffusion region, and the thin-film transistor. Claim 8 A display device according to claim 1, wherein the gate insulating film further comprises: a source contact hole penetrating the gate insulating film to expose the source region; and a drain contact hole penetrating the gate insulating film to expose the drain region, wherein the source electrode fills the source contact hole and extends to the upper surface of the gate insulating film while in contact with the exposed surface of the source region, and the drain electrode fills the drain contact hole and extends to the upper surface of the gate insulating film while in contact with the exposed surface of the drain region. Claim 9 A display device according to claim 1, wherein the conductive diffusion region is positioned to extend from the conductive region in the direction of the channel region, and includes a thin-film transistor. Claim 10 A display device comprising a thin-film transistor, wherein the active pattern is located on a substrate and includes a channel region, a source region located between the channel region, and a drain region; a gate electrode located on the active pattern; a gate insulating film located between the gate electrode and the channel region; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region, wherein the source region and the drain region each include a conductive region and a conductive diffusion region, and the conductive diffusion region includes a first region disposed at each corner portion of the boundary surface between the channel region and the conductive region; and a second region disposed in a rod shape between adjacent first regions, and the gate electrode includes a plurality of recesses located corresponding to the first region of the conductive diffusion region when viewed from a planar view; and a protrusion located corresponding to the second region of the conductive diffusion region. Claim 11 delete Claim 12 A display device comprising a thin-film transistor according to claim 1, wherein the upper surface of the conductive region of each of the drain region and the source region is located at the same level as the upper surface of the channel region, and the conductive diffusion region is located at the same level as the upper surface of the channel region. Claim 13 A display device comprising a thin-film transistor according to claim 1, wherein the upper surface of the conductive region of each of the drain region and the source region is located at a lower level than the upper surface of the channel region, and the conductive diffusion region is located at the same level as the upper surface of the channel region. Claim 14 A display device according to claim 1, wherein the active pattern comprises a thin-film transistor comprising at least one of an oxide semiconductor material of the indium gallium zinc oxide (IGZO) system and the indium zinc oxide (IZO) system.

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