Printed circuit board, electronic device, and printed circuit board preparation method

Abstract

An electronic device, a printed circuit board, and a printed circuit board preparation method. The printed circuit board comprises a layer structure body, a transmission line (1), which is used for transmitting a signal, and at least two plated-through holes (2), which penetrate through the layer structure body, wherein the transmission line (1) is located in the layer structure body, and the two ends of the transmission line (1) are directly connected to hole walls of the two plated-through holes (2), respectively.

Description

Printed circuit board, electronic device, and printed circuit board manufacturing method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202211038535.9 filed on August 29, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to the field of printed circuit technology, and in particular to a printed circuit board, an electronic device, and a method for preparing the printed circuit board. Background Art

[0004] PCB (Printed Circuit Board) products with a rate of 112Gbps have begun commercialization, and 224Gbps products are under research. The major technical challenge encountered is how to improve the system's SI (Signal Integrity) performance and increase bandwidth. As an important component of the system, the printed circuit board largely determines system performance.

[0005] Reducing passive losses in printed circuit boards (PCBs) is a current research hotspot, and plated vias (PTHs) are a crucial component of passive channels. Currently, PTHs are connected to transmission lines, allowing transmission lines from within the PCB to be routed to the outer layers through the PTHs, where they connect to chip pins or connector pins, forming a complete signal transmission path. However, these PCBs suffer from poor signal transmission integrity and significant signal loss.

[0006] Public content

[0007] On the one hand, an embodiment of the present disclosure provides a printed circuit board, comprising a layer structure body, a transmission line for transmitting signals, and at least two metallized holes passing through the layer structure body, wherein the transmission line is located in the layer structure body, and the two ends of the transmission line are directly connected to the hole walls of the two metallized holes respectively.

[0008] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the printed circuit board as described above.

[0009] On the other hand, an embodiment of the present disclosure also provides a method for preparing a printed circuit board, which is used to prepare the printed circuit board as described above, including: performing printed circuit board signal simulation, determining a target area of ​​the printed circuit board based on the simulation results, wherein the target area is an area where the signal integrity performance parameters do not meet preset conditions; and preparing the printed circuit board, wherein the metallized hole is located in the target area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a schematic cross-sectional view of a printed circuit board according to an embodiment of the present disclosure;

[0011] FIG2 is a schematic diagram of the connection between a metallized hole and a transmission line provided by an embodiment of the present disclosure;

[0012] FIG3 is a top view of a printed circuit board provided in an embodiment of the present disclosure;

[0013] FIG4 is a schematic diagram comparing the insertion loss effects of a printed circuit board in related art and a printed circuit board provided by an embodiment of the present disclosure; and

[0014] FIG5 is a schematic diagram comparing the return loss effects of a printed circuit board in related art and a printed circuit board provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Hereinafter, example embodiments will be described more fully with reference to the accompanying drawings, but the example embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth herein. These examples are provided to make the present disclosure more thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0016] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] The terms used herein are used only to describe specific embodiments and do not limit the present disclosure. As used herein, the singular forms "a", "an", and "the" also include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, they specify the presence of specific features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0018] The embodiments described herein may be described with reference to plan views and / or cross-sectional views, with the aid of idealized schematic diagrams of the present disclosure. Thus, the example illustrations may be modified based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions of the components, but are not intended to be limiting.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0020] In related technologies, metallized vias (PTHs) are connected to transmission lines. These PTHs allow transmission lines inside the PCB to be introduced into the outer layers of the PCB, where they connect to chip pins or connector pins, forming a complete signal transmission path. The signal transmission direction is: signal input (which can be the chip end) → PTH → external pad → transmission line → via pad → PTH → signal output. In this PTH-to-transmission line connection scheme, the PTH and transmission line are connected via via pads, which can affect impedance continuity and signal integrity, leading to significant signal loss and other issues.

[0021] The embodiments of the present disclosure provide a printed circuit board and a method for preparing the printed circuit board. By removing the via pads inside the PCB board, the metallized holes are directly connected to the transmission lines, thereby achieving impedance continuity of signal transmission and improving signal integrity.

[0022] Figure 1 is a schematic diagram of the cross-sectional structure of a printed circuit board provided in an embodiment of the present disclosure, Figure 2 is a schematic diagram of the connection between the metallized hole and the transmission line provided in an embodiment of the present disclosure, and Figure 3 is a top view of the printed circuit board provided in an embodiment of the present disclosure. Combined with Figures 1 to 3, the printed circuit board provided in an embodiment of the present disclosure includes a layer structure body, a transmission line 1 for transmitting signals, and at least two metallized holes 2 passing through the layer structure body. The transmission line 1 is located in the layer structure body, and the two ends of the transmission line 1 are directly connected to the hole walls of the two metallized holes 2 respectively.

[0023] In the printed circuit board provided in the embodiment of the present disclosure, the metallized holes 2 are located in the BGA (Ball Grid Array) area and / or the connector area of ​​the layer structure body, and the spacing between each metallized hole 2 is equal. The metallized holes 2 are formed into a hole structure by a drill rotating at high speed on the layer structure body, and metal is formed on the hole structure by electroplating or chemical plating to obtain the metallized holes 2. Generally, the metal of the metallized holes 2 is copper. The transmission line 1 can be prepared and formed by metallic copper, can be formed by etching a copper core board, or can be a copper line. It should be noted that the transmission line 1 and the metallized holes 2 are in the same circuit loop.

[0024] The layer structure body can be a single-layer structure or a multi-layer structure. A single-layer structure is a single-layer PCB board, and a multi-layer structure is a multi-layer PCB board. In the printed circuit board provided in the embodiment of the present disclosure, as shown in Figure 1, the layer structure body with a multi-layer structure is used as an example for explanation. The printed circuit board is a multi-layer board.

[0025] The printed circuit board provided in the embodiment of the present disclosure includes a layer structure body, a transmission line 1 for transmitting signals, and at least two metallized holes 2 that penetrate the layer structure body. The transmission line 1 is located in the layer structure body, and the two ends of the transmission line 1 are directly connected to the hole walls of the two metallized holes 2 respectively; the embodiment of the present disclosure removes the via pad located inside the layer structure body, and the transmission line 1 is directly connected to the hole walls of the metallized hole 2, which can reduce impedance mismatch and signal insertion loss and return loss, thereby improving signal integrity.

[0026] In some embodiments, both ends of the transmission line 1 are connected to the outer walls of the two metallized holes 2 respectively by electroplating.

[0027] To prevent breakage caused by a faster chemical reaction rate at the plated hole 2 than at other locations during the electroplating process, additional compensation can be applied to the connection between the plated hole 2 and the transmission line 1. This is done by increasing the width of the transmission line 1 at that location (the dimension along the vertical direction in FIG. 3 ). The amount of increased width is determined by the process level and capability. Therefore, in some embodiments, the width of the transmission line 1 at both ends is greater than the width of the portion of the transmission line 1 not connected to the two plated holes 2.

[0028] In some embodiments, as shown in FIG1 and FIG2 , the printed circuit board further includes solder pads 3. The number of solder pads 3 is the same as the number of metallized holes 2. The solder pads 3 are located on the first surface of the layer structure body. The solder pads 3 are electrically connected to the signal input or signal output of the printed circuit board. Each solder pad 3 covers each metallized hole 2 and is connected to the hole wall of each metallized hole 2. The material of the solder pads 3 is typically copper.

[0029] In some embodiments, the printed circuit board is a multilayer board. Accordingly, as shown in FIG1 , the layer structure body includes a first layer structure 41 and at least one second layer structure 42. Each second layer structure 42 is stacked with the first layer structure 41. The transmission line 1 is located within the first layer structure 41. The first layer structure 41 and the second layer structure 42 may be core boards. In the printed circuit board provided in the embodiment of the present disclosure, a second layer structure 42 is used as an example for illustration. In the printed circuit board shown in FIG1 , the second layer structure 42 is located on the side of the first layer structure 41 adjacent to the pad 3. The first surface of the layer structure body is the surface of the second layer structure 42 away from the first layer structure 41.

[0030] In some embodiments, the second layer structure 42 includes a stacked third dielectric layer 421 and a fourth dielectric layer 422, with the fourth dielectric layer 422 located on a side of the third dielectric layer 421 away from the pad 3. The first layer structure 41 includes a stacked first dielectric layer 411 and a second dielectric layer 412, with the first dielectric layer 411 located on a side of the second dielectric layer 412 adjacent to the pad 3.

[0031] In some embodiments, the printed circuit board is a single-layer board. Accordingly, the layer structure body includes a first layer structure, which includes a first dielectric layer and a second dielectric layer stacked together. In this case, the first surface of the layer structure body is the surface of the first dielectric layer facing away from the second dielectric layer, and the transmission line is located within the second dielectric layer. In other words, compared to a multi-layer printed circuit board, a single-layer printed circuit board lacks the second layer structure 42 and only has the first layer structure 41.

[0032] In some embodiments, as shown in FIG1 , the printed circuit board further comprises a fifth dielectric layer 5, which is located on a side of the layer structure body away from the pad 3. Back-drilled vias 6 are provided at positions of the fifth dielectric layer 5 corresponding to the metallized vias 2, penetrating the fifth dielectric layer 5. Each back-drilled via 6 is connected to each metallized via 2.

[0033] In some embodiments, each dielectric layer is generally composed of resin, glass fiber, filler and other components.

[0034] The impedance of the signal transmission line will not change when it is wired in the same line width and the same plane, which can ensure that the signal is transmitted indiscriminately, reduce signal reflection, and maximize the signal quality. However, after the transmission line passes through the layer, the impedance will change, the reflection will increase, the signal loss will increase, and the quality of the transmitted signal will deteriorate. The signal is transmitted through the metallized via through the layer to connect the transmission line. If the metallized via is input on the first layer of the four-layer printed circuit board and output on the third layer of the printed circuit board through the metallized via, then the residual end of the metallized via between the third and fourth layers of the printed circuit board (i.e., the hole copper) causes signal loss. Therefore, in the printed circuit board provided in the embodiment of the present disclosure, the back drilling 6 can be used to remove the excess hole copper of the metallized hole 2 on the side of the second dielectric layer 412 away from the pad 3, thereby reducing signal loss and improving signal transmission quality.

[0035] The disclosed embodiment only takes the pad design into consideration, achieving both signal integrity and design processability, and solving the via signal distortion problem that the prior art cannot achieve high performance.

[0036] An embodiment of the present disclosure further provides an electronic device, which includes the printed circuit board as described above.

[0037] The embodiment of the present disclosure further provides a method for preparing a printed circuit board, which is used to prepare the printed circuit board as described above. The printed circuit board preparation method includes the following steps S11 and S12.

[0038] Step S11 , performing printed circuit board signal simulation, and determining a target area of ​​the printed circuit board based on the simulation results. The target area is an area where signal integrity performance parameters do not meet preset conditions. It should be noted that the target area is part or all of the BGA area and / or connector area of ​​the printed circuit board.

[0039] In this step, signal simulation is performed on the printed circuit board according to the design requirements to locate target areas with large signal loss. For example, the simulation results show that there are discontinuities in the impedance of the metallized holes and the signal integrity performance parameters do not meet the preset conditions.

[0040] In some embodiments, the signal integrity performance parameter includes insertion loss and / or return loss.

[0041] Step S12: preparing a printed circuit board, with the metallized holes located in the target area.

[0042] It should be noted that, for the target area, the signal loss can be reduced by first reducing the aperture of the metallized hole, adjusting the line width of the transmission line, etc. If the above methods do not work, the via pad located inside the layer structure body can be removed, and the transmission line 1 can be directly connected to the hole wall of the metallized hole 2.

[0043] In the process of preparing printed circuit boards, photolithography GERBER data is first produced and designed using electronic design automation (EDA) software.

[0044] 1. Create a network layout diagram. Arrange the electronic components according to the design schematic.

[0045] 2. Connect the network. Use the connection method to connect the various components to form the entire network structure diagram.

[0046] 3. Create pad-free materials. In the BGA area and / or connector area where the metallized holes are set, optimize the via pads, delete the via pads or adjust the size of the via pads to the diameter of the metallized holes.

[0047] 4. Output the gerber file. The output is a gerber file in a universal format that can be used with a suffix that can be recognized by printed circuit board manufacturers.

[0048] After completing the photolithography of the GERBER data, prepare a printed circuit board without via pads.

[0049] 1. In the PCB design data, find the signal hole without pad.

[0050] 2. Inner core board pattern transfer and production. The inner core board undergoes processes such as lamination, exposure, and development to complete the inner layer pattern transfer and form the transmission line pattern on the inner core board.

[0051] 3. Lamination: Lamination of the prepreg and the inner core board to form a multi-layer PCB.

[0052] 4. Drilling: Perform mechanical drilling according to normal design requirements, with the drilling tool diameter being the designed drilling diameter, to obtain a back-drilled hole.

[0053] The printed circuit board preparation method of the embodiment of the present disclosure determines the target area with large signal loss through signal simulation. Within the target area, the via pad located inside the layer structure body is removed, and the transmission line 1 is directly connected to the hole wall of the metallized hole 2. This can reduce the impedance mismatch and the signal insertion loss and return loss, thereby improving the signal integrity.

[0054] It should be noted that, instead of removing the pads located within the layer structure body for the target area, the entire printed circuit board can be free of via pads located within the layer structure body, thereby achieving a design without via pads for the entire printed circuit board. Figure 4 is a schematic diagram comparing the insertion loss effects of a printed circuit board in the related art and the printed circuit board provided by an embodiment of the present disclosure, and Figure 5 is a schematic diagram comparing the return loss effects of a printed circuit board in the related art and the printed circuit board provided by an embodiment of the present disclosure. The following describes the test experimental results of the embodiment of the present disclosure in conjunction with Figures 4 and 5.

[0055] As shown in Figure 4, the thick solid line curve at the bottom of the figure represents the signal insertion loss curve for a PCB board with a 4-mil via pad in the related art, while the thin solid line curve at the top represents the signal insertion loss curve for the PCB board according to the present disclosure. In Figure 4, the x-axis represents frequency, and the y-axis represents insertion loss. As can be seen from Figure 4, at higher frequencies, the signal insertion loss curve for the PCB board according to the present disclosure is closer to zero, indicating lower signal loss.

[0056] As shown in Figure 5, the light-colored curve represents the signal return loss curve for a PCB board with a 4-mil via pad in the related art, while the dark-colored curve represents the signal return loss curve for a PCB board according to an embodiment of the present disclosure. In Figure 5, the x-axis represents frequency, and the y-axis represents return loss. As can be seen from Figure 5, at higher frequencies, the signal return loss of the related art PCB board is closer to zero, resulting in greater signal loss.

[0057] The printed circuit board of the embodiment of the present disclosure does not increase the complexity and difficulty of the printed circuit board manufacturing process, and can also improve impedance matching, reduce the impedance mismatch factor between the input and output ends, greatly improve the signal integrity of the metallized holes, and reduce signal loss. It solves the problem of balancing the signal integrity and design processability of the metallized holes under high-speed transmission requirements.

[0058] The embodiments of the present disclosure are applicable to high-speed printed circuit board design products, and are particularly suitable for wired and wireless products with speeds of 224 Gbps and above. They can be applied to printed circuit boards with a design speed of 224 Gbps and above, or to printed circuit boards with a design speed that does not reach 224 Gbps but requires low signal loss.

[0059] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, and the functional modules / units in the device can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor (such as a central processing unit, a digital signal processor, or a microprocessor), or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0060] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A printed circuit board, comprising a layer structure body, a transmission line for transmitting signals and at least two metallized holes penetrating the layer structure body, wherein the transmission line is located in the layer structure body, and two ends of the transmission line are directly connected to the hole walls of the two metallized holes respectively.

2. The printed circuit board according to claim 1, wherein: The two ends of the transmission line are respectively connected to the outer walls of the two metallized holes by electroplating.

3. The printed circuit board as described in claim 1 further includes a number of solder pads equal to the number of the metallized holes, wherein the solder pads are located on the first surface of the layer structure body, and the solder pads are electrically connected to the signal input terminal or the signal output terminal of the printed circuit board, and each of the solder pads respectively covers each of the metallized holes and is respectively connected to the hole wall of each of the metallized holes.

4. The printed circuit board according to claim 3, wherein: The layer structure body comprises a first layer structure, the first layer structure comprises a first dielectric layer and a second dielectric layer stacked, the first surface is a surface of the first dielectric layer away from the second dielectric layer, and the transmission line is located in the second dielectric layer.

5. The printed circuit board according to claim 3, wherein: The layer structure body includes a first layer structure and at least one second layer structure, each of the second layer structures is stacked with the first layer structure, the first surface is a surface of the second layer structure away from the first layer structure, and the transmission line is located in the first layer structure.

6. The printed circuit board according to claim 5, wherein: The second layer structure comprises a third dielectric layer and a fourth dielectric layer which are stacked, and the fourth dielectric layer is located on a side of the third dielectric layer away from the pad; The first layer structure includes a first dielectric layer and a second dielectric layer which are stacked, and the first dielectric layer is located on a side of the second dielectric layer adjacent to the pad.

7. The printed circuit board according to claim 4 or 5, further comprising a fifth dielectric layer, wherein the fifth dielectric layer is located on a side of the layer structure body away from the pad; A back-drilled hole penetrating the fifth dielectric layer is disposed at a position of the fifth dielectric layer corresponding to each of the metallized holes, and each of the back-drilled holes is connected to each of the metallized holes.

8. An electronic device comprising the printed circuit board according to any one of claims 1 to 7.

9. A method for preparing a printed circuit board, for preparing the printed circuit board according to any one of claims 1 to 7, comprising: Performing printed circuit board signal simulation, and determining a target area of ​​the printed circuit board according to the simulation result, wherein the target area is an area where the signal integrity performance parameter does not meet the preset conditions; as well as A printed circuit board is prepared, wherein the metallized hole is located in the target area.

10. The method of claim 9, wherein: The signal integrity performance parameter includes at least one of insertion loss or return loss.

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