Optical-digital communication architecture and devices

Abstract

Aspects of this technical solution can generate, by a neural network, a weight matrix, map the weight matrix to one or more of a plurality of VCSEL transceivers, and cause the one or more of the plurality of VCSEL transceivers to generate one or more beams according to the weight matrix. In an aspect, this technical solution can incorporate thin-film lithium niobate (TEEN) electro-optic modulators for encoding input activation values and use low- energy vertical-cavity surface-emitting lasers (VCSELs) for high-speed weight streaming. A combination of high clock rates (>10 GHz) and low energy costs (fl-scale) enabled by low- voltage operation can facilitate at least the technical improvement of scalable optical computing.

Description

OPTICAL-DIGITAL COMMUNICATION ARCHITECTURE AND DEVICESCROSS-REFERENCE TO RELATED PATENT APPLICATIONS

[0001] This application claims the benefit of priority under 35 U.S.C. § 119 to U.S. Provisional Patent Application Serial No. 63 / 445,128, entitled "ULTRALOW-ENERGY OPTICAL-DIGITAL COMPUTING AT CMOS COMPATIBLE VOLTAGES," filed February 13, 2023, the contents of such application being hereby incorporated by reference in its entirety and for all purposes as if completely and fully set forth herein.TECHNICAL FIELD

[0001] The present implementations relate generally to computing devices, including but not limited to an optical-digital communication architecture and devices.SUMMARY

[0002] Aspects of this technical solution are directed to a scalable time-wavelength- multiplexed optical neural network using high-bandwidth (>45 GHz) electro-optic modulators at CMOS compatible voltages (V7t=l .3 V). High precision (> 8 bits) allows image classification with accuracy close to ground truth. Thus, a technological solution for ultralow- energy computing with thin-film lithium niobate optics is provided.

[0003] At least one aspect is directed to a system. The system can include a memory and one or more processors. The system can generate, by a neural network, a weight matrix. The system can map the weight matrix to one or more of a plurality of VCSEL transceivers. The system can cause the one or more of the plurality of VCSEL transceivers to generate one or more beams according to the weight matrix.

[0004] At least one aspect is directed to a method. The method can include generating, by a neural network, a weight matrix. The method can include mapping the weight matrix to one or more of a plurality of VCSEL transceivers. The method can include causing the one or more of the plurality of VCSEL transceivers to generate one or more beams according to the weight matrix.

[0005] At least one aspect is directed to a system. The system can include an optical demultiplexer to separate an optical transmission into a plurality of components. The systemcan a photodiode array to transform each of the components into corresponding analog electrical transmissions. The system can an analog-to-digital (ADC) circuit to transmit one or more digital transmissions corresponding to one or more of the analog electrical transmissions.

[0006] At least one aspect is directed to a method. The method can include separating, by an optical demultiplexer, an optical transmission into a plurality of components. The method can include transforming, by a photodiode array structured to receive output of the optical demultiplexer, each of the components into corresponding analog electrical transmissions. The method can include transmitting, by an analog-to-digital (ADC) circuit structured to receive output of the photodiode array, one or more digital transmissions corresponding to one or more of the analog electrical transmissions.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] These and other aspects and features of the present implementations will become apparent to those ordinarily skilled in the art upon review of the following description of specific implementations in conjunction with the accompanying figures, wherein:

[0008] Fig. 1 illustrates a processor system in accordance with present implementations.

[0009] Fig. 2 illustrates a neural network with fully connected layers in accordance with present implementations.

[0010] Fig. 3 illustrates matrix vector multiplication with a VCSEL weight bank and data activation with a TFLN modulator in accordance with present implementations.

[0011] Fig. 4 illustrates a device corresponding to a neuron of a neural network having an optical-digital architecture in accordance with present implementations.

[0012] Fig. 5 illustrates a modulation bandwidth of a TFLN modulator in accordance with present implementations.

[0013] Fig. 6 illustrates a data encoding with a TFLN modulator with an example <0.4% error, in accordance with present implementations.

[0014] Fig. 7 illustrates a vector multiplier with a VCSEL and a TFLN modulator in accordance with present implementations.

[0015] Fig. 8 illustrates a time integrator of a vector multiplier with a VCSEL and a TFLN modulator in accordance with present implementations.

[0016] Fig. 9 illustrates a distribution corresponding to a TFLN modulator in accordance with present implementations.

[0017] Fig. 10 illustrates a scatter plot of a multiplication result in accordance with present implementations.

[0018] Fig. 11 illustrates a histogram of an error of a multiplication result in accordance with present implementations.

[0019] Fig. 12 illustrates a result of time-frequency multiplication, in accordance with present implementations.

[0020] Fig. 13 illustrates a classification vector in accordance with present implementations.

[0021] Fig. 14 illustrates a time-wavelength multiplexing matrix multiplexer architecture, in accordance with present implementations.

[0022] Fig. 15 illustrates an optical-digital architecture in accordance with present implementations.

[0023] Fig. 16 illustrates a system architecture including server and edge devices, in accordance with present implementations.

[0024] Fig. 17 illustrates a graphics processing unit (GPU) having an optical-digital architecture in accordance with present implementations.

[0025] Fig. 18 illustrates a cross-sectional view of a graphics processing unit (GPU) having an optical-digital architecture in accordance with present implementations.

[0026] Fig. 19 illustrates a cascading optical-digital architecture corresponding to a neural network architecture, in accordance with present implementations.

[0027] FIG. 20 depicts an example method of operating an optical-digital communication architecture according to this disclosure.

[0028] FIG. 21 depicts an example method of operating an optical-digital communication architecture according to this disclosure.DETAILED DESCRIPTION

[0029] The present implementations will now be described in detail with reference to the drawings, which are provided as illustrative examples of the implementations so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art. Notably, the figures and examples below are not meant to limit the scope of the present implementations to a single implementation, but other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the present implementations can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present implementations will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the present implementations. Implementations described as being implemented in software should not be limited thereto, but can include implementations implemented in hardware, or combinations of software and hardware, and vice-versa, as will be apparent to those skilled in the art, unless otherwise specified herein. In the present specification, an implementation showing a singular component should not be considered limiting; rather, the present disclosure is intended to encompass other implementations including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present implementations encompass present and future known equivalents to the known components referred to herein by way of illustration.

[0030] Optical neural networks (ONNs) are emerging to accelerate machine learning tasks with high optical bandwidth, low-loss data movement, and parallelism. For example, ONN systems based on silicon photonics show ONN scalability and ultralow latency. Neuromorphic computing with large-scale matrix operations can be memory -intensive. Thus, interfacing digital memory with high-speed, low-loss optical interconnects at complementary metal-oxide-semiconductor (CMOS) compatible voltages can be advantageous to eliminate a bottleneck, since various silicon photonics implementations cannot achieve all the above requirements simultaneously.

[0031] This technical solution can incorporate thin-film lithium niobate (TFLN) electro-optic modulators for encoding input activation values and use low-energy vertical -cavity surfaceemitting lasers (VCSELs) for high-speed weight streaming. A combination of high clock rates (>10 GHz) and low energy costs (fJ-scale) enabled by low-voltage operation can facilitate at least the technical improvement of scalable optical computing.

[0032] An example ONN architecture according to present implementations can include a number “n” of fully-connected layers. Each layer can perform a matrix-vector multiplication with time-wavelength multiplexing. The weight matrix Wijncan be mapped in “I” time steps to a bank of “j” individually addressable VCSEL transceivers of different wavelengths. The VCSEL beams can be combined and input to a broadband TFLN intensity modulator, where the input Xinis encoded. The cascaded modulation can lead to multiplication of laser intensity. At the receiver side, each weight beam can be demultiplexed and the resulting photocurrents can be accumulated over i time steps, yielding Si WijnXin. Since up to all the wavelengths can be modulated with the same TFLN modulator, the electronic power consumption for each data activation (~1 pJ / Symbol) can be amortized by a factor of j, which can be j=100 using, enabling computing orders of magnitude below existing electronic systems.

[0033] Fig. 1 illustrates a processor system in accordance with present implementations. As illustrated by way of example in Fig. 1, an example processing system 100 can include a system processor 110, a parallel processor 120, a transform processor 130, a system memory 140, and a communication interface 150. At least one of the example processing system 100 and the system processor 110 can include a processor bus 112 and a system bus 114.

[0034] The system processor 110 can execute one or more instructions. The system processor 110 can obtain one or more of the instructions via at least one of the system memory 140 and the communication interface 150. The system processor 110 can include an electronic processor, an integrated circuit, or any combination thereof, for example, including one or more of digital logic, analog logic, digital sensors, analog sensors, communication buses, volatile memory, nonvolatile memory, or any combination thereof. The system processor 110 can include but is not limited to, at least one microcontroller unit (MCU), microprocessor unit (MPU), central processing unit (CPU), graphics processing unit (GPU), physics processing unit (PPU), embedded controller (EC), or any combination thereof, for example. The system processor 110 can include a memory operable to store or storing one or more instructions for operating components of the system processor 110 and operating componentsoperably coupled to the system processor 110. The one or more instructions can include at least one of firmware, software, hardware, operating systems, embedded operating systems, or any combination thereof.

[0035] The processor bus 112 can communicate one or more instructions, signals, conditions, states, or any combination thereof, for example, between one or more of the system processor 110, the parallel processor 120, and the transform processor 130. The system bus 114 can communicate one or more instructions, signals, conditions, states, or any combination thereof, for example, between one or more of the system processor 110, the system memory 140, and the communication interface 150. The processor bus 112 and the system bus 114 can respectively include one or more channels, lines, traces, or any combination thereof, for example, that can perform digital or analog communication. Any devices or components associated with the processor bus 112 or the system bus 114 can also be associated with, integrated with, supplemented by or complemented by, for example, the system processor 110 or any component thereof.

[0036] The parallel processor 120 can execute one or more instructions concurrently, simultaneously, or any combination thereof. The parallel processor 120 can execute one or more instructions in a parallelized order in accordance with one or more parallelized instruction parameters. In some implementations, parallelized instruction parameters include one or more sets, groups, ranges, types, or any combination thereof, associated with various instructions. The parallel processor 120 can include one or more execution cores variously associated with various instructions. The parallel processor 120 can include one or more execution cores variously associated with various instruction types or any combination thereof. The parallel processor 120 can include an electronic processor, an integrated circuit, or any combination thereof, for example, including one or more of digital logic, analog logic, communication buses, volatile memory, nonvolatile memory, or any combination thereof. The parallel processor 120 can include but can include not limited to, at least one graphics processing unit (GPU), physics processing unit (PPU), embedded controller (EC), gate array, programmable gate array (PGA), field-programmable gate array (FPGA), applicationspecific integrated circuit (ASIC), or any combination thereof. Any electrical, electronic, or like devices, or components associated with the parallel processor 120 can also be associated with, integrated with, supplemented by, complemented by, or any combination thereof, the system processor 110 or any component thereof.

[0037] One or more cores of the parallel processor 120 can be linked with one or more parallelizable operations in accordance with one or more metrics, engines, models, or any combination thereof, of the technical solution discussed herein. For example, parallelizable operations can include processing portions of an image, video, waveform, audio waveform, processor thread, one or more layers of a learning model, one or more metrics of a learning model, one or more models of a learning system, or any combination thereof. For example, a predetermined number or predetermined set of one or more particular cores of the parallel processor 120 can be associated exclusively with one or more distinct sets of corresponding metrics, engines, models, or any combination thereof, in accordance with the technical solution discussed herein. A first core of the parallel processor 120 can be assigned to, associated with, configured to, or fabricated to, execute instructions or operations corresponding to a portion or subset of the instructions or operations of the technical solution discussed herein. Thus, the parallel processor 120 can parallelize execution across one or more metrics, engines, models, or any combination thereof.

[0038] The transform processor 130 can execute one or more instructions associated with one or more predetermined transformation processes. For example, a transformation process can include a Fourier transform, matrix operation, calculus operation, combinatoric operation, trigonometric operation, geometric operations encoding operation, decoding operation, compression operation, decompression operation, image processing operation, audio processing operation, speech processing operation, or any combination thereof. The transform processor 130 can execute one or more transformation processes in accordance with one or more transformation instruction parameters. For example, a transformation instruction parameter can include an instruction to link the transform processor 130 with a predetermined transformation process. The transform processor 130 can be linked with one or more transformation processes. The transform processor 130 can include a plurality of transform processors 130 associated with various predetermined transformation processes. The transform processor 130 can include a plurality of transformation processing cores each associated with, configured to execute, fabricated to execute, or any combination thereof, a predetermined transformation process. For example, the transform processor 130 can include a first processor or core configured to execute a first transformation process, and a second processor or core configured to execute a second transformation process. The transform processor 130 can include an electronic processor, an integrated circuit, or any combination thereof, including one or more of digital logic, analog logic, communication buses, volatilememory, nonvolatile memory, or any combination thereof. The transform processor 130 can include but is not limited to, at least one graphics processing unit (GPU), physics processing unit (PPU), embedded controller (EC), gate array, programmable gate array (PGA), field- programmable gate array (FPGA), application-specific integrated circuit (ASIC), or any combination thereof having an architecture distinct from the system processor 110 and the parallel processor 120. Any electrical, electronic, or like devices, or components associated with the transform processor 130 can also be associated with, integrated with, supplemented by or complemented by, for example, the system processor 110 or any component thereof.

[0039] The transform processor 130 can execute one or more predetermined transform processes in accordance with one or more metrics, engines, models, or any combination thereof, of the technical solution discussed herein. In some implementations, a predetermined transform process of the transform processor 130 can be associated with one or more corresponding metrics, engines, models, or any combination thereof, of the technical solution discussed herein. For example, the transform processor 130 can be assigned to, associated with, configured to, or fabricated to execute a matrix operation associated with one or more engines, metrics, models, or any combination thereof, of the technical solution discussed herein. Thus, the transform processor 130 can centralize, optimize, or coordinate, for example, execution of a transform process across one or more metrics, engines, models, or any combination thereof, of the technical solution discussed herein. The transform processor 130 can be fabricated to or configured to execute a particular transform process with a minimized or optimized device factor. For example, a device factor can include a physical logic footprint, logic complexity, heat expenditure, heat generation, power consumption, or any combination thereof, with respect to at least one metrics, engines, models, or any combination thereof.

[0040] The system memory 140 can store data associated with the example processing system 100. The system memory 140 can include a hardware memory device to store binary data, digital data, or any combination thereof. The system memory 140 can include one or more electrical components, electronic components, programmable electronic components, reprogrammable electronic components, integrated circuits, semiconductor devices, flip flops, arithmetic units, or any combination thereof. The system memory 140 can include at least one of a non-volatile memory device, a solid-state memory device, a flash memory device, and a NAND memory device. The system memory 140 can include one or moreaddressable memory regions disposed on one or more physical memory arrays. For example, a physical memory array can include a NAND gate array disposed on a particular semiconductor device, integrated circuit device, printed circuit board device, or any combination thereof.

[0041] The communication interface 150 can communicatively couple at least the system processor 110 to an external device. For example, an external device can include but is not limited to a smartphone, mobile device, wearable mobile device, tablet computer, desktop computer, laptop computer, cloud server, local server, or any combination thereof. The communication interface 150 can communicate one or more instructions, signals, conditions, states, or any combination thereof between one or more of the system processor 110 and the external device. The communication interface 150 can include one or more channels, lines, traces, or any combination thereof, for example, that can perform digital or analog communication. For example, the communication interface 150 can include one or more serial or parallel communication lines among multiple communication lines of a communication interface. The communication interface 150 can include one or more wired or wireless communication devices, systems, protocols, or interfaces. The communication interface 150 can include one or more logical or electronic devices including but not limited to integrated circuits, logic gates, flip flops, gate arrays, programmable gate arrays, or any combination thereof. The communication interface 150 can include one or more telecommunication devices including but not limited to antennas, transceivers, packetizers, wired interface ports, or any combination thereof. Any electrical, electronic, or like devices, or components associated with the communication interface 150 can also be associated with, integrated with, supplemented by or complemented by the system processor 110 or any component thereof.

[0042] Fig. 2 illustrates a neural network with fully connected layers in accordance with present implementations. As illustrated by way of example in FIG. 2, a neural network 200 can include at least an input layer 202, a hidden layer 204, and an output layer 206. The input layer 202 can include an input layer nodes 210, and an input layer network 212. The hidden layer 204 can include hidden layer nodes 220, and a hidden layer network 222. The output layer 206 can include an output layer nodes 230.

[0043] Fig. 3 illustrates matrix vector multiplication with a VCSEL weight bank and data activation with a TFLN modulator in accordance with present implementations. As illustratedby way of example in FIG. 3, a signal processing architecture 300 can include at least an optical tranmission components 302, an analog electrical output 304, a VCSEL array 310, an optical multiplexer 320, a modulator 330, a neural network 332, an activation vector 334, an optical demuiltiplexer 340, a photodiode array 350, and a summing circuit 360.

[0044] An example VCSEL can operate at 1550 nm with a 3 dB bandwidth of 13 GHz. With biasing at 1.5 V, it can emit 500 pW output power, which is edge-coupled to a TFLN modulator of 45 GHz bandwidth with a TI phase shift voltage of V7t=l .3 V. With this example calibration, the TFLN modulator is capable of encoding analog data with 8 bits of precision with a statistical error of 0.4%. Compute accuracy, can be validated by normal-distributed random floating point vectors, each with 10,000 symbols, as a weights vector Win to a VCSEL and an activation vector Xn to the TFLN modulator. After the photodetector, the multiplication result can be obtained with a statistical error of, for example, 1.4% compared to ground truth. This technical solution can implement neural network inference with a singlelayer MNIST digit classification with network size of 28 / 28^ 10. Each image with 28^28 pixels can be reshaped to a 1-D vector with 784 data points, multiplying with a weight vector of the same length. The product of the two vectors can be compared to a calculated result, indicating excellent consistency. The images can be classified by comparing the accumulated photon voltages resulting from the 10 weighting channels. For example, this technical solution including as input 20 random images in a single stream (based on available size of the system memory) with an example photonic multiplier obtained a classification accuracy of 90%, which is close to the electronic accuracy of the network (91%).

[0045] This technical solution is thus directed to an architecture with an ONN, a TFLN modulator and VCSEL arrays. This technical solution has at least the technical advantages of higher energy utilization and parallel computing ability. With photonic integration of interfacing VCSEL on TFLN, this technical solution can be fully integrated to reduce energy cost for both general-purpose computing accelerators and edge devices.

[0046] Fig. 4 illustrates a device 400 corresponding to a neuron of a neural network having an optical-digital architecture in accordance with present implementations. For example, in a configuration of a TFLN-modulator-based neuron, output can correspond to a final result or an input to a next layer of a neural network. Technical advantages from the modulator can include high bandwidth, high speed, low loss, low energy consumption, CMOS compatibility, and compact on-chip integration. Fig. 5 illustrates a modulation bandwidth 500 of a TFLNmodulator in accordance with present implementations. Fig. 6 illustrates a data encoding 600 with a TFLN modulator with an example <0.4% error, in accordance with present implementations.

[0047] Fig. 7 illustrates a vector multiplier 700 with a VCSEL and a TFLN modulator in accordance with present implementations. As illustrated by way of example in FIG. 7, a signal processing architecture 700 can include at least a VCSEL 710, a weight 712, a modulator 720, a modulator 720, an activation vector 722, and a photodiode 730. Fig. 8 illustrates a time integrator 800 of a vector multiplier with a VCSEL and a TFLN modulator in accordance with present implementations. Fig. 9 illustrates a distribution 900 corresponding to a TFLN modulator in accordance with present implementations. Fig. 10 illustrates a scatter plot 1000 of a multiplication result in accordance with present implementations. Fig. 11 illustrates a histogram 1100 of an error of multiplication result in accordance with present implementations.

[0048] Fig. 12 illustrates a result 1200 of time-frequency multiplication. For example, a top plot 1210 can correspond to a ground truth from a simulation, a middle plot 1220 can correspond to an experimental response, a bottom 1230 curve can correspond to a time integration, and circular dots on the bottom curvecan correspond to integrated values, in accordance with present implementations. Fig. 13 illustrates a classification vector in accordance with present implementations.

[0049] Fig. 14 illustrates a time-wavelength multiplexing matrix multiplexer architecture, in accordance with present implementations. The example architectures discussed herein are illustrated by way of example with VCSEL devices, but are not limited thereto. The example architectures discussed herein are illustrated by way of example with TFLN modulator devices, but are not limited thereto. For example, the system can convert transmission from a digital form to an optical form at the data center via one or more devices coupled with or integrated with a CMOS architecture. The system can communicate the optical transmission via fiber or waveguide (WG) to an edge device. The edge device can convert the optical transmission to a digital transmission.

[0050] Fig. 15 illustrates an optical-digital architecture in accordance with present implementations. For example, the optical-digital architecture 1500 can correspond to a modulator to receive an optical transmission having multiple components, a demultiplexer toseparate each optical component, a photodiode (PD) array to transform each optical component into an analog electrical transmission, and an ADC circuit to receive the analog electrical transmission and to generate a digital transmission, and to transmit the digital transmission to one or more client device, edge device, or the like.

[0051] Fig. 16 illustrates a system architecture 1600 including server and edge devices, in accordance with present implementations. This technical solution can achieve various technical improvements. For example, this technical solution can achieve a technical improvement of a high computation capacity from wavelength multiplexing. For example, this technical solution can achieve a technical improvement of low energy consumption from time multiplexing by, for example, an integrator, wavelength multiplexing by, for example, a VCSEL array, and d parallel computing by a TFLN modulator. For example, this technical solution can achieve a technical improvement of reduced system complexity and cost by a single layer architecture.

[0052] Fig. 17 illustrates a graphics processing unit (GPU) 1700 having an optical-digital architecture in accordance with present implementations. For example, Fig. 17 illustrates an on-chip optical GPU architecture applicable in but not limited to a single layer neural network. The GPU can have an electronic component (e.g., CMOS) and an optical component (e.g., a photonic integrated circuit or wafer region). Thus, CMOS-compatible and compact sizes of VCSEL and modulator enable a technical improvement of a large-scale integration in small area. For example, the modulator and VCSEL can achieve a technical improvement of a high-speed and low-energy consumed computing. Line 1702 indicates a line of crosssection corresponding to Fig. 18.

[0053] Fig. 18 illustrates a cross-sectional view of a graphics processing unit (GPU) 1800 having an optical-digital architecture in accordance with present implementations. For example, a photonic chip and a silicon-based CMOS chip can be integrated on a single die. For example, an on-chip CMOS processor can drive architectures in accordance with present implementations, to achieve a technical improvement of execution of a neural network with a chip-size electrical-optical hybrid processor. Technical improvements include CMOS- compatibility of optical and photonic components, and significantly reduced size due to integration into a chip device. Fig. 19 illustrates a cascading optical-digital architecture corresponding to a neural network architecture 1900, in accordance with presentimplementations. For example, the cascading architecture can implement neural network having any connection architecture between layers or neurons.

[0054] FIG. 20 depicts an example method of operating an optical-digital communication architecture according to this disclosure. At least one of the processing system 100, the signal processing architecture 300, the device 400, the optical-digital architecture 1500, the system architecture 1600, the GPU 1700, the GPU 1800, or any combination thereof, can perform method 2000. For example, the one or more of the processors performing the method of FIG. 20 can include a parallel processor. For example, the one or more of the processors performing the method of FIG. 20 can include a transform processor.

[0055] At 2010, the method 2000 can generate a weight matrix. At 2012, the method 2000 can generate the weight matrix by a neural network. For example, the neural network 200 can generate the weight matrix. For example, the method can include performing, by the neural network, matrix-vector multiplication with time-wavelength multiplexing to generate the weight matrix. For example, the system can perform, by the neural network, matrix-vector multiplication with time-wavelength multiplexing to generate the weight matrix. For example, the neural network 200 can perform matrix-vector multiplication with timewavelength multiplexing to generate the weight matrix. For example, the method can use a neural network that can include an optical neural network. For example, the neural network can include an optical neural network.

[0056] At 2020, the method 2000 can map the weight matrix to one or more of a plurality of VCSEL transceivers. For example, a VCSEL weight server can map the weight matrix to one or more of a plurality of VCSEL transceivers. For example, the method can use a plurality of VCSEL transceivers are individually addressable. For example, the method can use a plurality of VCSEL transceivers are of different wavelengths. For example, the system can include a plurality of VCSEL transceivers that are individually addressable. For example, the system can include a plurality of VCSEL transceivers that are of different wavelengths.

[0057] At 2030, the method 2000 can generate one or more beams according to the weight matrix. For example, an optical transceiver can generate one or more beams according to the weight matrix. At 2032, the method 2000 can cause the plurality of VCSEL transceivers to generate the one or more beams. For example, the DAC of the VCSEL weight server can cause the plurality of VCSEL transceivers to generate the one or more beams. For example,the method can include combining, by an optical multiplexer, the one or more beams. For example, the system can combine, by an optical multiplexer, the one or more beams. For example, the multiplexer 320 can combine the one or more beams.

[0058] For example, the method can include inputting the combined beams to the modulator. For example, the system can input the combined beams to the modulator. For example, the multiplexer 320 can input the combined beams to the modulator. For example, the method can include encoding, by a modulator, the one or more beams. For example, the method can include encoding, by the modulator, the combined beams. For example, the system can encode, by a modulator, the one or more beams. For example, the modulator 330 can encode the one or more beams. For example, the system can encode, by the modulator, the combined beams. For example, the modulator 330 can encode the combined beams.

[0059] FIG. 21 depicts an example method of operating an optical-digital communication architecture according to this disclosure. At least one of the processing system 100, the signal processing architecture 300, the device 400, the optical-digital architecture 1500, the system architecture 1600, the GPU 1700, the GPU 1800, or any combination thereof, can perform method 2100. For example, the one or more of the processors performing the method of FIG. 21 can include a parallel processor. For example, the one or more of the processors performing the method of FIG. 21 can include a transform processor.

[0060] At 2110, the method 2100 can separate an optical transmission into a plurality of components. For example, an edge device can separate an optical transmission into a plurality of components. At 2112, the method 2100 can separate the optical transmission by an optical demultiplexer. For example, the demultiplexer 340 can separate the optical transmission into a plurality of components. At 2120, the method 2100 can transform each of the components into corresponding analog electrical transmissions. For example, each of the photodiodes 350 can transform each of the components into corresponding analog electrical transmissions. At 2122, the method 2100 can transform each of the components by a photodiode array structured to receive output of the optical demultiplexer. For example, the photodiode array can include one or more of the photodiodes 350. At 2130, the method 2100 can transmit one or more digital transmissions for one or more of the analog electrical transmissions. At 2132, the method 2100 can transmit the digital transmissions by ADC circuit structured to receive output of the photodiode array.

[0061] For example, the system can include a modulator to receive the optical transmission can include the plurality of components. For example, the method can include receiving, by a modulator structured to provide output to the optical demultiplexer, the optical transmission can include the plurality of components. For example, the method can include generating, by the ADC circuit, the digital transmissions based on the one or more of the analog electrical transmissions. For example, the system can include a ADC circuit. The system can generate the digital transmissions based on the one or more of the analog electrical transmissions. For example, the system can include receiving, by the ADC circuit from the photodiode array, one or more of the analog electrical transmissions. For example, the system can include a ADC circuit. The system can receive, from the photodiode array, one or more of the analog electrical transmissions.

[0062] The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are illustrative, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "operably couplable," to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and / or physically interacting components and / or wirelessly interactable and / or wirelessly interacting components and / or logically interacting and / or logically interactable components.

[0063] With respect to the use of plural and / or singular terms herein, those having skill in the art can translate from the plural to the singular and / or from the singular to the plural as is appropriate to the context and / or application. The various singular / plural permutations may be expressly set forth herein for sake of clarity.

[0064] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intendedas "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but is not limited to," etc.).

[0065] Although the figures and description may illustrate a specific order of method steps, the order of such steps may differ from what is depicted and described, unless specified differently above. Also, two or more steps may be performed concurrently or with partial concurrence, unless specified differently above. Such variation may depend, for example, on the software and hardware systems chosen and on designer choice. All such variations are within the scope of the disclosure. Likewise, software implementations of the described methods could be accomplished with standard programming techniques with rule-based logic and other logic to accomplish the various connection steps, processing steps, comparison steps, and decision steps.

[0066] It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and / or "an" should typically be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, typically means at least two recitations, or two or more recitations).

[0067] Furthermore, in those instances where a convention analogous to "at least one of A, B, and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, and C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In thoseinstances where a convention analogous to "at least one of A, B, or C, etc." is used, in general, such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, or C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and / or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0068] Further, unless otherwise noted, the use of the words “approximate,” “about,” “around,” “substantially,” etc., mean plus or minus ten percent.

[0069] Directional indicators depicted herein are example directions to facilitate understanding of the examples discussed herein, and are not limited to the directional indicators depicted herein. Any directional indicator depicted herein can be modified to the reverse direction, or can be modified to include both the depicted direction and a direction reverse to the depicted direction, unless stated otherwise herein. While operations are depicted in the drawings in a particular order, such operations are not required to be performed in the particular order shown or in sequential order, and all illustrated operations are not required to be performed. Actions described herein can be performed in a different order. Where technical features in the drawings, detailed description or any claim are followed by reference signs, the reference signs have been included to increase the intelligibility of the drawings, detailed description, and claims. Accordingly, neither the reference signs nor their absence have any limiting effect on the scope of any clam elements.

[0070] Scope of the systems and methods described herein is thus indicated by the appended claims, rather than the foregoing description. The scope of the claims includes equivalents to the meaning and scope of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A system, comprising: a memory and one or more processors to: generate, by a neural network, a weight matrix; map the weight matrix to one or more of a plurality of VCSEL transceivers; and cause the one or more of the plurality of VCSEL transceivers to generate one or more beams according to the weight matrix.

2. The system of claim 1, the processors to: encode, by a modulator, the one or more beams.

3. The system of any of claims 1 and 2, the processors to: combine, by an optical multiplexer, the one or more beams.

4. The system of claim 3, the processors to: encode, by the modulator, the combined beams.

5. The system of claim 3, the processors to: input the combined beams to the modulator.

6. The system of any of claims 1-5, the processors to: perform, by the neural network, matrix-vector multiplication with time-wavelength multiplexing to generate the weight matrix.

7. The system of any of claims 1-6, the plurality of VCSEL transceivers are individually addressable.

8. The system of any of claims 1-7, the plurality of VCSEL transceivers are of different wavelengths.

9. The system of any of claims 1-8, one or more of the processors each comprising a parallel processor.

10. The system of any of claims 1-9, one or more of the processors each comprising a transform processor.

11. The system of any of claims 1-10, the neural network each comprising an optical neural network.

12. A method, comprising: generating, by a neural network, a weight matrix; mapping the weight matrix to one or more of a plurality of VCSEL transceivers; and causing the one or more of the plurality of VCSEL transceivers to generate one or more beams according to the weight matrix.

13. The method of claim 12, further comprising: encoding, by a modulator, the one or more beams.

14. The method of any of claims 12 and 13, further comprising: combining, by an optical multiplexer, the one or more beams.

15. The method of claim 14, further comprising: encoding, by the modulator, the combined beams.

16. The method of claim 14, further comprising: inputting the combined beams to the modulator.

17. The method of any of claims 12-16, further comprising: performing, by the neural network, matrix-vector multiplication with timewavelength multiplexing to generate the weight matrix.

18. The method of any of claims 12-17, the plurality of VCSEL transceivers are individually addressable.

19. The method of any of claims 12-18, the plurality of VCSEL transceivers are of different wavelengths.

20. The method of any of claims 12-19, one or more of the processors each comprising a parallel processor.

21. The method of any of claims 12-20, one or more of the processors each comprising a transform processor.

22. The method of any of claims 12-21, the neural network each comprising an optical neural network.

23. A system, comprising: an optical demultiplexer to separate an optical transmission into a plurality of components; a photodiode array to transform each of the components into corresponding analog electrical transmissions; and an analog-to-digital (ADC) circuit to transmit one or more digital transmissions corresponding to one or more of the analog electrical transmissions.

24. The system of claim 23, further comprising: a modulator to receive the optical transmission including the plurality of components.

25. The system of any of claims 23 and 24, the ADC circuit to: generate the digital transmissions based on the one or more of the analog electrical transmissions.

26. The system of any of claims 23-25, the ADC circuit to: receive, from the photodiode array, one or more of the analog electrical transmissions.

27. A method, comprising: separating, by an optical demultiplexer, an optical transmission into a plurality of components;transforming, by a photodiode array structured to receive output of the optical demultiplexer, each of the components into corresponding analog electrical transmissions; and transmitting, by an analog-to-digital (ADC) circuit structured to receive output of the photodiode array, one or more digital transmissions corresponding to one or more of the analog electrical transmissions.

28. The method of claim 23, further comprising: receiving, by a modulator structured to provide output to the optical demultiplexer, the optical transmission including the plurality of components.

29. The method of any of claims 27 and 28, further comprising: generating, by the ADC circuit, the digital transmissions based on the one or more of the analog electrical transmissions.

30. The system of any of claims 27-29, further comprising: receiving, by the ADC circuit from the photodiode array, one or more of the analog electrical transmissions.

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