Display panel and manufacturing method therefor, and display device

Abstract

Provided is a display panel, comprising: a base substrate, wherein the base substrate comprises at least one side area and a display area; a plurality of pixel units provided in the display area; a terminal provided on the base substrate and located in the side area; a first wiring provided on the base substrate, wherein one end of the first wiring is electrically connected to the terminal, and the other end is electrically connected to a pixel driving circuit; and a second wiring provided on the base substrate, wherein one end of the second wiring is electrically connected to the terminal, and the second wiring extends in a direction from the terminal to the side edge of the base substrate. The display panel comprises: a first conductive layer, a first planarization layer, a second conductive layer, and a second planarization layer which are successively provided on the base substrate. An orthographic projection of the terminal on the base substrate is spaced apart from an orthographic projection of the first planarization layer on the base substrate, and the orthographic projection of the terminal on the base substrate is spaced apart from an orthographic projection of the second planarization layer on the base substrate.

Description

Display panel, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] Light Emitting Diode (LED) technology has been developed for nearly three decades, and its application scope has been continuously expanding. For example, it can be applied to the display field and used as a backlight source for display devices or as an LED display screen. Currently, LED displays have emerged as a hot display carrier in outdoor displays and central control screen displays. With the development of technology and in order to meet the needs of users, the use of small screens to splice together to achieve large-screen display is one of the current development directions of LED displays. In spliced ​​display products, how to design the structure of the display panel so that the display panel can meet the requirements of the spliced ​​display product while also having the required reliability is one of the topics that display product researchers and developers are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising: a base substrate, the base substrate comprising at least one side region and a display region, the at least one side region being closer to a side edge of the base substrate than the display region; a plurality of pixel units arranged in the display region, the plurality of pixel units being distributed in an array on the base substrate, at least one of the pixel units comprising a light-emitting diode and a pixel driving circuit for driving the light-emitting diode; a terminal arranged on the base substrate and located in the side region; a first trace arranged on the base substrate, one end of the first trace being electrically connected to the terminal and the other end being electrically connected to the pixel driving circuit; and a second trace arranged on the base substrate, the first trace being electrically connected to the terminal and the other end being electrically connected to the pixel driving circuit. One end of the second trace is electrically connected to the terminal, and the second trace extends from the terminal toward the side edge of the base substrate, wherein the display panel includes: a first conductive layer arranged on the base substrate; a first planarization layer arranged on a side of the first conductive layer away from the base substrate; a second conductive layer arranged on a side of the first planarization layer away from the base substrate; and a second planarization layer arranged on a side of the second conductive layer away from the base substrate, wherein the orthographic projection of the terminal on the base substrate is spaced apart from the orthographic projection of the first planarization layer on the base substrate, and the orthographic projection of the terminal on the base substrate is spaced apart from the orthographic projection of the second planarization layer on the base substrate.

[0006] According to some exemplary embodiments, in a region between the terminal and a light emitting diode closest to the terminal, an orthographic projection of the second planarization layer on the base substrate falls within an orthographic projection of the first planarization layer on the base substrate.

[0007] According to some exemplary embodiments, the display panel also includes a first passivation layer arranged between the first planarization layer and the second conductive layer; and in the area between the terminal and the light-emitting diode closest to the terminal, the orthographic projection of the first planarization layer on the base substrate falls within the orthographic projection of the first passivation layer on the base substrate.

[0008] According to some exemplary embodiments, the display panel further includes a second passivation layer disposed on a side of the second planarization layer away from the base substrate; and in a region between the terminal and the light-emitting diode closest to the terminal, an orthographic projection of the second planarization layer on the base substrate falls within an orthographic projection of the second passivation layer on the base substrate.

[0009] According to some exemplary embodiments, the display panel includes a first via located in the first passivation layer and a second via located in the second passivation layer; the orthographic projection of the second via on the base substrate falls within the orthographic projection of the first via on the base substrate, and the orthographic projection of at least one of the first via and the second via on the base substrate falls within the orthographic projection of the terminal on the base substrate.

[0010] According to some exemplary embodiments, the terminal includes a first terminal portion located in the first conductive layer and a second terminal portion located in the second conductive layer.

[0011] According to some exemplary embodiments, the display panel includes a plurality of conductive pads located in the second conductive layer, the light-emitting diode includes a first electrode and a second electrode, the first electrode of the light-emitting diode contacts one of the conductive pads, and the second electrode of the light-emitting diode contacts another of the conductive pads; and the plurality of conductive pads include a first conductive pad closest to the side edge of the base substrate, and the first side of the orthographic projection of the second planarization layer on the base substrate is closer to the terminal than the first side of the orthographic projection of the first conductive pad on the base substrate, wherein the first side of the orthographic projection of the first conductive pad on the base substrate is a side facing the terminal among the respective side edges of the orthographic projection of the first conductive pad on the base substrate, and the first side of the orthographic projection of the second planarization layer on the base substrate is a side facing the terminal among the respective side edges of the orthographic projection of the second planarization layer on the base substrate.

[0012] According to some exemplary embodiments, the first side of the orthographic projection of the second planarization layer on the base substrate includes a first side portion, and the first side portion of the second planarization layer is a portion of the first side of the second planarization layer facing the terminal; and the first side of the orthographic projection of the first conductive pad on the base substrate and the first side portion of the first side of the orthographic projection of the second planarization layer on the base substrate are spaced a first prescribed distance in a first direction, wherein the first direction is perpendicular to the side edge of the base substrate.

[0013] According to some exemplary embodiments, the first side of the orthographic projection of the first planarization layer on the base substrate includes a first side portion, wherein the first side of the orthographic projection of the first planarization layer on the base substrate is a side facing the terminal among the sides of the orthographic projection of the first planarization layer on the base substrate, and the first side portion of the first planarization layer is a portion of the first side of the first planarization layer facing the terminal; and the first side portion of the first side of the orthographic projection of the first planarization layer on the base substrate is closer to the terminal than the first side portion of the first side of the orthographic projection of the second planarization layer on the base substrate.

[0014] According to some exemplary embodiments, a first side portion of a first side of an orthographic projection of the first planarization layer on the base substrate is spaced a second prescribed distance apart from a first side portion of a first side of an orthographic projection of the second planarization layer on the base substrate in the first direction.

[0015] According to some exemplary embodiments, the first side portion of the first side of the orthographic projection of the first planarization layer on the base substrate is spaced apart from the first side of the orthographic projection of the terminal on the base substrate by a third specified distance in the first direction, wherein the first side of the orthographic projection of the terminal on the base substrate is a side that is farthest from the side edge of the base substrate in the first direction among the sides of the orthographic projection of the terminal on the base substrate.

[0016] According to some exemplary embodiments, the third prescribed distance is greater than the first prescribed distance; and / or the first prescribed distance is greater than the second prescribed distance.

[0017] According to some exemplary embodiments, the display panel includes a plurality of the terminals, and there are gaps between the plurality of the terminals; the display panel includes a first retaining wall, the first retaining wall facing the gap in a first direction, wherein the first direction is perpendicular to the side edge of the base substrate; and a first side edge portion of a first side edge of a positive projection of at least a portion of the first retaining wall on the base substrate protrudes toward the gap in the first direction relative to the positive projection of the first planarization layer on the base substrate.

[0018] According to some exemplary embodiments, the first retaining wall includes a first retaining wall portion located in the first planarization layer and a second retaining wall portion located in the second planarization layer; and the first retaining wall portion is a portion that extends continuously with a portion of the first planarization layer located in the display area, and the second retaining wall portion is a portion that extends continuously with a portion of the second planarization layer located in the display area.

[0019] According to some exemplary embodiments, an orthographic projection of the second retaining wall portion on the base substrate falls within an orthographic projection of the first retaining wall portion on the base substrate.

[0020] According to some exemplary embodiments, the display panel includes a plurality of the terminals, and there are gaps between the plurality of the terminals; the display panel includes a second retaining wall, and the second retaining wall is opposite to the gap in a first direction, wherein the first direction is perpendicular to the side edge of the base substrate; the second retaining wall is spaced apart from the portion of the first planarization layer located in the display area, and the second retaining wall is closer to the gap than the portion of the first planarization layer located in the display area; and the second retaining wall is spaced apart from the portion of the second planarization layer located in the display area, and the second retaining wall is closer to the gap than the portion of the second planarization layer located in the display area.

[0021] According to some exemplary embodiments, the second retaining wall includes a first sub-retaining wall located in the first planarization layer and a second sub-retaining wall located in the second planarization layer; and an orthographic projection of the second sub-retaining wall on the base substrate falls within an orthographic projection of the first sub-retaining wall on the base substrate.

[0022] According to some exemplary embodiments, the second retaining wall further includes a third sub-retaining wall located in the first passivation layer and a fourth sub-retaining wall located in the second passivation layer; the first sub-retaining wall is spaced apart from a portion of the first planarization layer located in the display area; the second sub-retaining wall is spaced apart from a portion of the second planarization layer located in the display area; the third sub-retaining wall is a portion continuously extending with a portion of the first passivation layer located in the display area; and the fourth sub-retaining wall is a portion continuously extending with a portion of the second passivation layer located in the display area.

[0023] According to some exemplary embodiments, an orthographic projection of the second terminal portion on the base substrate falls within an orthographic projection of the first terminal portion on the base substrate.

[0024] According to some exemplary embodiments, the orthographic projection of the second via on the base substrate falls within the orthographic projection of the second terminal portion on the base substrate, and a portion of the second passivation layer covers the side edge of the second terminal portion; and / or, the orthographic projection of the first via on the base substrate falls within the orthographic projection of the first terminal portion on the base substrate, and a portion of the first passivation layer covers the side edge of the first terminal portion.

[0025] According to some exemplary embodiments, a vertical distance between a first side edge of an orthographic projection of the second terminal portion on the base substrate and a first side edge of an orthographic projection of the first terminal portion on the base substrate is greater than 2 micrometers, wherein the first side edge of an orthographic projection of the second terminal portion on the base substrate and the first side edge of an orthographic projection of the first terminal portion on the base substrate are sides on the same side of the orthographic projections of the two terminal portions on the base substrate.

[0026] According to some exemplary embodiments, a ratio of a size of the first retaining wall in the second direction to a size of a gap facing the first retaining wall in the second direction is between 0.6 and 1.5, wherein the second direction is perpendicular to the first direction.

[0027] According to some exemplary embodiments, an orthographic projection of the first retaining wall in the first direction does not overlap with an orthographic projection of the terminal in the first direction.

[0028] According to some exemplary embodiments, a ratio of a size of the second retaining wall in the second direction to a size of a gap facing the second retaining wall in the second direction is between 0.6 and 1, wherein the second direction is perpendicular to the first direction.

[0029] According to some exemplary embodiments, an orthographic projection of the second retaining wall in the first direction partially overlaps with an orthographic projection of the terminal in the first direction.

[0030] In another aspect, a display device is provided, wherein the display device includes the display panel as described above.

[0031] According to some exemplary embodiments, the display device includes a plurality of spliced ​​display panels.

[0032] In another aspect, a method for manufacturing a display panel is provided, wherein the method includes:

[0033] Providing a base substrate, the base substrate comprising a display area, a side area, and a to-be-cut area, wherein the side area is closer to a side edge of the base substrate than the display area, and the to-be-cut area is closer to a side edge of the base substrate than the side area;

[0034] forming a first conductive material layer on the base substrate;

[0035] Performing a patterning process on the first conductive material layer to form a first terminal portion located in the side region and a first trace extending from the at least one side region to the display region;

[0036] forming a first planarization layer on a side of the first terminal portion and the first trace away from the base substrate;

[0037] forming a second conductive material layer on a side of the first planarization layer away from the base substrate;

[0038] performing a patterning process on the second conductive material layer to form a second terminal portion located in the side region; and

[0039] forming a second planarization layer on a side of the second terminal portion away from the base substrate;

[0040] In which, the orthographic projection of each of the first terminal portion and the second terminal portion on the base substrate is spaced apart from the orthographic projection of the first planarization layer on the base substrate, and the orthographic projection of each of the first terminal portion and the second terminal portion on the base substrate is spaced apart from the orthographic projection of the second planarization layer on the base substrate.

[0041] According to some exemplary embodiments, in the step of performing a composition process on the first conductive material layer, a first test terminal portion located in the area to be cut is also formed; in the step of performing a composition process on the second conductive material layer, a second test terminal portion located in the area to be cut is also formed, wherein the orthographic projection of the second test terminal portion on the base substrate covers the orthographic projection of the first test terminal portion on the base substrate.

[0042] According to some exemplary embodiments, the method further includes: when the first test terminal portion and the second test terminal portion are located on the base substrate, performing a gold deposition process on the second terminal portion to form a protective layer on a surface of the second terminal portion away from the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0044] 1A to 1K schematically illustrate a flow chart of a method for processing a display panel to achieve narrow seam or seamless splicing, wherein FIG1A and FIG1J are top views of the display panel, schematically illustrating the front side of the display panel; FIG1K is a bottom view of the display panel, schematically illustrating the back side of the display panel; FIG1B, FIG1D, FIG1F, and FIG1H are side views of the display panel observed along the second direction in FIG1A; and FIG1C, FIG1E, FIG1G, and FIG1I are side views of the display panel observed along the first direction in FIG1A;

[0045] Figure 2 schematically shows the design distance requirements for terminals in the splicing edge space;

[0046] FIG3 is a schematic plan view of a display panel according to an embodiment of the present disclosure;

[0047] FIG4 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure;

[0048] FIG5 is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure, taken along line AA′ in FIG4 ;

[0049] 6 and 7 are respectively schematic plan views of display panels during processing according to some exemplary embodiments of the present disclosure, wherein FIG6 schematically shows a partial plan view of the display panel before the laser etching process after the sputtering process, and FIG7 schematically shows a partial plan view of the display panel after the laser etching process;

[0050] FIG8 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, schematically illustrating a retaining wall design;

[0051] FIG9 is a partial plan view of a display panel after a laser etching process according to some exemplary embodiments of the present disclosure;

[0052] 10A to 10F are schematic diagrams of intermediate structures of the display panel with the retaining wall design shown in FIG. 8 , wherein FIG. 10A to FIG. 10F schematically illustrate the structure of the display panel located in the terminal area and the display area adjacent to the terminal area;

[0053] FIG11 is a SEM image of a display panel with a retaining wall design after laser etching;

[0054] FIG12 is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure, and FIG13 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, wherein FIG12 and FIG13 schematically illustrate another retaining wall design;

[0055] FIG14 is a cross-sectional view of a display panel at a terminal according to some exemplary embodiments of the present disclosure;

[0056] FIG15 is a plan view of a display panel at a terminal according to some exemplary embodiments of the present disclosure;

[0057] FIG16 is a photograph of a structure at a terminal of a display panel after a gold deposition process according to some exemplary embodiments of the present disclosure;

[0058] FIG17 is a SEM image of a terminal of a display panel according to some exemplary embodiments of the present disclosure;

[0059] FIG18 is a cross-sectional view of a display panel at a terminal according to other exemplary embodiments of the present disclosure;

[0060] FIG19 is a plan view of a display panel at a terminal according to other exemplary embodiments of the present disclosure;

[0061] FIG20 is a SEM image of a terminal of a display panel according to some other exemplary embodiments of the present disclosure;

[0062] FIG21 schematically shows a process of testing terminals and terminals reacting during a gold deposition process on a display panel;

[0063] FIG22 is a SEM image of a terminal formed after the process shown in FIG21 is executed;

[0064] FIG23 is a cross-sectional view of the display panel at the test terminal before the gold deposition process is performed on the display panel;

[0065] FIG24 is a cross-sectional view of the display panel at the test terminal before the gold deposition process is performed on the display panel;

[0066] FIG25 is a plan view of the display panel shown in FIG24;

[0067] FIG26 is a SEM image of a terminal of the display panel having the structure shown in FIG24;

[0068] FIG. 27 is a flowchart of a method of manufacturing a display panel according to an exemplary embodiment of the present disclosure; and

[0069] FIG. 28 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure.

[0070] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0071] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0072] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0073] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0074] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0075] In this article, inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED represents an inorganic light-emitting element that is different from OLED. Specifically, inorganic light-emitting elements can include sub-millimeter light-emitting diodes (Mini Light Emitting Diode, abbreviated as Mini LED in English) and micro light-emitting diodes (Micro LED in English). Among them, micro light-emitting diodes (i.e. Micro LEDs) refer to ultra-small light-emitting diodes with a grain size of less than 100 microns, and sub-millimeter light-emitting diodes (i.e. Mini LEDs) refer to small light-emitting diodes with a grain size between Micro LEDs and traditional LEDs. For example, the grain size of Mini LEDs can be between 50 and 400 microns.

[0076] With the development of technology, LED display devices have been developing rapidly. For example, they are gradually being used in outdoor displays and large-screen displays for central control systems. The inventors have found that, on the one hand, in application scenarios such as outdoor displays and large-screen displays for central control systems, the display screen size needs to be larger. On the other hand, LED display devices used for outdoor displays and large-screen displays for central control systems are mainly used for users to watch from a distance. Based on this, multiple small screens can be spliced ​​together to achieve large-screen display. In the process of splicing multiple small screens into a large screen, the display panel needs to be processed to achieve narrow gaps or seamless splicing.

[0077] Figures 1A to 1K schematically show a flow chart of a method for processing a display panel to achieve narrow gaps or seamless splicing, wherein Figures 1A and 1J are top views of the display panel, which schematically show the front of the display panel, Figure 1K is a bottom view of the display panel, which schematically shows the back of the display panel, Figures 1B, 1D, 1F and 1H are side views of the display panel observed along the second direction in Figure 1A, and Figures 1C, 1E, 1G and 1I are side views of the display panel observed along the first direction in Figure 1A.

[0078] Referring to Figures 1A to 1K , terminals 2 are formed on the base substrate 1 of the display panel. Terminals 2 are electrically connected to the chip or circuit board via signal traces 3. In a narrow-slit or seamless splicing scheme, the chip or circuit board is placed on the back of the base substrate 1. Terminals 2 on the front of the base substrate 1 are electrically connected to the chip or circuit board on the back of the base substrate 1 via signal traces 3. To achieve this connection method, both side and back processes are required. Figure 1A schematically illustrates the splicing edge of a motherboard. In this embodiment, terminals 2 for connecting signal traces are located on the signal input side of the motherboard. As shown in Figures 1B and 1C , the motherboard needs to be edge-cut to reduce the size of the splicing edge. For example, laser cutting can be used for this cutting process. As shown in Figures 1D and 1E , the cut motherboard needs to be further edge-milled to further reduce the size of the splicing edge. After cutting and edge-milling, the display panel is formed. A protective film is then applied to the display area of ​​the display panel to prevent damage to the structures in the display area during subsequent processing. As shown in Figures 1F and 1G, a metal layer ML can be formed using a sputtering process. A portion of the metal layer ML is connected to the terminal 2, a portion is formed on the side of the display panel, and another portion is formed on the back of the display panel, for example, in the fan-out area on the back. For example, the metal layer ML may include Ti / Cu / Ti metal. As shown in Figures 1H and 1I, the metal layer ML is etched using an etching process to form a plurality of signal traces 3. For example, the etching process can be a laser etching process. In this way, the terminal 2 on the front is connected to the fan-out area on the back through the signal trace 3, and is then connected to the chip or circuit board.

[0079] In the narrow slit or seamless splicing solution, the signal traces 3 formed on the side of the display panel are used to introduce the data signals, power signals, scan signals and other signals on the display panel to the back of the display panel, and are bound to the chip or circuit board on the back. In the narrow slit or seamless splicing solution, the position design of the terminal 2 located on the front of the display panel is more important. On the one hand, the terminal 2 should not be too close to the edge of the display panel. The terminal 2 that is too close to the edge of the display panel has a higher risk of being damaged during the cutting and edging process; on the other hand, the terminal 2 should not be too far from the edge of the display panel. The terminal 2 that is too far from the edge of the display panel will cause the subsequent splicing seam to be wider, which is not conducive to the realization of narrow slit or seamless splicing. Figure 2 schematically shows the design distance requirements of the terminal in the splicing edge space. As shown in Figure 2, the splicing edge space design is divided into four parts along the first direction D1: the size of the part ground off from the cutting edge along the first direction D1 is Y1, which is used to protect the side wiring and the splicing seam margin (i.e., margin); the size of the edge after grinding away from the terminal 2 along the first direction D1 is Y2, and the size Y2 is designed to ensure that grinding does not damage the terminal 2; the size of the terminal 2 along the first direction D1 is Y3, which is used to ensure the contact area between the terminal 2 and the signal wiring 3; the size of the terminal 2 from the light-emitting device 5 (such as LED) along the first direction D1 is Y4, which is used to ensure that the above-mentioned sputtering process and etching process do not damage the light-emitting device 5.

[0080] In the exemplary embodiments of Figures 1A and 2 , a first direction D1 and a second direction D2 are schematically shown. For example, a plurality of pixel units may be arranged in an array along the first direction D1 and the second direction D2. It should be noted that the embodiments of the present disclosure are not limited thereto.

[0081] The inventors have discovered that in narrow-slit or seamless splicing solutions, the laser cutting and sputtering processes in the side edge processing can damage the planarization layer (e.g., including resin material) in the side edge region, and this can also have a cascading effect, damaging the planarization layer in the display area. Therefore, in the embodiments of the present disclosure, the planarization layer is removed at the terminals in the side edge region of the display panel.

[0082] Figure 3 is a schematic plan view of a display panel according to an embodiment of the present disclosure. Figure 4 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure. Figure 5 is a cross-sectional view of the display panel according to some exemplary embodiments of the present disclosure taken along line AA' in Figure 4. For example, Figures 4 and 5 schematically illustrate portions of the display panel located in the side regions where the terminals are located.

[0083] 3, 4, and 5, the display panel 100 may include a base substrate 1, the base substrate 1 including at least one side region NA and a display region AA, wherein the at least one side region NA is closer to a side edge 1S of the base substrate 1 than the display region AA. For example, the at least one side region NA may include an area where the terminal 2 is located, or an area where a splicing edge is located.

[0084] It should be noted that, in this document, unless otherwise specified, the term "side edge" refers to the side surface of a substrate, component or element, and in a plan view such as Figure 3 or Figure 4, the "side edge" is shown as a line, for example, the first side edge 1S is the lowermost line.

[0085] The display panel 100 may also include a plurality of pixel units P disposed in the display area AA. The plurality of pixel units P are distributed in an array on the base substrate 1, and at least one pixel unit P includes a light-emitting diode 5 and a pixel driving circuit 6 for driving the light-emitting diode 5. For example, the light-emitting diode 5 may include a sub-millimeter light-emitting diode or a micro light-emitting diode, which may adopt the structure of a light-emitting diode chip. The pixel driving circuit 6 may include at least one transistor T, which may include a source, a gate, a drain, and an active layer TACT. For example, the transistor T may have a dual-gate structure, which may include a first gate TG1 located below the active layer TACT and a second gate TG2 located above the active layer TACT.

[0086] Exemplarily, referring to Figure 5, the display panel 100 may include a plurality of film layers arranged on the base substrate 1, for example, the plurality of film layers include: a third conductive layer 13 arranged on the base substrate 1, a buffer layer BL arranged on the side of the third conductive layer 13 away from the base substrate, a semiconductor layer ACT arranged on the side of the buffer layer BL away from the base substrate, a first insulating layer IL1 arranged on the side of the semiconductor layer ACT away from the base substrate, a fourth conductive layer 14 arranged on the side of the first insulating layer IL1 away from the base substrate, a second insulating layer IL2 arranged on the side of the fourth conductive layer 14 away from the base substrate, a first conductive layer 11 arranged on the side of the second insulating layer IL2 away from the base substrate, a first planarization layer PLN1 arranged on the side of the first conductive layer 11 away from the base substrate, a first passivation layer PVX1 arranged on the side of the first planarization layer PLN1 away from the base substrate, a second conductive layer 12 arranged on the side of the first passivation layer PVX1 away from the base substrate, a second planarization layer PLN2 arranged on the side of the second conductive layer 12 away from the base substrate, and a second passivation layer PVX2 arranged on the side of the second planarization layer PLN2 away from the base substrate.

[0087] For example, the material of the base substrate 1 may include but is not limited to glass, quartz, plastic, silicon, polyimide, etc.

[0088] Continuing with FIG. 5 , the first gate electrode TG1 may be located in the third conductive layer 13, and the second gate electrode TG2 may be located in the fourth conductive layer 14. That is, the third conductive layer 13 and the fourth conductive layer 14 may be conductive layers containing gate materials. The active layer TACT may be located in the semiconductor layer ACT. The display panel 100 may include a conductive connection portion 111, for example, located in the first conductive layer 11, for electrically connecting the first gate electrode TG1 to the second gate electrode TG2.

[0089] The display panel 100 may include a plurality of conductive pads 121 in the second conductive layer 12. The light-emitting diode 5 includes a first electrode 51 and a second electrode 52. The first electrode 51 of the light-emitting diode contacts one conductive pad 121, and the second electrode 52 of the light-emitting diode contacts another conductive pad 121. One conductive pad 121 that contacts the first electrode 51 also contacts the conductive connection portion 111.

[0090] In the embodiments of the present disclosure, components such as the source and drain of the transistor T and the conductive connection portion 111 may be located in the first conductive layer 11. That is, the first conductive layer 11 may be a conductive layer containing source or drain material. Conductive pads for electrically connecting to electrodes of the light-emitting diode may be located in the second conductive layer 12. For example, the second conductive layer 12 may contain a material with high conductivity, such as Cu.

[0091] 4 and 5 , the display panel 100 may further include a terminal 2 provided on the base substrate 1 and located in the side area NA. As described above, the terminal 2 located on the front of the display panel 100 is connected to the fan-out area on the back through the signal trace 3, and is connected to the chip or circuit board. Specifically, the display panel 100 may include: a first trace SL1 provided on the base substrate 1, one end of the first trace SL1 being electrically connected to the terminal 2, and the other end being electrically connected to the pixel driving circuit 6; and a second trace SL2 provided on the base substrate 1, one end of the second trace SL2 being electrically connected to the terminal 2, and the second trace SL2 extending from the terminal 2 toward the side edge 1S of the base substrate 1. In this way, the data signal, power signal, scan signal and other signals generated by the chip or circuit board are input to the pixel driving circuit 6, and the pixel driving circuit 6 controls the light-emitting diode to emit light under the control of various signals.

[0092] 4 and 5 , the orthographic projection of the terminal 2 on the base substrate 1 is spaced apart from the orthographic projection of the first planarizing layer PLN1 on the base substrate 1, and the orthographic projection of the terminal 2 on the base substrate 1 is spaced apart from the orthographic projection of the second planarizing layer PLN2 on the base substrate 1. Exemplarily, in an embodiment of the present disclosure, a plurality of terminals 2 may be provided, and the orthographic projection of each terminal 2 on the base substrate 1 is spaced apart from the orthographic projection of the first planarizing layer PLN1 on the base substrate 1, and the orthographic projection of each terminal 2 on the base substrate 1 is spaced apart from the orthographic projection of the second planarizing layer PLN2 on the base substrate 1.

[0093] In this document, unless otherwise specified, the phrase "spaced apart" means that the two do not overlap. That is, in this embodiment, the orthographic projection of the terminal 2 on the base substrate 1 does not overlap with the orthographic projection of the first planarization layer PLN1 on the base substrate 1, and the orthographic projection of the terminal 2 on the base substrate 1 does not overlap with the orthographic projection of the second planarization layer PLN2 on the base substrate 1.

[0094] In the embodiment of the present disclosure, a planarization layer is not provided in the area where Terminal 2 is located. In other words, the planarization layer is removed from the terminals located in the side areas of the display panel. This prevents the planarization layer in the display area AA from being damaged during the laser cutting and sputtering processes in the side processing, which helps improve the reliability of the display panel.

[0095] Continuing with reference to Figures 4 and 5, in the area between the terminal 2 and the light-emitting diode 5 closest to the terminal 2, the orthographic projection of the second planarization layer PLN2 on the base substrate 1 falls within the orthographic projection of the first planarization layer PLN1 on the base substrate 1. That is, in the area between the plurality of terminals 2 and the row of light-emitting diodes 5 closest to the terminal 2, the orthographic projection of the second planarization layer PLN2 on the base substrate 1 falls within the orthographic projection of the first planarization layer PLN1 on the base substrate 1. That is, the edge of the second planarization layer PLN2 is closer to the inside than the edge of the first planarization layer PLN1, so that the second planarization layer PLN2 is completely located above the first planarization layer PLN1. When forming the first planarization layer PLN1, since the design of excavating the first planarization layer PLN1 needs to be carried out in the area where the terminal 2 is located, a step difference will be formed at the edge of the first planarization layer PLN1. In this embodiment, the second planarization layer PLN2 is completely located above the first planarization layer PLN1, which avoids the second planarization layer PLN2 from being formed at the step difference of the edge of the first planarization layer PLN1, and is beneficial to improving the reliability of the second planarization layer PLN2.

[0096] In an embodiment of the present disclosure, both the first passivation layer PVX1 and the second passivation layer PVX2 extend from the display area AA to the side area NA, that is, the first passivation layer PVX1 and the second passivation layer PVX2 are still provided in the side area NA. Referring to Figures 4 and 5, in the area between the terminal 2 and the light-emitting diode 5 closest to the terminal 2, that is, in the area between the plurality of terminals 2 and the row of light-emitting diodes 5 closest to the terminal 2, the orthographic projection of the first planarization layer PLN1 on the base substrate 1 falls within the orthographic projection of the first passivation layer PVX1 on the base substrate 1; the orthographic projection of the first planarization layer PLN1 on the base substrate 1 falls within the orthographic projection of the second passivation layer PVX2 on the base substrate 1; the orthographic projection of the second planarization layer PLN2 on the base substrate 1 falls within the orthographic projection of the first passivation layer PVX1 on the base substrate 1; the orthographic projection of the second planarization layer PLN2 on the base substrate 1 falls within the orthographic projection of the second passivation layer PVX2 on the base substrate 1. With this design, the first passivation layer PVX1 and the second passivation layer PVX2 are used to protect the first planarization layer PLN1 and the second planarization layer PLN2. Specifically, the edge of the first planarization layer PLN1 is wrapped by the first passivation layer PVX1, and the edge of the first planarization layer PLN1 is wrapped by the second passivation layer PVX2. Due to the protection of the two passivation layers, the sputtered Ti / Cu / Ti metal will not penetrate into the planarization layer during the sputtering process, which is beneficial to protecting the reliability of the pixel drive circuit and light-emitting diode in the display area of ​​the display panel.

[0097] The display panel 100 may include a first via hole VH1 located in the first passivation layer PVX1 and a second via hole VH2 located in the second passivation layer PVX2. The terminal 2 is formed in the first via hole VH1 and the second via hole VH2. Referring to Figures 4 and 5, the orthographic projection of the second via hole VH2 on the base substrate 1 falls within the orthographic projection of the first via hole VH1 on the base substrate 1. The orthographic projection of at least one of the first via hole VH1 and the second via hole VH2 on the base substrate 1 falls within the orthographic projection of the terminal 2 on the base substrate. For example, the orthographic projection of each of the first via hole VH1 and the second via hole VH2 on the base substrate 1 falls within the orthographic projection of the terminal 2 on the base substrate. The second via hole VH2 exposes at least a portion of the upper surface of the terminal 2, so that in the subsequent sputtering and etching processes, the signal trace 3 formed can contact the exposed upper surface of the terminal 2, thereby forming an electrical connection between the terminal 2 and the signal trace 3.

[0098] In the embodiment of the present disclosure, terminal 2 includes a first terminal portion 21 located in first conductive layer 11 and a second terminal portion 22 located in second conductive layer 12. For example, first terminal portion 21 comprises a source or drain electrode material, and second terminal portion 22 comprises a highly conductive material such as copper. Terminal 2 comprises a laminated structure, particularly one in which the upper layer comprises a highly conductive material such as copper. This structure helps reduce the contact resistance between terminal 2 and signal trace 3, thereby improving the electrical connection between the two.

[0099] 4 and 5 , the plurality of conducting pads 121 include a first conducting pad 121A closest to the side edge 1S of the base substrate 1 . The orthographic projection of the first conductive pad 121A on the substrate substrate 1 has a first side 121AS close to the side edge 1S of the substrate substrate 1, the orthographic projection of the first planarization layer PLN1 on the substrate substrate 1 has a first side PLN1S close to the side edge 1S of the substrate substrate 1, and the orthographic projection of the second planarization layer PLN2 on the substrate substrate 1 has a first side PLN2S close to the side edge 1S of the substrate substrate 1. That is, the first side 121AS of the orthographic projection of the first conductive pad 121A on the substrate substrate 1 is a side facing the terminal 2 among the side edges of the orthographic projection of the first conductive pad 121A on the substrate substrate 1, the first side PLN1S of the orthographic projection of the first planarization layer PLN1 on the substrate substrate 1 is a side facing the terminal 2 among the side edges of the orthographic projection of the first planarization layer PLN1 on the substrate substrate 1, and the first side PLN2S of the orthographic projection of the second planarization layer PLN2 on the substrate substrate 1 is a side facing the terminal 2 among the side edges of the orthographic projection of the second planarization layer PLN2 on the substrate substrate 1.

[0100] The orthographic projection of the terminal 2 on the base substrate 1 has a first side 2S that is far away from the side edge 1S of the base substrate 1. In other words, the first side 2S of the orthographic projection of the terminal 2 on the base substrate 1 is the side that is farthest away from the side edge 1S of the base substrate 1 in the first direction D1 among the sides of the orthographic projection of the terminal 2 on the base substrate 1. The first direction D1 is perpendicular to the side edge 1S of the base substrate 1.

[0101] In an embodiment of the present disclosure, the first side PLN2S of the orthographic projection of the second planarization layer PLN2 on the substrate 1 is closer to the terminal 2 than the first side 121AS of the orthographic projection of the first conductive pad 121A on the substrate 1. In other words, the first side PLN2S of the orthographic projection of the second planarization layer PLN2 on the substrate 1 is closer to the side edge 1S of the substrate 1 than the first side 121AS of the orthographic projection of the first conductive pad 121A on the substrate 1. Exemplarily, the first side PLN2S of the orthographic projection of the second planarization layer PLN2 on the substrate 1 includes a first side portion PLN2S1, which is the portion of the first side PLN2S of the second planarization layer that faces the terminal 2. The first side 121AS of the orthographic projection of the first conductive pad 121A on the substrate 1 and the first side portion PLN2S1 of the first side of the orthographic projection of the second planarization layer on the substrate are separated by a first prescribed distance A1 in the first direction D1.

[0102] The first side PLN1S of the orthographic projection of the first planarization layer PLN1 on the base substrate 1 includes a first side portion PLN1S1, wherein the first side portion PLN1S1 of the first planarization layer is the portion of the first side PLN1S of the first planarization layer facing the terminal 2. In the embodiment of the present disclosure, the first side portion PLN1S1 of the first side of the orthographic projection of the first planarization layer on the base substrate 1 is closer to the terminal 2 than the first side portion PLN2S1 of the first side of the orthographic projection of the second planarization layer on the base substrate. In other words, the first side portion PLN1S1 of the first side of the orthographic projection of the first planarization layer on the base substrate 1 is closer to the side edge 1S of the base substrate 1 than the first side portion PLN2S1 of the first side of the orthographic projection of the second planarization layer on the base substrate.

[0103] Illustratively, the first side portion PLN1S1 of the first side of the orthographic projection of the first planarization layer on the base substrate is spaced apart from the first side portion PLN2S1 of the first side of the orthographic projection of the second planarization layer on the base substrate by a second prescribed distance A2 in the first direction D1.

[0104] A first side portion PLN1S1 of a first side of an orthographic projection of the first planarization layer on the base substrate is spaced a third prescribed distance A3 from a first side 2S of an orthographic projection of the terminal on the base substrate in the first direction D1.

[0105] In an embodiment of the present disclosure, the third prescribed distance A3 is greater than the first prescribed distance A1; and / or the first prescribed distance A1 is greater than the second prescribed distance A2.

[0106] Exemplarily, the first specified distance A1 is related to factors such as process deviation and alignment deviation when forming the first conductive pad and the second planarization layer, the second specified distance A2 is related to factors such as process deviation and alignment deviation when forming the first planarization layer and the second planarization layer, and the third specified distance A3 is related to factors such as process deviation and alignment deviation when forming the second terminal portion and the first planarization layer and the sputtering process.

[0107] In some exemplary embodiments, the first prescribed distance A1, the second prescribed distance A2, and the third prescribed distance A3 may satisfy the following requirement: A1+A2+A3=(PD-L1)÷2-L2-L3-L4,

[0108] Among them, PD is the pitch of the pixel unit in the first direction, L1 is the size of the light-emitting diode in the first direction, L2 is the size of the joint in the first direction, L3 is the edging distance along the first direction, and L4 is the size of the terminal 2 in the first direction.

[0109] It should be noted that, as shown in FIG. 4 and FIG. 5 , the area from the step difference of the planarization layer to the side edge 1S of the base substrate 1 can be defined as a terminal area, which includes the terminal and the sputtering areas on both sides thereof.

[0110] Figures 6 and 7 are respectively plan schematic diagrams of the display panel during the processing according to some exemplary embodiments of the present disclosure, wherein Figure 6 schematically shows a partial plan view of the display panel that is about to start the laser etching process after the sputtering process, and Figure 7 schematically shows a partial plan view of the display panel after the laser etching process.

[0111] 6 and 7 , in the sputtering process, a metal layer 30, such as a Ti / Cu / Ti metal layer, can be plated on the terminal area, the side of the display panel, and the fan-out area on the back of the display panel. In the laser etching process, it is necessary to etch the metal layer 30 between each terminal 2 to remove the metal material between each terminal 2. In this laser etching process, in order to ensure that the metal layer between each terminal 2 is sufficiently etched to ensure that there is no short circuit between each terminal 2, the laser etching process will be performed for a relatively long time. The inventors have found that in some cases, there is a risk that the laser etching affects the planarization layer at the edge. For example, Figure 7 schematically shows this situation. The laser used for etching may irradiate the planarization layer, causing the edge of the planarization layer to be burned, resulting in the risk of the conductive pad being exposed.

[0112] It should be noted that Figure 7 is merely exemplary and is only intended to illustrate that there may be a risk of burning the edge of the planarization layer. However, this cannot be regarded as a limitation to the embodiments of the present disclosure. In the embodiments of the present disclosure, there are also situations where the edge of the planarization layer will not be damaged or burned during the laser etching process, such as the situations shown in Figures 4 and 5.

[0113] In some exemplary embodiments of the present disclosure, a planarization layer can be used to form a retaining wall between the terminals 2. For example, the first planarization layer PLN1 and the second planarization layer PLN2 can be extended between the terminals 2 to form a retaining wall. During the laser etching process, the retaining wall can act as a buffer to protect the conductive pad of the light-emitting diode from being affected by the laser etching.

[0114] FIG8 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, which schematically illustrates a retaining wall design. FIG9 is a partial plan view of a display panel after a laser etching process according to some exemplary embodiments of the present disclosure. Referring to FIG8 and FIG9, the display panel 100 includes a plurality of terminals 2, and there is a gap 20 between the plurality of terminals 2. The display panel 100 includes a first retaining wall 7, which is opposite to the gap 20 in the first direction D1. The first side portion PLN1S1 of the first side of the orthographic projection of at least a portion of the first retaining wall 7 on the base substrate 1 protrudes toward the gap 20 in the first direction D1 relative to the first side portion of the orthographic projection of the first planarization layer PLN1 on the base substrate 1.

[0115] For example, the first retaining wall 7 can be formed by a portion of the planarization layer, with the first retaining wall 7 being closer to the side edge 1S of the base substrate 1 than other portions of the planarization layer. Specifically, the first retaining wall 7 includes a first retaining wall portion 71 located in the first planarization layer PLN1 and a second retaining wall portion 72 located in the second planarization layer PLN2. The first retaining wall portion 71 is a portion that extends continuously with the portion of the first planarization layer PLN1 located in the display area AA, and the second retaining wall portion 72 is a portion that extends continuously with the portion of the second planarization layer PLN2 located in the display area. The orthographic projection of the second retaining wall portion 72 on the base substrate 1 falls within the orthographic projection of the first retaining wall portion 71 on the base substrate 1.

[0116] 8 and 9 , there is a gap 20 between any two adjacent terminals 2 , that is, the display panel 100 includes a plurality of gaps 20 . Accordingly, the display panel 100 includes a plurality of first retaining walls 7 , which are disposed opposite to the plurality of gaps 20 , respectively.

[0117] 10A to 10F are schematic diagrams of intermediate structures of the display panel with the retaining wall design shown in FIG. 8 , wherein FIG. 10A to 10F schematically illustrate the structure of the display panel located in the terminal area and the display area adjacent to the terminal area.

[0118] 10A , a patterning process is performed on the first conductive layer 11 to form a first terminal portion 21 in the terminal region and a first trace SL1 in the terminal region and the display region, wherein the first trace SL1 extends from the first terminal portion 21 toward the display region AA.

[0119] 10B , a first planarization layer PLN1 is formed, wherein the first planarization layer PLN1 includes a portion located in the display area AA and a first retaining wall portion 71 of the first retaining wall 7 located in the terminal area. The first retaining wall portion 71 protrudes toward the side edge 1S of the base substrate 1 relative to the portion of the first planarization layer PLN1 located in the display area AA.

[0120] 10C , a first passivation layer PVX1 is formed on a side of the first planarization layer PLN1 away from the base substrate, and a first via hole VH1 is formed in the first passivation layer PVX1. The orthographic projection of the first via hole VH1 on the base substrate 1 falls within the orthographic projection of the first terminal portion 21 on the base substrate 1, that is, the first via hole VH1 exposes a portion of the upper surface of the first terminal portion 21.

[0121] 10D , a second conductive layer 12 is formed on a side of the first passivation layer PVX1 away from the base substrate, and a patterning process is performed on the second conductive layer 12 to form a second terminal portion 22 in the terminal region and a conductive pad 121 in the display region. The second terminal portion 22 contacts the first terminal portion 21 below through the first via hole VH1.

[0122] Referring to Figure 10E, a second planarization layer PLN2 is formed on the side of the second conductive layer 12 away from the base substrate, wherein the second planarization layer PLN2 includes a portion located in the display area AA and a second retaining wall portion 72 of the first retaining wall 7 located in the terminal area. The second retaining wall portion 72 protrudes toward the side edge 1S of the base substrate 1 relative to the portion of the second planarization layer PLN2 located in the display area AA. The orthographic projection of the second planarization layer PLN2 including the second retaining wall portion 72 on the base substrate 1 still falls within the orthographic projection of the first planarization layer PLN1 including the first retaining wall portion 71 on the base substrate 1. In this way, the second retaining wall portion 72 can be avoided from being formed at the step difference of the first planarization layer PLN1.

[0123] 10F , a second passivation layer PVX2 is formed on a side of the second planarization layer PLN2 away from the base substrate, and a second via hole VH2 is formed in the second passivation layer PVX2. The orthographic projection of the second via hole VH2 on the base substrate 1 falls within the orthographic projection of the second terminal portion 22 on the base substrate 1, that is, the second via hole VH2 exposes a portion of the upper surface of the second terminal portion 22.

[0124] Referring to Figures 8 and 9 , during the laser etching process, the first retaining wall 7 can act as a buffer, protecting the conductive pads of the LEDs from the effects of laser etching. Figure 11 is a SEM image of a display panel with a retaining wall design after the laser etching process. As shown in Figure 11 , the SEM image clearly shows that the laser etching has etched a portion of the first retaining wall 7. Under the protection of the first retaining wall 7, the laser etching does not further damage the planarization layer in the display area, nor does it damage the conductive pads of the LEDs.

[0125] Continuing with FIG11 , after laser etching, only a portion of the first retaining wall 7 is etched away, while a portion remains. That is, after laser etching, the display panel 100 still includes the first retaining wall 7, and the orthographic projection of at least a portion of the first retaining wall 7 on the base substrate 1 protrudes toward the gap 20 in the first direction D1 relative to the first side portion PLN1S1 of the first side of the orthographic projection of the first planarization layer PLN1 on the base substrate 1.

[0126] In some exemplary embodiments, the ratio of the dimension of the first retaining wall 7 in the second direction D2 to the dimension of the gap 20 directly opposite the first retaining wall 7 in the second direction D2 is between 0.6 and 1.5, wherein the second direction D2 is perpendicular to the first direction D1, for example, the second direction D2 is parallel to the side edge 1S of the substrate. For example, the dimension of the first retaining wall 7 in the second direction D2 is smaller than the dimension of the gap 20 in the second direction D2. For example, the dimension of the second retaining wall portion 72 in the second direction D2 is smaller than the dimension of the first retaining wall portion 71 in the second direction D2.

[0127] In the embodiments of the present disclosure, the height of the first retaining wall 7 protruding toward the gap 20 (i.e., the dimension of the first retaining wall 7 along the first direction D1) is related to the damage caused by laser etching to the planarization layer. In other words, the height of the first retaining wall 7 protruding toward the gap 20 is designed so that the laser etching does not damage the planarization layer located in the display area AA. In some examples, the first retaining wall 7 does not extend into the gap 20 in the first direction D1. For example, the orthographic projection of the first retaining wall 7 in the first direction D1 does not overlap with the orthographic projection of the terminal 2 in the first direction D1. Specifically, the dimension of the second retaining wall portion 72 in the first direction D1 is smaller than the dimension of the first retaining wall portion 71 in the first direction D1.

[0128] Figure 12 is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure, and Figure 13 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, wherein Figures 12 and 13 schematically illustrate another retaining wall design. Referring to Figures 12 and 13, the display panel 100 includes a plurality of terminals 2, and there is a gap 20 between the plurality of terminals 2. The display panel 100 includes a second retaining wall 8, which is opposite to the gap 20 in the first direction D1. The second retaining wall 8 is spaced apart from the portion of the first planarization layer PLN1 located in the display area AA, and the second retaining wall 8 is closer to the gap 20 than the portion of the first planarization layer PLN1 located in the display area AA. The second retaining wall 8 is spaced apart from the portion of the second planarization layer PLN2 located in the display area AA, and the second retaining wall 8 is closer to the gap 20 than the portion of the second planarization layer PLN2 located in the display area AA.

[0129] In an embodiment of the present disclosure, the second retaining wall 8 includes a first sub-retaining wall 81 located in the first planarization layer PLN1 and a second sub-retaining wall 82 located in the second planarization layer PLN2. The orthographic projection of the second sub-retaining wall 82 on the base substrate 1 falls within the orthographic projection of the first sub-retaining wall 81 on the base substrate 1.

[0130] 12 , the second retaining wall 8 further includes a third sub-retaining wall 83 located in the first passivation layer PVX1 and a fourth sub-retaining wall 84 located in the second passivation layer PVX2. The first sub-retaining wall 81 is spaced apart from the portion of the first planarization layer PLN1 located in the display area AA. The second sub-retaining wall 82 is spaced apart from the portion of the second planarization layer PLN2 located in the display area AA. The third sub-retaining wall 83 is a portion that extends continuously with the portion of the first passivation layer PVX1 located in the display area AA. The fourth sub-retaining wall 84 is a portion that extends continuously with the portion of the second passivation layer PVX2 located in the display area AA.

[0131] In the embodiment shown in Figures 12 and 13, the main portion of the second retaining wall 8 includes a portion located within the first planarization layer PLN1 and a portion located within the second planarization layer PLN2. The portion of the second retaining wall 8 located within the first planarization layer PLN1 is spaced apart from the portion of the first planarization layer PLN1 located within the display area AA, i.e., it is disposed discontinuously. The first passivation layer PVX1 and the second passivation layer PVX2 are still disposed between the portion of the first planarization layer PLN1 located within the display area AA and the portion of the second planarization layer PLN2 located within the display area AA, and the second retaining wall 8. This design ensures that even if a portion of the second retaining wall 8 is removed by laser etching during the laser etching process, the two planarization layers located within the display area AA are still protected by the corresponding passivation layers. This prevents moisture from entering the display panel along the planarization layers during reliability testing, thereby improving the reliability and yield of the display panel.

[0132] Referring to Figures 12 and 13, the first sub-retaining wall 81 and the portion of the first planarizing layer PLN1 located in the display area AA are separated by a fourth specified distance A4. That is, the vertical distance between the first side edge PLN1S of the orthographic projection of the first planarizing layer PLN1 on the base substrate 1 and the first side edge 811 of the orthographic projection of the first sub-retaining wall 81 on the base substrate 1, which is adjacent to the first side edge PLN1S, is the fourth specified distance A4. This fourth specified distance A4 is designed to ensure that, while taking into account process factors, the first sub-retaining wall 81 can be separated from the planarizing layer located in the display area AA. The fourth specified distance A4 is related to the processing deviation and alignment deviation of the first planarizing layer PLN1 and the second planarizing layer PLN2.

[0133] The size of the second sub-retaining wall 82 along the first direction D1 is related to the damage caused by laser etching to the planarization layer. In other words, the size of the second sub-retaining wall 82 along the first direction D1 is designed to prevent laser etching from damaging the planarization layer in the display area AA. In some examples, the second retaining wall 8 extends into the gap 20 in the first direction D1. For example, the orthographic projection of the second retaining wall 8 in the first direction D1 partially overlaps with the orthographic projection of the terminal 2 in the first direction D1. Specifically, the size of the second sub-retaining wall 82 in the first direction D1 is smaller than the size of the first sub-retaining wall 81 in the first direction D1.

[0134] In some exemplary embodiments, a ratio of a size of the second retaining wall 8 in the second direction D2 to a size of the gap 20 directly facing the second retaining wall 8 in the second direction D2 is between 0.6 and 1.

[0135] Figure 14 is a cross-sectional view of a display panel at a terminal according to some exemplary embodiments of the present disclosure, Figure 15 is a plan view of a display panel at a terminal according to some exemplary embodiments of the present disclosure, Figure 16 is a photograph of the structure of the display panel at a terminal after a gold deposition process according to some exemplary embodiments of the present disclosure, and Figure 17 is an SEM image of a display panel at a terminal according to some exemplary embodiments of the present disclosure.

[0136] 14 and 15 , in the middle of terminal 2, the film layer structure, from bottom to top, includes: a portion of the first insulating layer IL1 located on the base substrate 1, a portion of the second insulating layer IL2 located on the first insulating layer IL1, a first terminal portion 21 located in the first via hole VH1, and a second terminal portion 22 located in the second via hole VH2. At the edge of terminal 2, the film layer structure, from bottom to top, includes: a portion of the first insulating layer IL1 located on the base substrate 1, a portion of the second insulating layer IL2 located on the first insulating layer IL1, the first terminal portion 21 located in the first via hole VH1, a portion of the first passivation layer PVX1 covering the edge of the first terminal portion 21, the second terminal portion 22 located in the second via hole VH2, and a portion of the second passivation layer PVX2 covering the edge of the second terminal portion 22.

[0137] In this embodiment, the orthographic projection of the second terminal portion 22 on the base substrate 1 covers the orthographic projection of the first terminal portion 21 on the base substrate 1. Specifically, the orthographic projection of the first terminal portion 21 on the base substrate 1 has a first side 21S, and the orthographic projection of the second terminal portion 22 on the base substrate 1 has a first side 22S, wherein the first side 22S of the orthographic projection of the second terminal portion on the base substrate and the first side 21S of the orthographic projection of the first terminal portion on the base substrate are the sides of the orthographic projections of the two terminal portions on the base substrate on the same side. For example, in the embodiment shown in FIG15 , the first side 22S of the orthographic projection of the second terminal portion on the base substrate and the first side 21S of the orthographic projection of the first terminal portion on the base substrate are the sides of the orthographic projections of the two terminal portions on the base substrate on the left side, on the right side, or on the bottom side. The first side 22S of the orthographic projection of the second terminal portion on the base substrate is further outward than the first side 21S of the orthographic projection of the first terminal portion on the base substrate.

[0138] The inventors have discovered through research that, since the second terminal portion 22 located in the upper layer at the edge of the terminal 2 wraps the first terminal portion 21 located in the lower layer, the second terminal portion 22 has a climbing structure at the edge of the first terminal portion 21, as shown in FIG14 . The second passivation layer PVX2 above the second terminal portion 22 is relatively thin, and the climbing structure of the second terminal portion 22 may cause the second passivation layer PVX2 at each edge of the terminal 2 to break or crack at the climbing structure, as shown in FIG17 . In the subsequent gold deposition process, since it is a chemical reaction in a liquid state, the liquid will penetrate from the crack to the surface of the second terminal portion 22, react, and cause a nickel-gold wire to grow at the crack, as shown in FIG16 . This nickel-gold wire is extremely easy to fall off and randomly enter the display area, thereby bringing risks such as short circuits.

[0139] Figure 18 is a cross-sectional view of a display panel at a terminal according to some other exemplary embodiments of the present disclosure, Figure 19 is a plan view of a display panel at a terminal according to some other exemplary embodiments of the present disclosure, and Figure 20 is an SEM image of a display panel at a terminal according to some other exemplary embodiments of the present disclosure.

[0140] With reference to Figures 18 and 19 , in the middle of the terminal 2, the film layer structure from bottom to top includes: a portion of the first insulating layer IL1 located on the base substrate 1, a portion of the second insulating layer IL2 located on the first insulating layer IL1, a first terminal portion 21 located in the first via hole VH1, and a second terminal portion 22 located in the second via hole VH2. At the edge of the terminal 2, the film layer structure from bottom to top includes: a portion of the first insulating layer IL1 located on the base substrate 1, a portion of the second insulating layer IL2 located on the first insulating layer IL1, the first terminal portion 21 located in the first via hole VH1, a portion of the first passivation layer PVX1 covering the edge of the first terminal portion 21, the second terminal portion 22 located in the second via hole VH2, and a portion of the second passivation layer PVX2 covering the edge of the second terminal portion 22.

[0141] In this embodiment, the orthographic projection of the second terminal portion 22 on the substrate 1 falls within the orthographic projection of the first terminal portion 21 on the substrate 1. Specifically, the orthographic projection of the first terminal portion 21 on the substrate 1 has a first side 21S, and the orthographic projection of the second terminal portion 22 on the substrate 1 has a first side 22S, wherein the first side 22S of the orthographic projection of the second terminal portion on the substrate and the first side 21S of the orthographic projection of the first terminal portion on the substrate are the sides of the orthographic projections of the two terminal portions on the substrate on the same side. For example, in the embodiment shown in FIG19 , the first side 22S of the orthographic projection of the second terminal portion on the substrate and the first side 21S of the orthographic projection of the first terminal portion on the substrate are the sides of the orthographic projections of the two terminal portions on the substrate on the left side, the side on the right side, or the side on the bottom side.

[0142] In this embodiment, the orthographic projection of the second via hole VH2 on the base substrate 1 falls within the orthographic projection of the second terminal portion 22 on the base substrate 1, and a portion of the second passivation layer PVX2 covers the side edge of the second terminal portion 22. The orthographic projection of the first via hole VH1 on the base substrate 1 falls within the orthographic projection of the first terminal portion 21 on the base substrate 1, and a portion of the first passivation layer PVX1 covers the side edge of the first terminal portion 21.

[0143] The first side 21S of the orthographic projection of the first terminal portion on the substrate is further outward than the first side 22S of the orthographic projection of the second terminal portion on the substrate. In some exemplary embodiments, the vertical distance between the first side 22S of the orthographic projection of the second terminal portion on the substrate and the first side 21S of the orthographic projection of the first terminal portion on the substrate is greater than a fifth specified distance A5. The fifth specified distance A5 is related to process variations during the formation of the first and second terminal portions. Taking process variations into account, to ensure that the orthographic projection of the second terminal portion 22 on the substrate 1 always falls within the orthographic projection of the first terminal portion 21 on the substrate 1, the fifth specified distance A5 can be equal to approximately 2 microns, that is, the vertical distance between the first side 22S of the orthographic projection of the second terminal portion on the substrate and the first side 21S of the orthographic projection of the first terminal portion on the substrate is greater than 2 microns. For example, the vertical distance between the first side 22S of the orthographic projection of the second terminal portion on the substrate and the first side 21S of the orthographic projection of the first terminal portion on the substrate is greater than 3.5 microns.

[0144] With this design, the second passivation layer PVX2 covering the edge of the second terminal portion 22 will not climb and have a large step difference. In this way, the second passivation layer PVX2 is prevented from breaking or cracking at the edge of the second terminal portion 22. As shown in FIG20 , the step difference at the edge of the second terminal portion 22 is improved, and the entire morphology is flat. The second passivation layer PVX2 located above the edge of the second terminal portion 22 is relatively smooth, and no breakage problem occurs. In other words, in the subsequent gold deposition process, the problem of defective nickel-gold wire is avoided.

[0145] Returning to FIG2 , before the motherboard is cut, a to-be-cut area including a cutting edge is provided on the motherboard. The width of the to-be-cut area is related to cutting process factors. At least a portion of the test unit CT can be provided in the to-be-cut area. When testing the display panel, a test trace 91 (see FIG21 ) can be led from the terminal 2 to the test unit, and the display panel can be screened for yield using the test unit. For example, the test unit may include a plurality of test terminals 9, and the test terminals 9 may include a conductive metal material, such as Ti / Al / Ti.

[0146] The inventors have discovered through research that the area of ​​the orthographic projection of the test terminal 9 on the base substrate 1 is larger than the area of ​​the orthographic projection of the terminal 2 on the base substrate 1. Moreover, in order to facilitate the contact between the test terminal 9 and the test trace, most of the upper surface of the test terminal 9 needs to be exposed. In this case, the test terminal 9 exposed over a large area may have an adverse effect on the electroless gold process of the terminal 2. Figure 21 schematically shows the process of the reaction between the test terminal and the terminal during the electroless gold process on the display panel. Figure 22 is an SEM image of the terminal formed after the process shown in Figure 21 is executed. Figure 23 is a cross-sectional view of the display panel at the test terminal before the electroless gold process is performed on the display panel. 21 and 23 , in the region where the test terminal 9 is located, the film layer structure, from bottom to top, includes: a portion of the first insulating layer IL1 located on the base substrate 1, a portion of the second insulating layer IL2 located on the first insulating layer IL1, the test terminal 9 located in the third via VH3, a portion of the first planarization layer PLN1 located on the side of the test terminal 9 away from the base substrate, a portion of the first passivation layer PVX1 located on the side of the first planarization layer PLN1 away from the base substrate, a portion of the second planarization layer PLN2 located on the side of the first passivation layer PVX1 away from the base substrate, and a portion of the second passivation layer PVX2 located on the side of the first planarization layer PLN1 away from the base substrate. That is, the test terminal 9 and the first terminal portion 21 of the terminal 2 can be located on the same layer, that is, the test terminal 9 can include a source or drain material, for example, Ti / Al / Ti. The third via VH3 exposes at least a portion of the upper surface of the test terminal 9.

[0147] The exposed upper surface of the test terminal 9 includes a large area of ​​Ti / Al / Ti, and the exposed upper surface of the terminal 2 includes a small area of ​​Cu. Since Ti / Al / Ti is highly active as the surface metal of the test terminal, it is more likely to undergo a replacement reaction in the gold plating process. Specifically, referring to Figure 21, during the micro-etching process of the gold plating process, compared with the small area of ​​Cu, the Ti in the large area of ​​Ti / Al / Ti is more likely to lose electrons. During the activation process of the gold plating process, the electron density on the surface of the test terminal 9 is large, and the palladium complex is more likely to obtain electrons and be activated on the surface of the test terminal 9. During the nickel plating process of the gold plating process, since terminal 2 obtains less palladium during the activation process, nickel plating is relatively difficult. During the gold plating process of the gold plating process, since terminal 2 is difficult to nickel plating, terminal 2 is difficult to gold plating, which ultimately leads to plating leakage on the upper surface of terminal 2. As shown in Figure 22, after the gold plating process, only a portion of the nickel-gold is formed on the upper surface of terminal 2, resulting in a large area of ​​incompleteness.

[0148] Figure 24 is a cross-sectional view of a display panel at a test terminal before a gold deposition process is performed on the display panel. Figure 25 is a plan view of the display panel shown in Figure 24. Figure 26 is a SEM image of a terminal of the display panel having the structure shown in Figure 24.

[0149] Referring to Figures 24 and 25, in the region where test terminal 9 is located, the film layer structure, from bottom to top, includes: a portion of the first insulating layer IL1 located on the base substrate 1, a portion of the second insulating layer IL2 located on the first insulating layer IL1, a first portion of test terminal 9 located in the third via hole VH3, a portion of the first planarization layer PLN1 located on the side of the first portion of test terminal 9 away from the base substrate, a portion of the first passivation layer PVX1 located on the side of the first planarization layer PLN1 away from the base substrate, a second portion of test terminal 9 located on the side of the first passivation layer PVX1 away from the base substrate, a portion of the second planarization layer PLN2 located on the side of the second portion of test terminal 9 away from the base substrate, and a portion of the second passivation layer PVX2 located on the side of the first planarization layer PLN1 away from the base substrate. In other words, in this embodiment, test terminal 9 includes two portions, namely the first portion and the second portion described above. Herein, the first portion of test terminal 9 may be referred to as the first test terminal portion 91, and the second portion of test terminal 9 may be referred to as the second test terminal portion 92. The first test terminal portion 91 and the first terminal portion 21 of the terminal 2 can be located on the same layer. That is, the first test terminal portion 91 of the test terminal 9 can include a source or drain material, such as Ti / Al / Ti. The second test terminal portion 92 and the second terminal portion 22 of the terminal 2 can be located on the same layer. That is, the second test terminal portion 92 of the test terminal 9 can include a metal such as Cu. The third via VH3 exposes at least a portion of the upper surface of the second test terminal portion 92 of the test terminal 9.

[0150] Continuing with reference to Figures 24 and 25 , the orthographic projection of the second test terminal portion 92 on the base substrate 1 overlaps the orthographic projection of the first test terminal portion 91 on the base substrate 1. For example, the orthographic projection of the second test terminal portion 92 on the base substrate 1 substantially overlaps with the orthographic projection of the first test terminal portion 91 on the base substrate 1. The second passivation layer PVX2, the second planarization layer PLN2, the first passivation layer PVX1, and the first planarization layer PLN1 sequentially cover the first test terminal portion 91, allowing the second test terminal portion 92 to completely cover the first test terminal portion 91. This effectively prevents process deviations and avoids the risk of exposing the first test terminal portion 91.

[0151] As shown in FIG26 , after the gold deposition process, the nickel-gold layer formed on the terminal 2 is spread out flat without any damaged parts, and the defects in the entire gold deposition process are effectively solved.

[0152] FIG27 is a flow chart of a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. As shown in FIG27 , the method may include steps S2710 to S2780.

[0153] It should be noted that some steps of the above manufacturing method can be performed individually or in combination, and can be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figure.

[0154] In step S2710, a base substrate 1 is provided, which includes a display area AA, a side area NA and a to-be-cut area TCA. The side area NA is closer to the side edge of the base substrate than the display area AA, and the to-be-cut area TCA is closer to the side edge of the base substrate than the side area NA.

[0155] In step S2720 , a first conductive material layer 11 ′ is formed on the base substrate 1 .

[0156] In step S2730 , a patterning process is performed on the first conductive material layer 11 ′ to form a first terminal portion 21 located in the side area NA and a first trace SL1 extending from at least one side area NA to the display area AA.

[0157] In step S2740 , a first planarization layer PLN1 is formed on a side of the first terminal portion 21 and the first trace SL1 away from the base substrate 1 .

[0158] In step S2750 , a second conductive material layer 12 ′ is formed on a side of the first planarization layer PLN 1 away from the base substrate 1 .

[0159] In step S2760 , a patterning process is performed on the second conductive material layer 12 ′ to form the second terminal portion 22 in the side area NA.

[0160] In step S2770 , a second planarization layer PLN2 is formed on a side of the second terminal portion 22 away from the base substrate 1 .

[0161] In some exemplary embodiments, in step S2730, i.e., in the step of performing a patterning process on the first conductive material layer 11', a first test terminal portion 91 is further formed in the area to be cut. In step S2760, in the step of performing a patterning process on the second conductive material layer 12', a second test terminal portion 92 is further formed in the area to be cut. The orthographic projection of the second test terminal portion 92 on the base substrate 1 overlaps the orthographic projection of the first test terminal portion 91 on the base substrate 1.

[0162] In step S2780 , when the first test terminal portion 91 and the second test terminal portion 92 are located on the base substrate, a gold deposition process is performed on the second terminal portion 22 to form a protection layer on the surface of the second terminal portion 22 away from the base substrate.

[0163] Some exemplary embodiments of the present disclosure further provide a display device. Referring to FIG28 , the display device includes at least two display substrates as described above. At least two display substrates as described above are spliced ​​together to form the display device.

[0164] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display panel. These features and advantages can be referred to the above description of the display substrate and will not be repeated here.

[0165] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0166] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, wherein, The display panel includes: a substrate, the substrate including at least one side region and a display region, the at least one side region being closer to a side edge of the substrate than the display region; a plurality of pixel units disposed in the display region, the plurality of pixel units being distributed in an array on the substrate, at least one of the pixel units including a light-emitting diode and a pixel driving circuit for driving the light-emitting diode; terminals disposed on the substrate and in the side region; a first trace disposed on the substrate, one end of the first trace being electrically connected to the terminal and the other end being electrically connected to the pixel driving circuit; and a second trace disposed on the substrate, one end of the second trace being electrically connected to the terminal, the second trace extending in a direction from the terminal toward the side edge of the substrate, wherein the display panel includes: a first conductive layer disposed on the substrate; a first planarization layer disposed on a side of the first conductive layer away from the substrate; a second conductive layer disposed on a side of the first planarization layer away from the substrate; and a second planarization layer disposed on a side of the second conductive layer away from the substrate, wherein a positive projection of the terminal on the substrate is spaced apart from a positive projection of the first planarization layer on the substrate, and a positive projection of the terminal on the substrate is spaced apart from a positive projection of the second planarization layer on the substrate.

2. The display panel according to claim 1, wherein, In a region between the terminal and the light-emitting diode closest to the terminal, a positive projection of the second planarization layer on the substrate falls within a positive projection of the first planarization layer on the substrate.

3. The display panel according to claim 1 or 2, wherein, The display panel further includes a first passivation layer disposed between the first planarization layer and the second conductive layer; and In a region between the terminal and the light-emitting diode closest to the terminal, a positive projection of the first planarization layer on the substrate falls within a positive projection of the first passivation layer on the substrate.

4. The display panel according to claim 3, wherein, The display panel further includes a second passivation layer disposed on a side of the second planarization layer away from the substrate; and In a region between the terminal and the light-emitting diode closest to the terminal, a positive projection of the second planarization layer on the substrate falls within a positive projection of the second passivation layer on the substrate.

5. The display panel according to claim 4, wherein, The display panel includes a first via in the first passivation layer and a second via in the second passivation layer; A positive projection of the second via on the substrate falls within a positive projection of the first via on the substrate, and a positive projection of at least one of the first via and the second via on the substrate falls within a positive projection of the terminal on the substrate.

6. The display panel according to any one of claims 1-5, wherein, The terminal includes a first terminal portion in the first conductive layer and a second terminal portion in the second conductive layer.

7. The display panel according to any one of claims 1-6, wherein, The display panel includes a plurality of conductive pads located in the second conductive layer. The light-emitting diode includes a first electrode and a second electrode. The first electrode of the light-emitting diode is in contact with one of the conductive pads, and the second electrode of the light-emitting diode is in contact with another one of the conductive pads; and The plurality of conductive pads includes a first conductive pad closest to the side edge of the substrate. A first side of the positive projection of the second planarization layer on the substrate is closer to the terminal than a first side of the positive projection of the first conductive pad on the substrate. Herein, the first side of the positive projection of the first conductive pad on the substrate is a side facing the terminal among the respective sides of the positive projection of the first conductive pad on the substrate, and the first side of the positive projection of the second planarization layer on the substrate is a side facing the terminal among the respective sides of the positive projection of the second planarization layer on the substrate.

8. The display panel according to claim 7, wherein, The first side of the positive projection of the second planarization layer on the substrate includes a first side portion, and the first side portion of the second planarization layer is a portion of the first side of the second planarization layer facing the terminal; and The first side of the positive projection of the first conductive pad on the substrate and the first side portion of the first side of the positive projection of the second planarization layer on the substrate are spaced apart by a first specified distance in a first direction, where the first direction is perpendicular to the side edge of the substrate.

9. The display panel according to claim 8, wherein, The first side of the positive projection of the first planarization layer on the substrate includes a first side portion. Herein, the first side of the positive projection of the first planarization layer on the substrate is a side facing the terminal among the respective sides of the positive projection of the first planarization layer on the substrate, and the first side portion of the first planarization layer is a portion of the first side of the first planarization layer facing the terminal; and The first side portion of the first side of the positive projection of the first planarization layer on the substrate is closer to the terminal than the first side portion of the first side of the positive projection of the second planarization layer on the substrate.

10. The display panel according to claim 9, wherein, The first side portion of the first side of the positive projection of the first planarization layer on the substrate and the first side portion of the first side of the positive projection of the second planarization layer on the substrate are spaced apart by a second specified distance in the first direction.

11. The display panel according to claim 10, wherein, The first side portion of the first side of the positive projection of the first planarization layer on the substrate and the first side of the positive projection of the terminal on the substrate are spaced apart by a third specified distance in the first direction, where the first side of the positive projection of the terminal on the substrate is a side of the positive projection of the terminal on the substrate that is farthest from the side edge of the substrate in the first direction among the respective sides of the positive projection of the terminal on the substrate.

12. The display panel according to claim 11, wherein, The third specified distance is greater than the first specified distance; and / or, the first specified distance is greater than the second specified distance.

13. The display panel according to any one of claims 1-12, wherein, The display panel includes a plurality of the terminals, and there are gaps between the plurality of the terminals; The display panel includes a first barrier rib, and the first barrier rib faces the gap in a first direction, where in, the first direction is perpendicular to the side edge of the substrate; and at least a part of the first barrier rib protrudes toward the gap in the first direction with respect to a first side portion of a first side of the orthographic projection of the first planarization layer on the substrate on the substrate.

14. The display panel according to claim 13, wherein, The first barrier rib includes a first barrier rib portion located in the first planarization layer and a second barrier rib portion located in the second planarization layer; and the first barrier rib portion is a portion continuously extending from a portion of the first planarization layer located in the display area, and the second barrier rib portion is a portion continuously extending from a portion of the second planarization layer located in the display area.

15. The display panel according to claim 14, wherein, The orthographic projection of the second barrier rib portion on the substrate falls within the orthographic projection of the first barrier rib portion on the substrate.

16. The display panel according to any one of claims 1-12, wherein, The display panel includes a plurality of the terminals, and there are gaps between the plurality of the terminals; The display panel includes a second barrier rib, and the second barrier rib faces the gap in a first direction, where the first direction is perpendicular to the side edge of the substrate; the second barrier rib is spaced apart from a portion of the first planarization layer located in the display area, and the second barrier rib is closer to the gap than the portion of the first planarization layer located in the display area; and the second barrier rib is spaced apart from a portion of the second planarization layer located in the display area, and the second barrier rib is closer to the gap than the portion of the second planarization layer located in the display area.

17. The display panel according to claim 16, wherein, The second barrier rib includes a first sub-barrier rib located in the first planarization layer and a second sub-barrier rib located in the second planarization layer; and the orthographic projection of the second sub-barrier rib on the substrate falls within the orthographic projection of the first sub-barrier rib on the substrate.

18. The display panel according to claim 17, wherein, The second barrier rib further includes a third sub-barrier rib located in the first passivation layer and a fourth sub-barrier rib located in the second passivation layer; the first sub-barrier rib is spaced apart from a portion of the first planarization layer located in the display area; the second sub-barrier rib is spaced apart from a portion of the second planarization layer located in the display area; the third sub-barrier rib is a portion continuously extending from a portion of the first passivation layer located in the display area; and the fourth sub-barrier rib is a portion continuously extending from a portion of the second passivation layer located in the display area.

19. The display panel according to claim 6, wherein, The orthographic projection of the second terminal portion on the substrate falls within the orthographic projection of the first terminal portion on the substrate.

20. The display panel according to claim 5, wherein, The orthographic projection of the second via on the substrate falls within the orthographic projection of the second terminal portion on the substrate, and a part of the second passivation layer covers the side edge of the second terminal portion; and / or, the orthographic projection of the first via on the substrate falls within the orthographic projection of the first terminal portion on the substrate, and a part of the first passivation layer covers the side edge of the first terminal portion.

21. The display panel according to claim 19, wherein, The perpendicular distance between the first side of the orthographic projection of the second terminal portion on the substrate substrate and the first side of the orthographic projection of the first terminal portion on the substrate substrate is greater than 2 micrometers, wherein the first side of the orthographic projection of the second terminal portion on the substrate substrate and the first side of the orthographic projection of the first terminal portion on the substrate substrate are the sides on the same side of the orthographic projections of the two terminal portions on the substrate substrate.

22. The display panel according to claim 13, wherein, The ratio of the dimension of the first barrier in the second direction to the dimension of the gap opposite the first barrier in the second direction is between 0.6 and 1.5, wherein the second direction is perpendicular to the first direction.

23. The display panel according to claim 22, wherein, The orthographic projection of the first barrier in the first direction does not overlap with the orthographic projection of the terminal in the first direction.

24. The display panel according to claim 16, wherein, The ratio of the dimension of the second barrier in the second direction to the dimension of the gap opposite the second barrier in the second direction is between 0.6 and 1, wherein the second direction is perpendicular to the first direction.

25. The display panel according to claim 24, wherein, The orthographic projection of the second barrier in the first direction partially overlaps with the orthographic projection of the terminal in the first direction.

26. A display device, wherein, The display device includes the display panel according to any one of claims 1 to 25.

27. The display device according to claim 26, wherein, The display device includes a plurality of the display panels spliced together.

28. A method for manufacturing a display panel, wherein, The method includes: Providing a substrate substrate, the substrate substrate including a display area, a side area, and a to-be-cut area, the side area being closer to the side edge of the substrate substrate than the display area, and the to-be-cut area being closer to the side edge of the substrate substrate than the side area; Forming a first conductive material layer on the substrate substrate; Performing a patterning process on the first conductive material layer to form a first terminal portion located in the side area and a first trace extending from the at least one side area to the display area; Forming a first planarization layer on a side of the first terminal portion and the first trace away from the substrate substrate; Forming a second conductive material layer on a side of the first planarization layer away from the substrate substrate; Performing a patterning process on the second conductive material layer to form a second terminal portion located in the side area; and Forming a second planarization layer on a side of the second terminal portion away from the substrate substrate, wherein the orthographic projection of each of the first terminal portion and the second terminal portion on the substrate substrate is spaced apart from the orthographic projection of the first planarization layer on the substrate substrate, and the orthographic projection of each of the first terminal portion and the second terminal portion on the substrate substrate is spaced apart from the orthographic projection of the second planarization layer on the substrate substrate.

29. The method according to claim 28, wherein, In the step of performing the patterning process on the first conductive material layer, a first test terminal portion located in the to-be-cut area is further formed; In the step of performing the patterning process on the second conductive material layer, a second test terminal portion located in the to-be-cut area is further formed, wherein the orthographic projection of the second test terminal portion on the substrate substrate covers the orthographic projection of the first test terminal portion on the substrate substrate.

30. The method according to claim 29, wherein, The method further includes: When the first test terminal portion and the second test terminal portion are located on the substrate, an electroless gold plating process is performed on the second terminal portion to form a protective layer on the surface of the second terminal portion away from the substrate.

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