Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises multiple repeating units (100), at least one repeating unit (100) comprises multiple sub-pixels, each sub-pixel comprises a pixel driving circuit, and the pixel driving circuit is separately connected to a scanning signal line (30), a first power line (51), a data signal line (52), and a compensation signal line (53); and in a direction perpendicular to the display substrate, the display substrate at least comprises a semiconductor layer and multiple conductive layers provided on a base, the first power line (51), the data signal line (52), and the compensation signal line (53) are disposed on the side of the semiconductor layer close to the base, and the scanning signal line (30) is disposed on the side of the semiconductor layer away from the base.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being respectively connected to a scanning signal line, a first power line, a data signal line and a compensation signal line, the scanning signal line being configured to provide a scanning signal to the pixel driving circuit, the first power line being configured to provide a power signal to the pixel driving circuit, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; in a direction perpendicular to the display substrate, the display substrate comprises at least a semiconductor layer and a plurality of conductive layers arranged on a base, the first power line, the data signal line and the compensation signal line being arranged on a side of the semiconductor layer close to the base, and the scanning signal line being arranged on a side of the semiconductor layer away from the base.

[0006] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a third conductive layer arranged on the base and sequentially arranged in a direction away from the base, the first power line, the data signal line and the compensation signal line are arranged in the second conductive layer, and the scanning signal line is arranged in the third conductive layer.

[0007] In an exemplary embodiment, the third conductive layer also includes a plurality of connecting electrodes, at least one connecting electrode being connected to the second conductive layer and the semiconductor layer at the same time through a via hole of a transition structure, the via hole of the transition structure including at least two half holes, the first insulating layer and the second insulating layer in one half hole are removed to expose the surface of the second conductive layer, and the second insulating layer in the other half hole is removed to expose the surface of the semiconductor layer.

[0008] In an exemplary embodiment, at least one repeating unit further includes a power connection line, wherein the shape of the power connection line is a line extending along the direction of the pixel row, and the shape of the first power line is a line extending along the direction of the pixel column. The power connection line is connected to the first power line to form a mesh structure for transmitting the first power signal.

[0009] In an exemplary embodiment, the power connection line and the first power line are provided in different conductive layers, and the power connection line is connected to the first power line through a via.

[0010] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor and a storage capacitor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the gate electrode of the second transistor and the first end of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is respectively connected to the second electrode of the third transistor and the second end of the storage capacitor, and the first electrode of the third transistor is connected to the compensation signal line; in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scanning signal line.

[0011] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors and the gate electrodes of the plurality of third transistors are connected to the same scan signal line.

[0012] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scan signal line.

[0013] In an exemplary embodiment, the scan signal line, the gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the third transistor are provided in the same layer.

[0014] In an exemplary embodiment, in at least one repetition unit, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors in adjacent pixel rows are connected to the same scan signal line.

[0015] In an exemplary embodiment, the plurality of repeating units include an n-1th repeating unit row, an nth repeating unit row, and an n+1th repeating unit row, where n is a positive integer greater than 1, and the nth repeating unit row includes a first pixel row and a second pixel row, the first pixel row being located on a side of the second pixel row close to the n-1th repeating unit row, and the second pixel row being located on a side of the first pixel row close to the n+1th repeating unit row; the first gate electrode and the third gate electrode included in the first pixel row in the nth repeating unit row are both located on a side of the scanning signal line close to the n-1th repeating unit row, and the first gate electrode and the third gate electrode included in the second pixel row in the nth repeating unit row are both located on a side of the scanning signal line close to the n+1th repeating unit row.

[0016] In an exemplary embodiment, the first end of the storage capacitor includes a first plate and a third plate, the second end of the storage capacitor includes a second plate, the orthographic projection of the second plate on the base at least partially overlaps with the orthographic projection of the first plate on the plane of the display substrate, the first plate and the second plate form a first capacitor, the orthographic projection of the second plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the third plate on the plane of the display substrate, the third plate and the second plate form a second capacitor, the first plate is respectively connected to the third plate, the second electrode of the first transistor and the gate electrode of the second transistor, the second plate is respectively connected to the second electrode of the second transistor and the second electrode of the third transistor, and the first capacitor and the second capacitor constitute a storage capacitor with a parallel structure.

[0017] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a driving circuit layer arranged on the base, a color filter structure layer arranged on a side of the driving circuit layer away from the base, and a light-emitting structure layer arranged on a side of the color filter structure layer away from the base, the driving circuit layer includes at least a first conductive layer, a second conductive layer, a semiconductor layer and a third conductive layer arranged in sequence along a direction away from the base, and the light-emitting structure layer includes at least a fourth conductive layer and a pixel definition layer arranged in sequence along a direction away from the base; in at least one sub-pixel, the first electrode is arranged in the first conductive layer, the second electrode is arranged in the semiconductor layer, the third electrode is arranged in the fourth conductive layer, and the third electrode is connected to the first electrode through a via.

[0018] In an exemplary embodiment, the multiple sub-pixels in at least one repeating unit include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the first sub-pixel and the second sub-pixel form a first pixel row, the third sub-pixel and the fourth sub-pixel form a second pixel row, the first sub-pixel and the third sub-pixel form a first pixel column, and the second sub-pixel and the fourth sub-pixel form a second pixel column; the color filter structure layer includes at least a red color filter layer, a blue color filter layer and a green color filter layer, the red color filter layer includes at least a red filter set in the first sub-pixel, the blue color filter layer includes at least a blue filter set in the second sub-pixel, and the green color filter layer includes at least a green filter set in the fourth sub-pixel.

[0019] In an exemplary embodiment, the red color film layer further includes a shielding strip, a first shielding block, a second shielding block, a third shielding block and a fourth shielding block; the orthographic projection of the shielding strip on the substrate at least partially overlaps with the orthographic projection of the scanning signal line on the substrate, the orthographic projection of the first shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the first sub-pixel on the substrate, the orthographic projection of the second shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the second sub-pixel on the substrate, the orthographic projection of the third shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the third sub-pixel on the substrate, and the orthographic projection of the fourth shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the fourth sub-pixel on the substrate.

[0020] In an exemplary embodiment, the red color filter layer further includes a shielding strip, a first shielding block and a third shielding block, and the blue color filter layer further includes a second shielding block and a fourth shielding block; the orthographic projection of the shielding strip on the substrate at least partially overlaps with the orthographic projection of the scanning signal line on the substrate, the orthographic projection of the first shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the first sub-pixel on the substrate, the orthographic projection of the second shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the second sub-pixel on the substrate, the orthographic projection of the third shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the third sub-pixel on the substrate, and the orthographic projection of the fourth shielding block on the substrate at least partially overlaps with the orthographic projection of the second transistor in the fourth sub-pixel on the substrate.

[0021] In an exemplary embodiment, in at least one sub-pixel, the fourth conductive layer includes at least the third electrode plate, and a pixel opening exposing the third electrode plate is provided on the pixel definition layer; in at least one repeating unit, at least one pixel groove is provided on the pixel definition layer, and the pixel groove includes any one or more of the following: a first pixel groove extending along the pixel row direction, and a second pixel groove extending along the pixel column direction.

[0022] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0023] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being respectively connected to a scan signal line, a first power line, a data signal line, and a compensation signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit, the first power line being configured to provide a power signal to the pixel driving circuit, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; the manufacturing method comprising:

[0024] A semiconductor layer and multiple conductive layers are formed on a substrate. The first power line, data signal line and compensation signal line are arranged on a side of the semiconductor layer close to the substrate. The scan signal line is arranged on a side of the semiconductor layer away from the substrate.

[0025] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0027] FIG1 is a schematic structural diagram of a display device;

[0028] FIG2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0029] FIG3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure;

[0030] FIG4 is a schematic structural diagram of a driving circuit layer in a display substrate according to an embodiment of the present disclosure;

[0031] FIG5 is a schematic structural diagram of a color filter structure layer in a display substrate according to an embodiment of the present disclosure;

[0032] FIG6 is a schematic diagram of the present invention after forming a first conductive layer pattern;

[0033] 7A, 7B and 7C are schematic diagrams of the present invention after forming a second conductive layer pattern;

[0034] 8A, 8B and 8C are schematic diagrams of a method of forming a semiconductor layer pattern according to the present invention;

[0035] 9A and 9B are schematic diagrams of a method of forming a second insulating layer pattern according to the present invention;

[0036] 10A to 10D are schematic diagrams of the present invention after forming a third conductive layer pattern;

[0037] 11A and 11B are schematic diagrams of a method of forming a red color film layer pattern according to the present invention;

[0038] 12A and 12B are schematic diagrams of a method of forming a green color filter layer pattern according to the present invention;

[0039] 13A and 13B are schematic diagrams of a method of forming a blue color filter layer pattern according to the present invention;

[0040] FIG14 is a schematic diagram of a method of forming a flat layer pattern according to the present invention;

[0041] 15A and 15B are schematic diagrams of the present invention after forming a fourth conductive layer pattern;

[0042] FIG16 is a schematic diagram of a method of forming a pixel definition layer pattern according to the present invention;

[0043] FIG17 is a schematic structural diagram of a driving circuit layer in another display substrate according to an embodiment of the present disclosure;

[0044] FIG18 is a schematic structural diagram of a color filter structure layer in another display substrate according to an embodiment of the present disclosure;

[0045] FIG19 is a schematic diagram of another embodiment of the present invention after forming a first conductive layer pattern;

[0046] 20A and 20B are schematic diagrams of another embodiment of the present invention after forming a second conductive layer pattern;

[0047] 21A and 21B are schematic diagrams of another embodiment of the present invention after forming a semiconductor layer pattern;

[0048] FIG22 is a schematic diagram of another embodiment of the present invention after forming a second insulating layer pattern;

[0049] 23A and 23B are schematic diagrams of another embodiment of the present invention after forming a third conductive layer pattern;

[0050] 24A and 24B are schematic diagrams of another embodiment of the present invention after forming a red color film layer pattern;

[0051] 25A and 25B are schematic diagrams of another embodiment of the present invention after forming a green color filter layer pattern;

[0052] 26A and 26B are schematic diagrams of another embodiment of the present invention after forming a blue color filter layer pattern;

[0053] FIG27 is a schematic diagram of another embodiment of the present invention after forming a flat layer pattern;

[0054] 28A and 28B are schematic diagrams of another embodiment of the present invention after forming a fourth conductive layer pattern;

[0055] FIG. 29 is a schematic diagram of another embodiment of the present invention after forming a pixel definition layer pattern.

[0056] DESCRIPTION OF NUMERALS: 10—substrate; 10A—first insulating layer; 10B—second insulating layer; 11—first connecting electrode; 12—second connecting electrode; 13—third connecting electrode; 14—fourth connecting electrode; 15—fifth connecting electrode; 16—sixth connecting electrode; 17—seventh connecting electrode; 18—eighth connecting electrode; 19—ninth connecting electrode; 20—tenth connecting electrode; 21—first active layer; 22—second active layer; 23—third active layer; 30—scanning signal line; 31—first gate electrode; 32—second gate electrode; 33—third gate electrode; 41—red filter; 42—blue filter; 43—green filter; 51—first power line; 52—data signal line; 53—compensation signal line; 54—power connecting line; 61—first plate; 62—second plate; 63—third electrode plate; 70—shielding strip; 71—first shielding block; 72—second shielding block; 73—third shielding block; 74—fourth shielding block; 100—repeating unit. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0058] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0059] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0060] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0061] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0062] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0063] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0064] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0065] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0066] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0067] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0068] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0069] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next level circuit under the control of a clock signal, where m can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0070] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being respectively connected to a scan signal line, a first power line, a data signal line, and a compensation signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit, the first power line being configured to provide a power signal to the pixel driving circuit, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; in a direction perpendicular to the display substrate, the display substrate comprises at least a semiconductor layer and a plurality of conductive layers arranged on a base, the first power line, the data signal line, and the compensation signal line being arranged on a side of the semiconductor layer close to the base, and the scan signal line being arranged on a side of the semiconductor layer away from the base.

[0071] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a third conductive layer arranged on the base and sequentially arranged in a direction away from the base, the first power line, the data signal line and the compensation signal line are arranged in the second conductive layer, and the scanning signal line is arranged in the third conductive layer.

[0072] In an exemplary embodiment, the third conductive layer also includes a plurality of connecting electrodes, at least one connecting electrode being connected to the second conductive layer and the semiconductor layer at the same time through a via hole of a transition structure, the via hole of the transition structure including at least two half holes, the first insulating layer and the second insulating layer in one half hole are removed to expose the surface of the second conductive layer, and the second insulating layer in the other half hole is removed to expose the surface of the semiconductor layer.

[0073] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor and a storage capacitor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the gate electrode of the second transistor and the first end of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is respectively connected to the second electrode of the third transistor and the second end of the storage capacitor, and the first electrode of the third transistor is connected to the compensation signal line; in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scanning signal line.

[0074] In an exemplary embodiment, the first end of the storage capacitor includes a first plate and a third plate, the second end of the storage capacitor includes a second plate, the orthographic projection of the second plate on the base at least partially overlaps with the orthographic projection of the first plate on the plane of the display substrate, the first plate and the second plate form a first capacitor, the orthographic projection of the second plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the third plate on the plane of the display substrate, the third plate and the second plate form a second capacitor, the first plate is respectively connected to the third plate, the second electrode of the first transistor and the gate electrode of the second transistor, the second plate is respectively connected to the second electrode of the second transistor and the second electrode of the third transistor, and the first capacitor and the second capacitor constitute a storage capacitor with a parallel structure.

[0075] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0076] Figure 2 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 2, in an exemplary embodiment, the display substrate may include multiple repeating units 100 in a direction parallel to the display substrate. At least one repeating unit 100 may include multiple sub-pixels. The multiple sub-pixels may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, a third sub-pixel P3 that emits a third color light, and a fourth sub-pixel P4 that emits a fourth color light. In an exemplary embodiment, a repeating unit is a basic unit that constitutes the display substrate. The display substrate is formed by repeatedly and continuously arranging the repeating units along at least one direction. That is, the display substrate is composed of multiple repeating units.

[0077] In an exemplary embodiment, four sub-pixels may be arranged in a square manner, which can effectively increase the aperture ratio and the light-transmitting area.

[0078] In an exemplary embodiment, in at least one repeating unit 100, the second subpixel P2 may be arranged on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be arranged on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be arranged on one side of the third subpixel P3 in the first direction X. The plurality of subpixels arranged sequentially along the first direction X may be referred to as a pixel row, and the plurality of subpixels arranged sequentially along the second direction Y may be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array, and the first direction X intersects the second direction Y.

[0079] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, the third subpixel P3 may be a white subpixel (W) that emits white light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light. In some possible embodiments, the arrangement of the RBWGs may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0080] In an exemplary embodiment, the display substrate may include, perpendicular to the display substrate, at least a driving circuit layer disposed on a substrate, a color filter structure layer disposed on a side of the driving circuit layer distal from the substrate, and a light-emitting structure layer disposed on a side of the color filter structure layer distal from the substrate. In at least one repeating unit, the driving circuit layer may include multiple circuit units, each of which may include at least a pixel driving circuit. The pixel driving circuits are connected to scan signal lines and data signal lines, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and output corresponding currents to the light-emitting devices. The color filter structure layer may include multiple color filter units, each of which may include at least a color filter layer configured to cause the corresponding sub-pixel to emit light of a desired color. The light-emitting structure layer may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit corresponding to the sub-pixel in which it is located, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0081] In exemplary embodiments, the circuit unit referred to in this disclosure refers to an area divided by pixel driver circuits. The color filter unit referred to in this disclosure refers to an area divided by color filter layers. The display unit referred to in this disclosure refers to an area divided by light-emitting devices. The orthographic projections of the circuit unit, the color filter layer, and the light-emitting unit on the substrate may correspond or may not correspond.

[0082] In the exemplary embodiment of the present disclosure, the positions of the circuit unit's orthographic projection on the substrate, the color filter layer's orthographic projection on the substrate, and the light-emitting unit's orthographic projection on the substrate are one-to-one corresponding, and the circuit unit, the color filter unit, and the light-emitting unit constitute sub-pixels. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0083] Figure 3 shows an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, at least one repeating unit may include four pixel driving circuits, which may be arranged in a square pattern and may have a 3T1C structure.

[0084] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 30, the first power line 51, the data signal line 52, and the compensation signal line 53.

[0085] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0086] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0087] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0088] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 30, a first electrode of the first transistor T1 is connected to the data signal line 52, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 30, the first transistor T1 inputs a data signal of the data signal line 52 to the gate electrode of the second transistor T2.

[0089] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0090] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 30, a first electrode of the third transistor T3 is connected to the compensation signal line 53, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0091] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30 .

[0092] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0093] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0094] In an exemplary embodiment, the light emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device EL is connected to the second node N2, and the second electrode of the light emitting device EL is connected to the second power line 52. The light emitting device EL emits light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0095] In an exemplary embodiment, the signal of the first power line 51 is a continuously provided high-level signal, and the signal of the second power line 52 is a continuously provided low-level signal.

[0096] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0097] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0098] Figure 4 is a schematic diagram of the structure of a driver circuit layer in a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driver circuit in a repeating unit (four subpixels) of a bottom-emission display substrate. In this exemplary embodiment, at least one repeating unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square, each of which includes a pixel driver circuit.

[0099] In an exemplary embodiment, at least one repeating unit may include a scan signal line 30, two first power lines 51, four data signal lines 52 and a compensation signal line 53, and the above signal lines are all connected to the pixel driving circuits in the four sub-pixels, the scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power line 51 is configured to provide a power signal to the pixel driving circuit, the data signal line 52 is configured to provide a data signal to the pixel driving circuit, and the compensation signal line 53 is configured to provide a compensation signal to the pixel driving circuit.

[0100] In an exemplary embodiment, the main portion of the scan signal line 30 extends along the first direction X and may be located in the middle of the repeating unit in the second direction Y. The main portions of the first power line 51, the data signal line 52, and the compensation signal line 53 extend along the second direction Y. Two first power lines 51 may be located on either side of the repeating unit in the first direction X, four data signal lines 52 and the compensation signal line 53 may be located between the two first power lines 51, two of the four data signal lines 52 may be located between one first power line 51 and the compensation signal line 53, and the other two of the four data signal lines 52 may be located between another first power line 51 and the compensation signal line 53. Thus, one scan signal line 30 extending along the first direction X, two first power lines 51 extending along the second direction Y, and one compensation signal line 53 extending along the second direction Y define a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 of a repeating unit.

[0101] In an exemplary embodiment, in at least one repetition unit, the four sub-pixels may be mirror-symmetrical with respect to the scan signal line 30 , and the four sub-pixels may be mirror-symmetrical with respect to the compensation signal line 53 .

[0102] In an exemplary embodiment, a pixel driving circuit for at least one sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C. The first transistor T1, the second transistor T2, and the third transistor T3 may each include an active layer, a gate electrode, a first electrode, and a second electrode. The storage capacitor C may include a first end and a second end. In an exemplary embodiment, the first electrode of the first transistor T1 is connected to the data signal line 52, the second electrode of the first transistor T1 is respectively connected to the gate electrode of the second transistor T2 and the first end of the storage capacitor C, the first electrode of the second transistor T2 is connected to the first power line 51, the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the compensation signal line 53.

[0103] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scanning signal line 30 .

[0104] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0105] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0106] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a base, a semiconductor layer disposed on the base, and a plurality of conductive layers, the first power line 51, the data signal line 52, and the compensation signal line 53 may be disposed on a side of the semiconductor layer close to the base, and the scanning signal line 30 may be disposed on a side of the semiconductor layer away from the base.

[0107] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a first insulating layer arranged on a side of the second conductive layer away from the substrate, a semiconductor layer arranged on a side of the first insulating layer away from the substrate, a second insulating layer arranged on a side of the semiconductor layer away from the substrate, and a third conductive layer arranged on a side of the second insulating layer away from the substrate.

[0108] In an exemplary embodiment, the first conductive layer may include at least a first plate 61 of a storage capacitor, the second conductive layer may include at least a third connecting electrode 13 as a shielding layer, a first power line 51, a data signal line 52 and a compensation signal line 53, the semiconductor layer may include at least an active layer of three transistors and a second plate 62 of a storage capacitor, and the third conductive layer may include at least a scanning signal line 30.

[0109] In an exemplary embodiment, the third conductive layer may further include a first gate electrode 31, a second gate electrode 32 and a third gate electrode 33, that is, the scan signal line 30, the first gate electrode 31, the second gate electrode 32 and the third gate electrode 33 are arranged in the same layer and are formed simultaneously through the same patterning process.

[0110] In an exemplary embodiment, the first gate electrode 31 and the third gate electrode 33 are connected to the scan signal line 30 , and the second gate electrode 32 is connected to the second plate 62 .

[0111] In an exemplary embodiment, the scan signal line 30 , the first gate electrode 31 , and the third gate electrode 33 are an integral structure connected to each other.

[0112] In an exemplary embodiment, in a plurality of pixel driving circuits in adjacent pixel rows, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0113] In an exemplary embodiment, the plurality of repeating units of the display substrate may include an n-1th repeating unit row, an nth repeating unit row, and an n+1th repeating unit row, arranged sequentially along the second direction Y, where n is a positive integer greater than 1. Each repeating unit row may include a first pixel row and a second pixel row. The first pixel row may include a plurality of first sub-pixels and a plurality of second sub-pixels, and the second pixel row may include a plurality of third sub-pixels and a plurality of fourth sub-pixels. For example, in the nth repeating unit row, the first pixel row is located on a side of the second pixel row that is closer to the n-1th repeating unit row, and the second pixel row is located on a side of the first pixel row that is closer to the n+1th repeating unit row.

[0114] In an exemplary embodiment, the first gate electrode and the third gate electrode included in the first pixel row in the nth repeating unit row are both located on the side of the scanning signal line 30 close to the (n-1)th repeating unit row, and the first gate electrode and the third gate electrode included in the second pixel row in the nth repeating unit row are both located on the side of the scanning signal line 30 close to the (n+1)th repeating unit row.

[0115] In an exemplary embodiment, in at least one repeating unit row, the first gate electrode and the third gate electrode included in the first pixel row have a first distance from the scanning signal line 30, and the first gate electrode and the third gate electrode included in the second pixel row have a second distance from the scanning signal line 30, and the ratio of the first distance to the second distance can be approximately 0.95 to 1.05.

[0116] In an exemplary embodiment, the first distance and the second distance may be substantially equal.

[0117] In an exemplary embodiment, the third conductive layer may further include a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18 and a ninth connecting electrode 19, at least one of the above connecting electrodes is simultaneously connected to the second conductive layer and the semiconductor layer through a via hole of the transition structure, the via hole of the transition structure includes at least two half holes, the first insulating layer and the second insulating layer in one half hole are removed to expose the surface of the second conductive layer, and the second insulating layer in the other half hole is removed to expose the surface of the semiconductor layer.

[0118] In an exemplary embodiment, the fifth connection electrode 15 may connect the second electrode of the second transistor T2 to the first electrode plate 61 through a via hole of the transfer structure.

[0119] In an exemplary embodiment, the sixth connection electrode 16 may connect the second electrode of the third transistor T3 to the first electrode plate 61 through a via hole of the transfer structure.

[0120] In an exemplary embodiment, the seventh connection electrode 17 may realize the connection between the data signal line 52 and the first electrode of the first transistor T1 through a via hole of the transfer structure.

[0121] In an exemplary embodiment, the eighth connection electrode 18 may connect the first power line 51 to the first electrode of the second transistor T2 through a via hole, and the second electrode of the second transistor T2 is connected to the second electrode plate 62 .

[0122] In an exemplary embodiment, the ninth connection electrode 19 may realize the connection between the compensation signal line 53 and the first electrode of the third transistor T3 through a via hole of the transfer structure.

[0123] Figure 5 is a schematic diagram of the structure of a color filter structure layer in a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a color filter layer in a repeating unit (four sub-pixels) of a bottom-emission display substrate. As shown in Figure 5, in an exemplary embodiment, at least one repeating unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged in a square, each sub-pixel including a color filter layer.

[0124] In an exemplary embodiment, the color filter structure layer may include at least a red color filter layer, a blue color filter layer and a green color filter layer. The red color filter layer may include at least a red filter 41 set in the first sub-pixel P1, the blue color filter layer may include at least a blue filter 42 set in the second sub-pixel P2, and the green color filter layer may include at least a green filter 43 set in the fourth sub-pixel P4.

[0125] In an exemplary embodiment, the red color filter layer may further include a shielding strip 70 , a first shielding block 71 , a second shielding block 72 , a third shielding block 73 , and a fourth shielding block 74 .

[0126] In an exemplary embodiment, the shielding strip 70 may be in the shape of a strip extending along the first direction X and may be disposed in the middle of the repeating unit in the second direction Y, and the orthographic projection of the shielding strip 70 on the substrate at least partially overlaps with the orthographic projection of the scanning signal line 30 on the substrate.

[0127] In an exemplary embodiment, the first blocking block 71 may be disposed in the first subpixel P1 , and an orthographic projection of the first blocking block 71 on the substrate at least partially overlaps an orthographic projection of the second transistor T2 in the first subpixel P1 on the substrate.

[0128] In an exemplary embodiment, the second blocking block 72 may be disposed in the second subpixel P2 , and an orthographic projection of the second blocking block 72 on the substrate at least partially overlaps an orthographic projection of the second transistor T2 in the second subpixel P2 on the substrate.

[0129] In an exemplary embodiment, the third blocking block 73 may be disposed in the third subpixel P3 , and an orthographic projection of the third blocking block 73 on the substrate at least partially overlaps an orthographic projection of the second transistor T2 in the third subpixel P3 on the substrate.

[0130] In an exemplary embodiment, the fourth blocking block 74 may be disposed in the fourth subpixel P4 , and an orthographic projection of the fourth blocking block 74 on the substrate at least partially overlaps an orthographic projection of the second transistor T2 in the fourth subpixel P4 on the substrate.

[0131] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0132] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1 , second sub-pixel P2 , third sub-pixel P3 and fourth sub-pixel P4 ) of a repeating unit as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0133] (101) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG6 .

[0134] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate may include at least a first connection electrode 11 , a second connection electrode 12 , and a first electrode plate 61 .

[0135] In an exemplary embodiment, the shape of the first electrode plate 61 can be rectangular, and the corners of the rectangle can be chamfered. The first electrode plate 61 can serve as a transparent lower electrode plate of a transparent storage capacitor. The first electrode plate 61 is configured to form a transparent first capacitor with a subsequently formed second electrode plate.

[0136] In an exemplary embodiment, the shape of the first connection electrode 11 can be a strip shape with a main portion extending along the first direction X, the first end of the first connection electrode 11 is connected to the first electrode plate 61, and the second end of the first connection electrode 11 extends in a direction away from the first electrode plate 61. The first connection electrode 11 is configured to be connected to a third connection electrode formed subsequently.

[0137] In an exemplary embodiment, the shape of the second connection electrode 12 can be rectangular, the first end of the second connection electrode 12 is connected to the first electrode plate 61, the second end of the second connection electrode 12 extends in a direction away from the first electrode plate 61, and the second connection electrode 12 is configured to be connected to a fourth connection electrode formed subsequently.

[0138] In an exemplary embodiment, in the first subpixel P1 and the second subpixel P2, the first connection electrode 11 may be disposed on one side of the first electrode plate 61 in the opposite direction of the second direction Y, and the second connection electrode 12 may be disposed on one side of the first electrode plate 61 in the second direction Y. In the third subpixel P3 and the fourth subpixel P4, the first connection electrode 11 may be disposed on one side of the first electrode plate 61 in the second direction Y, and the second connection electrode 12 may be disposed on one side of the first electrode plate 61 in the opposite direction of the second direction Y.

[0139] In an exemplary embodiment, in the first pixel column, an edge of the first connection electrode 11 on a side close to the second pixel column may be substantially flush with an edge of the first electrode plate 61 on a side close to the second pixel column. In the second pixel column, an edge of the first connection electrode 11 on a side close to the first pixel column may be substantially flush with an edge of the first electrode plate 61 on a side close to the first pixel column.

[0140] In an exemplary embodiment, the first connection electrode 11 , the second connection electrode 12 , and the first electrode plate 61 of each sub-pixel may be an integrated structure connected to each other.

[0141] In an exemplary embodiment, the areas of the first plates 61 in the respective sub-pixels may be substantially the same, so that the capacities of the storage capacitors in the respective sub-pixels are substantially the same.

[0142] In an exemplary embodiment, the positions of the respective patterns in the first conductive layer in the first subpixel P1 and the positions of the respective patterns in the first conductive layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the first conductive layer in the second subpixel P2 and the positions of the respective patterns in the first conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line, the positions of the respective patterns in the first conductive layer in the first subpixel P1 and the positions of the respective patterns in the first conductive layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the respective patterns in the first conductive layer in the third subpixel P3 and the positions of the respective patterns in the first conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line. The horizontal reference line may be a straight line extending along the first direction X and bisecting the repeating unit in the second direction Y, and the vertical reference line may be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0143] In an exemplary embodiment, the first conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0144] (102) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second conductive layer, as shown in FIG7A , FIG7B , and FIG7C , where FIG7B is a schematic diagram of the second conductive layer in FIG7A , and FIG7C is a cross-sectional view taken along line AA in FIG7A .

[0145] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a third connection electrode 13 and a fourth connection electrode 14 .

[0146] In an exemplary embodiment, the third connection electrode 13 may be rectangular and may be located on a side of the first electrode plate 61 away from the second connection electrode 12. The orthographic projection of the third connection electrode 13 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 11 on the substrate, and the third connection electrode 13 directly overlaps the first connection electrode 11. In an exemplary embodiment, the third connection electrode 13 is configured to connect to a subsequently formed fifth connection electrode and to shield the second transistor from light, thereby reducing the intensity of light incident on the second transistor and lowering leakage current of the second transistor, thereby alleviating the impact of light on the characteristics of the second transistor.

[0147] In an exemplary embodiment, the fourth connection electrode 14 can be rectangular in shape and can be located on the side of the first electrode plate 61 away from the first connection electrode 11. The orthographic projection of the fourth connection electrode 14 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 12 on the substrate, and the fourth connection electrode 14 is directly overlapped with the second connection electrode 12. The fourth connection electrode 14 is configured to be connected to the sixth connection electrode formed subsequently.

[0148] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may include at least two first power lines 51 , four data signal lines 52 , and one compensation signal line 53 .

[0149] In an exemplary embodiment, the main portions of the first power lines 51, the data signal lines 52, and the compensation signal lines 53 extend along the second direction Y, the first first power line 51 may be located on the side opposite to the first direction X of the repeating unit, the second first power line 51 may be located on the side of the repeating unit in the first direction X, the compensation signal line 53 may be located between the two first power lines 51, two of the four data signal lines 52 may be located between the first first power line 51 and the compensation signal line 53, and the other two of the four data signal lines 52 may be located between the second first power line 51 and the compensation signal line 53.

[0150] In an exemplary embodiment, the first power supply line 51 and the compensation signal line 53 may define a first pixel column, and the two data signal lines 52 are disposed in the first pixel column. The second first power supply line 51 and the compensation signal line 53 may define a second pixel column, and the two data signal lines 52 are disposed in the second pixel column.

[0151] In an exemplary embodiment, the positions of the two first power lines 51 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the two data signal lines 52 located on the side opposite to the compensation signal line 53 in the first direction X and the positions of the two data signal lines 52 located on the side of the compensation signal line 53 in the first direction X may be substantially mirror-symmetrical with respect to the vertical reference line. The positions of the third connection electrode 13 and the fourth connection electrode 14 in the first subpixel P1 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the second subpixel P2 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line.

[0152] In an exemplary embodiment, the first power line 51, the data signal line 52 and the compensation signal line 53 can be straight lines or broken lines of equal width, or straight lines or broken lines of unequal width. The use of straight lines or broken lines of variable width can not only facilitate the layout of the pixel structure, but also reduce parasitic capacitance.

[0153] As shown in FIG10C , the display substrate may include a first conductive layer disposed on a base 10 and a second conductive layer disposed on a side of the first conductive layer away from the base. The first conductive layer may include at least a second connection electrode 12 disposed on the base 10, and the second conductive layer may include at least a fourth connection electrode 14 disposed on the second connection electrode 12, with the fourth connection electrode 14 directly overlapping the second connection electrode 12.

[0154] (103) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG8A, FIG8B, and FIG8C, where FIG8B is a schematic diagram of the semiconductor layer in FIG8A, and FIG8C is a cross-sectional view taken along the AA line in FIG8A.

[0155] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode 62, the first active layer 21 serving as the active layer of the first transistor T1, the second active layer 22 serving as the active layer of the second transistor T2, the third active layer 23 serving as the active layer of the third transistor T3, and the second electrode 62 serving as the middle electrode of the storage capacitor.

[0156] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 may be disposed on one side of the first electrode plate 61 of the subpixel in the second direction Y, and the second active layer 22 may be disposed on the side of the first electrode plate 61 of the subpixel opposite to the second direction Y. The orthographic projection of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the third connecting electrode 13 of the subpixel on the substrate. The third active layer 23 of the first subpixel P1 may be disposed on one side of the first active layer 21 of the subpixel in the first direction X, and the third active layer 23 of the second subpixel P2 may be disposed on the side of the first active layer 21 of the subpixel opposite to the first direction X.

[0157] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 may be disposed on a side of the first electrode plate 61 of the subpixel opposite to the second direction Y, and the second active layer 22 may be disposed on a side of the first electrode plate 61 of the subpixel in the second direction Y, with the orthographic projection of the second active layer 22 on the substrate at least partially overlapping the orthographic projection of the third connection electrode 13 of the subpixel on the substrate. The third active layer 23 of the third subpixel P3 may be disposed on a side of the first active layer 21 of the subpixel in the first direction X, and the third active layer 23 of the fourth subpixel P4 may be disposed on a side of the first active layer 21 of the subpixel opposite to the first direction X.

[0158] In an exemplary embodiment, the second active layer 22 of the first subpixel P1 and the second active layer 22 of the second subpixel P2 may be interconnected as an integral structure, and the second active layer 22 of the third subpixel P3 and the second active layer 22 of the fourth subpixel P4 may be interconnected as an integral structure. By providing a shared source electrode for the second transistors of two adjacent subpixels in a pixel row, the present disclosure not only saves space but also reduces the number of via connection structures, simplifying the manufacturing process.

[0159] In an exemplary embodiment, the orthographic projection of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the third connecting electrode 13 on the substrate, so that the first electrode 61 serving as a shielding layer can shield the channel region of the second transistor T2, thereby preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0160] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0161] In an exemplary embodiment, a first region of the first active layer 21 is adjacent to the corresponding data signal line 52 , and a second region of the first active layer 21 is connected to the second electrode plate 62 .

[0162] In an exemplary embodiment, the orthographic projection of the first region of the second active layer 22 on the substrate does not overlap with the orthographic projection of the third connecting electrode 13 on the substrate, and the orthographic projection of the second region and the channel region of the second active layer 22 on the substrate at least partially overlap with the orthographic projection of the third connecting electrode 13 on the substrate.

[0163] In an exemplary embodiment, a first region of the third active layer 23 is adjacent to the compensation signal line 53 , and a second region of the third active layer 23 is adjacent to the fourth connection electrode 14 .

[0164] In an exemplary embodiment, for the first active layer 21, the second active layer 22, and the third active layer 23, positions of the three active layers in the first subpixel P1 and the three active layers in the third subpixel P3 may be substantially mirror-symmetrical with respect to a vertical reference line, positions of the three active layers in the second subpixel P2 and the three active layers in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line, positions of the three active layers in the first subpixel P1 and the three active layers in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, and positions of the three active layers in the second subpixel P2 and the three active layers in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line.

[0165] In an exemplary embodiment, the shape of the second electrode plate 62 can be rectangular, the corners of the rectangle can be chamfered, and it can be arranged between the second active layer 22 and the third active layer 23 of the sub-pixel. The orthographic projection of the second electrode plate 62 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 61 on the substrate. The second electrode plate 62 can serve as a transparent intermediate electrode plate of a transparent storage capacitor, and the first electrode plate 61 and the second electrode plate 62 form a transparent first capacitor.

[0166] In an exemplary embodiment, the second electrode plate 62 and the first active layer 21 may be an integral structure connected to each other.

[0167] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0168] In an exemplary embodiment, the area of ​​the second electrode 62 in each sub-pixel may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0169] In an exemplary embodiment, the position of each pattern in the semiconductor layer in the first sub-pixel P1 and the position of each pattern in the semiconductor layer in the third sub-pixel P3 can be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the semiconductor layer in the second sub-pixel P2 and the position of each pattern in the semiconductor layer in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the semiconductor layer in the first sub-pixel P1 and the position of each pattern in the semiconductor layer in the second sub-pixel P2 can be substantially mirror-symmetrical with respect to a vertical reference line, and the position of each pattern in the semiconductor layer in the third sub-pixel P3 and the position of each pattern in the semiconductor layer in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to a vertical reference line.

[0170] As shown in Figure 8C, the display substrate may include at least a first conductive layer arranged on a substrate 10, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a first insulating layer 10A arranged on a side of the second conductive layer away from the substrate, and a semiconductor layer arranged on a side of the first insulating layer 10A away from the substrate.

[0171] In an exemplary embodiment, the first insulating layer 10A covers the second conductive layer, the first conductive layer in a region other than the second conductive layer, and the substrate 10 , and the semiconductor layer may include at least a third active layer 23 disposed on the first insulating layer 10A.

[0172] (104) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the semiconductor layer, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG9A and FIG9B , FIG9B being a cross-sectional view taken along line AA in FIG9A .

[0173] In an exemplary embodiment, the plurality of via holes of each sub-pixel in the display substrate includes at least a first via hole V1 , a second via hole V2 , a third via hole V3 , a fourth via hole V4 , a fifth via hole V5 , a sixth via hole V6 and a seventh via hole V7 .

[0174] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer 21 and the data signal line 52 on the substrate. The first via hole V1 is a via hole with a transfer structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region of the first active layer 21. The first and second insulating layers in the deep half hole are etched away, exposing the surface of the data signal line 52. This allows the via hole in the transfer structure, consisting of the two half holes, to simultaneously expose the first region of the first active layer 21 and the data signal line 52. The first via hole V1 is configured to allow a subsequently formed seventh connection electrode to be connected to the first region of the first active layer 21 and the data signal line 52 simultaneously through the via hole.

[0175] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first region of the second active layer 22 on the substrate, the first insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first region of the second active layer 22, and the second via hole V2 is configured to connect the subsequently formed eighth connecting electrode to the first region of the second active layer 22 through the via hole.

[0176] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer 22 and the third connecting electrode 13 on the substrate. The third via hole V3 is a via hole with a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the second region of the second active layer 22, while the first and second insulating layers in the deep half hole are etched away, exposing the surface of the third connecting electrode 13. This transition structure, formed by the two half holes, simultaneously exposes the second region of the second active layer 22 and the third connecting electrode 13. The third via hole V3 is configured to allow a subsequently formed fifth connecting electrode to be simultaneously connected to the second region of the second active layer 22 and the third connecting electrode 13 through the via hole.

[0177] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the compensation signal line 53 on the substrate. The fourth via V4 is a via hole with a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region of the third active layer 23. The first and second insulating layers in the deep half hole are etched away, exposing the surface of the compensation signal line 53. This transition structure, formed by the two half holes, simultaneously exposes the first region of the third active layer 23 and the compensation signal line 53. The fourth via V4 is configured to allow a subsequently formed ninth connecting electrode to be connected to both the first region of the third active layer 23 and the compensation signal line 53 through the via hole.

[0178] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 14 on the substrate. The fifth via hole V5 is a via hole with a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the second region of the third active layer 23, while the first and second insulating layers in the deep half hole are etched away, exposing the surface of the fourth connecting electrode 14. This transition structure, formed by the two half holes, simultaneously exposes the second region of the third active layer 23 and the fourth connecting electrode 14. The fifth via hole V5 is configured to allow a subsequently formed sixth connecting electrode to be simultaneously connected to the second region of the third active layer 23 and the fourth connecting electrode 14 through the via hole.

[0179] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second electrode plate 62 on the substrate, the first insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the second electrode plate 62, and the sixth via V6 is configured to connect the subsequently formed second gate electrode to the second electrode plate 62 through the via.

[0180] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first power line 51 on the substrate, the first insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first power line 51, and the seventh via hole V7 is configured to connect the subsequently formed eighth connecting electrode to the first power line 51 through the via hole.

[0181] As shown in Figure 9B, the display substrate may include at least a first conductive layer arranged on a substrate 10, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a first insulating layer 10A arranged on a side of the second conductive layer away from the substrate, a semiconductor layer arranged on a side of the first insulating layer 10A away from the substrate, and a second insulating layer 10B arranged on a side of the semiconductor layer away from the substrate.

[0182] In an exemplary embodiment, the second insulating layer 10B covers the third active layer 23 and the first insulating layer 10A exposed in the area outside the third active layer 23. The second insulating layer 10B includes at least a fifth via hole V5 of the transfer structure. The fifth via hole V5 may include at least two half holes: a shallow half hole V5-1 and a deep half hole V5-2. The second insulating layer 10B in the shallow half hole V5-1 is removed to expose the surface of the third active layer 23 in the semiconductor layer. The second insulating layer 10B and the first insulating layer 10A in the deep half hole V5-2 are removed to expose the surface of the fourth connecting electrode 14 in the second conductive layer.

[0183] In an exemplary embodiment, during the process of forming the second insulating layer pattern, a dry etching process is used to form a plurality of vias, and simultaneously, a primary conductive process is performed on the semiconductor layer exposed within the vias. During the primary conductive process, the edge portions of the semiconductor layer covered by the second insulating layer near the vias are also conductively conductive. Specifically, the primary conductively conductive semiconductor layer extends away from the vias, forming a primary conductive region 23A.

[0184] (105) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the second insulating layer, as shown in FIG10A, FIG10B, FIG10C, and FIG10D, where FIG10B is a schematic diagram of the third conductive layer in FIG10A, and FIG10C and FIG10D are cross-sectional views taken along the AA line in FIG10A.

[0185] In an exemplary embodiment, the third conductive layer of a repeating unit in the display substrate may include a scan signal line 30, and the third conductive layer of each sub-pixel in the display substrate may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a ninth connecting electrode 19, a first gate electrode 31, a second gate electrode 32 and a third gate electrode 33.

[0186] In an exemplary embodiment, the main portion of the scan signal line 30 extends along the first direction X and can be arranged in the middle of the repeating unit in the second direction Y, that is, between the first sub-pixel P1 and the second sub-pixel P2 and the third sub-pixel P3 and the fourth sub-pixel P4. The scan signal line 30 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0187] In an exemplary embodiment, the first gate electrode 31 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 30 close to the first active layer 21. A first end of the first gate electrode 31 is connected to the scan signal line 30, and a second end of the first gate electrode 31 extends toward the first active layer 21. The orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21 on the substrate. In an exemplary embodiment, the first gate electrode 31 may serve as the gate electrode of the first transistor T1, so that the scan signal line 30 can control whether the first transistor T1 is turned on or off.

[0188] In an exemplary embodiment, the second gate electrode 32 may be in the shape of a strip extending along the first direction X. A first end of the second gate electrode 32 is connected to the second electrode plate 62 via a sixth via V6, and a second end of the second gate electrode 32 extends toward the second active layer 22. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. In an exemplary embodiment, the second gate electrode 32 may serve as the gate electrode of the second transistor T2 and may control whether the second transistor T2 is turned on or off.

[0189] In an exemplary embodiment, since the second gate electrode 32 is connected to the second electrode plate 62, and the second electrode plate 62 is connected to the first region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 62 have the same potential, so that the second electrode plate 62 has the potential of the first node in the pixel driving circuit.

[0190] In an exemplary embodiment, the third gate electrode 33 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 30 close to the third active layer 23. A first end of the third gate electrode 33 is connected to the scan signal line 30, and a second end of the third gate electrode 33 extends toward the third active layer 23. The orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate. In an exemplary embodiment, the third gate electrode 33 may serve as the gate electrode of the third transistor T3, so that the scan signal line 30 can control the conduction or disconnection of the third transistor T3.

[0191] In an exemplary embodiment, in one sub-pixel, one scan signal line 30 is connected to both the first gate electrode 31 and the third gate electrode 33 , so that the scan signal line 30 can control the on / off switching of the first transistor T1 and the third transistor T3 in one sub-pixel.

[0192] In an exemplary embodiment, in one pixel row, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, so that the scan signal line 30 can control the on or off of all first transistors T1 and all third transistors T3 in one pixel row.

[0193] In an exemplary embodiment, in one repeating unit, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, so that the scan signal line 30 can simultaneously control the on or off of all first transistors T1 and all third transistors T3 in the repeating unit.

[0194] In an exemplary embodiment, the fifth connection electrode 15 may be rectangular in shape and may be disposed on a side of the second electrode plate 62 away from the scan signal line 30 . The fifth connection electrode 15 is connected to both the second region of the second active layer 22 and the third connection electrode 13 through the third via hole V3 .

[0195] In the exemplary embodiment, the fifth connection electrode 15 is connected to both the second region of the second active layer 22 and the third connection electrode 13, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first electrode plate 61. Therefore, the fifth connection electrode 15 allows the second electrode of the second transistor and the first electrode plate 61 to have the same potential. In the exemplary embodiment, the fifth connection electrode 15 is configured to be connected to a tenth connection electrode formed subsequently.

[0196] In an exemplary embodiment, the sixth connection electrode 16 may be rectangular in shape and may be disposed on a side of the second electrode plate 62 close to the scan signal line 30 . The sixth connection electrode 16 is connected to both the second region of the third active layer 23 and the fourth connection electrode 14 through a fifth via hole V5 .

[0197] In an exemplary embodiment, since the sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14 at the same time, the fourth connection electrode 14 is connected to the second connection electrode 12, and the second connection electrode 12 is connected to the first electrode plate 61, the sixth connection electrode 16 enables the second electrode and the first electrode plate 61 of the third transistor to have the same potential.

[0198] In an exemplary embodiment, the fifth connection electrode 15 and the sixth connection electrode 16 realize the connection between the second electrode of the second transistor, the second electrode of the third transistor and the first electrode plate 61, so that the fifth connection electrode 15 and the first electrode plate 61 have the potential of the second node in the pixel driving circuit.

[0199] In an exemplary embodiment, the seventh connection electrode 17 may be rectangular and may be disposed between the first gate electrode 31 and the first power line 51. The seventh connection electrode 17 is connected to both the first region of the first active layer 21 and the data signal line 52 through a first via hole V1, thereby enabling the data signal line 52 to write a data signal into the first electrode of the first transistor T1. In an exemplary embodiment, each data signal line 52 may be connected to the first region of the first active layer in a sub-pixel through the first via hole V1, thereby enabling four data signal lines 52 to write data signals into the four first transistors T1 in a repeating unit.

[0200] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. The first data signal line may be located on one side of the first power supply line 51 in the first pixel column in the first direction X and may be connected to the first region of the first active layer in the first subpixel P1. The second data signal line may be located on one side of the first data signal line in the first direction X and may be connected to the first region of the first active layer in the third subpixel P3. The third data signal line may be located on one side of the compensation signal line 53 in the first direction X and may be connected to the first region of the first active layer in the second subpixel P2. The fourth data signal line may be located on one side of the third data signal line in the first direction X and may be connected to the first region of the first active layer in the fourth subpixel P4.

[0201] In an exemplary embodiment, the shape of the eighth connection electrode 18 can be a strip shape extending along the first direction X, and can be arranged on the side of the second electrode plate 62 away from the scanning signal line 30. The first end of the eighth connection electrode 18 is connected to the first power line 51 through the seventh via V7, and the second end of the eighth connection electrode 18 is connected to the first area of ​​the second active layer 22 through the second via V2, thereby enabling the first power line 51 to write the first power signal into the first electrode of the second transistor T2.

[0202] In an exemplary embodiment, the first power line 51 in the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first sub-pixel P1 and the third sub-pixel P3. The first power line 51 in the second pixel column can simultaneously provide a first power signal to the pixel driving circuits in the second sub-pixel P2 and the fourth sub-pixel P4. Thus, the first power lines 51 in a repeating unit form a one-to-two structure. By designing the first power lines as a one-to-two structure, the display substrate of the present disclosure reduces the number of signal lines and the space occupied. The structure is simple, the layout is rational, and the layout space is fully utilized, improving space utilization and facilitating enhanced resolution and transparency.

[0203] In an exemplary embodiment, the two first power lines 51 in a repeating unit are symmetrically arranged relative to the compensation signal line 53, and the second transistor T2 of the first pixel column and the second transistor T2 of the second pixel column are symmetrically arranged relative to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the voltage drop written by the first power line to the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0204] In an exemplary embodiment, the ninth connection electrode 19 may be rectangular in shape and may be disposed between the third gate electrodes 33 of two adjacent sub-pixels in the first direction X. The ninth connection electrode 19 is connected to the first region of the third active layer 23 and the compensation signal line 53 simultaneously through the fourth via hole V4, thereby enabling the compensation signal line 53 to write the compensation signal into the first electrode of the third transistor T3.

[0205] In an exemplary embodiment, compensation signal line 53 can simultaneously provide compensation signals to the pixel driver circuit in each sub-pixel. Therefore, four pixel driver circuits in a repeating unit can share a single compensation signal line 53, i.e., the compensation signal lines 53 in a repeating unit form a one-to-four structure. By designing the display substrate of the present disclosure as a one-to-four structure, the number of signal lines is reduced, the space occupied is reduced, the structure is simple, the layout is rational, and the layout space is fully utilized, thereby improving space utilization and enhancing resolution and transparency.

[0206] In an exemplary embodiment, the compensation signal line 53 is arranged between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged with respect to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the RC delay of the compensation signal written into the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0207] In an exemplary embodiment, the position of each pattern in the third conductive layer in the first subpixel P1 and the position of each pattern in the third conductive layer in the third subpixel P3 can be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the third conductive layer in the second subpixel P2 and the position of each pattern in the third conductive layer in the fourth subpixel P4 can be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the third conductive layer in the first subpixel P1 and the position of each pattern in the third conductive layer in the second subpixel P2 can be substantially mirror-symmetrical with respect to a vertical reference line, and the position of each pattern in the third conductive layer in the third subpixel P3 and the position of each pattern in the third conductive layer in the fourth subpixel P4 can be substantially mirror-symmetrical with respect to a vertical reference line.

[0208] Figures 10C and 10D illustrate a structure in which the sixth connection electrode 16 is simultaneously connected to the second region of the third active layer 23 and the fourth connection electrode 14 through a via hole in the transfer structure. The display substrate may include at least a first conductive layer disposed on a substrate 10, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a first insulating layer 10A disposed on a side of the second conductive layer away from the substrate, a semiconductor layer disposed on a side of the first insulating layer 10A away from the substrate, a second insulating layer 10B disposed on a side of the semiconductor layer away from the substrate, and a third conductive layer disposed on a side of the second insulating layer 10B away from the substrate.

[0209] In an exemplary embodiment, the first conductive layer may include at least a second connection electrode 12 disposed on the substrate 10, and the second conductive layer may include at least a fourth connection electrode 14 disposed on the second connection electrode 12, with the fourth connection electrode 14 directly overlapping the second connection electrode 12. The first insulating layer 10A covers the fourth connection electrode 14, the exposed area of ​​the substrate 10 and the second connection electrode 12 outside the fourth connection electrode 14, and the semiconductor layer may include at least a third active layer 23 disposed on the first insulating layer 10A. The second insulating layer 10B covers the third active layer 23 and the exposed area of ​​the first insulating layer 10A outside the third active layer 23. The third conductive layer may include at least a sixth connection electrode 16 disposed on the second insulating layer 10B, and the sixth connection electrode 16 is connected to both the third active layer 23 and the fourth connection electrode 14 through a fifth via V5 of the transfer structure.

[0210] In an exemplary embodiment, during the process of forming the third conductive layer pattern, a wet etching process is first used to form the third conductive layer pattern, thereby enabling at least one connecting electrode to simultaneously connect to the second conductive layer and the semiconductor layer through the via hole of the transition structure. The fifth via hole V5 of the transition structure can include at least two half-holes: a shallow half-hole V5-1 and a deep half-hole V5-2. The second insulating layer 10B in the shallow half-hole V5-1 is removed, exposing the surface of the third active layer 23 in the semiconductor layer. The second insulating layer 10B and the first insulating layer 10A in the deep half-hole V5-2 are removed, exposing the surface of the fourth connecting electrode 14 in the second conductive layer. This allows the sixth connecting electrode 16 to simultaneously connect to the third active layer 23 and the fourth connecting electrode 14 through the shallow half-hole V5-1 and the deep half-hole V5-2. In an exemplary embodiment, a distance is provided between the end of the sixth connecting electrode 16 located in the shallow half-hole V5-1 region and the edge of the shallow half-hole V5-1, meaning that the sixth connecting electrode 16 does not fully cover the shallow half-hole V5-1, as shown in FIG. 10C .

[0211] In an exemplary embodiment, after the third conductive layer pattern is formed by a wet etching process, the second insulating layer in the area outside the third conductive layer is etched by a dry etching process using a self-alignment process with the third conductive layer as a mask. While etching away the second insulating layer, the exposed semiconductor layer is subjected to a second conductorization to form a second conductorization area 23B, as shown in FIG10D.

[0212] In an exemplary embodiment, during the second conductorization process, the edge portion of the semiconductor layer covered by the third conductive layer is also conductorized, that is, the semiconductor layer that is conductorized for the second time extends toward the area that was conductorized for the first time, forming a double conductorization area in the overlapping area of ​​the first conductorization area and the second conductorization area, thereby ensuring a reliable connection between the third conductive layer and the semiconductor layer.

[0213] (106) Forming a third insulating layer and a red color filter layer pattern. In an exemplary embodiment, forming the third insulating layer and the red color filter layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, thereby forming a third insulating layer covering the aforementioned pattern. Subsequently, applying a red color filter film, and patterning the red color filter film through a patterning process to form a red color filter layer pattern on the flat layer, as shown in FIG11A and FIG11B , where FIG11B is a schematic diagram of the red color filter layer in FIG11A .

[0214] In an exemplary embodiment, the red color film layer in one repeating unit in the display substrate may include a red filter 41 , a shielding bar 70 , a first shielding block 71 , a second shielding block 72 , a third shielding block 73 , and a fourth shielding block 74 .

[0215] In an exemplary embodiment, the red filter 41 may be rectangular in shape and may be disposed in the first sub-pixel P1 . The red filter 41 is configured to enable the first sub-pixel P1 to emit red light.

[0216] In an exemplary embodiment, the shielding strip 70 may be in the shape of a strip extending along the first direction X, and may be disposed in the middle of the repeating unit in the second direction Y, that is, between the first sub-pixel P1 and the second sub-pixel P2 and the third sub-pixel P3 and the fourth sub-pixel P4. The orthographic projection of the shielding strip 70 on the substrate at least partially overlaps with the orthographic projection of the scanning signal line 30 on the substrate to shield the scanning signal line 30.

[0217] In an exemplary embodiment, the first blocking block 71 may be shaped like a strip extending along the first direction X and may be disposed in the first sub-pixel P1. The orthographic projection of the first blocking block 71 on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 in the first sub-pixel P1 on the substrate to block the second transistor T2 in the first sub-pixel P1.

[0218] In an exemplary embodiment, the red filter 41 , the blocking strip 70 , and the first blocking block 71 may be an integrated structure connected to each other.

[0219] In an exemplary embodiment, the second blocking block 72 may be in the shape of a strip extending along the first direction X and may be disposed in the second sub-pixel P2, wherein the orthographic projection of the second blocking block 72 on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 in the second sub-pixel P2 on the substrate to block the second transistor T2 in the second sub-pixel P2.

[0220] In an exemplary embodiment, the third blocking block 73 may be shaped like a strip extending along the first direction X and may be disposed in the third sub-pixel P3. The orthographic projection of the third blocking block 73 on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 in the third sub-pixel P3 on the substrate to block the second transistor T2 in the third sub-pixel P3.

[0221] In an exemplary embodiment, the fourth blocking block 74 may be in the shape of a strip extending along the first direction X and may be disposed in the fourth sub-pixel P4. The orthographic projection of the fourth blocking block 74 on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 in the fourth sub-pixel P4 on the substrate to block the second transistor T2 in the fourth sub-pixel P4.

[0222] In an exemplary embodiment, the present disclosure uses a red color filter layer to shield the second transistors T2 of the four sub-pixels, which can improve the shielding effect and effectively ensure the electrical performance of the second transistors T2.

[0223] (107) Forming a green color filter layer pattern. In an exemplary embodiment, forming the green color filter layer pattern may include: coating a green color filter film on the substrate on which the aforementioned pattern is formed, patterning the green color filter film through a patterning process, and forming a green color filter layer pattern on the flat layer, as shown in FIG12A and FIG12B , where FIG12B is a schematic diagram of the green color filter layer in FIG12A .

[0224] In an exemplary embodiment, the green color filter layer in one repeating unit in the display substrate may include a green color filter 43 .

[0225] In an exemplary embodiment, the green filter 43 can be rectangular in shape and can be set in the fourth sub-pixel P4. A groove can be set at the corner position of the green filter 43 near the eleventh via hole V11. The green filter 43 is configured to make the fourth sub-pixel P4 emit green light.

[0226] (108) Forming a blue color filter layer pattern. In an exemplary embodiment, forming the blue color filter layer pattern may include: coating a blue color filter film on the substrate on which the aforementioned pattern is formed, patterning the blue color filter film through a patterning process, and forming the blue color filter layer pattern on the flat layer, as shown in FIG13A and FIG13B , where FIG13B is a schematic diagram of the blue color filter layer in FIG13A .

[0227] In an exemplary embodiment, the blue color filter layer in one repeating unit in the display substrate may include a blue color filter 42 .

[0228] In an exemplary embodiment, the blue filter 42 may be rectangular in shape and may be disposed in the second sub-pixel P2 . The blue filter 42 is configured to enable the second sub-pixel P2 to emit blue light.

[0229] (109) Forming a flat layer pattern. In an exemplary embodiment, forming the flat layer pattern may include: coating a flat film on the substrate on which the aforementioned pattern is formed, patterning the flat film and the third insulating film through a patterning process to form a flat layer pattern covering the color filter structure layer, wherein a plurality of via holes are provided on the flat layer, as shown in FIG. 14 .

[0230] In an exemplary embodiment, the via holes of each sub-pixel in the display substrate include at least an eleventh via hole V11 .

[0231] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 15 on the substrate, the third insulating layer and the planar layer in the eleventh via hole V11 are etched away to expose the surface of the fifth connecting electrode 15, and the eleventh via hole V11 is configured to connect the subsequently formed tenth connecting electrode to the fifth connecting electrode 15 through the via hole.

[0232] In an exemplary embodiment, this process uses one patterning process to simultaneously form vias on the third insulating layer and the planar layer, that is, the third insulating layer and the planar layer share one mask process, effectively reducing the number of patterning processes.

[0233] (110) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern on the color filter layer, as shown in FIG15A and FIG15B , where FIG15B is a schematic diagram of the fourth conductive layer in FIG15A .

[0234] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in the display substrate may include at least the tenth connection electrode 20 and the third electrode plate 63 .

[0235] In an exemplary embodiment, the third plate 63 may be rectangular, with chamfered corners. The orthographic projection of the third plate 63 on the substrate at least partially overlaps with the orthographic projection of the second plate 62 on the substrate, and may serve as a transparent upper plate of a transparent storage capacitor. The third plate 63 and the second plate 62 form a transparent second capacitor. In an exemplary embodiment, the third plate 63 also serves as the anode of the light-emitting device.

[0236] In an exemplary embodiment, the four third plates 63 (anodes) in a repeating unit are arranged in a square, with the upper left anode connected to the pixel driving circuit in the first sub-pixel P1, the upper right anode connected to the pixel driving circuit in the second sub-pixel P2, the lower left anode connected to the pixel driving circuit in the third sub-pixel P3, and the lower right anode connected to the pixel driving circuit in the fourth sub-pixel P4. In some possible implementations, the arrangement of the anodes can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0237] In an exemplary embodiment, the tenth connecting electrode 20 can be rectangular in shape and can be located on the side of the third electrode plate 63 away from the scanning signal line 30. The first end of the tenth connecting electrode 20 is connected to the third electrode plate 63, and the second end of the tenth connecting electrode 20 extends in a direction away from the scanning signal line 30 and is connected to the fifth connecting electrode 15 through the eleventh via hole V11.

[0238] In an exemplary embodiment, in at least one sub-pixel, the tenth connection electrode 20 and the third electrode plate 63 may be an integral structure connected to each other.

[0239] In an exemplary embodiment, the first conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0240] In the exemplary embodiment, the third electrode 63 is connected to the tenth connection electrode 20, the tenth connection electrode 20 is connected to the fifth connection electrode 15, the fifth connection electrode 15 is connected to the third connection electrode 13, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first electrode 61. As a result, the first electrode 61 and the third electrode 63 have the potential of the second node in the pixel driving circuit. Since the second electrode 62 has the potential of the first node in the pixel driving circuit, the first electrode 61 having the second node potential and the second electrode 62 having the first node potential form a first capacitor, and the third electrode 63 having the second node potential and the second electrode 62 having the first node potential form a second capacitor. The first capacitor and the second capacitor are connected in parallel, and the parallel structure of the first capacitor and the second capacitor constitute a complete storage capacitor.

[0241] In an exemplary embodiment, since the first electrode plate 61 and the third electrode plate 63 are made of a transparent conductive material and the second electrode plate 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0242] The present disclosure utilizes a first conductive layer of a transparent conductive material, a semiconductor layer of a transparent metal oxide, and a fourth conductive layer of a transparent conductive material to form a first capacitor and a second capacitor in a parallel structure. The first capacitor and the second capacitor in the parallel structure constitute a complete storage capacitor. On the one hand, this can effectively increase the capacitance value of the storage capacitor. On the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, thereby effectively reducing the occupied area.

[0243] In an exemplary embodiment, the position of each pattern in the fourth conductive layer in the first subpixel P1 and the position of each pattern in the fourth conductive layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the fourth conductive layer in the second subpixel P2 and the position of each pattern in the fourth conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the fourth conductive layer in the first subpixel P1 and the position of each pattern in the fourth conductive layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the position of each pattern in the fourth conductive layer in the third subpixel P3 and the position of each pattern in the fourth conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0244] (111) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition film through a patterning process to form a pixel definition layer, as shown in FIG16 .

[0245] In an exemplary embodiment, a pixel opening K is provided on the pixel definition layer of each sub-pixel in the display substrate, and the pixel definition film within the pixel opening K is removed to expose a portion of the surface of the third electrode plate 63. The orthographic projection of the pixel opening K on the substrate is within the range of the orthographic projection of the third electrode plate 63 on the substrate.

[0246] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the pixel opening K may be similar to that of the third electrode plate 63 , and in a plane perpendicular to the substrate, the cross-sectional shape of the pixel opening K may be rectangular or trapezoidal.

[0247] In exemplary embodiments, the shape of the pixel opening may include any one or more of a triangle, a rectangle, a trapezoid, a parallelogram, a pentagon, a hexagon, a circle, and an ellipse.

[0248] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels may be the same or different, and the areas of the pixel openings of the four sub-pixels may be the same or different.

[0249] In an exemplary embodiment, the shapes and areas of the pixel openings of the four sub-pixels may be different to accommodate the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product lifespan.

[0250] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0251] (112) Forming an organic light-emitting layer and a cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and the cathode pattern may include: first forming an organic light-emitting layer pattern, wherein the organic light-emitting layer is connected to the third electrode 63 through the pixel opening K. Then forming a cathode, wherein the cathode is connected to the organic light-emitting layer.

[0252] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0253] (113) Forming an encapsulation layer pattern. In an exemplary embodiment, forming an encapsulation layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first encapsulation layer. Subsequently, using an inkjet printing process to inkjet print an organic material on the first encapsulation layer, and after curing into a film, forming a second encapsulation layer. Subsequently, using an open mask to deposit a second inorganic thin film to form a third encapsulation layer, the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation layer. The first encapsulation layer and the third encapsulation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second encapsulation layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0254] In the exemplary embodiment, at this point, the preparation of the display substrate of this embodiment is completed.

[0255] Figure 17 is a schematic diagram of the structure of a driver circuit layer in another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driver circuit in a repeating unit (four sub-pixels) in a bottom-emission display substrate. As shown in Figure 17, the main structure of the driver circuit layer in the display substrate of this embodiment is substantially the same as that of the previous embodiment, except that at least one repeating unit may include a power connection line 54, which is connected to the first power line 51 to form a mesh structure for transmitting the first power signal.

[0256] In an exemplary embodiment, the structures and connection relationships of the fifth connecting electrode 15 to the ninth connecting electrode 19, the first gate electrode 31 to the third gate electrode 33, the scanning signal line 30, the first power line 51, the data signal line 52, and the compensation signal line 53 are basically the same as those in the aforementioned embodiment and are not repeated here.

[0257] In an exemplary embodiment, the third conductive layer of this embodiment may further include a power connection line 54. The power connection line 54 may be in the shape of a line extending along the first direction X and may be respectively arranged in the first pixel row and the second pixel row. The power connection line 54 is connected to the first power line 51 through a via, so that the power connection line 54 extending along the first direction X and the first power line 51 extending along the second direction Y form a mesh structure on the display substrate for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0258] Figure 18 is a schematic diagram of the color filter structure layer in another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the color filter layer within a repeating unit (four sub-pixels) of a bottom-emission display substrate. As shown in Figure 18 , the main structure of the color filter structure layer in this embodiment is substantially the same as that of the previous embodiment, with the difference being that the second transistor T2 of the second sub-pixel P2 and the fourth sub-pixel P4 is shielded by the blue color filter layer.

[0259] In an exemplary embodiment, the red color film layer may include a red filter 41, a blocking strip 70, a first blocking block 71 and a third blocking block 73, the blue color film layer may include a blue filter 42, a second blocking block 72 and a fourth blocking block 74, and the green color film layer may include a green filter 43, and the positions of the above patterns are substantially the same as those in the aforementioned embodiment.

[0260] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1 , second sub-pixel P2 , third sub-pixel P3 and fourth sub-pixel P4 ) of a repeating unit as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0261] (201) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG19 .

[0262] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate may include at least a first connection electrode 11, a second connection electrode 12, and a first electrode plate 61. The positions, shapes, and functions of the above patterns are substantially the same as those in the previous embodiment, except that, in a first pixel column, an edge of the first connection electrode 11 away from the second pixel column may be substantially flush with an edge of the first electrode plate 61 away from the second pixel column. In a second pixel column, an edge of the first connection electrode 11 away from the first pixel column may be substantially flush with an edge of the first electrode plate 61 away from the first pixel column.

[0263] (202) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer, as shown in FIG. 20A and FIG. 20B , where FIG. 20B is a schematic diagram of the second conductive layer in FIG. 20A .

[0264] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may include at least two first power lines 51, four data signal lines 52 and one compensation signal line 53, and the positions, shapes and functions of the above patterns are substantially the same as those in the previous embodiment.

[0265] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a third connecting electrode 13 and a fourth connecting electrode 14. The position, shape and function of the above patterns are basically the same as those in the aforementioned embodiment. The difference is that due to the different position of the first connecting electrode 11, the overlapping position of the third connecting electrode 13 and the first connecting electrode 11 is different.

[0266] (203) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG21A and FIG21B , where FIG21B is a schematic diagram of the semiconductor layer in FIG21A .

[0267] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode 62. The position, shape, and function of the above patterns are substantially the same as those in the aforementioned embodiment, except that the second active layer 22 in the four sub-pixels is separately provided, that is, there is no connection between the second active layer 22 of the first sub-pixel P1 and the second active layer 22 of the second sub-pixel P2, and there is no connection between the second active layer 22 of the third sub-pixel P3 and the second active layer 22 of the fourth sub-pixel P4.

[0268] (204) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the semiconductor layer, wherein a plurality of via holes are provided on the second insulating layer, as shown in FIG. 22 .

[0269] In an exemplary embodiment, the multiple via holes of each sub-pixel in the display substrate include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6 and a seventh via hole V7. The positions, shapes and functions of the above via holes are basically the same as those in the aforementioned embodiment, except that the fourth via hole V4 includes two shallow half holes and a deep hole located between the two shallow half holes, and the seventh via hole V7 is configured to connect a subsequently formed power connection line to the first power line 51 through the via hole.

[0270] In an exemplary embodiment, the fourth via hole V4 includes two shallow half holes and a deep hole located between the two shallow half holes. The second insulating layer in the two shallow half holes is etched away to expose the surface of the first area of ​​the third active layer 23 in the first pixel column and the surface of the first area of ​​the third active layer 23 in the second pixel column, respectively. The first insulating layer and the second insulating layer in the deep hole are etched away to expose the surface of the compensation signal line 53, so that the via hole of the transfer structure composed of the two shallow half holes and the one deep hole simultaneously exposes the compensation signal line 53, the first area of ​​the third active layer 23 in the first pixel column, and the first area of ​​the third active layer 23 in the second pixel column. The fourth via hole V4 is configured to allow the subsequently formed ninth connecting electrode to be simultaneously connected to the compensation signal line 53, the first area of ​​the third active layer 23 in the first pixel column, and the first area of ​​the third active layer 23 in the second pixel column through the via hole.

[0271] (205) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the second insulating layer, as shown in FIG. 23A and FIG. 23B , where FIG. 23B is a schematic diagram of the third conductive layer in FIG. 23A .

[0272] In an exemplary embodiment, the third conductive layer of a repeating unit in the display substrate may include a scanning signal line 30 and a power connection line 54, and the third conductive layer of each sub-pixel in the display substrate may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a ninth connecting electrode 19, a first gate electrode 31, a second gate electrode 32 and a third gate electrode 33. The position, shape and function of the above patterns are basically the same as those in the aforementioned embodiment, except that the eighth connecting electrode 18 and the ninth connecting electrode 19 are different.

[0273] In an exemplary embodiment, the shape of the eighth connection electrode 18 can be a strip shape extending along the second direction Y, the first end of the eighth connection electrode 18 is connected to the power connection line 54, and the second end of the eighth connection electrode 18 extends toward the second electrode plate 62 and is connected to the first area of ​​the second active layer 22 through the second via hole V2.

[0274] In an exemplary embodiment, the ninth connection electrode 19 may be rectangular in shape and may be disposed between the third gate electrodes 33 of two adjacent sub-pixels in the first direction X. The ninth connection electrode 19 is simultaneously connected to the compensation signal line 53, the first region of the third active layer 23 in the first pixel column, and the first region of the third active layer 23 in the second pixel column through the fourth via hole V4, thereby enabling the compensation signal line 53 to write the compensation signal into the first electrode of the third transistor T3.

[0275] In an exemplary embodiment, the power connection line 54 may be in the shape of a line extending along the first direction X and may be disposed in the first pixel row and the second pixel row, respectively. The power connection line 54 is connected to the first power line 51 through the seventh via hole V7. Since the power connection line 54 is connected to the eighth connection electrode 18, and the eighth connection electrode 18 is connected to the first region of the second active layer 22, the first power line 51 is enabled to write the first power signal to the first electrode of the second transistor T2.

[0276] In an exemplary embodiment, since the power connection lines 54 are connected to the display substrate, the power connection lines 54 extending along the first direction X and the first power lines 51 extending along the second direction Y form a mesh structure on the display substrate for transmitting the first power signal. This can not only effectively reduce the resistance of the first power lines and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0277] (206) Forming a third insulating layer and a red color filter layer pattern. In an exemplary embodiment, forming the third insulating layer and the red color filter layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, thereby forming a third insulating layer covering the aforementioned pattern. Subsequently, applying a red color filter film, and patterning the red color filter film through a patterning process to form a red color filter layer pattern on the flat layer, as shown in FIG. 24A and FIG. 24B , where FIG. 24B is a schematic diagram of the red color filter layer in FIG. 24A .

[0278] In an exemplary embodiment, the red color film layer in one repeating unit in the display substrate may include a red filter 41, a blocking strip 70, a first blocking block 71 and a third blocking block 73, and the positions, shapes and functions of the above patterns are substantially the same as those in the aforementioned embodiment.

[0279] (207) Forming a green color filter layer pattern. In an exemplary embodiment, forming the green color filter layer pattern may include: coating a green color filter film on the substrate on which the aforementioned pattern is formed, patterning the green color filter film through a patterning process, and forming a green color filter layer pattern on the flat layer, as shown in FIG. 25A and FIG. 25B , where FIG. 25B is a schematic diagram of the green color filter layer in FIG. 25A .

[0280] In an exemplary embodiment, the green color filter layer in one repeating unit in the display substrate may include a green filter 43 , and the position, shape, and function of the green filter 43 are substantially the same as those in the aforementioned embodiment.

[0281] (208) Forming a blue color filter layer pattern. In an exemplary embodiment, forming the blue color filter layer pattern may include: coating a blue color filter film on the substrate on which the aforementioned pattern is formed, patterning the blue color filter film through a patterning process, and forming the blue color filter layer pattern on the flat layer, as shown in FIG. 26A and FIG. 26B , where FIG. 26B is a schematic diagram of the blue color filter layer in FIG. 26A .

[0282] In an exemplary embodiment, the blue color filter layer in one repeating unit in the display substrate may include a blue color filter 42 , a second blocking block 72 , and a fourth blocking block 74 .

[0283] In the exemplary embodiment, the position, shape, and function of the blue filter 42 are substantially the same as those in the previous embodiment.

[0284] In an exemplary embodiment, the second blocking block 72 may be in the shape of a strip extending along the first direction X and may be disposed in the second sub-pixel P2, wherein the orthographic projection of the second blocking block 72 on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 in the second sub-pixel P2 on the substrate to block the second transistor T2 in the second sub-pixel P2.

[0285] In an exemplary embodiment, the blue filter 42 and the second blocking block 72 may be an integral structure connected to each other.

[0286] In an exemplary embodiment, the fourth blocking block 74 may be rectangular in shape and may be disposed in the fourth sub-pixel P4, wherein the orthographic projection of the fourth blocking block 74 on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 in the fourth sub-pixel P4 on the substrate to block the second transistor T2 in the fourth sub-pixel P4.

[0287] In an exemplary embodiment, the present disclosure uses a red color filter layer to block the second transistor T2 of the first sub-pixel P1 and the third sub-pixel P3, and uses a blue color filter layer to block the second transistor T2 of the second sub-pixel P2 and the fourth sub-pixel P4, which can improve the blocking effect and effectively ensure the electrical performance of the second transistor T2.

[0288] (209) Forming a flat layer pattern. In an exemplary embodiment, forming the flat layer pattern may include: coating a flat film on the substrate on which the aforementioned pattern is formed, patterning the flat film and the third insulating film through a patterning process to form a flat layer pattern covering the color filter structure layer, wherein a plurality of via holes are provided on the flat layer, as shown in FIG. 27 .

[0289] In an exemplary embodiment, the via holes of each sub-pixel in the display substrate include at least an eleventh via hole V11 , and the position, shape, and function of the eleventh via hole V11 are substantially the same as those in the aforementioned embodiment.

[0290] (210) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern on the color filter layer, as shown in FIG. 28A and FIG. 28B , where FIG. 28B is a schematic diagram of the fourth conductive layer in FIG. 28A .

[0291] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in the display substrate may include at least a third electrode plate 63 .

[0292] In an exemplary embodiment, the third electrode plate 63 may be rectangular, with chamfered corners. The orthographic projection of the third electrode plate 63 on the substrate at least partially overlaps the orthographic projection of the second electrode plate 62 on the substrate, and is connected to the fifth connection electrode 15 via an eleventh via hole V11. The third electrode plate 63 may serve as a transparent upper plate of a transparent storage capacitor, with the third electrode plate 63 and the second electrode plate 62 forming a transparent second capacitor. In an exemplary embodiment, the third electrode plate 63 also serves as the anode of the light-emitting device.

[0293] In an exemplary embodiment, the four third plates 63 (anodes) in a repeating unit are arranged in a square. The upper left anode is connected to the pixel driving circuit in the first subpixel P1, the upper right anode is connected to the pixel driving circuit in the second subpixel P2, the lower left anode is connected to the pixel driving circuit in the third subpixel P3, and the lower right anode is connected to the pixel driving circuit in the fourth subpixel P4. In some possible implementations, the arrangement of the anodes can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0294] In the exemplary embodiment, the third electrode 63 is connected to the fifth connection electrode 15, the fifth connection electrode 15 is connected to the third connection electrode 13, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first electrode 61. Thus, the first electrode 61 and the third electrode 63 have the potential of the second node in the pixel driving circuit. Since the second electrode 62 has the potential of the first node in the pixel driving circuit, the first electrode 61 having the second node potential and the second electrode 62 having the first node potential form a first capacitor, and the third electrode 63 having the second node potential and the second electrode 62 having the first node potential form a second capacitor. The first and second capacitors are connected in parallel, and the parallel structure of the first and second capacitors constitutes a complete storage capacitor.

[0295] In an exemplary embodiment, since the first electrode plate 61 and the third electrode plate 63 are made of a transparent conductive material and the second electrode plate 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0296] The present disclosure utilizes a first conductive layer of a transparent conductive material, a semiconductor layer of a transparent metal oxide, and a fourth conductive layer of a transparent conductive material to form a first capacitor and a second capacitor in a parallel structure. The first capacitor and the second capacitor in the parallel structure constitute a complete storage capacitor. On the one hand, this can effectively increase the capacitance value of the storage capacitor. On the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, thereby effectively reducing the occupied area.

[0297] (211) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition film through a patterning process to form a pixel definition layer, as shown in FIG. 29 .

[0298] In an exemplary embodiment, a pixel opening K is opened on the pixel definition layer of each sub-pixel in the display substrate, and the position, shape and function of the pixel opening K are substantially the same as those in the aforementioned embodiment.

[0299] In an exemplary embodiment, at least one first pixel groove F1 and at least one second pixel groove F2 are further provided on the pixel definition layer in at least one repeating unit.

[0300] In an exemplary embodiment, the first pixel groove F1 may be in the shape of a strip with a main portion extending along the first direction X (pixel row direction) and may be disposed on both sides of the repeating unit in the second direction Y (pixel column direction). The second pixel groove F2 may be in the shape of a strip with a main portion extending along the second direction Y and may be disposed in the middle of the repeating unit in the first direction X, between adjacent pixel openings K in the first direction X. In an exemplary embodiment, the first pixel groove F1 and the second pixel groove F2 are configured to interrupt the subsequently formed organic light-emitting layer, blocking the lateral propagation path of hole-type carriers, eliminating lateral leakage, and reducing lateral crosstalk between sub-pixels.

[0301] (212) The organic light-emitting layer, cathode and encapsulation layer patterns are formed, which will not be described in detail here.

[0302] In the exemplary embodiment, at this point, the preparation of the display substrate of this embodiment is completed.

[0303] The display substrate may include a driving circuit layer disposed on a substrate, a color filter structure layer disposed on a side of the driving circuit layer away from the substrate, a light-emitting structure layer disposed on a side of the color filter structure layer away from the substrate, and an encapsulation layer disposed on a side of the light-emitting structure layer away from the substrate. In a direction perpendicular to the substrate, the driving circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a flat layer disposed sequentially on the substrate. The color filter structure layer may include a red filter, a blue filter, a green filter, a shielding strip, and a plurality of shielding blocks. The light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.

[0304] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0305] In an exemplary embodiment, the second conductive layer and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, and the third insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The planar layer can be made of an organic material, such as a resin.

[0306] Currently, existing display substrates face complex production processes and high production costs. For example, the manufacturing process for the drive structure layer in one display substrate requires nine masking steps, which not only reduces production efficiency and increases production costs, but also affects product yield.

[0307] An embodiment of the present disclosure provides a display substrate with a bottom emission structure. By arranging structures such as a first power line, a data signal line, and a compensation signal line in a second conductive layer, which is located on the side of the semiconductor layer close to the substrate, and arranging structures such as a scanning signal line and gate electrodes of multiple transistors in a third conductive layer, which is located on the side of the semiconductor layer away from the substrate, not only one conductive layer is reduced, but also the patterning process of the transfer via and the patterning process of the transfer conductive layer are reduced, so that the preparation process of the driving structure layer only requires six patterning processes, reducing the number of patterning processes, effectively improving production efficiency, effectively reducing production costs, and maximizing product yield.

[0308] The pixels of the display substrate of the embodiment of the present disclosure are arranged in a square manner, which can effectively increase the aperture ratio and the area of ​​the light-transmitting region, and is more suitable for display-type displays.

[0309] The display substrate of the disclosed embodiment uses a 3T1C pixel drive circuit with one scan signal line, and one scan signal line is connected to the first transistor and the third transistor in the pixel drive circuit. By reducing the number of scan signal lines, not only can the structure of the pixel drive circuit be simplified and the occupied area of ​​the pixel drive circuit be reduced, which is conducive to achieving high-resolution display, but also the light-transmitting area of ​​the light-transmitting area can be effectively increased, improving the space ratio of the light-transmitting area, which is conducive to achieving high-transparency display. In addition, since a repeating unit only requires one scan signal line to drive, the number of its corresponding gate drive circuit (GOA) and clock signal line (CLK) can be reduced exponentially, effectively reducing the occupied area of ​​the gate drive circuit and clock signal line, which is conducive to achieving a narrow frame and improving product advantages.

[0310] The embodiment of the present disclosure displays a substrate that forms a first capacitor and a second capacitor in a sandwich structure by utilizing a first conductive layer, a semiconductor layer, and a fourth conductive layer. The first capacitor and the second capacitor in a parallel structure constitute a storage capacitor. On the one hand, this can effectively increase the capacitance value of the storage capacitor. On the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, thereby effectively reducing the occupied area of ​​the pixel driving circuit and facilitating high-resolution display.

[0311] The exemplary embodiment of the present disclosure shows that the substrate is composed of a transparent storage capacitor composed of a transparent conductive layer and a transparent semiconductor layer, so that light can be emitted through the transparent storage capacitor. Therefore, the storage capacitor can be set in the pixel opening, which can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel aperture ratio.

[0312] The exemplary embodiment of the present disclosure displays a substrate that adopts a first power line structure with a non-mesh structure, which can effectively increase the pixel aperture ratio and improve the display effect.

[0313] The exemplary embodiment of the present disclosure displays a substrate that uses first power lines and power connection lines to form a mesh structure for transmitting a first power signal. This not only effectively reduces the resistance of the first power lines and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves display uniformity, and improves display quality.

[0314] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0315] The structure and preparation process shown in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0316] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0317] An exemplary embodiment of the present disclosure further provides a method for manufacturing a display substrate, wherein the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels forming at least two pixel rows and two pixel columns, and at least one sub-pixel includes a pixel driving circuit, wherein the pixel driving circuit is respectively connected to a scan signal line, a first power line, a data signal line, and a compensation signal line, wherein the scan signal line is configured to provide a scan signal to the pixel driving circuit, the first power line is configured to provide a power signal to the pixel driving circuit, the data signal line is configured to provide a data signal to the pixel driving circuit, and the compensation signal line is configured to provide a compensation signal to the pixel driving circuit; the manufacturing method includes:

[0318] A semiconductor layer and multiple conductive layers are formed on a substrate. The first power line, data signal line and compensation signal line are arranged on a side of the semiconductor layer close to the substrate. The scan signal line is arranged on a side of the semiconductor layer away from the substrate.

[0319] In an exemplary embodiment, forming a semiconductor layer and a plurality of conductive layers on a substrate may include:

[0320] forming a first conductive layer on the substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate, wherein the second conductive layer at least includes the first power line, the data signal line, and the compensation signal line;

[0321] forming a first insulating layer covering the second conductive layer and a semiconductor layer disposed on a side of the first insulating layer away from the substrate;

[0322] A second insulating layer covering the semiconductor layer and a third conductive layer arranged on a side of the second insulating layer away from the substrate are formed, wherein the third conductive layer at least includes the scan signal line.

[0323] In an exemplary embodiment, the third conductive layer also includes a plurality of connecting electrodes, at least one connecting electrode being connected to the second conductive layer and the semiconductor layer at the same time through a via hole of a transition structure, the via hole of the transition structure including at least two half holes, the first insulating layer and the second insulating layer in one half hole are removed to expose the surface of the second conductive layer, and the second insulating layer in the other half hole is removed to expose the surface of the semiconductor layer.

[0324] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0325] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being respectively connected to a scan signal line, a first power line, a data signal line and a compensation signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit, the first power line being configured to provide a power signal to the pixel driving circuit, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; in a direction perpendicular to the display substrate, the display substrate comprises at least a semiconductor layer and a plurality of conductive layers arranged on a substrate, the first power line, the data signal line and the compensation signal line being arranged on a side of the semiconductor layer close to the substrate, and the scan signal line being arranged on a side of the semiconductor layer away from the substrate.

2. The display substrate according to claim 1, wherein: In a direction perpendicular to the display substrate, the display substrate at least includes a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a third conductive layer arranged on the base and arranged in sequence along a direction away from the base, the first power line, the data signal line and the compensation signal line are arranged in the second conductive layer, and the scanning signal line is arranged in the third conductive layer.

3. The display substrate according to claim 2, wherein: The third conductive layer also includes a plurality of connecting electrodes, at least one connecting electrode is simultaneously connected to the second conductive layer and the semiconductor layer through a via hole of a transfer structure, the via hole of the transfer structure includes at least two half holes, the first insulating layer and the second insulating layer in one half hole are removed to expose the surface of the second conductive layer, and the second insulating layer in the other half hole is removed to expose the surface of the semiconductor layer.

4. The display substrate according to claim 1, wherein: At least one repeating unit also includes a power connection line, the shape of the power connection line is a line shape extending along the direction of the pixel row, the shape of the first power line is a line shape extending along the direction of the pixel column, and the power connection line is connected to the first power line to form a mesh structure for transmitting the first power signal.

5. The display substrate according to claim 4, wherein: The power connection line and the first power line are arranged in different conductive layers, and the power connection line is connected to the first power line through a via hole.

6. The display substrate according to any one of claims 1 to 5, wherein: The pixel driving circuit at least includes a first transistor, a second transistor, a third transistor and a storage capacitor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the gate electrode of the second transistor and the first end of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is respectively connected to the second electrode of the third transistor and the second end of the storage capacitor, and the first electrode of the third transistor is connected to the compensation signal line; in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scanning signal line.

7. The display substrate according to claim 6, wherein: In the plurality of pixel driving circuits of at least one pixel row, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scanning signal line.

8. The display substrate according to claim 6, wherein: In the plurality of pixel driving circuits of at least one repeating unit, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scanning signal line.

9. The display substrate according to claim 6, wherein: The scanning signal line, the gate electrode of the first transistor, the gate electrode of the second transistor and the gate electrode of the third transistor are arranged in the same layer.

10. The display substrate according to claim 6, wherein: In at least one repetitive unit, gate electrodes of a plurality of first transistors and gate electrodes of a plurality of third transistors in adjacent pixel rows are connected to the same scanning signal line.

11. The display substrate according to claim 10, wherein: The multiple repeating units include an n-1th repeating unit row, an nth repeating unit row and an n+1th repeating unit row, where n is a positive integer greater than 1, and the nth repeating unit row includes a first pixel row and a second pixel row, the first pixel row is located on a side of the second pixel row close to the n-1th repeating unit row, and the second pixel row is located on a side of the first pixel row close to the n+1th repeating unit row; the first gate electrode and the third gate electrode included in the first pixel row in the nth repeating unit row are both located on a side of the scanning signal line close to the n-1th repeating unit row, and the first gate electrode and the third gate electrode included in the second pixel row in the nth repeating unit row are both located on a side of the scanning signal line close to the n+1th repeating unit row.

12. The display substrate according to claim 6, wherein: The first end of the storage capacitor includes a first electrode plate and a third electrode plate, and the second end of the storage capacitor includes a second electrode plate, the orthographic projection of the second electrode plate on the base at least partially overlaps with the orthographic projection of the first electrode plate on the plane of the display substrate, the first electrode plate and the second electrode plate form a first capacitor, the orthographic projection of the second electrode plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the third electrode plate on the plane of the display substrate, the third electrode plate and the second electrode plate form a second capacitor, the first electrode plate is respectively connected to the third electrode plate, the second electrode of the first transistor and the gate electrode of the second transistor, the second electrode plate is respectively connected to the second electrode of the second transistor and the second electrode of the third transistor, and the first capacitor and the second capacitor constitute a storage capacitor with a parallel structure.

13. The display substrate according to claim 12, wherein: In a direction perpendicular to the display substrate, the display substrate comprises a driving circuit layer arranged on the substrate, a color filter structure layer arranged on a side of the driving circuit layer away from the substrate, and a light emitting structure layer arranged on a side of the color filter structure layer away from the substrate, the driving circuit layer at least comprises a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer arranged in sequence along a direction away from the substrate, and the light emitting structure layer at least comprises a fourth conductive layer and a pixel definition layer arranged in sequence along a direction away from the substrate; In at least one sub-pixel, the first electrode plate is arranged in the first conductive layer, the second electrode plate is arranged in the semiconductor layer, the third electrode plate is arranged in the fourth conductive layer, and the third electrode plate is connected to the first electrode plate through a via hole.

14. The display substrate according to claim 13, wherein: The multiple sub-pixels in at least one repeating unit include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the first sub-pixel and the second sub-pixel form a first pixel row, the third sub-pixel and the fourth sub-pixel form a second pixel row, the first sub-pixel and the third sub-pixel form a first pixel column, and the second sub-pixel and the fourth sub-pixel form a second pixel column; the color film structure layer includes at least a red color film layer, a blue color film layer and a green color film layer, the red color film layer includes at least a red filter arranged in the first sub-pixel, the blue color film layer includes at least a blue filter arranged in the second sub-pixel, and the green color film layer includes at least a green filter arranged in the fourth sub-pixel.

15. The display substrate according to claim 14, wherein: The red color film layer also includes a shielding strip, a first shielding block, a second shielding block, a third shielding block and a fourth shielding block; the shielding strip's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the scanning signal line on the substrate, the first shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the first sub-pixel on the substrate, the second shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the second sub-pixel on the substrate, the third shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the third sub-pixel on the substrate, and the fourth shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the fourth sub-pixel on the substrate.

16. The display substrate according to claim 14, wherein: The red color filter layer also includes a shielding strip, a first shielding block and a third shielding block, and the blue color filter layer also includes a second shielding block and a fourth shielding block; the shielding strip's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the scanning signal line on the substrate, the first shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the first sub-pixel on the substrate, the second shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the second sub-pixel on the substrate, the third shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the third sub-pixel on the substrate, and the fourth shielding block's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second transistor in the fourth sub-pixel on the substrate.

17. The display substrate according to claim 13, wherein: In at least one sub-pixel, the fourth conductive layer includes at least the third electrode plate, and the pixel definition layer is provided with a pixel opening exposing the third electrode plate; in at least one repeating unit, the pixel definition layer is provided with at least one pixel groove, and the pixel groove includes any one or more of the following: a first pixel groove extending along the pixel row direction, and a second pixel groove extending along the pixel column direction.

18. A display device, wherein: Comprising the display substrate as claimed in any one of claims 1 to 17.

19. A method for preparing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being respectively connected to a scan signal line, a first power line, a data signal line, and a compensation signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit, the first power line being configured to provide a power signal to the pixel driving circuit, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; the preparation method comprising: A semiconductor layer and a plurality of conductive layers are formed on a substrate, the first power line, the data signal line and the compensation signal line are arranged on a side of the semiconductor layer close to the substrate, and the scanning signal line is arranged on a side of the semiconductor layer away from the substrate.

20. The display substrate according to claim 19, wherein: A semiconductor layer and a plurality of conductive layers are formed on a substrate, comprising: Forming a first conductive layer and a second conductive layer disposed on the substrate at a side of the first conductive layer away from the substrate, wherein the second conductive layer at least includes the first power line, the data signal line and the compensation signal line; forming a first insulating layer covering the second conductive layer and a semiconductor layer disposed on a side of the first insulating layer away from the substrate; A second insulating layer covering the semiconductor layer and a third conductive layer disposed on a side of the second insulating layer away from the substrate are formed, wherein the third conductive layer at least includes the scanning signal line.

21. The display substrate according to claim 20, wherein: The third conductive layer also includes a plurality of connecting electrodes, at least one connecting electrode is simultaneously connected to the second conductive layer and the semiconductor layer through a via hole of a transfer structure, the via hole of the transfer structure includes at least two half holes, the first insulating layer and the second insulating layer in one half hole are removed to expose the surface of the second conductive layer, and the second insulating layer in the other half hole is removed to expose the surface of the semiconductor layer.

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