Quantum circuit processing method and apparatus, and computer, storage medium and program product

Abstract

A quantum circuit processing method, which is executed by means of a computer device, and comprises: acquiring a quantum program to be parsed, and performing quantum circuit parsing on said quantum program, so as to obtain circuit information comprised in said quantum program, wherein the circuit information comprises N quantum circuits, and quantum gates comprised in the N quantum circuits, N being a positive integer (S301); on the basis of a gate association relationship between the quantum gates comprised in the N quantum circuits, aligning the quantum gates comprised in the N quantum circuits, so as to obtain aligned quantum gate arrangement circuit data (S302); and generating a quantum processing instruction according to the quantum gate arrangement circuit data, wherein the execution sequence of the quantum gates comprised in the N quantum circuits which is specified in the quantum processing instruction is different from the execution sequence of the quantum gates comprised in the N quantum circuits which is specified in said quantum program (S303).

Description

Quantum circuit processing method, device, computer, storage medium and program product

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 2023107153416, filed on June 15, 2023, entitled “Quantum circuit processing method, device, computer, storage medium and program product,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a quantum circuit processing method, device, computer, storage medium, and program product. Background Art

[0004] Superconducting quantum chips are currently in the noisy intermediate-scale quantum (NISQ) era, characterized by limited qubit coherence time, errors in qubit gates (limited fidelity), and systematic errors introduced by qubit measurement operations. Superconducting quantum computing is implemented using quantum circuits running on superconducting quantum chips. These circuits typically contain numerous single-qubit and two-qubit gates. This requires timing control of the quantum circuits. Currently, this is done by manually inputting numerous constraints, resulting in low quantum circuit processing efficiency and complex quantum gate processing. Furthermore, current timing control of quantum circuits restricts the rules for aligning quantum gates, resulting in limited flexibility.

[0005] Summary of the Invention

[0006] According to various embodiments of the present application, a quantum circuit processing method, apparatus, computer, storage medium, and program product are provided.

[0007] In one aspect, an embodiment of the present application provides a quantum circuit processing method, which is executed by a computer device and includes:

[0008] Obtaining a quantum program to be analyzed, performing quantum circuit analysis on the quantum program to be analyzed, and obtaining circuit information included in the quantum program to be analyzed, wherein the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer;

[0009] Aligning the quantum gates included in the N quantum circuits based on gate association relationships between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data; and

[0010] A quantum processing instruction is generated according to the quantum gate arrangement circuit data, wherein an execution order of the quantum gates included in the N quantum circuits specified in the quantum processing instruction is different from an execution order of the quantum gates included in the N quantum circuits specified in the quantum program to be analyzed.

[0011] In one aspect, an embodiment of the present application provides a quantum circuit processing device, the device comprising:

[0012] Program acquisition module, used to obtain the quantum program to be parsed;

[0013] a program analysis module, configured to perform quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed, wherein the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer;

[0014] a quantum arrangement module, configured to align the quantum gates included in the N quantum circuits based on gate association relationships between the quantum gates included in the N quantum circuits, and obtain aligned quantum gate arrangement circuit data; and

[0015] An instruction generation module is configured to generate a quantum processing instruction based on the quantum gate arrangement circuit data, wherein an execution order of the quantum gates included in the N quantum circuits specified in the quantum processing instruction is different from an execution order of the quantum gates included in the N quantum circuits specified in the quantum program to be analyzed.

[0016] In one aspect, an embodiment of the present application provides a computer device, comprising a processor and a memory, wherein the memory is configured to store computer-readable instructions, and the processor is configured to call the computer-readable instructions to execute a method according to any embodiment of the present application;

[0017] On one hand, an embodiment of the present application provides a computer-readable storage medium, which stores computer-readable instructions. The computer-readable instructions are loaded and executed by a processor to enable the processor to perform the method of any embodiment of the present application.

[0018] On one hand, an embodiment of the present application provides a computer program product, including computer-readable instructions, which implement the method of any embodiment of the present application when executed by a processor.

[0019] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0021] FIG1 is a diagram of a network interaction architecture for quantum circuit processing provided by an embodiment of the present application;

[0022] FIG2 is a schematic diagram of a quantum circuit processing scenario provided by an embodiment of the present application;

[0023] FIG3 is a flow chart of a method for quantum circuit processing provided in an embodiment of the present application;

[0024] FIG4 is a schematic diagram of a program parsing process provided by an embodiment of the present application;

[0025] FIG5 is a schematic diagram of a circuit analysis scenario provided by an embodiment of the present application;

[0026] FIG6 is a schematic diagram of a directed graph construction scenario provided in an embodiment of the present application;

[0027] FIG7 is a schematic diagram of a quantum gate arrangement according to an embodiment of the present application;

[0028] FIG8 is a second schematic diagram of a quantum gate arrangement provided in an embodiment of the present application;

[0029] FIG9 is a third schematic diagram of a quantum gate arrangement provided in an embodiment of the present application;

[0030] FIG10 is a fourth schematic diagram of a quantum gate arrangement provided in an embodiment of the present application;

[0031] FIG11 is a simplified flowchart of quantum analysis provided by an embodiment of the present application;

[0032] FIG12 is a schematic diagram of a quantum circuit processing device provided in an embodiment of the present application;

[0033] FIG13 is a schematic structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] Among them, if it is necessary to collect object (such as user, etc.) data in this application, a prompt interface or pop-up window will be displayed before or during the collection. The prompt interface or pop-up window is used to remind the user that certain data is currently being collected, such as quantum programs to be parsed, etc. Only after the user confirms the prompt interface or pop-up window, the relevant steps for data acquisition will be started, otherwise the process will end. Moreover, the acquired user data will be used in reasonable and legal scenarios or purposes. Optionally, in some scenarios where user data needs to be used but has not been authorized by the user, authorization can be requested from the user, and the user data can be used when the authorization is passed.

[0036] In an embodiment of the present application, please refer to FIG1 , which is a network interaction architecture diagram for quantum circuit processing provided by an embodiment of the present application. As shown in FIG1 , a computer device 101 can obtain a quantum program to be parsed, perform quantum circuit parsing on the quantum program to be parsed, model the quantum circuit corresponding to the quantum program to be parsed, obtain quantum gate arrangement circuit data, and implement timing control of the quantum circuit. Moreover, this process realizes independent modeling of the quantum circuit, can adapt to different quantum languages, and can improve the flexibility of timing control. The quantum gate arrangement circuit data is then converted into quantum processing instructions, which are instructions at the physical level. In this case, the quantum gates included in the N quantum circuits have a first execution sequence in the quantum processing instructions that is different from the second execution sequence in the quantum program to be parsed. This implements the timing arrangement of the quantum circuit, improves the flexibility of quantum circuit management, and improves the convenience and efficiency of quantum gate processing. Optionally, the computer device 101 can obtain the quantum program to be parsed from local storage space; or, it can obtain the quantum program to be parsed from any business device, such as business device 102a, business device 102b, or business device 102c. For example, the computer device 101 may receive a quantum analysis request sent by the business device 102a, obtain the quantum program to be analyzed carried in the quantum analysis request, perform quantum circuit analysis on the quantum program to be analyzed, and perform quantum modeling based on the analysis results and the gate association relationship between the quantum gates indicated by the quantum program to be analyzed to obtain quantum gate arrangement circuit data, convert the quantum gate arrangement circuit data into quantum processing instructions, and send the quantum processing instructions to the business device 102a, etc.

[0037] It is understood that the business device mentioned in the embodiments of the present application can also be considered as a computer device, and the computer device in the embodiments of the present application includes but is not limited to a terminal device or a server. In other words, the computer device can be a server or a terminal device, or a system consisting of a server and a terminal device. Among them, the terminal device mentioned above can be an electronic device, including but not limited to a mobile phone, a tablet computer, a desktop computer, a laptop computer, a PDA, a vehicle-mounted device, an augmented reality / virtual reality (AR / VR) device, a helmet display, a smart TV, a wearable device, a smart speaker, a digital camera, a camera and other mobile internet devices (mobile internet device, MID) with network access capability, or a terminal device in scenarios such as a train, a ship, or a flight. As shown in Figure 1, the terminal device can be a laptop computer (as shown in business device 102b), a mobile phone (as shown in business device 102c) or a business device (as shown in object device 102a), etc. Figure 1 only lists some of the devices. Optionally, the business device 102a refers to a device located in a vehicle 103. The servers mentioned above can be independent physical servers, server clusters or distributed systems composed of multiple physical servers, or cloud servers that provide basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, vehicle-road collaboration, content delivery networks (CDNs), and big data and artificial intelligence platforms. The computer devices can be the aforementioned terminal devices or servers, connected to quantum circuits or integrated with quantum circuits; alternatively, the computer devices can be quantum devices that carry quantum information, such as quantum chips.

[0038] Specifically, see Figure 2, which is a schematic diagram of a quantum circuit processing scenario provided by an embodiment of the present application. As shown in Figure 2, a computer device can obtain a quantum program 201 to be parsed, perform quantum circuit parsing on the quantum program to be parsed, and obtain circuit information included in the quantum program 201 to be parsed. This circuit information is used to represent relevant information about the quantum circuit 202 corresponding to the quantum program 201 to be parsed, such as the N quantum circuits included in the quantum circuit 202 and the quantum gates 203 included in the N quantum circuits. This circuit information is used to represent the quantum semantics of the quantum program 201 to be parsed, that is, the composition information of the quantum circuit. Furthermore, based on the gate correlation relationship between the quantum gates 203 included in the N quantum circuits, the quantum gates included in the N quantum circuits can be aligned to obtain aligned quantum gate arrangement circuit data 204. This is equivalent to independently modeling the quantum circuit 202 according to the quantum semantics of the quantum program 201 to be analyzed, so that the quantum gate arrangement circuit data 204 obtained by modeling conforms to the gate correlation relationship between the quantum gates 203 included in the N quantum circuits, and realizes the timing control of the quantum gates 203 included in the N quantum circuits, that is, quantum gate alignment. This process is equivalent to an independent module that can be compatible with different quantum languages ​​and improve the flexibility and convenience of quantum gate processing. Furthermore, the quantum gate arrangement circuit data 204 can be converted into quantum processing instructions 205. The first execution sequence of the quantum gates included in the N quantum circuits in the quantum processing instructions is different from the second execution sequence in the quantum program to be analyzed. The first execution sequence and the second execution sequence are both used to represent the execution order of the quantum gates included in the N quantum circuits, realizing seamless expansion and translation of the model, realizing timing control and implementation of the quantum circuit 202, and improving the accuracy and efficiency of quantum circuit processing.

[0039] Furthermore, the key words involved in this application are explained as follows:

[0040] Quantum Circuit: An abstract concept that represents the circuit that operates on quantum bits in a quantum computer. It includes the representation of quantum bit units, circuits (timelines), and the operations of various quantum logic gates. Finally, quantum measurements are usually required to read the results.

[0041] Quantum bit: A unit of measurement in quantum information science. Traditional computers use 0s and 1s, and quantum computers also use 0s and 1s to represent information. However, a qubit can be both 0 and 1 at the same time. This effect, called quantum superposition, is a unique property of quantum computers.

[0042] Quantum gate: The quantum gate in this application is slightly different from the conventional quantum gate. The quantum gate in this application includes quantum bit gate and quantum measurement gate. For the sake of uniformity, quantum bit gate and quantum measurement gate are collectively referred to as quantum gate.

[0043] A qubit gate is a fundamental quantum circuit in quantum computing that operates on a relatively small number of qubits. Unlike traditional logic gates, a quantum gate is reversible and can be represented using a unitary matrix, where the unitary matrix represents the Hermitian conjugate matrix as equal to its inverse. Quantum gates include, but are not limited to, Hadamard gates, quantum NOT (Pauli-X) gates, quantum rotation Y (Pauli-Y) gates, quantum rotation Z (Pauli-Z) gates, quantum swap (SWAP) gates, and controlled NOT (CNOT) gates.

[0044] A single-bit gate is a logic gate that acts on a single qubit. Single-bit gates include, but are not limited to, Hadamard gates, Pauli-X gates, Pauli-Y gates, and Pauli-Z gates, and are denoted as h-gates.

[0045] A two-qubit gate is a logic gate that operates on two qubits. This gate can include, but is not limited to, a SWAP gate and a CNOT gate, and can be denoted as a cx gate.

[0046] A multi-bit gate refers to a logic gate that operates on multiple qubits. This number can be two or more (in which case, a multi-bit gate can be considered to include a two-bit gate) or three or more. Multi-bit gates may include, but are not limited to, quantum Friedkin (CSWAP) gates, and may be referred to as CCNOT gates or CCX gates.

[0047] Quantum Language: Quantum language is a research direction in quantum computing. Its scope includes building a standard assembly instruction set based on the logic gate capabilities of quantum computers, and can continue to abstractly construct more advanced computer languages. It can even mix the fields of classical computer languages ​​to create hybrid languages.

[0048] Decoherence, also known as quantum decoherence, is the gradual loss of quantum coherence in an open quantum system over time due to quantum entanglement with the external environment. Decoherence eliminates inter-quantum interference, transforming the system's quantum behavior into classical behavior.

[0049] Optionally, the data involved in the embodiments of the present application can be stored in a computer device, or the data can be stored based on cloud storage technology or a blockchain network, etc., which is not limited here.

[0050] Further, please refer to Figure 3, which is a flow chart of a method for quantum circuit processing provided by an embodiment of the present application. As shown in Figure 3, the quantum circuit processing process includes the following steps:

[0051] Step S301: Obtain a quantum program to be analyzed, perform quantum circuit analysis on the quantum program to be analyzed, and obtain circuit information included in the quantum program to be analyzed. The circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer.

[0052] In an embodiment of the present application, a computer device can obtain a quantum program to be parsed, wherein each quantum program has its corresponding quantum language, and the grammatical rules of the quantum language are usually expressed in the form of a standard Extended Backus-Naur Form (EBNF), that is, a meta-grammar that describes a context-free method for computer programming languages ​​and formal languages.

[0053] The circuit information includes N quantum circuits and the quantum gates included in the N quantum circuits; N is a positive integer; each quantum gate is located in one or at least two quantum circuits. For example, a single-bit gate is located in one quantum circuit, a two-bit gate is located in two quantum circuits, and a multi-bit gate is located in two or more quantum circuits. Optionally, a multi-bit gate refers to a logic gate that acts on multiple quantum bits, which can be two or more (in which case, the multi-bit gate can be considered to include the two-bit gate) or three or more, and the specific definition can be based on needs.

[0054] The circuit information represents the quantum circuit information corresponding to the quantum program to be solved, including the initial time frames corresponding to the quantum gates included in the N quantum circuits in the quantum program to be solved. This information is equivalent to the circuit representation of the quantum program to be solved. The time frames are used only to indicate the processing order of the corresponding quantum gates, and do not indicate the processing duration of the corresponding quantum gates. That is, the durations between two adjacent time frames may vary. For example, the duration from time frame 1 to time frame 2 may be the same as or different from the duration from time frame 2 to time frame 3.

[0055] Specifically, a program parsing method can be referred to in FIG4 , which is a schematic diagram of a program parsing process provided by an embodiment of the present application. As shown in FIG4 , a computer device can perform lexical analysis on the quantum program to be parsed to obtain quantum keywords in the quantum program to be parsed; based on the quantum keywords, a grammatical analysis is performed on the quantum program to be parsed to obtain circuit information included in the quantum circuit to be parsed. Optionally, the above-mentioned lexical analysis can be performed by a lexical analyzer, and the grammatical analysis can be performed by a grammatical analyzer, wherein the lexical analyzer and the grammatical analyzer can be pre-built.

[0056] Optionally, the programming language type of the quantum program to be parsed can be obtained, and quantum keywords corresponding to the programming language type can be obtained, where the quantum keywords can include gate processing keywords. Optionally, the quantum keywords can also include gate definition keywords, where the gate processing keywords are used to indicate the execution of the quantum gate, and the gate definition keywords are used to initialize the quantum gate. That is to say, only the relevant code statements for indicating the execution of the quantum gate can be obtained, or on this basis, the code statements for initializing the quantum gate can also be obtained.

[0057] For example, assuming the program language type is open quantum assembly language (openQASM), quantum keywords corresponding to the open quantum assembly language type can be obtained. The quantum keywords can include gate processing keywords such as "h," "cx," and "measz." Optionally, the quantum keywords can also include gate definition keywords such as "qreg" and "creg." Furthermore, quantum code segments in the quantum program to be parsed can be identified based on the quantum keywords. The quantum code segment includes M code statements, where M is a positive integer. For example, assuming the quantum code segment is obtained:

[0058] qreg q[4]; / / indicates the definition of 4 quantum bits;

[0059] creg c[4]; / / represents the classical bit used to store measurement results;

[0060] hq[1]; / / single-bit gate in quantum circuit q1;

[0061] cx q[1],q[2]; / / Two-bit gate located in quantum circuit q1 and quantum circuit q2;

[0062] cx q[0],q[1]; / / Two-bit gate located between quantum circuit q0 and quantum circuit q1;

[0063] hq[3]; / / single-bit gate in quantum circuit q3;

[0064] hq[0]; / / single-bit gate in quantum circuit q0;

[0065] measz q[0]—>c[0]; / / Measure quantum circuit q0 and store the measurement result in c[0];

[0066] measz q[1]—>c[1]; / / Measure quantum circuit q1 and store the measurement result in c[1];

[0067] hq[2]; / / single-bit gate in quantum circuit q2;

[0068] measz q[2]—>c[2]; / / Measure quantum circuit q2 and store the measurement result in c[2];

[0069] …

[0070] Since program code is generally executed one code statement at a time, each code statement can be considered to correspond to an initial time frame. Furthermore, based on the order of the M code statements, quantum circuit analysis can be performed on the M code statements to obtain circuit information included in the quantum program to be analyzed; this circuit information is used to characterize the quantum circuit indicated by the M code statements.

[0071] Specifically, see Figure 5, which is a schematic diagram of a circuit parsing scenario provided by an embodiment of the present application. As shown in Figure 5, quantum circuit parsing is performed on a quantum program 501 to be parsed, obtaining circuit information 502 included in the quantum program to be parsed. Taking the aforementioned quantum code segment as an example, quantum circuit parsing is performed on M code statements to obtain circuit information 502 for visually representing the quantum program to be parsed.

[0072] Specifically, the code statement "qreg q[4]" can be used to determine that there are quantum circuits q0, q1, q2, and q3 in the quantum circuit. That is, taking N as 4 as an example, the quantum gates included in the N quantum circuits are determined in sequence, such as quantum gate 50a located in quantum circuit q1, quantum gate 50b located between quantum circuit q1 and quantum circuit q2, quantum gate 50c located between quantum circuit q0 and quantum circuit q1, quantum gate 50d located in quantum circuit q3, quantum gate 50e located in quantum circuit q0, quantum gate 50f located in quantum circuit q0, quantum gate 50g located in quantum circuit q1, quantum gate 50h located in quantum circuit q2, and quantum gate 50i located in quantum circuit q2, etc.

[0073] 5 as an example, the quantum gates included in the N quantum circuits include single-bit gates 5021 (such as quantum gates 50a and 50e), two-bit gates 5022 (such as quantum gates 50b and 50c), and quantum measurement gates 5023 (such as quantum gates 50f and 50g).

[0074] The above examples only illustrate some of the quantum gates shown in FIG5 . Optionally, the quantum gates included in the N quantum circuits may also include multi-bit gates located in at least three quantum circuits. The description here uses single-bit gates and two-bit gates as examples. The processing method for multi-bit gates can be found in the two-bit gate.

[0075] Among them, since the two-bit gate and the multi-bit gate are located in multiple quantum circuits at the same time, the implementation of one quantum circuit may depend on the status of other quantum circuits. In other words, the timing of the quantum gates included in the N quantum circuits cannot be directly controlled. In this case, step S302 can be executed.

[0076] Alternatively, a program parsing method may be used in which a computer device may input a quantum program to be parsed into a program parsing model for parsing, thereby determining the programming language type corresponding to the quantum program to be parsed. The program parsing model is a pre-trained model that can parse the code statements used to process quantum gates in a quantum program.

[0077] Furthermore, in the program parsing model, the code statements included in the quantum program to be parsed are detected based on the programming language type, and the quantum gate processing statements in the code statements included in the quantum program to be parsed are obtained. In other words, the quantum gate processing statements can be directly obtained. The number of quantum gate processing statements is one or at least two. When there are at least two quantum gate processing statements, the at least two quantum gate processing statements may be discontinuous in the quantum program to be parsed. In the program parsing model, quantum circuit parsing is performed on the quantum gate processing statements based on their statement order to obtain circuit information included in the quantum program to be parsed. The circuit information is used to represent the quantum circuit indicated by the quantum gate processing statement, as shown in circuit information 502 in Figure 5. Each column in circuit information 502 corresponds to a time frame, and the time frame arrangement order of the quantum gates included in the N quantum circuits in the circuit information is the same as the statement order of the quantum gate processing statements.

[0078] Further optionally, the quantum gates included in the N quantum circuits can be used as nodes, and the edges between the quantum gates included in the N quantum circuits can be determined based on the circuit information, and the nodes and the edges can be constructed into a quantum directed graph model; the quantum directed graph model is used to indicate the gate association relationship between the quantum gates included in the N quantum circuits. The quantum directed graph model can be denoted as G = (V, E), where V is used to represent the quantum gate, and E is used to represent the edges (i.e., directed edges) between the quantum gates included in the N quantum circuits, which is used to represent the gate association relationship between the quantum gates included in the N quantum circuits.

[0079] Specifically, see FIG6 , which is a schematic diagram of a directed graph construction scenario provided in an embodiment of the present application. As shown in FIG6 , assuming that circuit information 601 is obtained, for example, circuit information 601 may include a single-bit gate 6011, a two-bit gate 6012, and a quantum measurement gate 6013 in the quantum program to be analyzed. The number of any one quantum gate may be one or at least two. Optionally, circuit information 601 may also include multi-bit gates in the quantum program to be analyzed. Here, single-bit gates, two-bit gates, and quantum measurement gates are used as examples to illustrate only some possible quantum gates corresponding to the quantum program to be analyzed.

[0080] Furthermore, the quantum gates included in the N quantum circuits are used as nodes. Based on circuit information 601, the edges (i.e., directed edges) between the quantum gates included in the N quantum circuits are determined, and the nodes and edges are constructed into a quantum directed graph model 602. In FIG6 , H() is used to represent a single-bit gate, cx() is used to represent a two-bit gate, and Measz() is used to represent a quantum measurement gate. For example, H(q1) is used to represent a single-bit gate located in quantum circuit q1. The directed edges between nodes in quantum directed graph model 602 are irreversible. That is, based on the irreversible property of directed edges in quantum directed graph model 602, the gate association relationships between the quantum gates included in the N quantum circuits are represented.

[0081] Step S302 , aligning the quantum gates included in the N quantum circuits based on the gate association relationship between the quantum gates included in the N quantum circuits, and obtaining aligned quantum gate arrangement circuit data.

[0082] In an embodiment of the present application, a computer device may align quantum gates included in N quantum circuits based on a quantum directed graph model to obtain aligned quantum gate arrangement circuit data.

[0083] The gate correlation between quantum gates refers to the dependence of quantum gates on other quantum gates in a quantum circuit, which can be called a dependency relationship. For two quantum gates with a correlation relationship, if one quantum gate depends on the other, the arrangement of the quantum gate that depends on the other is affected by the arrangement of the quantum gate on which it depends. For example, the timing frame corresponding to the quantum gate that depends on the other quantum gate may be later than the timing frame corresponding to the quantum gate on which it depends. Alignment can refer to aligning quantum gates in time frames according to specific rules.

[0084] Specifically, in a first quantum gate arrangement method, a computer device can perform front partial order alignment on the quantum gates included in the N quantum circuits based on the gate correlation relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data.

[0085] Among them, the front partial order alignment refers to aligning the first quantum gate among the quantum gates included in each quantum circuit, and arranging the subsequent quantum gates included in the N quantum circuits without changing the properties of the quantum circuit, that is, without changing the gate correlation relationship between the quantum gates included in the N quantum circuits.

[0086] Specifically, the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits can be used as the first reference timing position. Based on the correlation relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to the first reference timing position to obtain the aligned quantum gate arrangement circuit data; the first quantum gate refers to the first processed quantum gate indicated by the circuit information.

[0087] Specifically, taking the circuit information 502 shown in FIG5 as an example, the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits is used as the first reference timing position. That is, the first quantum gate can be kept unchanged. As shown in FIG5 , the first quantum gate is quantum gate 50a.

[0088] Furthermore, while maintaining the gate association relationship of the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to the first reference timing position, thereby obtaining the quantum gate arrangement circuit data 701 shown in FIG. 7 . FIG. 7 is a first schematic diagram of a quantum gate arrangement provided in an embodiment of the present application.

[0089] At this time, the gate association relationship between each quantum gate in the quantum gate arrangement circuit data 701 conforms to the quantum directed graph model, and each quantum gate is aligned to the first reference timing position (i.e., time frame 701a), thereby reducing the running time of the quantum circuit. In other words, the running process of the quantum circuit can be kept under the condition of quantum bit coherence as much as possible, thereby reducing the error caused by the limited quantum bit coherence time. In other words, the error of the quantum bit gate is reduced to a certain extent, the accuracy and efficiency of quantum circuit processing are improved, and the efficiency of quantum gate processing is improved.

[0090] In the quantum gate arrangement circuit data 701 at this time, in the same quantum circuit, two adjacent quantum gates without gate correlation constraints between quantum gates are also located in adjacent time frames.

[0091] For example, in quantum circuit q0, there is no gate association constraint between the adjacent quantum gates 50e and 50f. Therefore, quantum gates 50e and 50f correspond to adjacent time frames, namely, time frame 701d and time frame 701e.

[0092] For another example, take quantum gate 50c. This quantum gate 50c is the first quantum gate in quantum circuit q0 and should be aligned to the first reference timing position (i.e., time frame 701a). However, quantum gate 50c depends on quantum gate 50b located in quantum circuits q1 and q2, and quantum gate 50b depends on quantum gate 50a, also located in quantum circuit q1. Therefore, quantum gate 50c should be located after time frame 701a of quantum gate 50a and time frame 701b of quantum gate 50b, that is, quantum gate 50c corresponds to time frame 701c, etc. Similarly, the forward partial order alignment of the quantum gates included in N quantum circuits can be achieved to obtain quantum gate arrangement circuit data.

[0093] In a second quantum gate arrangement method, a computer device can perform post-partial order alignment on the quantum gates included in the N quantum circuits based on the gate correlation relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data.

[0094] Among them, post-partial order alignment refers to aligning the last quantum gate among the quantum gates included in each quantum circuit, and arranging the subsequent quantum gates included in the N quantum circuits without changing the properties of the quantum circuit, that is, without changing the gate correlation relationship between the quantum gates included in the N quantum circuits.

[0095] Specifically, a timing position corresponding to a second quantum gate among the quantum gates included in the N quantum circuits is used as a second reference timing position, and based on the correlation relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to the second reference timing position to obtain aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0096] Specifically, taking the circuit information 502 shown in FIG5 as an example, the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits is used as the second reference timing position. That is, the second quantum gate can be kept unchanged. As shown in FIG5 , the second quantum gate is quantum gate 50i.

[0097] Furthermore, while maintaining the gate association relationship of the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to the second reference timing position, thereby obtaining the quantum gate arrangement circuit data 801 shown in FIG8 . FIG8 is a second schematic diagram of a quantum gate arrangement provided in an embodiment of the present application.

[0098] At this time, the gate association relationship between each quantum gate in the quantum gate arrangement circuit data 801 conforms to the quantum directed graph model, and each quantum gate is aligned to the second reference timing position (i.e., time frame 801e), thereby reducing the running time of the quantum circuit. In other words, the running process of the quantum circuit can be placed under the condition of quantum bit coherence as much as possible, thereby reducing the error caused by the limited quantum bit coherence time, and reducing the error of the quantum bit gate to a certain extent, thereby improving the accuracy and efficiency of quantum circuit processing, and improving the efficiency of quantum gate processing.

[0099] In the quantum gate arrangement circuit data 801 at this time, in the same quantum circuit, two adjacent quantum gates without gate association constraints between quantum gates are also located in adjacent time frames.

[0100] For example, quantum gate 50e and quantum gate 50f correspond to adjacent time frames, namely, time frame 801d and time frame 801e.

[0101] For example, consider quantum gate 50b, which is adjacent to quantum gate 50h in quantum circuit q2. Quantum gate 50b depends on quantum gate 50c, which in turn depends on quantum gate 50e. Therefore, the time frame of quantum gate 50b should precede time frame 801c of quantum gate 50c and time frame 801d of quantum gate 50e. That is, time frame 801b is not adjacent to time frame 801d of quantum gate 50h. Similarly, post-partial order alignment of the quantum gates included in N quantum circuits can be achieved to obtain quantum gate arrangement circuit data.

[0102] The gate associations between the quantum gates in the N quantum circuits can include pre-order and post-order associations. The pre-order associations indicate the quantum gates that must be executed before each quantum gate is executed; the post-order associations indicate the quantum gates that can be triggered after each quantum gate is executed. The pre-order associations can be used to implement quantum gate arrangement method 1, while the post-order associations can be used to implement quantum gate arrangement method 2.

[0103] Optionally, in a third quantum gate arrangement method, a computer device can obtain M quantum measurement gates included in N quantum circuits, where M is a positive integer, and at least a portion of the N quantum circuits includes at least one quantum measurement gate. Based on gate associations between the quantum gates included in the N quantum circuits, the M quantum measurement gates are aligned while maintaining the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits, thereby obtaining aligned quantum gate arrangement circuit data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame; the quantum bit gates are the quantum gates included in the N quantum circuits, excluding the M quantum measurement gates; and the time frame is used to represent the execution order of the quantum gates included in the N quantum circuits.

[0104] For example, a possible implementation process can be seen in Figure 9, which is a third schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. As shown in Figure 9, a computer device can align the quantum measurement gates corresponding to N quantum circuits (such as quantum measurement gate 50f in quantum circuit q0, quantum measurement gate 50g in quantum circuit q1, and quantum measurement gate 50i in quantum circuit q2) to obtain an initial measurement alignment model 901, delete the idle time frames in the N quantum circuits, and obtain quantum gate arrangement circuit data 902. In other words, the quantum bit gates included in the N quantum circuits are maintained, and the quantum measurement gates corresponding to the N quantum circuits are aligned and placed after the quantum bit gates included in the N quantum circuits to obtain quantum gate arrangement circuit data 902, so that each quantum measurement gate in quantum gate arrangement circuit data 902 is located in the same time frame. Through the above process, measurement operations can be performed on all quantum bit gates at the same time, which can reduce the systematic error introduced by quantum bit measurement and improve the accuracy of quantum circuit operation results to a certain extent.

[0105] Further optionally, in a fourth quantum gate arrangement, M quantum measurement gates included in N quantum circuits can be obtained, where M is a positive integer, and at least a portion of the N quantum circuits includes at least one quantum measurement gate. Each quantum circuit may include no quantum measurement gates or at least one quantum measurement gate. Based on gate correlations between the quantum gates included in the N quantum circuits, the M quantum measurement gates are aligned while maintaining the execution order of the qubit gates in the quantum gates included in the N quantum circuits to obtain measurement alignment data; the M quantum measurement gates in the quantum gate arrangement data are in the same time frame.

[0106] The acquisition process of the measurement alignment data can refer to the generation process of quantum gate arrangement circuit data in quantum gate arrangement mode 3. For example, the measurement alignment data obtained based on the example shown in FIG5 is the quantum gate arrangement circuit data 902 shown in FIG9 .

[0107] Furthermore, based on the gate association relationships between the quantum gates included in the N quantum circuits, the M quantum measurement gates can be kept in the same time frame in the measurement alignment data, and the qubit gates can be aligned to obtain aligned quantum gate arrangement circuit data. Specifically, referring to FIG10 , FIG10 is a fourth schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. The M quantum measurement gates can be kept in the same time frame in the measurement alignment data, and the qubit gates can be aligned in a forward partial order using the aforementioned quantum gate arrangement method 1 to obtain quantum gate arrangement circuit data 1001. Alternatively, the M quantum measurement gates can be kept in the same time frame in the measurement alignment data, and the qubit gates can be aligned in a backward partial order using the aforementioned quantum gate arrangement method 2 to obtain quantum gate arrangement circuit data 1002.

[0108] Through the above process, the time required for quantum circuit processing can be shortened, the efficiency of quantum circuit processing can be improved, quantum failure caused by quantum bit decoherence can be avoided, the accuracy of quantum circuit processing can be improved, and the precision of quantum circuit operation can be improved.

[0109] In some embodiments, a computer device may obtain the bit coherence time of quantum gates included in N quantum circuits and obtain the maximum processing time corresponding to the N quantum circuits. If the bit coherence time is less than the maximum processing time, the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits is used as the second reference timing position. Based on the correlation between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to the second reference timing position to obtain the aligned quantum gate arrangement circuit data; the second quantum gate is the last processed quantum gate indicated by the circuit information.

[0110] In some embodiments, a computer device can obtain the bit coherence time of the quantum gates included in N quantum circuits and the maximum processing time corresponding to the N quantum circuits. If the bit coherence time is less than the maximum processing time, that is, by the time the N quantum circuits are finally measured, some quantum gates may have decohered, then the quantum gates included in the N quantum circuits are aligned using any of the aforementioned quantum gate arrangement methods 1, 2, or 4 to obtain quantum gate arrangement circuit data.

[0111] Furthermore, if the bit coherence time is greater than or equal to the maximum processing time, any one of the above-mentioned quantum gate arrangement method 1, quantum gate arrangement method 2, quantum gate arrangement method 3 or quantum gate arrangement method 4 is used to align the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data.

[0112] Of course, it is optional that if the bit coherence time is less than the longest processing time, the above-mentioned quantum gate arrangement method 1 or quantum gate arrangement method 2 is used to align the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data; if the bit coherence time is greater than or equal to the longest processing time, the above-mentioned quantum gate arrangement method 3 is used to align the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data.

[0113] Alternatively, the bit coherence time of the quantum gates can be disregarded and quantum gate arrangement method 4 can be directly used to align the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data. The calling conditions of each of the above quantum gate arrangements can be updated as needed and are not limited here.

[0114] Alternatively, the computer device may obtain circuit operation data of the quantum circuit corresponding to the quantum program to be analyzed and determine a circuit optimization direction for the quantum circuit based on the circuit operation data. The circuit optimization direction may include, but is not limited to, time optimization, measurement optimization, and overall optimization.

[0115] Furthermore, the target quantum alignment method corresponding to the circuit optimization direction can be obtained. Based on the gate correlation relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned using the target quantum alignment method to obtain the aligned quantum gate arrangement circuit data.

[0116] For example, the target quantum alignment corresponding to the time optimization direction is the above-mentioned quantum gate arrangement method 1 and quantum gate arrangement method 2; the target quantum alignment corresponding to the measurement optimization direction is the above-mentioned quantum gate arrangement method 3; the target quantum alignment corresponding to the comprehensive optimization direction is the above-mentioned quantum gate arrangement method 4, etc.

[0117] Specifically, if the circuit optimization direction is time optimization, quantum gate arrangement 1 or quantum gate arrangement 2 is determined as the target quantum alignment method. Specifically, the implementation process of the target quantum alignment method can be based on the correspondence between the circuit optimization direction and the quantum gate arrangement method, as described above for quantum gate arrangements 1 through 4, and will not be repeated here. Through the above process, a quantum gate arrangement that better meets the requirements of the quantum circuit corresponding to the quantum program to be solved can be used to align the quantum program to be solved, thereby improving the accuracy of quantum circuit processing.

[0118] In some embodiments, a computer device may obtain timing control parameters, obtain a quantum gate arrangement corresponding to the timing control parameters, employ the quantum gate arrangement corresponding to the timing control parameters, execute a gate correlation relationship between the quantum gates included in the N quantum circuits, align the quantum gates included in the N quantum circuits, and obtain the aligned quantum gate arrangement circuit data.

[0119] For example, timing control options can be output, and in response to a selection operation on a target timing control option in the timing control options, the timing control parameters carried by the target timing control option can be obtained. This makes the timing control of quantum gates in the quantum program to be solved more convenient, and improves the flexibility and convenience of quantum circuit processing.

[0120] Step S303 : generating a quantum processing instruction based on the quantum gate arrangement circuit data, wherein the execution order of the quantum gates included in the N quantum circuits specified in the quantum processing instruction is different from the execution order of the quantum gates included in the N quantum circuits specified in the quantum program to be parsed.

[0121] In an embodiment of the present application, the P quantum gates included in the quantum gate arrangement circuit data and the quantum circuit corresponding to each quantum gate can be obtained; P is a positive integer. Based on the target time frames in which the P quantum gates are located in the quantum gate arrangement circuit data, and the quantum circuit corresponding to each quantum gate, quantum processing instructions for the P quantum gates are generated; the quantum gates included in the N quantum circuits have a first execution sequence in the quantum processing instruction that is different from the second execution sequence in the quantum program to be parsed. Among them, the first execution sequence refers to the execution order of the quantum gates included in the N quantum circuits in the quantum processing instruction, such as which quantum gates are executed in the same time frame, the order of different time frames, etc.; the second execution sequence refers to the execution order of the quantum gates included in the N quantum circuits in the quantum program to be parsed, thereby achieving the timing rearrangement of the quantum gates in the quantum circuit.

[0122] For example, the P quantum gates included in the quantum gate arrangement circuit data and the quantum circuit corresponding to each quantum gate can be obtained; the instruction generation language is obtained, and the instruction template corresponding to the instruction generation language is obtained. For example, the instruction generation language is eqasm, and the instruction template of the instruction generation language eqasm includes a declaration template: SMIS Sd (for declaring a single-bit gate) and SMIS Td (for declaring a two-bit gate), etc., where d is used to represent the label of the corresponding quantum gate; the instruction template may also include an execution template: H (for representing a single-bit gate), CNOT (for representing a two-bit gate), MEASZ (for representing a quantum measurement gate), and “|” (for dividing a quantum gate).

[0123] In particular, the computer device can display candidate instruction language options in response to a timing reordering operation on a quantum circuit; and in response to a selection operation on an instruction generation language from the candidate instruction language options, obtain the instruction generation language. The candidate instruction language option can refer to a language type supported by a device for executing subsequently generated quantum processing instructions. Alternatively, the computer device can obtain a preset language configured by a business object (i.e., a business person who manages the quantum circuit, etc.) and determine the preset language as the instruction generation language. Alternatively, the computer device can directly determine the default language as the instruction generation language, which refers to the language used by the computer device to generate instructions after performing timing reordering on the quantum gates in any quantum circuit.

[0124] Taking the quantum gate arrangement circuit data 1001 shown in FIG10 as an example, the above declaration template can be used to generate declaration instructions for P quantum gates and the quantum circuit corresponding to each quantum gate, and obtain quantum declaration instructions as shown below:

[0125] SMIS S0, {0} / / is used to represent the single-bit gate S0 located in the quantum circuit q0 (i.e., {0}), i.e., quantum gate 50e;

[0126] SMIS S1, {1} / / is used to represent the single-bit gate S1 located in the quantum circuit q1 (i.e., {1}), i.e., quantum gate 50a;

[0127] SMIS S2, {2} / / is used to represent the single-bit gate S2 located in the quantum circuit q2 (i.e., {2}), i.e., quantum gate 50h;

[0128] SMIS S3, {3} / / is used to represent the single-bit gate S3 located in the quantum circuit q3 (i.e., {3}), i.e., quantum gate 50d;

[0129] SMIT T1, {1, 2} / / is used to represent the two-bit gate T1 located in quantum circuit q1 and quantum circuit q2 (i.e., {1, 2}), i.e., quantum gate 50b;

[0130] SMIT T2, {0, 1} / / is used to represent the two-bit gate T2 located in the quantum circuit q0 and the quantum circuit q1 (ie, {0, 1}), ie, the quantum gate 50c.

[0131] Using the above execution template, based on the target time frames of the P quantum gates in the quantum gate arrangement circuit data 1001 and the quantum circuits corresponding to each quantum gate, quantum execution instructions for the P quantum gates are generated as follows:

[0132] 0, H S1 | H S3 / / is used to indicate that in the starting time frame (assuming it is time frame 1), single-bit gate S1 and single-bit gate S3 are executed. 0 is used to indicate that a new time frame is not started.

[0133] 1, CNOT T1 / / is used to indicate that a new time frame (recorded as time frame 2) is started based on the previous time frame, and the two-bit gate T1 is executed. 1 is used to indicate the start of a new time frame;

[0134] 1, CNOT T2|H S2 / / is used to indicate that a new time frame (recorded as time frame 3) is started based on the previous time frame, and the two-bit gate T2 and the single-bit gate S2 are executed;

[0135] 1, H S0 / / is used to indicate that a new time frame (recorded as time frame 4) is started based on the previous time frame and the single-bit gate S0 is executed;

[0136] 1, MEASZ S0|MEASZ S1|MEASZ S2 / / is used to indicate the measurement processing of quantum circuit q0, quantum circuit q1 and quantum circuit q2.

[0137] Furthermore, the quantum declaration instruction and the quantum execution instruction are combined to form a quantum processing instruction for P quantum gates. Optionally, a wait instruction, such as QWAIT 10000, can be inserted between the quantum declaration instruction and the quantum execution instruction to generate a quantum processing instruction for P quantum gates.

[0138] Furthermore, quantum processing instructions can be executed to measure and process the quantum program to be analyzed, thereby obtaining the quantum information of the quantum corresponding to the quantum program to be analyzed. Specifically, the quantum processing instructions are still instructions for the aforementioned quantum circuit, but are processed after the quantum gates in the quantum circuit are reordered. The connection method between the quantum gates in the quantum circuit itself remains unchanged. In other words, it can be considered that the computer device executes the quantum processing instructions on the quantum circuit to achieve measurement processing of the quantum program to be analyzed. Specifically, the quantum gates included in the quantum circuit (i.e., the quantum gates included in the N quantum circuits) are measured and processed to obtain the quantum information of the quantum corresponding to the quantum program to be analyzed. Among them, this quantum information is used to represent the physical state and quantum properties of the quantum.

[0139] Furthermore, quantum applications can be developed based on quantum information. For example, in quantum communication scenarios, encryption parameters can be obtained based on quantum information and the measurement results of the quantum program to be analyzed. The encryption parameters are used to encrypt the communication data, obtain encrypted data, and transmit the encrypted data.

[0140] This method utilizes the non-replicability of quantum and the randomness of measurement to generate quantum cryptography (i.e., encryption parameters) to encrypt communication data. Of course, as quantum research advances, the quantum information obtained in this application can also be applied to other scenarios, which will not be described in detail here.

[0141] The quantum circuit can be integrated into a computer device or a target service device (in which case the computer device can send quantum processing instructions to the target service device). The target service device can be the aforementioned service device with an integrated quantum circuit. The device containing the quantum circuit can be referred to as a quantum management device. When the quantum management device includes quantum processing instructions, it can execute the quantum processing instructions and perform measurement processing on the quantum circuit.

[0142] Optionally, the quantum management device can respond to a quantum measurement request for a quantum circuit by invoking a quantum processing instruction, executing the quantum processing instruction, and performing measurement processing on the quantum circuit. Alternatively, upon receiving a quantum processing instruction, the quantum management device can execute the quantum processing instruction and perform measurement processing on the quantum circuit. For example, if the quantum management device is a computer device, this occurs when the computer device generates the quantum processing instruction, or if the quantum management device is a target service device, this occurs when the target service device receives the quantum processing instruction. Alternatively, the quantum processing instruction can be added to the code location of the quantum program to be parsed, thereby annotating the quantum program to be parsed. This is equivalent to replacing the quantum program to be parsed with the quantum processing instruction. In this case, the quantum processing instruction can be directly triggered using the triggering method of the quantum program to be parsed. Annotation processing refers to changing the quantum program to be parsed from an executable state to a non-executable state.

[0143] Specifically, the above process can be simply summarized as shown in FIG11 , which is a simplified flowchart of quantum analysis provided by an embodiment of the present application. As shown in FIG11 , the process may include the following steps:

[0144] Step S1101: perform quantum circuit analysis.

[0145] In the embodiment of the present application, referring to the relevant description in step S301 of FIG. 3 , quantum circuit analysis is performed on the quantum program to be analyzed to obtain circuit information.

[0146] Step S1102: Establish a directed graph model.

[0147] In the embodiment of the present application, reference may be made to the relevant description in step S301 of FIG. 3 above to construct a directed graph model based on circuit information.

[0148] Step S1103: Acquire timing control parameters.

[0149] In the embodiment of the present application, the timing control parameters may be obtained by referring to the relevant description in step S302 of FIG. 3 to determine the quantum gate arrangement for timing rearrangement of the quantum program to be analyzed.

[0150] Step S1104: re-arrange the circuit information.

[0151] In the embodiment of the present application, referring to the relevant description in step S302 of FIG. 3 , the quantum gate arrangement method obtained in step S1103 is used to perform time sequence rearrangement on the circuit information to generate quantum gate arrangement circuit data.

[0152] Step S1105: Generate quantum processing instructions.

[0153] In the embodiment of the present application, reference may be made to the relevant description in step S303 of FIG3 above, which will not be repeated here.

[0154] In an embodiment of the present application, a quantum program to be analyzed is obtained, and quantum circuit analysis is performed on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer; based on gate association relationships between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to obtain aligned quantum gate arrangement circuit data; and quantum processing instructions are generated based on the quantum gate arrangement circuit data.

[0155] Through the above process, the quantum circuit can be directly parsed, that is, the quantum program to be parsed corresponding to the quantum circuit, making it possible to automatically analyze the quantum circuit. Based on the obtained quantum circuit, the individual quantum gates are aligned and the timing of the quantum gates is controlled to suppress the noise caused by quantum characteristics and improve the accuracy of quantum computing results. Moreover, based on the semantics of the input quantum program to be parsed (i.e., circuit information), the gate relationships of the quantum gates are independently modeled, improving the efficiency and accuracy of quantum circuit processing and enhancing the convenience and flexibility of quantum gate processing.

[0156] Further, please refer to Figure 12, which is a schematic diagram of a quantum circuit processing device provided in an embodiment of the present application. The quantum circuit processing device can be a computer program (including program code, etc.) running on a computer device. For example, the quantum circuit processing device can be an application software; the device can be used to execute the corresponding steps of the method provided in the embodiment of the present application. As shown in Figure 12, the quantum circuit processing device 1200 can be used in the computer device in the embodiment corresponding to Figure 3. Specifically, the device can include: a program acquisition module 11, a program parsing module 12, a quantum arrangement module 13, and an instruction generation module 14.

[0157] A program acquisition module 11 is used to acquire the quantum program to be parsed;

[0158] A program analysis module 12 is configured to perform quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed, where the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer.

[0159] A quantum arrangement module 13 is configured to align the quantum gates included in the N quantum circuits based on gate association relationships between the quantum gates included in the N quantum circuits, and obtain aligned quantum gate arrangement circuit data;

[0160] The instruction generation module 14 is configured to generate a quantum processing instruction based on the quantum gate arrangement circuit data, wherein the execution order of the quantum gates included in the N quantum circuits specified in the quantum processing instruction is different from the execution order of the quantum gates included in the N quantum circuits specified in the quantum program to be analyzed.

[0161] The program parsing module 12 includes:

[0162] A language parsing unit 12a is used to obtain the programming language type of the quantum program to be parsed;

[0163] A key acquisition unit 12b is used to obtain quantum keywords corresponding to the programming language type;

[0164] A code recognition unit 12c is used to identify a quantum code segment in the quantum program to be parsed based on quantum keywords, where the quantum code segment includes M code statements, where M is a positive integer;

[0165] The circuit analysis unit 12d is configured to perform quantum circuit analysis on the M code statements based on the statement order of the M code statements to obtain circuit information included in the quantum program to be analyzed, where the circuit information is used to characterize the quantum circuit indicated by the M code statements.

[0166] The program parsing module 12 includes:

[0167] A model parsing unit 12e is used to input the quantum program to be parsed into the program parsing model for parsing, and determine the programming language type corresponding to the quantum program to be parsed;

[0168] A statement detection unit 12f is used to detect the code statements included in the quantum program to be parsed based on the program language type in the program parsing model, and obtain the quantum gate processing statements in the code statements included in the quantum program to be parsed;

[0169] The information acquisition unit 12g is configured to perform quantum circuit analysis on the quantum gate processing statements based on the statement sequence of the quantum gate processing statements to obtain circuit information included in the quantum program to be analyzed. The circuit information is used to characterize the quantum circuit indicated by the quantum gate processing statements.

[0170] The device 1200 further includes:

[0171] A directed construction module 15 is configured to use the quantum gates included in the N quantum circuits as nodes, determine the edges between the quantum gates included in the N quantum circuits based on the circuit information, and construct the nodes and edges into a quantum directed graph model; the quantum directed graph model is configured to indicate the gate association relationship between the quantum gates included in the N quantum circuits;

[0172] The quantum arrangement module 13 is specifically configured to align the quantum gates included in the N quantum circuits based on a quantum directed graph model to obtain aligned quantum gate arrangement circuit data.

[0173] In some embodiments, the quantum arrangement module 13 includes:

[0174] The first arrangement unit 13a is configured to use the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits as a first reference timing position, and based on the correlation relationship between the quantum gates included in the N quantum circuits, align the quantum gates included in the N quantum circuits to the first reference timing position to obtain aligned quantum gate arrangement circuit data; the first quantum gate refers to the first processed quantum gate indicated by the circuit information.

[0175] In some embodiments, the quantum arrangement module 13 includes: a second arrangement unit 13b, which is used to use the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, and based on the correlation relationship between the quantum gates included in the N quantum circuits, align the quantum gates included in the N quantum circuits to the second reference timing position to obtain aligned quantum gate arrangement circuit data, where the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0176] The quantum arrangement module 13 includes a coherence analysis unit 13c for obtaining the bit coherence time of the quantum gates included in the N quantum circuits and obtaining the longest processing time corresponding to the N quantum circuits.

[0177] The second arrangement unit 13b is further configured to, if the bit coherence time is less than the longest processing time, use the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, and align the quantum gates included in the N quantum circuits to the second reference timing position based on the correlation relationship between the quantum gates included in the N quantum circuits, to obtain aligned quantum gate arrangement circuit data, where the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0178] In some embodiments, the quantum arrangement module 13 includes:

[0179] The measurement acquisition unit 13d is configured to acquire M quantum measurement gates included in the N quantum circuits, where M is a positive integer and at least a portion of the N quantum circuits includes at least one quantum measurement gate.

[0180] The third arrangement unit 13e is used to maintain the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits based on the gate association relationship between the quantum gates included in the N quantum circuits, align the M quantum measurement gates, and obtain aligned quantum gate arrangement circuit data. The M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame. The quantum bit gate refers to the quantum gate included in the N quantum circuits, excluding the M quantum measurement gates. The time frame is used to represent the execution order of the quantum gates included in the N quantum circuits.

[0181] In some embodiments, the quantum arrangement module 13 includes:

[0182] The measurement acquisition unit 13d is further configured to acquire M quantum measurement gates included in the N quantum circuits, where M is a positive integer and at least a portion of the N quantum circuits includes at least one quantum measurement gate.

[0183] An initial arrangement unit 13f is configured to maintain the execution order of the qubit gates in the quantum gates included in the N quantum circuits based on the gate association relationship between the quantum gates included in the N quantum circuits, align the M quantum measurement gates, and obtain measurement alignment data, wherein the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame;

[0184] The fourth arrangement unit 13g is used to keep the M quantum measurement gates in the same time frame in the measurement alignment data based on the gate association relationship between the quantum gates included in the N quantum circuits, align the quantum bit gates, and obtain the aligned quantum gate arrangement circuit data.

[0185] In some embodiments, the quantum arrangement module 13 includes:

[0186] The optimization determination unit 13h is used to obtain circuit operation data of the quantum circuit corresponding to the quantum program to be analyzed, and determine the circuit optimization direction of the quantum circuit based on the circuit operation data.

[0187] The gate arrangement unit 13i is used to obtain the target quantum alignment method corresponding to the circuit optimization direction. Based on the gate association relationship between the quantum gates included in the N quantum circuits, the target quantum alignment method is used to align the quantum gates included in the N quantum circuits to obtain the aligned quantum gate arrangement circuit data.

[0188] In some embodiments, the instruction generation module 14 includes:

[0189] The gate analysis unit 14a is used to obtain P quantum gates included in the quantum gate arrangement circuit data, and the quantum circuit corresponding to each quantum gate; P is a positive integer.

[0190] The instruction generation unit 14b is used to generate quantum processing instructions for the P quantum gates based on the target time frames of the P quantum gates in the quantum gate arrangement circuit data and the quantum circuit corresponding to each quantum gate.

[0191] In some embodiments, the apparatus 1200 further includes:

[0192] The instruction execution module 16 is used to execute quantum processing instructions, measure and process the quantum program to be analyzed, and obtain the quantum information corresponding to the quantum program to be analyzed;

[0193] The quantum application module 17 is used to perform quantum applications based on quantum information.

[0194] The embodiment of the present application provides a quantum circuit processing device that can obtain a quantum program to be analyzed, perform quantum circuit analysis on the quantum program to be analyzed, and obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and the quantum gates included in the N quantum circuits; N is a positive integer; based on the gate correlation relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to obtain the aligned quantum gate arrangement circuit data; based on the quantum gate arrangement circuit data, quantum processing instructions are generated. Through the above process, the quantum circuit can be directly analyzed, that is, the quantum program to be analyzed corresponding to the quantum circuit, so that the automatic analysis of the quantum circuit can be achieved. Moreover, based on the obtained quantum circuit, the alignment of each quantum gate is achieved, and the timing control of the quantum gate is achieved to suppress the noise influence caused by the characteristics of quantum and improve the accuracy of quantum computing results. Moreover, according to the semantics of the input quantum program to be analyzed (i.e., circuit information), the gate correlation relationship of the quantum gate is independently modeled, thereby improving the efficiency and accuracy of quantum circuit processing and improving the convenience and flexibility of quantum gate processing.

[0195] Referring to Figure 13, Figure 13 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. As shown in Figure 13, the computer device in the embodiment of the present application may include: one or more processors 1301, a memory 1302, and an input / output interface 1303. The processor 1301, the memory 1302, and the input / output interface 1303 are connected via a bus 1304. The memory 1302 is used to store a computer program, which includes computer-readable instructions. The input / output interface 1303 is used to receive and output data, such as for data exchange between a computer device and a business device, or for data exchange between a computer device and a quantum device; the processor 1301 is used to execute the program instructions stored in the memory 1302.

[0196] The processor 1301 can at least perform the following operations: obtaining a quantum program to be analyzed, performing quantum circuit analysis on the quantum program to be analyzed, and obtaining circuit information included in the quantum program to be analyzed, where the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer; aligning the quantum gates included in the N quantum circuits based on gate association relationships between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data; and generating a quantum processing instruction based on the quantum gate arrangement circuit data, where an execution order of the quantum gates included in the N quantum circuits specified in the quantum processing instruction is different from an execution order of the quantum gates included in the N quantum circuits specified in the quantum program to be analyzed.

[0197] In some feasible implementations, the processor 1301 may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc.

[0198] The memory 1302 may include a read-only memory and a random access memory, and provides instructions and data to the processor 901 and the input / output interface 1303. A portion of the memory 1302 may also include a non-volatile random access memory. For example, the memory 1302 may also store device type information.

[0199] In a specific implementation, the computer device can execute the implementation methods provided by the various steps in Figure 3 through its built-in functional modules. For details, please refer to the implementation methods provided by the various steps in Figure 3, which will not be repeated here.

[0200] The embodiment of the present application provides a computer device, including: a processor, an input / output interface, and a memory. The processor obtains computer-readable instructions in the memory, executes the various steps of the method shown in FIG3, and performs quantum circuit processing operations. The embodiment of the present application realizes obtaining a quantum program to be analyzed, performing quantum circuit analysis on the quantum program to be analyzed, obtaining circuit information included in the quantum program to be analyzed, the circuit information including N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer; based on the gate association relationship between the quantum gates included in the N quantum circuits, aligning the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data; and generating quantum processing instructions based on the quantum gate arrangement circuit data, wherein the execution order of the quantum gates included in the N quantum circuits specified in the quantum processing instruction is different from the execution order of the quantum gates included in the N quantum circuits specified in the quantum program to be analyzed. Through the above process, the quantum circuit can be directly parsed, that is, the quantum program to be parsed corresponding to the quantum circuit, making it possible to automatically analyze the quantum circuit. Based on the obtained quantum circuit, the individual quantum gates are aligned and the timing of the quantum gates is controlled to suppress the noise caused by quantum characteristics and improve the accuracy of quantum computing results. Moreover, based on the semantics of the input quantum program to be parsed (i.e., circuit information), the gate relationships of the quantum gates are independently modeled, improving the efficiency and accuracy of quantum circuit processing and enhancing the convenience and flexibility of quantum gate processing.

[0201] The embodiment of the present application also provides a computer-readable storage medium, which stores computer-readable instructions, and the computer-readable instructions are suitable for being loaded by the processor and executing the quantum circuit processing method provided by each step in Figure 3. For details, please refer to the implementation methods provided by each step in Figure 3, which will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the computer-readable storage medium embodiment involved in this application, please refer to the description of the method embodiment of this application. As an example, the computer-readable instructions can be deployed to be executed on one computer device, or on multiple computer devices located at one location, or on multiple computer devices distributed at multiple locations and interconnected by a communication network.

[0202] The computer-readable storage medium can be the quantum circuit processing device provided in any of the aforementioned embodiments or the internal storage unit of the computer device, such as the hard disk or memory of the computer device. The computer-readable storage medium can also be an external storage device of the computer device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped with the computer device. Furthermore, the computer-readable storage medium can also include both the internal storage unit of the computer device and an external storage device. The computer-readable storage medium is used to store the computer-readable instructions and other programs and data required by the computer device. The computer-readable storage medium can also be used to temporarily store data that has been output or is about to be output.

[0203] The embodiment of the present application also provides a computer program product, which includes computer-readable instructions, which are stored in a computer-readable storage medium. The processor of the computer device reads the computer-readable instructions from the computer-readable storage medium, and the processor executes the computer-readable instructions, so that the computer device executes the method provided in the various optional methods in Figure 3, and directly analyzes the quantum circuit, that is, the quantum program to be analyzed corresponding to the quantum circuit, so that the automatic analysis of the quantum circuit can be achieved, and based on the obtained quantum circuit, the alignment of each quantum gate is achieved, and the timing control of the quantum gate is achieved to suppress the noise effect caused by the characteristics of quantum and improve the accuracy of the quantum computing results. Moreover, according to the semantics of the input quantum program to be analyzed (i.e., circuit information), the gate correlation relationship of the quantum gate is independently modeled, thereby improving the efficiency and accuracy of quantum circuit processing and improving the convenience and flexibility of quantum gate processing.

[0204] The terms "first", "second", etc. in the description, claims, and drawings of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or device comprising a series of steps or units is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other step units inherent to these processes, methods, apparatuses, products, or devices.

[0205] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in this description according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0206] The methods and related devices provided in the embodiments of the present application are described with reference to the method flow charts and / or structural diagrams provided in the embodiments of the present application. Specifically, each process and / or block in the method flow charts and / or structural diagrams, as well as combinations of processes and / or blocks in the flow charts and / or structural diagrams, can be implemented by computer-readable instructions. These computer-readable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable quantum circuit processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable quantum circuit processing device produce a device for implementing the functions specified in one or more processes in the flow charts and / or one or more blocks in the structural diagrams. These computer-readable instructions can also be stored in a computer-readable memory capable of directing the computer or other programmable quantum circuit processing device to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device that implements the functions specified in one or more processes in the flow charts and / or one or more blocks in the structural diagrams. These computer-readable instructions can also be loaded onto a computer or other programmable quantum circuit processing device, so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the structural diagram.

[0207] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0208] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A quantum circuit processing method, executed by a computer device, comprising: Acquire a quantum program to be analyzed, perform quantum circuit analysis on the quantum program to be analyzed, and obtain circuit information included in the quantum program to be analyzed, wherein the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer; Based on the gate association relationship between the quantum gates included in the N quantum circuits, align the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data; and A quantum processing instruction is generated according to the quantum gate arrangement circuit data, wherein the execution order of the quantum gates included in the N quantum circuits specified by the quantum processing instruction is different from the execution order specified by the quantum program to be analyzed.

2. The method according to claim 1, wherein the step of performing quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed comprises: Obtaining a program language type of the quantum program to be parsed, and obtaining a quantum keyword corresponding to the program language type; Identify a quantum code segment in the quantum program to be parsed based on the quantum keyword, wherein the quantum code segment includes M code statements, where M is a positive integer; Based on the statement order of the M code statements, the M code statements are subjected to quantum circuit analysis to obtain circuit information included in the quantum program to be analyzed, wherein the circuit information is used to characterize the quantum circuit indicated by the M code statements.

3. The method according to claim 1, wherein the step of performing quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed comprises: Inputting the quantum program to be parsed into a program parsing model for parsing, and determining a program language type corresponding to the quantum program to be parsed; In the program parsing model, code statements included in the quantum program to be parsed are detected based on the program language type to obtain quantum gate processing statements in the code statements included in the quantum program to be parsed; Based on the statement sequence of the quantum gate processing statements, the quantum gate processing statements are subjected to quantum circuit analysis to obtain circuit information included in the quantum program to be analyzed, wherein the circuit information is used to characterize the quantum circuit indicated by the quantum gate processing statements.

4. The method according to any one of claims 1 to 3, further comprising: Taking the quantum gates included in the N quantum circuits as nodes, determining the edges between the quantum gates included in the N quantum circuits based on the circuit information, and constructing the nodes and the edges into a quantum directed graph model, wherein the quantum directed graph model is used to indicate the gate association relationship between the quantum gates included in the N quantum circuits; The step of aligning the quantum gates included in the N quantum circuits based on the gate association relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data includes: Based on the quantum directed graph model, the quantum gates included in the N quantum circuits are aligned to obtain aligned quantum gate arrangement circuit data.

5. The method according to any one of claims 1 to 3, wherein the quantum gates included in the N quantum circuits are aligned based on the gate association relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, comprising: Taking the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits as the first reference timing position, based on the association relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to the first reference timing position to obtain aligned quantum gate arrangement circuit data, wherein the first quantum gate refers to the first processed quantum gate indicated by the circuit information.

6. The method according to any one of claims 1 to 3, wherein the quantum gates included in the N quantum circuits are aligned based on the gate association relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, comprising: Taking the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, based on the association relationship between the quantum gates included in the N quantum circuits, aligning the quantum gates included in the N quantum circuits to the second reference timing position to obtain aligned quantum gate arrangement circuit data, wherein the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

7. The method according to any one of claims 1 to 3, wherein the quantum gates included in the N quantum circuits are aligned based on the gate association relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, comprising: Obtaining bit coherence times of quantum gates included in the N quantum circuits, and obtaining the longest processing time corresponding to the N quantum circuits; If the bit coherence time is less than the longest processing time, the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits is used as the second reference timing position, and based on the association relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned to the second reference timing position to obtain aligned quantum gate arrangement circuit data, where the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

8. The method according to any one of claims 1 to 3, wherein the quantum gates included in the N quantum circuits are aligned based on the gate association relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, comprising: Acquire M quantum measurement gates included in the N quantum circuits, where M is a positive integer, and at least a portion of the N quantum circuits includes at least one quantum measurement gate; Based on the gate association relationship between the quantum gates included in the N quantum circuits, the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits is maintained, and the M quantum measurement gates are aligned to obtain aligned quantum gate arrangement circuit data, wherein the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame, the quantum bit gate refers to the quantum gate included in the N quantum circuits, except the M quantum measurement gates, and the time frame is used to represent the execution order of the quantum gates included in the N quantum circuits.

9. The method according to any one of claims 1 to 3, wherein the quantum gates included in the N quantum circuits are aligned based on the gate association relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, comprising: Acquire M quantum measurement gates included in the N quantum circuits, where M is a positive integer, and at least a portion of the N quantum circuits includes at least one quantum measurement gate; Based on the gate association relationship between the quantum gates included in the N quantum circuits, the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits is maintained, and the M quantum measurement gates are aligned to obtain measurement alignment data, and the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame; Based on the gate association relationship between the quantum gates included in the N quantum circuits, the M quantum measurement gates are kept in the same time frame in the measurement alignment data, the quantum bit gates are aligned, and the aligned quantum gate arrangement circuit data is obtained.

10. The method according to claim 1, wherein the quantum gates included in the N quantum circuits are aligned based on the gate association relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, comprising: Acquiring circuit operation data of a quantum circuit corresponding to the quantum program to be analyzed, and determining a circuit optimization direction of the quantum circuit based on the circuit operation data; A target quantum alignment method corresponding to the circuit optimization direction is obtained, and based on the gate association relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are aligned using the target quantum alignment method to obtain aligned quantum gate arrangement circuit data.

11. The method according to any one of claims 1 to 10, wherein generating a quantum processing instruction according to the quantum gate arrangement circuit data comprises: Obtaining P quantum gates included in the quantum gate arrangement circuit data, and a quantum circuit corresponding to each quantum gate, where P is a positive integer; Based on the target time frames where the P quantum gates are located in the quantum gate arrangement circuit data, and the quantum circuit corresponding to each quantum gate, quantum processing instructions for the P quantum gates are generated.

12. The method according to any one of claims 1 to 11, further comprising: Executing the quantum processing instruction, measuring and processing the quantum program to be analyzed, and obtaining quantum information of the quantum corresponding to the quantum program to be analyzed; Perform quantum applications based on the quantum information.

13. A quantum circuit processing device, comprising: A program acquisition module is used to obtain the quantum program to be parsed; A program analysis module, used to perform quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed, wherein the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits, where N is a positive integer; A quantum arrangement module, configured to align the quantum gates included in the N quantum circuits based on the gate association relationship between the quantum gates included in the N quantum circuits, and obtain aligned quantum gate arrangement circuit data; and An instruction generation module is used to generate a quantum processing instruction according to the quantum gate arrangement circuit data, wherein the execution order of the quantum gates included in the N quantum circuits specified in the quantum processing instruction is different from the execution order of the quantum gates included in the N quantum circuits specified in the quantum program to be analyzed.

14. A computer device comprising a processor and a memory, wherein the memory is used to store computer-readable instructions, and the processor is used to call the computer-readable instructions to execute the method according to any one of claims 1 to 12.

15. A computer-readable storage medium storing computer-readable instructions, wherein the computer-readable instructions are loaded and executed by a processor, so that the processor executes the method according to any one of claims 1 to 12.

16. A computer program product, comprising computer readable instructions, wherein when the computer readable instructions are executed by a processor, the method according to any one of claims 1 to 12 is implemented.

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