Semiconductor device

Abstract

The present invention realizes a semiconductor device 1 having a high degree of freedom in in terms of designing the width of a channel region 5 and the width of a JFET region 8 in a trench MOSFET having a vertical-channel fin structure.　The semiconductor device 1 is a trench MOSFET having a vertical-channel fin structure, wherein: width-direction end portions of the bottom surfaces of a plurality of trenches 2 are disposed in a body region 9; the channel region 5 is connected to the body region 9, and a channel current flows in the vertical direction in the channel region 5; the JFET region 8 has a first JFET region 8A and a second JFET region 8B disposed closer to the channel region 5 than the first JFET region 8A; and the width of the second JFET region 8B is greater than the width of the first JFET region 8A.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] As one type of trench MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] 17 is a perspective view for explaining the structure of a conventional trench MOSFET with a vertical channel fin structure, in which the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are not shown.

[0004] 17 shows a conventional semiconductor device 1 that has a longitudinal direction in a first direction and a lateral direction in a second direction when viewed from above, and has a plurality of trenches 2 arranged in the second direction. Note that the trenches 2 shown by dotted lines in the cross section at the front of Fig. 17 show positions that virtually correspond to the trenches 2 in order to explain the positional relationship between other components and the trenches 2.

[0005] The first conductivity type source region 3 includes a region at least a portion of which has a fin structure separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3 and in contact with the source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. Ends of the bottom surfaces of the plurality of trenches 2 in the first direction are located in the body region 9. The channel region 5 is connected to the body region 9. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0006] 17 has a gate insulating film disposed inside the trench 2 and a gate electrode including a region at least partially disposed inside the trench 2, and a channel current flows vertically (in the depth direction) in the channel region 5. The gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2.

[0007] Incidentally, an example of a patent document related to such technology is Patent Document 1. Although the names of the components and the detailed structure are different, paragraphs 0048 to 0052, FIG. 3, and FIG. 14 to FIG. 18 of Patent Document 1 describe a configuration similar to FIG. 17 described above.

[0008] Japanese Patent Application Laid-Open No. 2004-207289

[0009] According to the structure of the conventional semiconductor device 1 shown in FIG. 17, the trench pitch can be reduced to increase the channel density, thereby increasing the number of channels, thereby reducing the on-resistance of the entire semiconductor chip.

[0010] Furthermore, due to the presence of the JFET region 8 formed between the body regions 9, a depletion layer extends from the body region 9 to the JFET region 8 in the event of a short circuit, causing pinch-off, thereby providing a high short-circuit resistance.

[0011] Furthermore, since the ends of the bottom surfaces of the plurality of trenches 2 in the first direction are located within the body region 9, the three-dimensional corners of the trenches 2 are located within the body region 9. As a result, even when a high voltage is applied, the concentration of the electric field is alleviated at the three-dimensional corners of the trenches 2, where the electric field is likely to concentrate and breakdown of the gate insulating film is likely to occur, and breakdown of the gate insulating film can be suppressed.

[0012] Here, the on-resistance can also be reduced by increasing the width of the channel region 5 (the length of the channel region 5 in the first direction) to reduce the channel resistance.

[0013] 17 , the channel region 5 has a fin structure separated by a plurality of trenches 2, and the ends of the bottom surfaces of the plurality of trenches 2 in the first direction are disposed in the body region 9, and the channel region 5 is connected to the body region 9. Therefore, the width of the channel region 5 is the width of the trench 2 in the longitudinal direction (the length of the trench 2 in the first direction) minus the overlap width between the trench 2 and the body region 9, and the width of the channel region 5 is the same as the width of the JFET region 8 immediately below it (the length of the JFET region 8 in the first direction). Therefore, the width of the channel region 5 and the width of the JFET region 8 immediately below it cannot be designed independently, and if an attempt is made to reduce the on-resistance by increasing the width of the channel region 5 to improve performance, the width of the JFET region 8 also increases, resulting in a problem of reduced short-circuit resistance and breakdown voltage, and thus reduced reliability, and there has been a trade-off between performance and reliability.

[0014] The problem to be solved by the present invention is to realize a semiconductor device in which there is a high degree of freedom in designing the width of the channel region and the width of the JFET region in a trench MOSFET with a vertical channel fin structure.

[0015] In order to achieve the above object, a semiconductor device of the present invention includes a first conductivity type source region including a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed from above and arranged in the second direction, at least a portion of which has a fin structure separated by the plurality of trenches, a second conductivity type channel region in contact with a lower surface of the source region and having a fin structure separated by the plurality of trenches, a gate insulating film disposed inside the trenches, a gate electrode including a region at least a portion of which is disposed inside the trenches, and a first conductivity type gate electrode disposed below the channel region. and a body region of a second conductivity type arranged on a side of the JFET region, wherein ends of bottom surfaces of the plurality of trenches in the first direction are arranged in the body region, the channel region is connected to the body region, and a channel current flows in the channel region in a vertical direction, the JFET region has a first JFET region and a second JFET region arranged closer to the channel region than the first JFET region, and the length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction.

[0016] According to the present invention, it is possible to realize a semiconductor device in which there is a high degree of freedom in designing the width of the channel region and the width of the JFET region in a trench MOSFET with a vertical channel fin structure.

[0017] 1 is a perspective view showing a schematic configuration of a semiconductor device of Example 1. FIG. 1 is an X1-X1′ cross-sectional view of FIG. 1. FIG. 1 is an X2-X2′ cross-sectional view of FIG. 1. FIG. 1 is a Y1-Y1′ cross-sectional view of FIG. 1. FIG. 2 is an X1-X1′ cross-sectional view corresponding to FIG. 2, showing another example of the schematic configuration of the semiconductor device of Example 1. FIG. 2 is an X1-X1′ cross-sectional view showing a schematic configuration of a semiconductor device of Example 2, schematically showing the expansion of a depletion layer during normal operation. FIG. 2 is an X1-X1′ cross-sectional view showing a schematic configuration of a semiconductor device of Example 2, schematically showing the expansion of a depletion layer during short-circuiting or blocking. FIG. 3 is an X1-X1′ cross-sectional view showing a schematic configuration of a semiconductor device of Example 2, schematically showing the expansion of a depletion layer during short-circuiting or blocking. FIG. 4 is a diagram showing a trade-off between performance and reliability in a reliability-oriented design in the semiconductor device of Example 2. FIG. 5 is a diagram showing a trade-off between performance and reliability in a performance-oriented design in the semiconductor device of Example 2. FIG. 6 is an X1-X1′ cross-sectional view showing a schematic configuration of a semiconductor device of Example 3, schematically showing the expansion of a depletion layer during short-circuiting or blocking. FIG. 7 is an X1-X1′ cross-sectional view showing a schematic configuration of a semiconductor device of Example 4. 12 is a diagram showing an impurity concentration profile in the depth direction along Z1-Z1' in Figure 11. An X1-X1' cross-sectional view showing a schematic configuration of a semiconductor device of Example 5. A diagram explaining the relationship between the integral value of the dose amount in the JFET region and the electric field of the gate insulating film in a semiconductor device of Example 6. An X1-X1' cross-sectional view explaining a manufacturing method for a semiconductor device of Example 7. A diagram showing an impurity concentration profile in the depth direction along Z2-Z2' in Figure 15, explaining a manufacturing method for a semiconductor device of Example 7. A perspective view schematically explaining the structure of a trench MOSFET with a conventional vertical channel fin structure.

[0018] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0019] FIG. 1 is a perspective view showing a schematic configuration of a semiconductor device of Example 1. FIG. 2 is a cross-sectional view taken along X1-X1' in FIG. 1. FIG. 3 is a cross-sectional view taken along X2-X2' in FIG. 1. FIG. 4 is a cross-sectional view taken along Y1-Y1' in FIG. 1. Note that the gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and drain electrode 13 are not shown in FIG. 1.

[0020] The semiconductor device 1 of this embodiment has a plurality of trenches 2, a source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of the first conductivity type, and a body region 9 of the second conductivity type.

[0021] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0022] The plurality of trenches 2 have a longitudinal direction in a first direction (the X1-X1' direction in FIG. 1) when viewed in a plan view, and a lateral direction in a second direction (the Y1-Y1' direction in FIG. 1), and are arranged in a plurality of rows in the second direction. Note that the trenches 2 shown by dotted lines in the cross sections of FIGS. 1 and 2 show positions that virtually correspond to the trenches 2 in order to explain the positional relationship between other components and the trenches 2.

[0023] The first conductivity type source region 3 includes a region having a fin structure at least a portion of which is separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3 and in contact with the source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. Therefore, the width of the channel region 5 is the width of the trench 2 in the longitudinal direction minus the overlap width between the trench 2 and the body region 9.

[0024] A gate insulating film 6 is disposed inside the trench 2. At least a portion of a gate electrode 7 is also disposed inside the trench 2. The gate electrodes 7 disposed inside the trench 2 are connected to each other outside the trench 2. The gate electrodes 7 can be formed of, for example, polysilicon.

[0025] In the semiconductor device 1 of this embodiment, a channel current flows vertically (in the depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. In other words, it is a trench MOSFET with a vertical channel fin structure. Therefore, by reducing the trench pitch and increasing the channel density, the number of channels can be increased, thereby reducing the on-resistance of the entire semiconductor chip. In addition, the presence of the JFET region 8 formed between the body regions 9 allows a depletion layer to extend from the body region 9 to the JFET region 8 and pinch off during a short circuit, resulting in high short-circuit resistance.

[0026] The semiconductor device 1 of this embodiment also includes a drift region 10 of the first conductivity type arranged below the JFET region 8, a drain region 11 of the first conductivity type arranged below the drift region 10, a source electrode 12 arranged on the front surface side, a drain electrode 13 arranged on the back surface side, and an interlayer insulating film 14.

[0027] The source electrode 12 is an electrode made of a metal such as aluminum, and is electrically connected to the source region 3. In this embodiment, the source electrode 12 is electrically connected to the body region 9 via the contact region 4 of the second conductivity type, which has a higher impurity concentration than the body region 9, but the present invention is not limited to this, and the source electrode 12 may be directly connected to the body region 9.

[0028] The drain electrode 13 is an electrode made of a metal such as aluminum, and is electrically connected to the drain region 11 .

[0029] The interlayer insulating film 14 is formed between the mutually connected portions of the gate electrodes 7 and the source region 3. The interlayer insulating film 14 is also formed so as to cover the upper and side portions of the mutually connected portions of the gate electrodes 7.

[0030] In the semiconductor device 1 of this embodiment, the ends of the bottom surfaces of the plurality of trenches 2 in the first direction are located within the body region 9. This results in a structure in which three-dimensional corners of the trenches 2 are present within the body region 9. Therefore, even when a high voltage is applied, the concentration of the electric field is alleviated at the three-dimensional corners of the trenches 2, where the electric field is likely to concentrate and breakdown of the gate insulating film 6 is likely to occur, and breakdown of the gate insulating film 6 can be suppressed.

[0031] Furthermore, in the semiconductor device 1 of this embodiment, the JFET region 8 has a first JFET region 8A and a second JFET region 8B disposed closer to the channel region 5 than the first JFET region 8A, and the width of the second JFET region 8B (the length in the first direction of the second JFET region 8B) is longer than the width of the first JFET region 8A (the length in the first direction of the first JFET region 8A). As a result, even if there is a constraint that the width of the channel region 5 and the width of the second JFET region 8B directly below it must be the same, the widths of the channel region 5 and the first JFET region 8A are not subject to that constraint, and they can be designed independently. Furthermore, the smaller the width of the JFET region 8, the more likely it is that a depletion layer extending from the body region 9 to the JFET region 8 will close and pinch off within the JFET region 8 during a short circuit, thereby increasing the short-circuit resistance. Therefore, by increasing the width of the channel region 5 to reduce the on-resistance in order to improve performance, while making the width of the first JFET region 8A smaller, it is possible to ensure short-circuit resistance and breakdown voltage, and therefore reliability can also be ensured.Compared to the conventional case where the JFET region 8 has only one width, there is a high degree of design freedom, improving the trade-off between performance and reliability and making it possible to achieve both performance and reliability.In addition, since the width of the first JFET region 8A can be changed independently of the width of the channel region 5 according to the required breakdown voltage, design changes become easier.

[0032] As described above, according to this embodiment, in a trench MOSFET with a vertical channel fin structure, it is possible to realize a semiconductor device 1 having a high degree of freedom in designing the width of the channel region 5 and the width of the JFET region 8.

[0033] It is desirable that the position in the depth direction of the lower end of the gate electrode 7 disposed inside the trench 2 overlaps with the position in the depth direction of the second JFET region 8B. Here, the position in the depth direction of the lower end of the gate electrode 7 may be the same as the position in the depth direction of the upper end or the lower end of the second JFET region 8B, but in consideration of manufacturing variations, it is desirable that the position in the depth direction of the lower end of the gate electrode 7 is deeper than the position in the depth direction of the upper end of the second JFET region 8B and shallower than the position in the depth direction of the lower end of the second JFET region 8B.

[0034] It is also desirable that the width of the first JFET region 8A is 0.1 μm or more and the width of the second JFET region 8B is 5 μm or less, but this is not limitative.

[0035] The impurity concentration of the first JFET region 8A may be the same as or different from the impurity concentration of the second JFET region 8B.

[0036] As for the impurity concentrations, in this embodiment, the first JFET region 8A and the second JFET region 8B are shown as n, the body region 9 and the channel region 5 as p, the drift region 10 as low-concentration n-, the source region 3 and the drain region 11 as high-concentration n+, and the contact region 4 as high-concentration p+, but this is not limitative as long as the intended operation of this embodiment can be realized. For example, the first JFET region 8A and the second JFET region 8B may be low-concentration n-.

[0037] The semiconductor device 1 of this embodiment can be formed using, for example, an n+ type SiC substrate, but is not limited to this and may also be formed using a Si substrate, etc. Furthermore, for portions of this specification where no special description is given regarding the manufacturing method, the semiconductor device can be manufactured using a general semiconductor device manufacturing method, such as forming an n+ type drain region 11 on an n+ type SiC substrate and forming an n- type drift region 10 by epitaxial growth, and so detailed description thereof will be omitted.

[0038] FIG. 5 is a cross-sectional view taken along the line X1-X1' corresponding to FIG. 2, showing another example of the schematic configuration of the semiconductor device according to the first embodiment.

[0039] 2, the JFET region 8 and the body region 9 are shown in simplified shapes such as rectangles, but in reality, since each region is fabricated by ion implantation or epitaxial growth, they may have a shape with a smooth boundary without corners, as shown in Fig. 5, and there may be no clear boundary between the first JFET region 8A and the second JFET region 8B. Even in this case, the width of the second JFET region 8B is formed larger than the width of the first JFET region 8A, just like in Fig. 2.

[0040] In the following examples, the shape shown in FIG. 5 will be used as a base.

[0041] Example 2 is a modification of Example 1, in which the first conductivity type impurity concentration of the second JFET region 8B is lower than the first conductivity type impurity concentration of the first JFET region 8A. Note that when the first conductivity type impurity concentration of the second JFET region 8B is 1×10 １５ cm －３ The first conductivity type impurity concentration of the first JFET region 8A is 1×10 ２０ cm －３ The following is desirable, but not limited to:

[0042] FIG. 6 is an X1-X1′ cross-sectional view showing the schematic configuration of the semiconductor device of Example 2, and is a diagram schematically illustrating the expansion of the depletion layer during normal operation. FIG. 7 is an X1-X1′ cross-sectional view showing the schematic configuration of the semiconductor device of Example 2, and is a diagram schematically illustrating the expansion of the depletion layer during short-circuiting or blocking. The depletion layer 17 expands more easily when the impurity concentration is low. Note that the expansion of the depletion layer 17 varies depending on the applied drain voltage value and the impurity concentration in each region, so FIGS. 6 and 7 are merely examples.

[0043] 6, during normal operation, the depletion layer 17 tends to expand in the second JFET region 8B, which has a low concentration, but the second JFET region 8B is wide, so the resistance in the second JFET region 8B is sufficiently low. Furthermore, although the first JFET region 8A is narrow, the depletion layer 17 does not easily extend from the body region 9 because of the high concentration, so the resistance is sufficiently low, resulting in high performance.

[0044] 7, during short circuit or blocking, the depletion layer 17 closes and pinches off in the second JFET region 8B because the second JFET region 8B has a low concentration, saturating the current. Because the second JFET region 8B is pinched off, the electric field in the gate insulating film 6 at the bottom of the trench 2 can be reduced.

[0045] Furthermore, as in this embodiment, the structure in which the width of the second JFET region 8B is larger than the width of the first JFET region 8A and the first conductivity type impurity concentration of the second JFET region 8B is lower than the first conductivity type impurity concentration of the first JFET region 8A has the advantage that the electrical characteristics of the semiconductor device 1 are less susceptible to manufacturing variations within a wafer or between wafers. Specifically, because the width of the second JFET region 8B is wide, even if the width varies during manufacturing, the change in resistance of the JFET region 8B is small. Furthermore, because the first JFET region 8A has a high concentration, the depletion layer 17 does not easily extend, so even if the width varies during manufacturing, the change in resistance of the JFET region 8B is small. Furthermore, the first JFET region 8A needs a width large enough to prevent the depletion layer 17 from closing during normal operation. However, even if the width varies during manufacturing, the high concentration makes the depletion layer 17 less likely to extend, so the effect of width variations is small. Regarding the short-circuit resistance, the width of the second JFET region 8B that pinches off in the event of a short circuit is wider, so the effect of width variations is reduced. Also, the need for precise adjustment of the exposure dose in the photo process during manufacturing can be reduced.

[0046] Next, the characteristics of the semiconductor device 1 of this embodiment will be described.

[0047] The semiconductor device 1 of this embodiment can widen the design window compared to the prior art. An example will be described with reference to FIGS.

[0048] Fig. 8 is a diagram showing the trade-off between performance and reliability in the case of a reliability-oriented design in the semiconductor device of Example 2. Fig. 9 is a diagram showing the trade-off between performance and reliability in the case of a performance-oriented design in the semiconductor device of Example 2. In Figs. 8 and 9, the horizontal axis represents the width of the first JFET region 8A, the vertical axis on the left represents the short-circuit saturation current as an example of reliability, and the vertical axis on the right represents the resistance of the JFET region 8 as an example of performance. Note that other indices may be used as indicators of performance and reliability.

[0049] In FIG. 8 , 101 indicates the characteristics of the short-circuit saturation current of a conventional specification, and 102 indicates the resistance characteristics of the JFET region 8 of a conventional specification. Here, the conventional specification refers to a specification in which the second JFET region 8B is not present and the entire JFET region 8 is composed only of the first JFET region 8A. Note that the characteristics vary depending on the depth and impurity concentration of the first JFET region 8A, so the characteristics shown in FIG. 8 are only an example. The short-circuit saturation current characteristics 101 of a conventional specification increase as the width of the first JFET region 8A increases, so a threshold point 103 equal to the threshold value of the allowable short-circuit saturation current becomes the upper limit of the design width of the first JFET region 8A. The resistance characteristics 102 of the JFET region 8 of a conventional specification increase as the width of the first JFET region 8A decreases, and rapidly increase when the width of the first JFET region 8A becomes smaller than a threshold point 104 at which the depletion layer 17 pinches off in the JFET region 8 during normal operation. Therefore, the threshold point 104 is the lower limit of the design width of the first JFET region 8A. The region between the upper and lower design limits is the design window. A design window 105 of the width of the first JFET region 8A according to conventional specifications has the size shown in FIG. 8.

[0050] In contrast, 111 indicates the characteristics of the saturation current at short circuit in the reliability-oriented specification of this embodiment, and 112 indicates the resistance characteristics of the JFET region 8 in the reliability-oriented specification of this embodiment.

[0051] In the reliability-oriented specification and performance-oriented specification of this embodiment, a second JFET region 8B is added which is wider than the first JFET region 8A and has a lower impurity concentration of the first conductivity type. As an example, an example will be described in which the impurity concentration of the second JFET region 8B is lower than that of the JFET region 8 of the conventional specification, and the impurity concentration of the first JFET region 8A is higher than that of the JFET region 8 of the conventional specification, but this is not limiting.

[0052] The reliability-oriented specification in this embodiment is realized, for example, when the impurity concentration of the second JFET region 8B is set to a relatively low concentration, when the width of the second JFET region 8B is set to a relatively narrow value, or when the impurity concentration of the first JFET region 8A is set to a value close to the impurity concentration of the second JFET region 8B, but is not limited to these. Note that the characteristics change depending on the depth and impurity concentration of the first JFET region 8A and the width, depth, and impurity concentration of the second JFET region 8B, so the example shown in Figure 8 is just an example.

[0053] Regarding the reliability index, in the characteristic 111 of the short-circuit saturation current of the reliability-oriented specification, the depletion layer 17 closes and pinches off in the second JFET region 8B before the first JFET region 8A at high voltage, preventing a large current (short-circuit current) from flowing, and therefore the short-circuit saturation current can be made smaller than the characteristic 101 of the short-circuit saturation current of the conventional specification, even if the width of the first JFET region 8A is the same. Accordingly, the threshold point 113 corresponding to the threshold point 103 moves to the right of the threshold point 103, and the upper limit of the design width of the first JFET region 8A is expanded.

[0054] Regarding performance indices, the resistance characteristic 112 of the JFET region 8 of the reliability-oriented specification has some regions where the resistance is somewhat higher than the resistance characteristic 102 of the JFET region 8 of the conventional specification, but because the second JFET region 8B is wider than the first JFET region 8A and the first JFET region 8A has a higher concentration than the conventional specification, the threshold point 114 (pinch-off point) at which the depletion layer 17 pinches off in the first JFET region 8A during normal operation can be shifted to the left of the threshold point 104 of the conventional specification. In this way, by shifting the threshold point 114 to the left of the threshold point 104, the lower limit of the design width of the first JFET region 8A is expanded.

[0055] Therefore, the design window 115 for the width of the first JFET region 8A of the reliability-oriented specifications in this embodiment can be made wider than the design window 105 for the width of the first JFET region 8A of the conventional specifications.

[0056] 8 shows an example in which the impurity concentration of the first JFET region 8A with reliability-oriented specifications is higher than the impurity concentration of the first JFET region 8A with conventional specifications, but it may be the same as the impurity concentration of the first JFET region 8A with conventional specifications. In that case, threshold point 114 is closer to threshold point 104, so the lower limit of the design width of the first JFET region 8A does not change much, but the saturation current during short circuit is further reduced compared to that in FIG. 8, so the upper limit of the design is expanded. Therefore, even in this case, design window 115 can be wider than design window 105.

[0057] The performance-oriented design of FIG. 9 has specifications in which the resistance of the JFET region 8 is lowered and the current during normal operation is increased compared to the reliability-oriented design of FIG.

[0058] In FIG. 9, the characteristic 101 of the saturation current at short circuit of the conventional specification and the characteristic 102 of the resistance of the JFET region 8 of the conventional specification are the same as those in FIG.

[0059] In contrast to this, 121 indicates the characteristics of the saturation current at short circuit in the performance-oriented specifications of this embodiment, and 122 indicates the characteristics of the resistance of the JFET region 8 in the performance-oriented specifications of this embodiment.

[0060] The performance-oriented specification of this embodiment can be realized, for example, by making the impurity concentration of the second JFET region 8B higher than the impurity concentration of the second JFET region 8B in the reliability-oriented specification while satisfying the condition that the second JFET region 8B has a lower concentration than the first JFET region 8A. This is not limited to this, and at least one of the impurity concentrations of the first JFET region 8A and the second JFET region 8B may be higher than the reliability-oriented specification while satisfying the condition that the second JFET region 8B has a lower concentration than the first JFET region 8A. Note that the characteristics vary depending on the depth and impurity concentration of the first JFET region 8A and the width, depth, and impurity concentration of the second JFET region 8B, so the example shown in FIG. 9 is merely an example.

[0061] Regarding performance indicators, the resistance characteristic 122 of the JFET region 8 with performance-oriented specifications is smaller than the resistance characteristic 102 of the JFET region 8 with conventional specifications. This allows for a larger current during normal operation, improving performance. Because the first JFET region 8A is highly doped, pinch-off does not occur even if the width of the first JFET region 8A is narrower than that of the conventional specifications. Therefore, the threshold point 124 at which the depletion layer 17 pinches off in the first JFET region 8A during normal operation is shifted to the left of the threshold point 104. Note that the second JFET region 8B is wide and does not pinch off during normal operation.

[0062] Regarding the reliability index, the characteristic 121 of the short-circuit saturation current of the performance-oriented specification has a larger short-circuit saturation current than the characteristic 101 of the short-circuit saturation current of the conventional specification, and although threshold point 123 corresponding to threshold point 103 has shifted to the left of threshold point 103, threshold point 124 corresponding to threshold point 104 has also shifted to the left, so that the design window 125 of the width of the first JFET region 8A of the performance-oriented specification is wider than the design window 105 of the width of the first JFET region 8A of the conventional specification. Furthermore, at high voltages, the depletion layer 17 closes and pinches off in the second JFET region 8B, preventing a large current (short-circuit current) from flowing, thereby improving performance and ensuring reliability.

[0063] Example 3 is a modification of Example 1, in which the first conductivity type impurity concentration of the second JFET region 8B is higher than the first conductivity type impurity concentration of the first JFET region 8A. Note that when the first conductivity type impurity concentration of the first JFET region 8A is 1×10 １５ cm －３ or more, and the first conductivity type impurity concentration of the second JFET region 8B is 1×10 ２０ cm －３ The following is desirable, but not limited to:

[0064] FIG. 10 is a cross-sectional view taken along the line X1-X1' showing the schematic configuration of the semiconductor device of the third embodiment, and is a diagram showing the expansion of the depletion layer during short-circuiting or blocking.

[0065] Example 3 differs from Example 2 in that the depletion layer 17 closes and pinches off in a part of the first JFET region 8A and the drift region 10. Although the location where the depletion layer 17 closes and pinches off differs from Example 2, the width of the channel region 5 and the width of the first JFET region 8A can also be designed independently in this example. Furthermore, compared to Example 2, the pinched-off path can be made longer, which increases the resistance of the path through which the saturation current flows, thereby suppressing the saturation current.

[0066] Although not shown, the second JFET region 8B has a high impurity concentration and therefore has a low resistance during normal operation.

[0067] Example 4 is a modification of Example 1, and has a channel return region 15 in a part of the second JFET region 8B, which has a higher concentration of first conductivity type impurities than the other part of the second JFET region 8B.

[0068] FIG. 11 is an X1-X1′ cross-sectional view showing a schematic configuration of a semiconductor device of Example 4. FIG. 12 is a diagram showing an impurity concentration profile in the depth direction along Z1-Z1′ in FIG. 11. In FIG. 12, the horizontal axis represents depth and the vertical axis represents impurity concentration. Note that FIG. 12 shows an example in which a channel return region 15 is provided in Example 2, but the present invention is not limited to this and may be applied to Example 1 or 3.

[0069] In addition to the effects of the first to third embodiments, this embodiment can prevent the base of the second conductivity type impurity concentration in the channel region 5 from spreading by the channel push-back region 15 as shown in FIG.

[0070] Example 5 is a modification of Example 1, in which the first JFET region 8A has a first conductivity type impurity concentration different from the first conductivity type impurity concentration of the second JFET region 8B, and the JFET region having a higher first conductivity type impurity concentration of either the first JFET region 8A or the second JFET region 8B has, between the body region 9, a low concentration region having a first conductivity type impurity concentration lower than other regions, or an intrinsic region 16 that is not doped with first conductivity type impurities.

[0071] FIG. 13 is a cross-sectional view taken along the line X1-X1' showing a schematic configuration of a semiconductor device according to the fifth embodiment.

[0072] 13 shows an example in which an intrinsic region 16 is provided in the first JFET region 8A, which has a higher concentration, than the second JFET region 8B, as in Example 2. However, this is not limiting, and a low-concentration region, in which the concentration of the first conductivity type impurity is lower than in other portions, may be used instead of the intrinsic region 16. It is desirable that the low-concentration region has a sufficiently low concentration.

[0073] For example, if the second JFET region 8B is made very lightly doped, it is necessary to make the first JFET region 8A somewhat highly doped in order to reduce the resistance of the JFET region 8. However, in that case, the junction electric field at the boundary between the first JFET region 8A and the body region 9 becomes high, which may cause undesirable behavior such as avalanche multiplication and hot carrier effects. Therefore, by providing an intrinsic region 16 (i-layer) as shown in Figure 13, the maximum electric field can be reduced by the following formula:

[0074] Emax (with i layer) / Emax (without i layer) = (1+d ２ / Wd ２ ) ０．５ −d / Wd where Wd is the width of the depletion layer in the pn junction, and d is the width of the i-layer.

[0075] In addition, when the second JFET region 8B has a higher concentration than the first JFET region 8A as in the third embodiment, a low concentration region or intrinsic region 16 may be provided in the second JFET region 8B having a higher concentration.

[0076] The sixth embodiment is a modification of the first embodiment.

[0077] In the semiconductor device 1 of this embodiment, at least some of the parameters of the width, depth, and first conductivity type impurity concentration of the first JFET region 8A and the width, depth, and first conductivity type impurity concentration of the second JFET region 8B are set so that (1) the integral value of the dose amount in the JFET region 8 is minimized, (2) the maximum value of the quasi-Fermi level in the JFET region 8 when a voltage is applied during normal operation is minimized, and (3) the depth of the depletion layer 17 that spreads into the drift region 10 when a short circuit occurs is maximized.

[0078] 14 is a diagram illustrating the relationship between the integral value of the dose in the JFET region and the electric field in the gate insulating film in the semiconductor device of Example 6. In Fig. 14, the horizontal axis represents the integral value of the dose in the JFET region 8, and the vertical axis represents the electric field in the gate insulating film 6 during blocking. Note that the integral value of the dose in the JFET region 8 on the horizontal axis is the integral value of the dose in the entire JFET region 8, which is the sum of the first JFET region 8A and the second JFET region 8B.

[0079] Condition (1) can reduce the electric field of the gate insulating film 6 during blocking. Note that, as shown in FIG. 14, within the design range of this embodiment, an example in which the relationship between the two is approximately linear is shown, but the present invention is not limited to this.

[0080] Condition (2) makes it possible to reduce the on-resistance of the entire JFET region 8 during normal operation.

[0081] Condition (3) allows the current flowing through the JFET region 8 during a short circuit to be minimized, thereby reducing the saturation current.

[0082] Furthermore, in combination with the second embodiment, (4) the design windows 115, 125 (see FIGS. 8 and 9) for the width of the first JFET region 8A may be set to be wider than a predetermined value or to be maximized.

[0083] As a design method, for example, at least some of the parameters among the width, depth, and first conductivity type impurity concentration of the first JFET region 8A and the width, depth, and first conductivity type impurity concentration of the second JFET region 8B may be set as variables, and the remaining parameters may be fixed, and numerical values ​​that satisfy the requirements of conditions (1) to (3) or (1) to (4) may be found. Note that this design may be done manually, or an optimization system using AI (Artificial Intelligence) may be used.

[0084] According to this embodiment, a semiconductor device that achieves both high performance and reliability can be realized.

[0085] The seventh embodiment is a modification of the first embodiment.

[0086] Fig. 15 is an X1-X1' cross-sectional view illustrating the manufacturing method of the semiconductor device of Example 7. Fig. 16 is a diagram illustrating the impurity concentration profile in the depth direction along Z2-Z2' in Fig. 15, illustrating the manufacturing method of the semiconductor device of Example 7. In Fig. 16, the horizontal axis represents depth and the vertical axis represents impurity concentration.

[0087] In this embodiment, when the body region 9 is formed using the resist 18 as a mask, ions are implanted so that the peak position in the depth direction of the second conductivity type impurity concentration is at a depth position in the first JFET region 8A, thereby giving a part of the body region 9 a protruding shape, and it is possible to form the body region 9 in a shape in which the width of the second JFET region 8B is larger than the width of the first JFET region 8A with a single ion implantation.

[0088] As a result, the semiconductor device 1 of this embodiment has a structure in which the peak position of the second conductivity type impurity concentration in the body region 9 in the depth direction overlaps with the position in the depth direction of the first JFET region 8A.

[0089] The manufacturing method and structure are not limited to these, and the body region 9 may be formed in two steps so that the width of the second JFET region 8B is larger than the width of the first JFET region 8A. In this case, the concentration of the second conductivity type impurity in the body region 9 does not need to have a peak in the depth direction.

[0090] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0091] 1: semiconductor device, 2: trench, 3: source region, 4: contact region, 5: channel region, 6: gate insulating film, 7: gate electrode, 8: JFET region, 8A: first JFET region, 8B: second JFET region, 9: body region, 10: drift region, 11: drain region, 12: source electrode, 13: drain electrode, 14: interlayer insulating film, 15: channel return region, 16: intrinsic region, 17: depletion layer, 18: resist

Claims

a gate electrode including a region at least a portion of which is disposed inside the trench; a first conductivity type JFET region disposed below the channel region; and a second conductivity type body region disposed to one side of the JFET region, wherein the first direction end of a bottom surface of the plurality of trenches is disposed within the body region, the channel region is connected to the body region, and a channel current flows vertically through the channel region, the JFET region having a first JFET region and a second JFET region disposed closer to the channel region than the first JFET region, and wherein the length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction.

2. A semiconductor device according to claim 1, wherein the concentration of the first conductive type impurity in said second JFET region is lower than the concentration of the first conductive type impurity in said first JFET region.

3. In the method according to claim 2, the first conductive type impurity concentration of the second JFET region is 1×10 １５ cm －３ or more, and the first conductivity type impurity concentration of the first JFET region is 1×10 ２０ cm －３ A semiconductor device characterized in that:

4. A semiconductor device according to claim 1, wherein the concentration of the first conductive type impurity in said second JFET region is higher than the concentration of the first conductive type impurity in said first JFET region.

5. The method according to claim 4, wherein the first conductive type impurity concentration of the first JFET region is 1×10 １５ cm －３or more, and the first conductivity type impurity concentration of the second JFET region is 1×10 ２０ cm －３ A semiconductor device characterized in that:

6. A semiconductor device according to claim 1, wherein a peak position in the depth direction of the concentration of the second conductive type impurity in said body region overlaps with a position in the depth direction of said first JFET region.

7. A semiconductor device according to claim 1, wherein the position in the depth direction of the lower end of the gate electrode disposed inside the trench overlaps with the position in the depth direction of the second JFET region.

8. A semiconductor device according to claim 1, further comprising a channel return region in a part of said second JFET region, said channel return region having a higher concentration of first conductivity type impurities than the other part of said second JFET region.

9. A semiconductor device according to claim 1, further comprising: a contact region provided on the surface side of the body region and having a second conductivity type impurity concentration higher than that of the body region; and a source electrode connected to the contact region and the source region.

10. A semiconductor device according to claim 1, wherein the length of the first JFET region in the first direction is 0.1 μm or more, and the length of the second JFET region in the first direction is 5 μm or less.

11. A semiconductor device according to claim 1, characterized in that a first conductivity type impurity concentration of the first JFET region is different from a first conductivity type impurity concentration of the second JFET region, and the JFET region having a higher first conductivity type impurity concentration of the first JFET region or the second JFET region has, between the body region, a low concentration region having a first conductivity type impurity concentration lower than other portions, or an intrinsic region that is not doped with first conductivity type impurities.

12. A semiconductor device according to claim 1, further comprising: a drift region of a first conductivity type disposed below said JFET region; and a drain region of the first conductivity type disposed below said drift region.

13. A semiconductor device according to claim 12, characterized in that at least some of the parameters of the length in the first direction, depth, and first conductivity type impurity concentration of the first JFET region, and the length in the first direction, depth, and first conductivity type impurity concentration of the second JFET region are set so that the integral value of the dose in the JFET region is minimized, the maximum value of the quasi-Fermi level of the JFET region when a voltage is applied during normal operation is minimized, and the depth of the depletion layer that spreads in the drift region when a short circuit occurs is maximized.

14. A semiconductor device according to claim 1, wherein the length of said trench in said first direction is longer than the length of said second JFET region in said first direction.

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