A process for increasing cell density of dual trench MOSFET

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a process for improving the cell density of a double trench MOSFET, including: injecting phosphorus elements of different concentrations into a semiconductor epitaxial layer to form an N substrate layer and a drift layer; continuing to ion-implant boron elements into the upper layer of the drift layer to form a P body region; ion-implanting at the center of the P body region to form an N well layer, and ion-implanting in the upper P body region to form a P well layer and a P-well layer; etching the surface of the semiconductor epitaxial layer by an etching process to form a rectangular groove; and depositing metal aluminum on both sides of the rectangular groove to form an L-type source. In the preparation process, the L-type source adopts an inwardly recessed design to contact the N well layer, and the prepared MOSFET device is not prone to heat accumulation and thus reduces the power consumption of the MOSFET device even when a smaller size is adopted. This process design using the source recess can greatly improve the cell density of the MOSFET device.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and in particular to a process for improving the cell density of double-trench MOSFETs. Background Art

[0002] Dual-Gate MOSFET (DG-MOSFET for short) is a special type of metal oxide semiconductor field effect transistor (MOSFET) with two independent gates. It is mainly used to improve the performance of the device, especially in high-frequency applications, low-power applications and analog circuits. Compared with conventional single-gate MOSFET, dual-trench MOSFET can provide better controllability, gain and lower power consumption.

[0003] The existing patent discloses a double-trench SiC MOSFET cell structure, device and preparation method (CN116072710A), which belongs to the field of semiconductor device technology. The cell structure includes: N+ type SiC substrate, first N-type SiC drift layer, multiple floating P+ type shielding rings arranged in the first N-type SiC drift layer, second N-type SiC drift layer, source P+ type shielding layer arranged at both sides of the second N-type SiC drift layer, gate trench, gate dielectric layer, gate electrode. In the technology disclosed in the patent, when a larger number of cell structures are used to stack into a MOSFET device with a constant volume and higher power, exponential heat accumulation often occurs after long-term use, and as the heat accumulates, the temperature control instruction of the MOSFET device will be triggered, thereby reducing the working power of the MOSFET device. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a process for improving the cell density of double trench MOSFET, thereby solving the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a process for improving the cell density of a double trench MOSFET comprises the following steps:

[0006] S1. Injecting phosphorus elements of different concentrations into the semiconductor epitaxial layer to form an N substrate layer and a drift layer;

[0007] S2, continue to form a P body region in the upper layer of the drift layer by ion implantation of boron elements;

[0008] S3, forming an N-well layer at the center of the P-body region by ion implantation, and continuing to implant ions in the upper P-body region to form a P-well layer and a P-well layer;

[0009] S4, etching the surface of the semiconductor epitaxial layer through an etching process to form a rectangular groove;

[0010] S5, depositing metal aluminum on both sides of the rectangular groove to form an L-shaped source;

[0011] S6, filling the trench with a silicon dioxide insulating material, and etching the filled silicon dioxide insulating material to form a gate oxide layer;

[0012] S7, depositing polysilicon material in the groove etched in the silicon dioxide insulating material to form a gate, and depositing silicon dioxide insulating material on the exposed surface of the gate;

[0013] S8, depositing metal in the source region and the drain region to form a metal source cover sheet and a drain;

[0014] S9. Conduct electrical performance tests on the MOSFET structure, and package the MOSFET structure after passing the test.

[0015] Furthermore, in step S1, the doping concentration of the N substrate layer is ; The doping concentration of the drift layer is .

[0016] Furthermore, in step S3, the doping concentration of the P well layer is ; The doping concentration of the P-well layer is .

[0017] Furthermore, in step S5, the L-type source is in ohmic contact with both the P-well layer and the N-well layer.

[0018] Furthermore, in step S6, at a temperature of Silicon dioxide is deposited into the trench by chemical vapor deposition at ℃ to form a gate oxide layer.

[0019] Furthermore, in step S9, the electrical performance of the MOSFET structure is determined to be qualified according to the increment of the threshold voltage changing with temperature after the MOSFET structure is connected to the gate voltage, the increment of the switching time changing with temperature, and the transconductance coefficient of the MOSFET structure, which are:

[0020]

[0021] In the formula, The qualified index coefficient that indicates the electrical performance of the MOSFET structure, represents the increment of threshold voltage changing with temperature, represents the increment of switching time as the temperature changes, Represents the transconductance coefficient of the MOSFET structure.

[0022] Furthermore, the transconductance coefficient of the MOSFET structure is determined based on the current gain of the MOSFET structure at unit width, the width-to-length ratio of the channel in the MOSFET structure, and the difference between the gate voltage and the threshold voltage. Then:

[0023]

[0024] In the formula, represents the transconductance coefficient of the MOSFET structure, Represents the current gain of the MOSFET structure per unit width, represents the channel width of the MOSFET structure, represents the channel length of the MOSFET structure, Indicates the gate voltage connected, Represents the threshold voltage.

[0025] Furthermore, when When , it means that the electrical performance of the tested MOSFET structure is qualified;

[0026] when When , it means that the electrical performance of the tested MOSFET structure is unqualified.

[0027] Beneficial effects:

[0028] 1. The present invention uses an inwardly recessed design for the L-shaped source to contact the N-well layer during the preparation process, so that the power consumption of the MOSFET device is not easily reduced due to heat accumulation even when the MOSFET device is smaller in size. This process design using the recessed source can greatly improve the cell density of the MOSFET device.

[0029] 2. The present invention can efficiently judge whether the electrical performance of the MOSFET structure using this process is qualified by measuring the increment of the threshold voltage changing with temperature, the increment of the switching time changing with temperature, and the transconductance coefficient of the MOSFET structure after the MOSFET structure is connected to the gate voltage. This judgment method can effectively solve the problem of too many collection indicators when using general electrical performance judgment rules. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1-8 The figure is a flow chart of the preparation of high-density cells in the present invention.

[0031] In the figure: 1, drain; 2, N substrate layer; 3, drift layer; 4, L-type source; 5, metal source cover; 6, gate oxide layer; 7, gate; 8, P well layer; 9, N well layer; 10, P-well layer. DETAILED DESCRIPTION

[0032] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Example 1

[0034] like Figure 1 -8, according to one aspect of the present invention, a process for improving the cell density of a double trench MOSFET is provided, comprising the following steps:

[0035] Step 1: Phosphorus elements of different concentrations are injected into the semiconductor epitaxial layer to form an N substrate layer 2 and a drift layer 3; the doping concentration of the N substrate layer 2 is ; The doping concentration of the drift layer 3 is .

[0036] Step 2: Continue to form a P body region in the upper layer of the drift layer 3 by ion implantation of boron elements.

[0037] Step 3: Form an N-well layer 9 by ion implantation at the center of the P-body region, and continue to implant ions in the upper P-body region to form a P-well layer 8 and a P-well layer 10; the doping concentration of the P-well layer 8 is ; The doping concentration of the P-well layer 10 is .

[0038] Step 4: etching the surface of the semiconductor epitaxial layer through an etching process to form a rectangular groove;

[0039] Step 5: Deposit metal aluminum on both sides of the rectangular groove to form an L-shaped source 4; the L-shaped source 4 is in ohmic contact with both the P-well layer 8 and the N-well layer 9. The L-shaped source 4 is designed with metal and is concave inward, which can take away the heat accumulated in the MOS device.

[0040] Step 6: Fill the trench with silicon dioxide insulating material, and etch the filled silicon dioxide insulating material to form a gate oxide layer 6; At ℃, silicon dioxide is deposited into the trench by chemical vapor deposition to form a gate oxide layer 6.

[0041] Step 7: deposit polysilicon material in the groove etched in the silicon dioxide insulating material to form a gate 7 , and deposit silicon dioxide insulating material on the exposed surface of the gate 7 .

[0042] Step 8: Deposit metal in the source region and the drain region to form a metal source cover sheet 5 and a drain 1 (such as Figure 8 As shown in FIG. 1 ), the metal source cover sheet 5 is a traditional source design. The process in the present invention further designs the source with an L-shaped source 4, which can accelerate the heat dissipation.

[0043] Step 9: Conduct electrical performance test on the MOSFET structure, and package the MOSFET structure after passing the test. The electrical performance of the MOS semiconductor device can be judged by using the increment of the threshold voltage with temperature after the gate voltage is connected to the MOSFET structure, the increment of the switching time with temperature, and the transconductance coefficient of the MOSFET structure.

[0044] Example 2

[0045] like Figure 8 As shown, the electrical performance of the MOSFET structure is determined to be qualified based on the increment of the threshold voltage changing with temperature after the MOSFET structure is connected to the gate voltage, the increment of the switching time changing with temperature, and the transconductance coefficient of the MOSFET structure:

[0046]

[0047] In the formula, The qualified index coefficient that indicates the electrical performance of the MOSFET structure, represents the increment of threshold voltage changing with temperature, represents the increment of switching time as the temperature changes, Represents the transconductance coefficient of the MOSFET structure.

[0048] The transconductance coefficient of the MOSFET structure is determined based on the current gain of the MOSFET structure at unit width, the width-to-length ratio of the channel in the MOSFET structure, and the difference between the gate voltage and the threshold voltage. Then we have:

[0049]

[0050] In the formula, represents the transconductance coefficient of the MOSFET structure, Represents the current gain of the MOSFET structure per unit width, represents the channel width of the MOSFET structure, represents the channel length of the MOSFET structure, Indicates the gate voltage connected, Represents the threshold voltage.

[0051] when When , it means that the electrical performance of the tested MOSFET structure is qualified;

[0052] when When , it means that the electrical performance of the tested MOSFET structure is unqualified.

[0053] Among them, in the calculation of the transconductance coefficient of the MOSFET structure, the channel width of the MOSFET structure is W=10μm, the channel length is L=1μm, the threshold voltage is Vth=0.5V, the process constant is k=400μA / V (representing the combination of electron mobility and gate oxide capacitance), and the gate-source voltage is VGS=1.5V; that is, the conversion units are: , , , , , then we have:

[0054]

[0055] From the above calculation, we can know that the transconductance coefficient of the MOSFET structure is The increment of the threshold voltage changing with temperature is (The increment of the threshold voltage with temperature = 0.7V at 25°C - 0.55V at 100°C), the increment of the switching time with temperature is (Unit: nanoseconds, the increment of switching time with temperature change = 35 nanoseconds at 100°C - 20 nanoseconds at 25°C). Then:

[0056]

[0057] From the above calculation, we can know that the qualified index coefficient of the electrical performance of the MOSFET structure in this test is , and compare multiple groups of data, there are:

[0058]

[0059] From the data in the above table, we can know that when the sample data tends to infinity, there will be an obvious electrical performance decomposition line about the qualified coefficient. When , it means that the electrical performance of the tested MOSFET structure is qualified; when When , it means that the electrical performance of the tested MOSFET structure is unqualified.

[0060] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A process for increasing the cell density of a double trench MOSFET, characterized in that: The following steps are involved: S1, forming an N substrate layer (2) and a drift layer (3) by injecting phosphorus elements of different concentrations into the semiconductor epitaxial layer; S2, continuing to form a P body region in the upper layer of the drift layer (3) by ion implantation of boron elements; S3, forming an N well layer (9) at the center of the P body region by ion implantation, and continuing to implant ions in the upper P body region to form a P well layer (8) and a P-well layer (10); S4, etching the surface of the semiconductor epitaxial layer through an etching process to form a rectangular groove; S5, depositing metal aluminum onto the inner walls of both sides of the rectangular groove and the upper surface of the P-well layer (8), thereby forming an L-shaped source (4), wherein the inner wall of the rectangular groove is the longitudinal part of the L-shaped source (4), and the upper surface of the P-well layer (8) is the lateral part of the L-shaped source (4); S6, filling the trench with a silicon dioxide insulating material, and etching the filled silicon dioxide insulating material to form a gate oxide layer (6); S7, depositing polysilicon material in the groove etched in the silicon dioxide insulating material to form a gate (7), and depositing silicon dioxide insulating material on the exposed surface of the gate (7); S8, depositing metal in the source region and the drain region to form a metal source cover sheet (5) and a drain (1); S9. Conduct electrical performance tests on the MOSFET structure, and package the MOSFET structure after passing the test.

2. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In step S1, the doping concentration of the N substrate layer (2) is ; The doping concentration of the drift layer (3) is .

3. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In step S3, the doping concentration of the P-well layer (8) is ; The doping concentration of the P-well layer (10) is .

4. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In the step S5, the L-type source (4) is in ohmic contact with both the P-well layer (8) and the N-well layer (9).

5. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In step S6, at a temperature of At ℃, silicon dioxide is deposited into the trench by chemical vapor deposition to form a gate oxide layer (6).

6. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In step S9, whether the electrical performance of the MOSFET structure is qualified is determined according to the increment of the threshold voltage changing with temperature after the MOSFET structure is connected to the gate voltage, the increment of the switching time changing with temperature, and the transconductance coefficient of the MOSFET structure, which are: In the formula, The qualified index coefficient that indicates the electrical performance of the MOSFET structure; Indicates the increment of threshold voltage changing with temperature, unit ; Indicates the increment of switching time with temperature change, unit ; Indicates the transconductance coefficient of the MOSFET structure, unit .

7. The process for increasing the cell density of a dual trench MOSFET according to claim 6, characterized in that: The transconductance coefficient of the MOSFET structure is determined based on the current gain of the MOSFET structure at unit width, the width-to-length ratio of the channel in the MOSFET structure, and the difference between the gate voltage and the threshold voltage. Then we have: In the formula, Represents the transconductance coefficient of the MOSFET structure; It represents the current gain of the MOSFET structure under unit width, unit ; Indicates the channel width of the MOSFET structure, in units ; Indicates the channel length of the MOSFET structure, in units ; Indicates the gate voltage connected, unit ; Indicates the threshold voltage, unit .

8. The process for increasing the cell density of a dual trench MOSFET according to claim 6, characterized in that: when When , it means that the electrical performance of the tested MOSFET structure is qualified; when When , it means that the electrical performance of the tested MOSFET structure is unqualified.

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