Switching drive apparatus

Abstract

This switching drive apparatus for supplying a drive voltage or a drive current to a gate terminal of a semiconductor element comprises: a first circuit that has a turn-on resistor and a first switching element, and that charges the gate terminal when the semiconductor element is turned on; a second circuit that has a turn-off resistor and a second switching element, and that discharges the gate terminal when the semiconductor element is turned off; a third circuit that is connected to the gate terminal, that has a gate resistor and a third switching element, and that discharges or charges the gate terminal; and a control device that controls turning-on / off of the first to third switching elements.

Description

Switching Drive Device

[0001] The present invention relates to a switching driver.

[0002] To reduce the size and increase the output density of power converters, it is necessary to reduce the loss of power semiconductors. However, there is a trade-off between the reduction in loss due to high-speed switching and the increase in surge voltage during switching. For this reason, a multi-stage gate resistor driver circuit has been known that increases the switching speed while suppressing surge voltage within an allowable voltage range (see, for example, Patent Document 1).

[0003] Japanese Patent Application Publication No. 2021-129396

[0004] The technology of Patent Document 1 aims to speed up switching via a P-type MOSFET (PMOS) in the charging circuit when turning on, and via an N-type MOSFET (NMOS) in the discharging circuit when turning off. However, there is a problem in that the provision of a PMOS and an NMOS increases the circuit size and circuit cost.

[0005] A switching driver according to an aspect of the present invention is a switching driver that supplies a drive voltage or drive current to a gate terminal of a semiconductor device, the switching driver comprising: a first circuit having a turn-on resistor and a first switching element and charging the gate terminal when the semiconductor device is turned on; a second circuit having a turn-off resistor and a second switching element and discharging the gate terminal when the semiconductor device is turned off; a third circuit connected to the gate terminal, having a gate resistor and a third switching element and discharging or charging the gate terminal; and a control device that controls the on / off of the first, second, and third switching elements. The control device, when the semiconductor device is turned on, controls charging by the first circuit and discharging or charging by the third circuit to perform a first turn-on operation mode, and then performs a second turn-on operation mode that is slower than the first turn-on operation mode. When the semiconductor device is turned off, the control device controls discharging by the second circuit and discharging or charging by the third circuit to perform a first turn-off operation mode, and then performs a second turn-off operation mode that is slower than the first turn-off operation mode.

[0006] According to the present invention, it is possible to provide a switching driver that can suppress surges and increase switching speed while keeping the circuit scale small.

[0007] FIG. 1 is a diagram illustrating a portion of the configuration of a power conversion device. FIG. 2 is a diagram illustrating details of a switching driver according to a first embodiment. (A), (B), (C), (D), (E), and (F) are diagrams illustrating example waveforms of each signal at turn-off in the first embodiment. (A), (B), (C), (D), (E), and (F) are diagrams illustrating example waveforms of each signal at turn-on in the first embodiment. FIG. 3 is a diagram illustrating a configuration for detecting the state of a power semiconductor in a switching driver. (a) shows the relationship between the time width at turn-off and the drain-source voltage, and (b) shows the relationship between the time width at turn-off and the drain-source current. (a), (b), and (c) are diagrams illustrating a method for setting the time width at turn-on. FIG. 4 is a diagram illustrating a modified example of the first embodiment. FIG. 5 is a diagram illustrating a switching driver according to a second embodiment. (A), (B), (C), (D), (E), and (F) are diagrams illustrating example waveforms of each signal at turn-off in the second embodiment. (A), (B), (C), (D), (E), and (F) are diagrams illustrating example waveforms of each signal at turn-on in the second embodiment. FIG. 10 is a diagram illustrating a switching driver according to a third embodiment.

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, identical or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the content described below merely shows an example of an embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0009] First Embodiment Fig. 1 is a diagram showing an application example of a switching drive device according to this embodiment, and is a diagram showing a portion of the configuration of a power conversion device. The power conversion device drives, for example, an electric motor mounted on an electric vehicle. The electric motor has a three-phase coil, and the power conversion device is provided with a three-phase switching arm for applying a predetermined current pattern to the three-phase coil. Fig. 1 shows a three-phase switching arm 500U, which is one phase of a three-phase switching arm 500U, 500V, 500W, provided in the power conversion device.

[0010] The three-phase switching arm 500U is provided with an upper arm power semiconductor 42 and a lower arm power semiconductor 41. For example, semiconductor elements such as IGBTs, Si-MOSFETs, and GaN-MOSFETs are used for the power semiconductors 41 and 42. Note that FIG. 1 shows a case where MOSFETs are used for the power semiconductors 41 and 42.

[0011] The power semiconductors 41 and 42 are provided with a high-voltage side terminal for the main circuit (a collector terminal for an IGBT, or a drain terminal for a MOSFET), a low-voltage side terminal for the main circuit (an emitter terminal for an IGBT, or a source terminal for a MOSFET), and a control terminal (a gate terminal). Note that multiple power semiconductors may be connected in parallel according to the desired output current value.

[0012] The positive wiring 52 on the upper arm side is connected to the positive terminal of a DC voltage source such as a battery (not shown). The negative wiring 51 on the lower arm side is connected to the negative terminal of the DC voltage source. The positive wiring 52 is connected to the high-voltage side terminal (drain terminal) for the main circuit of the power semiconductor 42. The low-voltage side terminal (source terminal) for the main circuit of the power semiconductor 42 is connected to the output terminal 53 of the three-phase switching arm 500U and the high-voltage side terminal (drain terminal) for the main circuit of the power semiconductor 41. The low-voltage side terminal (source terminal) for the main circuit of the power semiconductor 41 is connected to the negative wiring 51. The output terminal 53 is connected to a load such as an electric motor.

[0013] The gate terminal Gp and source terminal Sp of the power semiconductor 41 are connected to the gate terminal 13 and source terminal 14, respectively, of the gate driver 10 that supplies drive power to the power semiconductor 41. The gate terminal Gp and source terminal Sp of the power semiconductor 42 are connected to the gate terminal 13 and source terminal 14, respectively, of the gate driver 20 that supplies drive power to the power semiconductor 42.

[0014] The gate drive devices 10, 20 are connected to a control circuit 30. The control circuit 30 is configured, for example, by a microcomputer. The control circuit 30 outputs control commands to each of the gate drive devices 10, 20 based on drive commands input from a higher-level control device (not shown), and individually controls the on / off of each of the power semiconductors 41, 42. As a result, an AC voltage is output to a load such as an electric motor via an output terminal 53.

[0015] Fig. 2 is a diagram illustrating the details of a switching driver. The basic configuration of a switching driver is made up of either gate driver 10 or 20 and a control circuit 30, and the example shown in Fig. 2 shows switching driver 1 made up of gate driver 10 and control circuit 30. A switching driver made up of gate driver 20 and control circuit 30 has the same configuration as switching driver 1 shown in Fig. 2 and operates in the same way. The following description will be given using switching driver 1 as an example.

[0016] 2 is a diagram showing a power semiconductor 41 and a switching driver 1 corresponding to the power semiconductor 41, and shows details of the gate driver 10. The gate driver 20 in FIG. 1 has a similar configuration to the gate driver 10. The gate driver 10 includes a first charging circuit C1 having a switching element M1, a first discharging circuit C2 having a switching element M2, and a second discharging circuit C3 having a switching element M3. In the following explanation, an example will be described in which the power semiconductor 41 and switching elements M2 and M3 are N-type MOSFETs, and the switching element M1 is a P-type MOSFET.

[0017] The first charging circuit C1 includes a positive power supply V1, a switching element M1, an on-gate resistor R1, and a backflow prevention diode Di1. The source terminal S1 of the switching element M1 is connected to the positive power supply V1. The gate terminal G1 of the switching element M1 is connected to a signal terminal 11 of the gate driver 10. The drain terminal D1 of the switching element M1 is connected to one end of the on-gate resistor R1. The other end of the on-gate resistor R1 is connected to the anode of the backflow prevention diode Di1.

[0018] The first discharge circuit C2 includes a switching element M2, an off-gate resistor R2, and a backflow prevention diode Di2. A source terminal S2 of the switching element M2 is connected to a source terminal 14 of the gate driver 10. A gate terminal G2 of the switching element M2 is connected to a signal terminal 11 of the gate driver 10. A drain terminal D2 of the switching element M2 is connected to one end of the off-gate resistor R2. The other end of the off-gate resistor R2 is connected to the cathode of the backflow prevention diode Di2.

[0019] The second discharge circuit C3 includes a switching element M3 and a charge / discharge gate resistor R3. One end of the charge / discharge gate resistor R3 is connected to the gate terminal 13 of the gate driver 10. The other end of the charge / discharge gate resistor R3 is connected to the drain terminal D3 of the switching element M3. The source terminal S3 of the switching element M3 is connected to the source terminal 14 of the gate driver 10. The gate terminal G3 of the switching element M3 is connected to the signal terminal 12 of the gate driver 10.

[0020] The cathode of the reverse current prevention diode Di1 is connected to the anode of the reverse current prevention diode Di2, and is also connected to the gate terminal 13 of the gate driver 10 and one end of the charge / discharge gate resistor R3. The first discharge circuit C2 and the second discharge circuit C3 are connected in parallel to the gate terminal 13. Note that the reverse current prevention diodes Di1 and Di2 may be omitted.

[0021] Signal terminals 11 and 12 of the gate driver 10 are connected to the control circuit 30. A gate terminal 13 of the gate driver 10 is connected to a gate terminal Gp of the power semiconductor 41. A source terminal 14 of the gate driver 10 is connected to a source terminal Sp of the power semiconductor 41. In the example shown in FIG. 2 , the signal terminals 11 and 12 are connected to a common control circuit 30, but a configuration in which each signal terminal 11 and 12 is individually connected to two independently provided control circuits may also be used.

[0022] (Explanation of Operation at Turn-Off) FIG. 3 shows example waveforms of each signal when the power semiconductor 41 is turned off. Waveform (A) shows the voltage waveform of the signal terminal 11. Waveform (B) shows the voltage waveform of the signal terminal 12. Waveform (C) shows the voltage between the gate and source (GpSp) of the power semiconductor 41 (hereinafter referred to as the gate-source voltage Vgs). Waveform (D) shows the voltage between the drain and source (DpSp) of the power semiconductor 41 (hereinafter referred to as the drain-source voltage Vds). Waveform (E) shows the current flowing between the drain and source (DpSp) of the power semiconductor 41 (hereinafter referred to as the drain-source current Ids). Waveform (F) shows the waveform of the switching loss of the power semiconductor 41. Note that the waveforms indicated by dashed lines in FIG. 3 show signal waveforms in a configuration in which the second discharge circuit C3 is deleted from the circuit diagram shown in FIG. 2 (hereinafter referred to as the conventional configuration).

[0023] As shown by the solid line in waveform (A), at time t0, a control command to turn off power semiconductor 41 is input from control circuit 30 to signal terminal 11 of gate driver 10. That is, the voltage of signal terminal 11 is switched from L level to H level. When this signal is input to gate terminals G1 and G2 of switching elements M1 and M2, switching element M1, which is a P-type MOSFET, switches from ON to OFF, and switching element M2, which is an N-type MOSFET, switches from OFF to ON.

[0024] Furthermore, as shown in waveform (B), at time t0, a control command to switch switching element M3 from off to on is input to signal terminal 12. That is, the voltage of signal terminal 12 is switched from low to high. When this signal is input to gate terminal G3 of switching element M3, switching element M3, which is an N-type MOSFET, switches from off to on. Note that the timing at which the control command to switch on is input to signal terminal 12 may be later than time t0.

[0025] When switching element M2 is turned on (switching element M1 is turned off) at time t0, the gate-source capacitance of power semiconductor 41 starts to discharge from the gate terminal Gp of power semiconductor 41 in FIG. 2 via backflow prevention diode Di2, off-gate resistor R2, and switching element M2. Furthermore, when switching element M3 is turned on at time t0, the gate-source capacitance of power semiconductor 41 starts to discharge from the gate terminal Gp of power semiconductor 41 via charge-discharge gate resistor R3 and switching element M3. As a result, as shown by the solid line in waveform (C), the gate-source voltage Vgs of power semiconductor 41 starts to decrease.

[0026] When the gate-source voltage Vgs of the power semiconductor 41 reaches the mirror period at time t1, the drain-source voltage Vds of the power semiconductor 41 begins to increase, as shown by the solid line in waveform (D). In the case of a conventional configuration, as shown by the dashed line in waveform (C), the discharge time constant τ1 of the drain-source voltage Vds of the power semiconductor 41 is CR2, where C is the gate capacitance of the power semiconductor 41. In contrast, in this embodiment, as shown in waveform (B), the switching element M3 is also turned on at time t0, so the discharge time constant τ2 of the drain-source voltage Vds of the power semiconductor 41 is C(R2 / / R3). Note that R2 / / R3 represents the combined resistance of the parallel-connected resistors R2 and R3. Therefore, while the switching element M3 is on (t1 to t2), the discharge rate of the gate-source voltage Vgs of the power semiconductor 41 is accelerated, and the drain-source voltage Vds increases rapidly.

[0027] As shown in waveform (C), when the mirror period of the gate-source voltage Vgs ends at time t2, the current (drain-source current Ids) flowing between the drain and source of the power semiconductor 41 begins to decrease as shown in waveform (E). At this time t2, a control command to turn off the switching element M3 is input from the control circuit 30 to the signal terminal 12. That is, the voltage of the signal terminal 12 is switched from the H level to the L level. Note that the timing at which the OFF control command is input to the signal terminal 12 may be later than time t2. After time t2, the discharge time constant of the gate-source voltage Vgs of the power semiconductor 41 is CR2, which is the same as in the conventional configuration. Therefore, the drain-source surge voltage of the power semiconductor 41, which is related to the discharge time constant and occurs after time t2, is the same as in the conventional configuration.

[0028] The amount of switching loss of the power semiconductor 41 is expressed as the integrated sum of the drain-source voltage Vds of the power semiconductor 41 and the drain-source current Ids of the power semiconductor 41. As shown in waveform (F), in the case of the conventional configuration (dashed line), the off-gate resistance R2 is set large to suppress the drain-source voltage Vds of the power semiconductor 41 below the allowable voltage, and switching loss occurs from time t0 to time t3. On the other hand, in this embodiment, the discharge rate is increased by turning on the switching element M3 at time t0, and therefore, loss occurs in a shorter period from time t1 to time t3, as shown in waveform (F). As such, in this embodiment, the period during which switching loss occurs is shorter than in the case of the conventional configuration (dashed line), and therefore the amount of loss, which is the time integral of the loss, is also smaller than in the case of the conventional configuration. That is, in the first embodiment, the amount of switching loss at turn-off can be reduced compared to the case of the conventional configuration.

[0029] (Explanation of operation at turn-on) FIG. 4 is a diagram showing example waveforms of each signal when the power semiconductor 41 is turned on. Waveform (A) shows the voltage waveform of the signal terminal 11. Waveform (B) shows the voltage waveform of the signal terminal 12. Waveform (C) shows the gate-source voltage Vgs of the power semiconductor 41. Waveform (D) shows the drain-source voltage Vds of the power semiconductor 42 on the upper arm side shown in FIG. 1. Waveform (E) shows the drain-source current Ids of the power semiconductor 41. Waveform (F) shows the switching loss of the power semiconductor 41. As in the case of FIG. 3, the waveforms shown by dashed lines show signal waveforms in the case of a conventional configuration.

[0030] As shown by the solid line in waveform (A), at time t0, a control command to turn on the power semiconductor 41 is input from the control circuit 30 to the signal terminal 11 of the gate driver 10. That is, the voltage at the signal terminal 11 is switched from an H level to an L level. When this signal is input to the gate terminals G1 and G2 of the switching elements M1 and M2, the switching element M1 switches from OFF to ON, and the switching element M2 switches from ON to OFF. When the switching element M1 is turned on, the gate-source capacitance of the power semiconductor 41 in FIG. 2 is charged by a charging current flowing through the positive-side power supply V1, the switching element M1, the backflow prevention diode Di1, and the on-gate resistor R1. As a result, the gate-source voltage Vgs of the power semiconductor 41 begins to increase, as shown by the solid line in waveform (C).

[0031] At time t1, when the gate-source voltage Vgs of the power semiconductor 41 exceeds the threshold voltage Vth, as shown by the solid lines in waveforms (D) and (E), the drain-source voltage Vds of the power semiconductor 42 on the upper arm side in FIG. 1 begins to increase, and the drain-source current Ids of the power semiconductor 41 begins to increase. In other words, when the power semiconductor 41 on the lower arm side is turned on, the drain-source voltage Vds of the power semiconductor 41 decreases, and conversely, the drain-source voltage Vds of the power semiconductor 42 on the upper arm side, which is in the off state, increases.

[0032] As shown in waveform (B), at time t2, a control command to turn on switching element M3 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from L level to H level. Note that the timing at which the ON control command is input to signal terminal 12 may be earlier than time t2.

[0033] When the voltage at the signal terminal 12 rises to the H level at time t2, the switching element M3 turns on, and the gate-source capacitance of the power semiconductor 41 is discharged from the gate terminal Gp of the power semiconductor 41 via the charge-discharge gate resistor R3 and the switching element M3. As a result, when the switching element M3 is on, the gate-source voltage Vgs of the power semiconductor 41 converges to a voltage value determined by the ratio of the charge-discharge gate resistor R3 of the second discharge circuit C3 to the on-gate resistor R1 of the first charge circuit C1. As shown by the solid lines in waveforms (C) and (D), the gate-source voltage Vgs of the power semiconductor 41 is maintained constant from time t2 to time t3. As a result, the change in the drain-source current Ids of the power semiconductor 41 becomes gradual, and the increase in the drain-source voltage Vds of the upper-arm power semiconductor 42 is gradual and suppressed.

[0034] As shown in waveform (B), at time t3, a control command to turn off switching element M3 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from H level to L level. Note that the timing at which the OFF control command is input to signal terminal 12 may be later than time t3. As shown by the solid line in waveform (F), switching loss in power semiconductor 41 occurs from time t1 to time t4.

[0035] In the conventional configuration (dashed line), the on-gate resistance R1 is set large to suppress the drain-source voltage Vds of the upper arm power semiconductor 42 below the allowable voltage. In contrast, in this embodiment, the charging rate is slowed by turning on the switching element M3, suppressing the drain-source voltage Vds of the power semiconductor 42 below the allowable voltage. This allows the on-gate resistance R1 to be set smaller than in the conventional configuration, enabling a faster charging rate during the period when the switching element M3 is off. As a result, as shown in waveform (F), the period during which losses occur is shorter than in the conventional configuration (dashed line). In other words, in the first embodiment, the amount of switching loss at turn-on can be reduced compared to the conventional configuration.

[0036] (Control command generation method in control circuit 30) Next, a description will be given of a control command generation method in the control circuit 30. The control command from the control circuit 30 described above is preferably generated in accordance with the state of the power semiconductor 41. Fig. 5 shows a circuit configuration related to the switching driver 1, similar to the case of Fig. 2, and includes means for detecting the state of the power semiconductor 41.

[0037] 5, means for detecting the state of the power semiconductor 41 include an element current detection unit 61 that detects the drain-source current Ids of the power semiconductor 41, an element voltage detection unit 62 that detects the drain-source voltage Vds of the power semiconductor 41, and an element temperature detection unit 63 that detects the temperature Tj of the power semiconductor 41. A drive command S from a higher-level control device and state detection information (Ids, Vds, Tj) of each of the detection units 61 to 63 are input to the control circuit 30.

[0038] The control circuit 30 sends a control command to each of the signal terminals 11 and 12 of the gate driver 10 based on only the drive command S or on both the drive command S and the state detection information (Ids, Vds, Tj). Note that the state detection information for the power semiconductor 41 can be any information other than the above, such as the rising edge of the rate of change of the drain-source voltage Vds or the falling edge of the rate of change of the drain-source voltage Vds and the drain-source current Ids. In this way, the control circuit 30 can more appropriately control the switching operation of the power semiconductor 41 by generating a control command according to the detected state of the power semiconductor 41.

[0039] Although not shown, instead of the control circuit 30, a control circuit 30A that outputs a control command to the signal terminal 11 and a control circuit 30B that outputs a control command to the signal terminal 12 may be separately provided. The drive command S from the higher level and the state detection information (Ids, Vds, Tj) of the power semiconductor 41 are input separately to each of the control circuits 30A and 30B.

[0040] Next, control using the state detection information (Ids, Vds, Tj) will be described. Regarding the control command input to the signal terminal 12 of the gate driver 10 in FIG. 2, i.e., the H level of the voltage of the signal terminal 12 shown in waveform (B) in FIGS. 3 and 4, the duration of the H level is defined as Δt on. The duration Δt on may be set based on the drain-source voltage Vds of the power semiconductor 41 detected by the device voltage detector 62 in FIG. 5, or based on the drain-source current Ids detected by the device current detector 61. In this case, both the detection values ​​of the device voltage detector 62 and the device current detector 61 may be used, or only one of them may be used.

[0041] First, a method for generating a control command for the signal terminal 12 when the power semiconductor 41 is turned off will be described. The larger the time width Δt on in FIG. 3 , the faster the switching speed during turn-off. FIG. 6( a) illustrates a case in which the time width Δt on during turn-off is set based on the drain-source voltage Vds. As shown in FIG. 6( a), the larger the detected value of the element voltage detection unit 62, the smaller the time width Δt on is set, and the smaller the detected value, the larger the time width Δt on is set. In this case, a maximum value (Δt on_max) and a minimum value (Δt on_min) may be set for the time width Δt on. Furthermore, the value of the time width Δt on does not need to change linearly; a discrete value may be used. This setting is because the smaller the drain-source voltage Vds of the power semiconductor 41, the greater the voltage difference to the allowable voltage, thereby enabling faster switching. Setting the time width Δt on as shown in FIG. 6( a) enables high-speed switching over a wider range depending on the drain-source voltage Vds of the power semiconductor 41, thereby reducing switching losses.

[0042] FIG. 6B shows a case where the turn-off time width Δt on is set based on the drain-source current Ids. In this case, the larger the detection value of the device current detection unit 61, the smaller the time width Δt on is set, and the smaller the detection value of the device current detection unit 61, the larger the time width Δt on is set. In this case, a maximum value (Δt on_max) and a minimum value (Δt on_min) may be set for the time width Δt on. Furthermore, the value of the time width Δt on does not need to change linearly, and a discrete value may be used. The reason for setting the time width Δt on in this manner is that the smaller the drain-source current Ids of the power semiconductor 41, the larger the voltage difference to the allowable voltage, thereby enabling faster switching speeds. By setting the time width Δt on as shown in FIG. 6B, high-speed switching can be achieved over a wider range depending on the drain-source current Ids of the power semiconductor 41, thereby reducing switching losses.

[0043] Next, a method for generating a control command for the signal terminal 12 when the power semiconductor 41 is turned on will be described. The smaller the time width Δt on shown in waveform (B) in Figure 4, the faster the switching speed at turn-on. In Figure 4, the fall time of the time width Δt on of the voltage signal at the signal terminal 12 may be, for example, the turn-on end time of the power semiconductor 41, or a value obtained by adding or subtracting any time from the turn-on end time. In this case, the rise time of the time width Δt on is set to a value obtained by subtracting the time width Δt on from the fall time.

[0044] FIG. 7A illustrates a case in which the turn-on time duration Δt on is set based on the drain-source voltage Vds detected by the device voltage detection unit 62. In this case, the time duration Δt on is set to a larger value as the detection value of the device voltage detection unit 62 increases, and the time duration Δt on is set to a smaller value as the detection value decreases. A maximum value (Δt on_max) and a minimum value (Δt on_min) may be set for the time duration Δt on. Furthermore, the value of the time duration Δt on does not need to change linearly, and a discrete value may be used. The reason for setting the time duration Δt on in this manner is that the smaller the drain-source voltage Vds of the power semiconductor 41, the greater the voltage difference to the allowable voltage. Therefore, performing such a turn-on operation can further increase the switching speed. Setting the time duration Δt on as shown in FIG. 7A enables high-speed switching over a wider range depending on the drain-source voltage Vds of the power semiconductor 41, thereby reducing switching losses.

[0045] FIG. 7B illustrates a case in which the turn-on time width Δt on is set based on the drain-source current Ids detected by the device current detection unit 61. In this case, the time width Δt on is set to a larger value as the detection value of the device current detection unit 61 increases, and the time width Δt on is set to a smaller value as the detection value of the device current detection unit 61 decreases. In this case, a maximum value (Δt on_max) and a minimum value (Δt on_min) may be set for the time width Δt on. Furthermore, the value of the time width Δt on does not need to change linearly, and a discrete value may be used. The reason for setting the time width Δt on in this manner is that the smaller the drain-source current Ids of the power semiconductor 41, the larger the voltage difference to the allowable voltage. Therefore, performing such a turn-on operation can further increase the switching speed. Setting the time width Δt on as shown in FIG. 7B enables high-speed switching over a wider range depending on the drain-source current Ids of the power semiconductor 41, thereby reducing switching loss.

[0046] FIG. 7C illustrates a case in which the turn-on time width Δt on is set based on the temperature Tj of the power semiconductor 41 detected by the element temperature detection unit 63. In this case, the time width Δt on is set to a larger value as the temperature Tj increases, and the time width Δt on is set to a smaller value as the temperature Tj decreases. A maximum value (Δt on_max) and a minimum value (Δt on_min) may be set for the time width Δt on. Furthermore, the value of the time width Δt on does not need to change linearly, and a discrete value may be used. The reason for setting the time width Δt on in this manner is that the lower the temperature Tj of the power semiconductor 41, the greater the voltage difference to the allowable voltage. Therefore, performing such a turn-on operation can further increase the switching speed. Setting the time width Δt on as shown in FIG. 7C enables high-speed switching over a wider range depending on the temperature Tj of the power semiconductor 41, thereby reducing switching losses.

[0047] (Modification) FIG. 8 is a diagram showing a modification of the first embodiment described above. In the modification shown in FIG. 8, the second discharge circuit C3 is configured with two discharge circuits connected in parallel. One of the parallel-connected discharge circuits includes a charge / discharge gate resistor 3R and a switching element M3, and the other includes a charge / discharge gate resistor 5R and a switching element M5. In the example shown in FIG. 8, the charge / discharge gate resistors 3R and 5R are variable resistors, but they do not have to be variable resistors. Note that the number of parallel-connected discharge circuits in the second discharge circuit C3 may be three or more.

[0048] The values ​​of the charge / discharge gate resistors 3R and 5R may be determined in response to a control command from the control circuit 30, or may be determined using the detected values ​​of the device current detector 61, device voltage detector 62, and device temperature detector 63 shown in FIG. 5. In the configuration of FIG. 8, for example, turning on all of the switching devices M2, M3, and M5 during turn-off can further increase the speed. Note that, in the case of the second discharge circuit C3 shown in FIG. 2, by using a variable resistor as the charge / discharge gate resistor R3, the value of the variable resistor can be controlled in accordance with the device temperature Tj, for example, to more appropriately control charge and discharge.

[0049] Second Embodiment Fig. 9 is a diagram illustrating a switching driver 1 according to a second embodiment of the present invention. The switching driver 1 shown in Fig. 9 includes a control circuit 30 and a gate driver 10A that sends drive power to a power semiconductor 41. Although not shown, the switching driver for the power semiconductor 42 on the upper arm side also includes a gate driver having a configuration similar to that of the gate driver 10A.

[0050] The gate driver 10A includes a first charging circuit C1 having a switching element M1, a first discharging circuit C2 having a switching element M2, and a second charging circuit C4 having a switching element M4. In the following explanation, an example will be given in which the power semiconductor 41 and the switching element M2 are N-type MOSFETs, and the switching elements M1 and M4 are P-type MOSFETs.

[0051] The first charging circuit C1 and the first discharging circuit C2 of the gate driver 10A have the same configuration as the first charging circuit C1 and the first discharging circuit C2 of the gate driver 10 shown in FIG. 2. The second charging circuit C4 includes a switching element M4 and a charge / discharge gate resistor R4. The source terminal S4 of the switching element M4 is connected to the positive power supply V2. The gate terminal G4 of the switching element M4 is connected to a signal terminal 12 of the gate driver 10A. The drain terminal D4 of the switching element M4 is connected to one end of the charge / discharge gate resistor R4. The other end of the charge / discharge gate resistor R4 is connected to the gate terminal 13 of the gate driver 10A.

[0052] The cathode of the reverse current prevention diode Di1 is connected to the anode of the reverse current prevention diode Di2, and is also connected to the gate terminal 13 of the gate driver 10A and the other end of the charge / discharge gate resistor R4. The first charging circuit C1 and the second charging circuit C4 are connected in parallel to the gate terminal 13. Note that the reverse current prevention diodes Di1 and Di2 may be omitted.

[0053] The signal terminals 11 and 12 of the gate driver 10A are connected to the control circuit 30. The gate terminal 13 of the gate driver 10A is connected to the gate terminal Gp of the power semiconductor 41. The source terminal 14 of the gate driver 10A is connected to the source terminal Sp of the power semiconductor 41. In the example shown in FIG. 9 , the signal terminals 11 and 12 are connected to a common control circuit 30, but the signal terminals 11 and 12 may be connected to two independently provided control circuits. The potentials of the positive-side power supplies V1 and V2 may be different, but are generally set to the same potential, and in this embodiment, a case where they are set to the same potential will be described as an example.

[0054] (Explanation of operation at turn-off) FIG. 10 is a diagram showing example waveforms of each signal when the power semiconductor 41 is turned off. Waveform (A) shows the voltage waveform of the signal terminal 11. Waveform (B) shows the voltage waveform of the signal terminal 12. Waveform (C) shows the gate-source voltage Vgs of the power semiconductor 41. Waveform (D) shows the drain-source voltage Vds of the power semiconductor 41. Waveform (E) shows the drain-source current Ids of the power semiconductor 41. Waveform (F) shows the waveform of the switching loss of the power semiconductor 41. Note that the waveforms shown by dashed lines in FIG. 10 show signal waveforms in the case of a conventional configuration in which the second charging circuit C4 is deleted from the circuit diagram shown in FIG. 9.

[0055] As shown by the solid line in waveform (A), at time t0, a control command to turn off power semiconductor 41 is input from control circuit 30 to signal terminal 11 of gate driver 10. That is, the voltage of signal terminal 11 is switched from L level to H level. When this signal is input to gate terminals G1 and G2 of switching elements M1 and M2, switching element M1, which is a P-type MOSFET, switches from ON to OFF, and switching element M2, which is an N-type MOSFET, switches from OFF to ON.

[0056] When switching element M2 is turned on (switching element M1 is turned off) at time t0, discharge of the gate-source capacitance of power semiconductor 41 starts from the gate terminal Gp of power semiconductor 41 via backflow prevention diode Di2, off-gate resistor R2, and switching element M2. As a result, as shown by the solid line in waveform (C), the gate-source voltage Vgs of power semiconductor 41 starts to decrease.

[0057] As described in the first embodiment, in the case of the conventional configuration (dashed line), the value of the off-gate resistor R2 is set large to suppress the drain-source voltage Vds of the power semiconductor 41 below the allowable voltage. On the other hand, in the second embodiment, the value of the off-gate resistor R2 of the first discharge circuit C2 is set smaller than that of the conventional configuration. For example, in the example shown in FIG. 10 , the value of the off-gate resistor R2 is set so that the discharge time constant of the gate-source voltage Vgs from time t0 to time t1 is the same as the time constant τ2 shown in FIG. 3 . Therefore, the slope of the solid line of the gate-source voltage Vgs from time t0 to time t1 in FIG. 10 is the same as the slope of the solid line from time t0 to time t1 in waveform (C) in FIG. 3 .

[0058] When the gate-source voltage Vgs of the power semiconductor 41 reaches the mirror period at time t1, the drain-source voltage Vds of the power semiconductor 41 begins to increase, as shown by the solid line in waveform (D). When the mirror period for the gate-source voltage Vgs of the power semiconductor 41 ends at time t2, as shown by the solid line in waveform (C), the drain-source current Ids of the power semiconductor 41 begins to decrease, as shown in waveform (E).

[0059] As shown in waveform (B), at time t21, a control command to turn on switching element M4 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from H level to L level. Note that the timing (time t21) at which the ON control command is input to signal terminal 12 may be later than time t2.

[0060] When the switching element M4 is turned on at time t21, a charging current flows through the positive-side power supply V2, the switching element M4, and the charge / discharge gate resistor R4. As a result, when the switching element M4 is on, the gate-source voltage Vgs of the power semiconductor 41 converges to a voltage value determined by the ratio of the charge / discharge gate resistor R4 of the second charging circuit C4 to the off-gate resistor R2 of the first discharging circuit C2. In this way, by turning on the switching element M4 while discharging is being performed in the first discharging circuit C2, the discharge rate is slowed down, and the drain-source voltage Vds of the power semiconductor 41 is suppressed to an allowable voltage or less.

[0061] Therefore, as described above, it is possible to set the value of off-gate resistor R2 smaller than in the conventional configuration, and the discharge rate during the period when switching element M3 is off can be made faster than in the conventional configuration. As a result, as shown by the solid line in waveform (F), the period during which loss occurs is shorter than in the conventional configuration (dashed line) in which off-gate resistor R2 is made larger. In other words, the second embodiment also allows for a reduction in switching loss during turn-off compared to the conventional configuration.

[0062] In the example shown in Figure 10, the timing when an OFF control command is input to the signal terminal 12, i.e., the timing when it switches from L level to H level, time t3, may be simultaneous with time t3 when the drain-source current Ids becomes zero, or may be later than time t3.

[0063] (Explanation of operation at turn-on) FIG. 11 is a diagram showing example waveforms of each signal when the power semiconductor 41 is turned on. Waveform (A) shows the voltage waveform of the signal terminal 11. Waveform (B) shows the voltage waveform of the signal terminal 12. Waveform (C) shows the gate-source voltage Vgs of the power semiconductor 41. Waveform (D) shows the drain-source voltage Vds of the power semiconductor 42 on the upper arm side shown in FIG. 1. Waveform (E) shows the drain-source current Ids of the power semiconductor 41. Waveform (F) shows the switching loss of the power semiconductor 41. In addition, the waveforms shown by dashed lines show signal waveforms in the case of a conventional configuration in which the second charging circuit C4 is deleted from the circuit diagram shown in FIG. 9.

[0064] As shown in waveform (A), at time t0, a control command to turn on the power semiconductor 41 is input from the control circuit 30 to the signal terminal 11 of the gate driver 10. That is, the voltage of the signal terminal 11 is switched from H level to L level. When this signal is input to the gate terminals G1 and G2 of the switching elements M1 and M2, the switching element M1 switches from OFF to ON, and the switching element M2 switches from ON to OFF. When the switching element M1 turns ON (the switching element M2 turns OFF) at time t0, a charging current flows via the positive-side power supply V1, the switching element M1, the backflow prevention diode Di1, and the on-gate resistor R1.

[0065] Furthermore, as shown in waveform (B), at time t0, a control command to switch switching element M4 from off to on is input from control circuit 30 to signal terminal 12. That is, the voltage at signal terminal 12 is switched from H level to L level. When switching element M4 is turned on at time t0, a charging current flows via positive-side power supply V2, switching element M4, and charge / discharge gate resistor R4. Note that the timing at which the on control command is input to signal terminal 12 may be later than time t0.

[0066] When charging is performed using only the first charging circuit C1, as in the conventional configuration without the second charging circuit C4, the charging time constant τ3 of the drain-source voltage Vds of the power semiconductor 41 is CR1, where C is the gate capacitance of the power semiconductor 41. In contrast, in the second embodiment, charging is performed using the first charging circuit C1 and the second charging circuit C4 connected in parallel, so the charging time constant τ4 of the drain-source voltage Vds of the power semiconductor 41 is C(R1 / / R4). R1 / / R4 represents the combined resistance of the parallel-connected resistors R1 and R4. Therefore, while the switching element M4 is on, the charging speed of the gate-source voltage Vds of the power semiconductor 41 is increased, and the drain-source voltage Vds increases more rapidly than in the conventional configuration.

[0067] As shown by the solid line in waveform (C), at time t1, when the gate-source voltage Vgs of the power semiconductor 41 exceeds the threshold voltage (Vth), the drain-source voltage Vds of the power semiconductor 42 on the upper arm side begins to increase, and the drain-source current Ids of the power semiconductor 41 also begins to increase, as shown by the solid lines in waveforms (D) and (E).

[0068] As shown in waveform (B), at time t2, a control command to turn off switching element M4 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from L level to H level. Note that the timing at which the OFF control command is input to signal terminal 12 may be later than time t2. After time t2, the charging time constant of gate-source voltage Vgs of power semiconductor 41 becomes CR1, the same as in the conventional configuration. Therefore, the drain-source surge voltage of power semiconductor 41 related to the charging time constant, which occurs after time t2, becomes the same as in the conventional configuration.

[0069] As shown by the solid line in the waveform (F), the switching loss of the power semiconductor 41 occurs between time t1 and time t4, and the loss period can be made shorter compared to the case of the conventional configuration (dashed line) in which the on-gate resistance R1 is increased to suppress the drain-source voltage Vds of the power semiconductor 42 in the paired arm. That is, in the second embodiment as well, the amount of switching loss at turn-on can be reduced compared to the case of the conventional configuration.

[0070] After time t3, as shown in waveform (B), a control command to turn on switching element M4 may be input from control circuit 30 to signal terminal 12 to perform high-speed switching. As a result, when switching element M4 is on, the gate-source voltage Vgs rises at a high speed as shown in waveform (C), so the turn-on operation is accelerated and the amount of switching loss in power semiconductor 41 is further reduced.

[0071] In the second embodiment, the configuration including the element current detector 61, the element voltage detector 62, and the element temperature detector 63 shown in FIG. 5 can also be applied.

[0072] Third Embodiment FIG. 12 is a diagram showing a switching driver 1 according to a third embodiment. While the gate driver 10 shown in FIG. 2 is a voltage-driven gate driver, the gate driver 10B shown in FIG. 12 shows an example in which the voltage-driven gate driver has been changed to a constant-current-driven gate driver. The switching elements M1, M2, and M3 have been replaced with constant-current-driven switching elements. Note that while FIG. 12 shows a system using an operational amplifier, the system does not necessarily have to use an operational amplifier. A control command is input from the control circuit 30 to the positive input terminal of each operational amplifier via signal terminals 11, 12, and 15 of the gate driver 10B.

[0073] Furthermore, instead of using constant current drive types for all of the switching elements M1, M2, and M3, it is also possible to use a combination of voltage drive and constant current drive types. For example, if it is desired to use constant current drive type for turn-off and voltage drive type for turn-on, the switching elements M2 and M3 can be configured as shown in FIG. 12, and the switching element M1 can be configured as shown in FIG. 2. In the case of a voltage drive type, the circuit configuration is simple, but the amount of current varies depending on the load. On the other hand, a constant current drive type is easy to control because the current is constant, but the circuit configuration is somewhat more complicated than that of a voltage drive type.

[0074] 12 shows the configuration of FIG. 2 in which the voltage-driven switching elements M1, M2, and M3 are replaced with constant-current-driven switching elements, but constant-current-driven switching elements can also be applied to the configuration of FIG. 9.

[0075] According to the embodiment and modified examples of the present invention described above, the following advantageous effects are achieved.

[0076] (1) As shown in Figures 2 to 4, 9 to 12, etc., a switching drive device 1 that supplies a drive voltage or drive current to a gate terminal Gp of a power semiconductor 41 includes: a first circuit (first charging circuit C1) that has a turn-on resistor R1 and a first switching element M1 and charges the gate terminal Gp when the power semiconductor 41 is turned on; a second circuit (first discharging circuit C2) that has a turn-off resistor R2 and a second switching element M2 and discharges the gate terminal Gp when the power semiconductor 41 is turned off; a third circuit (second discharging circuit C3 or second charging circuit C4) that is connected to the gate terminal Gp and has a gate resistor (charge-discharge gate resistor R3 or R4) and a third switching element M3 or M4 and discharges or charges the gate terminal Gp; and a control device (control circuit 30) that controls the on / off of the first to third switching elements M1 to M4.

[0077] Then, when the power semiconductor 41 is turned on, the control circuit 30 controls charging by the first circuit (first charging circuit C1) and charging or discharging by the third circuit (second discharging circuit C3 or second charging circuit C4) to execute a first turn-on operation mode from time t0 to t2 in FIG. 4 or FIG. 11, and then executes a second turn-on operation mode from time t2 to t3 in FIG. 4 or from time t2 to t3 in FIG. 11, which is slower than the first turn-on operation mode. By executing the first and second turn-on operation modes in this manner, it is possible to shorten the period during which switching loss occurs in the power semiconductor 41 while suppressing surge voltage at turn-on. As a result, the amount of switching loss at turn-on can be reduced.

[0078] Furthermore, when the power semiconductor 41 is turned off, the discharging by the second circuit (first discharging circuit C2) and the discharging or charging by the third circuit (second discharging circuit C3 or second charging circuit C4) are controlled to execute a first turn-off operation mode from time t0 to t2 in FIG. 3 or from time t0 to t21 in FIG. 10, and then execute a second turn-off operation mode from time t2 to t3 in FIG. 3 or from time t21 to t3 in FIG. 10, which is slower than the first turn-off operation mode. By executing the first and second turn-off operation modes in this manner, it is possible to shorten the period during which switching loss occurs in the power semiconductor 41 while suppressing surge voltage during turn-off. As a result, the amount of switching loss during turn-off can be reduced.

[0079] As described above, the switching drive device 1 can suppress surges and reduce switching losses at turn-on and turn-off while suppressing cost increases simply by adding a third circuit (second discharge circuit C3 or second charge circuit C4) to the first circuit (first charge circuit C1) and the second circuit (first discharge circuit C2).

[0080] (2) In (1) above, as shown in Figures 2 and 12, the third circuit is a second discharge circuit C3 provided in parallel with the first discharge circuit C2 (second circuit). In the first turn-on operation mode from time t0 to t2 in Figure 4, charging is performed by the first charging circuit C1 (first circuit), and in the second turn-on operation mode from time t2 to t3, charging is performed by the first charging circuit C1 and discharging is performed by the second discharging circuit C3. In the first turn-off operation mode from time t0 to t2 in Figure 3, discharging is performed by the first discharging circuit C2 and the second discharging circuit C3, and in the second turn-off operation mode from time t2 to t3, discharging is performed by the first discharging circuit C2.

[0081] In the switching driver 1 shown in Figures 2 and 12, in the second turn-on operation mode shown in Figure 4, charging is performed by the first charging circuit C1 while discharging by the second discharging circuit C3 is performed, thereby suppressing surges due to slower charging. This allows the on-gate resistor R1 to be set smaller than in the conventional case. As a result, the charging rate in the first turn-on operation mode can be increased compared to the conventional case, thereby reducing switching loss during turn-on. Furthermore, in the first turn-off operation mode shown in Figure 3, discharging is performed by the first discharging circuit C2 and the second discharging circuit C3. This causes the discharge time constant τ2 of the drain-source voltage Vds of the power semiconductor 41 to become C(R2 / / R3), thereby increasing the discharge rate of the gate-source voltage Vds of the power semiconductor 41. As a result, the period during which switching loss occurs is shorter than in the conventional case, thereby reducing switching loss during turn-off.

[0082] (3) In (1) above, as shown in Fig. 9, the third circuit is a second charging circuit C4 provided in parallel with the first charging circuit C1 (first circuit). In the first turn-on operation mode from time t0 to t2 in Fig. 11, charging is performed by the first charging circuit C1 and by the second charging circuit C4, and in the second turn-on operation mode from time t2 to t3, charging is performed by the first charging circuit C1. In the first turn-off operation mode from time t0 to t21 in Fig. 10, discharging is performed by the first discharging circuit C2, and in the second turn-off operation mode from time t21 to t3, discharging is performed by the first discharging circuit C2 and charging is performed by the second charging circuit C4.

[0083] In the switching driver 1 of FIG. 9 , in the first turn-on operation mode from time t0 to t2 in FIG. 11 , charging is performed by the first charging circuit C1 and the second charging circuit C4, so the charging time constant τ4 of the drain-source voltage Vds of the power semiconductor 41 is C(R1 / / R4). This increases the discharge rate of the gate-source voltage Vds of the power semiconductor 41, shortening the period during which switching losses occur compared to conventional devices, thereby reducing the amount of switching loss during turn-on. Furthermore, in the second turn-off operation mode shown in FIG. 10 , the discharge rate is slowed by turning on the switching element M4 while discharging is being performed by the first discharging circuit C2, allowing the off-gate resistor R2 to be set smaller than conventional devices. As a result, the discharge rate in the first turn-off operation mode is increased, shortening the period during which switching losses occur compared to conventional devices, thereby reducing the amount of switching loss during turn-off.

[0084] (4) In the above (1), when the third circuit is the second discharge circuit C3 that discharges as shown in Fig. 2, after the second turn-on operation mode is executed, the first turn-on operation mode in which charging is performed by the first charging circuit C1 (first circuit) is executed again as shown after time t3 in Fig. 4. Also, when the third circuit is the second charging circuit C4 that charges as shown in Fig. 9, after the second turn-off operation mode in Fig. 10 is executed, the first turn-off operation mode in which discharging is performed by the first discharge circuit C2 (second circuit) is executed again as shown after time t3 in Fig. 10. By performing such control, the switching operation of the power semiconductor 41 can be performed at higher speed.

[0085] (5) In the above (1), as shown in Fig. 5 etc., detection units (element current detection unit 61, element voltage detection unit 62, element temperature detection unit 63) that detect at least one of the voltage Vds, current Ids, and temperature Tj of the power semiconductor 41 are further provided, and the control circuit 30 controls the on / off of the third switching element M3 based on the detection information (voltage Vds, current Ids, and temperature Tj) of the detection units. In this way, by controlling the on / off of the third switching element M3 in accordance with the detected state of the power semiconductor 41, the switching operation of the power semiconductor 41 can be more appropriately controlled.

[0086] (6) For example, in the above (2), the discharge period (time duration Δt on ) by the third circuit (second discharge circuit C3) in the first turn-off operation mode from time t0 to t2 in FIG. 3 is set to be longer as the input voltage (drain-source voltage Vds) of the power semiconductor 41 or the drain-source current Ids flowing through the power semiconductor 41 becomes lower, as shown in FIGS. 6( a) and 6(b).

[0087] (7) For example, in the above (2), the discharge period (time duration Δt on ) by the third circuit (second discharge circuit C3) in the second turn-on operation mode from time t2 to t3 in FIG. 4 is set to be longer as the input voltage Vds of the power semiconductor 41, the drain-source current Ids flowing through the power semiconductor 41, or the device temperature Tj of the power semiconductor 41 increases, as shown in FIG. 7 .

[0088] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these details as long as the features of the invention are not impaired. Furthermore, although various embodiments and modifications have been described above, the present invention is not limited to these details. Other aspects conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0089] 1...Switching drive device, 10, 10A, 10B, 20...Gate drive device, 30...Control circuit, 41, 42...Power semiconductor, 51...Negative wiring, 52...Positive wiring, 53...Output terminal, 61...Element current detection unit, 62...Element voltage detection unit, 63...Element temperature detection unit, C1...First charging circuit, C2...First discharging circuit, C3...Second discharging circuit, Di1, Di2...Backflow prevention diode, M1, M2, M3, M4, M5...Switching element, R1...On gate resistor, R2...Off gate resistor, R3, R4, R5...Charge / discharge gate resistor, V1, V2...Positive side power supply, Δt on...Time width

Claims

1. A switching driver that supplies a drive voltage or drive current to a gate terminal of a semiconductor element, comprising: a first circuit having a turn-on resistor and a first switching element, and charging the gate terminal when the semiconductor element is turned on; a second circuit having a turn-off resistor and a second switching element, and discharging the gate terminal when the semiconductor element is turned off; a third circuit connected to the gate terminal, having a gate resistor and a third switching element, and discharging or charging the gate terminal; and a control device that controls the on / off of the first to third switching elements, wherein the control device: when the semiconductor element is turned on, controls the charging by the first circuit and the discharging or charging by the third circuit to execute a first turn-on operation mode, and then executes a second turn-on operation mode that is slower than the first turn-on operation mode; and when the semiconductor element is turned off, controls the discharging by the second circuit and the discharging or charging by the third circuit to execute the first turn-off operation mode, and then executes the second turn-off operation mode that is slower than the first turn-off operation mode.

2. A switching drive device as claimed in claim 1, wherein the third circuit is a discharge circuit provided in parallel with the second circuit, and in the first turn-on operation mode, charging is performed by the first circuit, in the second turn-on operation mode, charging is performed by the first circuit and discharging is performed by the third circuit, in the first turn-off operation mode, discharging is performed by the second circuit and discharging is performed by the third circuit, and in the second turn-off operation mode, discharging is performed by the second circuit.

3. A switching drive device as claimed in claim 1, wherein the third circuit is a charging circuit provided in parallel with the first circuit, and in the first turn-on operation mode, charging is performed by the first circuit and by the third circuit, in the second turn-on operation mode, charging is performed by the first circuit, in the first turn-off operation mode, discharging is performed by the second circuit, and in the second turn-off operation mode, discharging is performed by the second circuit and charging is performed by the third circuit.

4. A switching drive device as claimed in claim 1, wherein, when the third circuit is a circuit which performs discharging, after executing the second turn-on operation mode, the first turn-on operation mode is executed again, and when the third circuit is a circuit which performs charging, after executing the second turn-off operation mode, the first turn-off operation mode is executed again.

5. A switching drive device as claimed in claim 1, further comprising a detection unit which detects at least one of the voltage, current and temperature of the semiconductor element, and the control device controls the on / off of the third switching element based on the detection information of the detection unit.

6. A switching driver according to claim 2, wherein the discharge period by said third circuit in said first turn-off operation mode is set to be longer as the input voltage to said semiconductor element or the current flowing through said semiconductor element becomes lower.

7. A switching drive device as claimed in claim 2, wherein the discharge period by said third circuit in said second turn-on operation mode is set to be longer as the input voltage to said semiconductor element, the current flowing through said semiconductor element, or the device temperature of said semiconductor element increases.

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