Display driving device, display device comprising same, and operating method thereof

Abstract

A display driving device of the present invention, which can prevent damage to a source driver IC and pixels during a bidirectional driving operation, comprises: a first source driver IC disposed on one side of a display panel and connected to one end of a first data line; and a second source driver IC disposed on the other side of the display panel and connected to the other end of the first data line, wherein the first and second source driver ICs include: an amplifier connected to the first data line; a control signal generating circuit for generating a charge sharing control signal when an operation control signal indicates a charge sharing operation, and generating a precharge control signal when the operation control signal indicates a precharge operation; and a switch circuit for connecting the first data line and a second data line adjacent to the first data line to each other in response to the charge sharing control signal, and supplying a predetermined precharge voltage to the first data line in response to the precharge control signal.

Description

Display driving device, display device including same, and operating method thereof

[0001] The present invention relates to a source driver IC, and more particularly, to a source driver IC having a bidirectional driving structure.

[0002] A display driver IC (DDI) is a display driving chip that controls the pixels that make up an organic light emitting diode (OLED) display or a liquid crystal display (LCD) to enable the implementation of various colors. Each pixel includes sub-pixels that display red, green, and blue colors, and the DDI controls the operation of the transistors connected to each of the sub-pixels.

[0003] A DDI may include a gate driver IC and a source driver IC.

[0004] The gate driver IC controls the on / off operation of the red subpixel, green subpixel, and blue subpixel through an on or off driving signal converted into an analog voltage. The source driver IC controls the pixel so that it can display the desired gradation by supplying an image signal to each pixel for color implementation through the data line connected to the pixel.

[0005] As display devices have become larger in size, the length of data lines has increased, leading to a recognized problem of varying voltage drop (IR-Drop) depending on the location on a single data line. To address this, a bidirectional driving structure has been proposed, which simultaneously drives the display panel from both the top and bottom, by arranging source driver ICs so that they are each connected to a single data line at the top and bottom of the display panel.

[0006] However, there is a problem that if an output difference occurs between the upper source driver IC and the lower source driver IC during a bidirectional driving operation by the source driver ICs arranged at the top and bottom of the display panel, or if either the upper source driver IC or the lower source driver IC does not operate, the pixel connected to the data line or the source driver IC may be damaged due to overcurrent.

[0007] The present invention is intended to solve the above-described problems, and its technical task is to provide a display driving device capable of preventing damage to a source driver IC and pixels during a bidirectional driving operation, a display device including the same, and an operating method thereof.

[0008] According to an aspect of the present invention for achieving the above-described technical problem, a display driving device includes: a first source driver IC disposed on one side of a display panel and connected to one end of a first data line; and a second source driver IC disposed on the other side of the display panel and connected to the other end of the first data line, wherein the first and second source driver ICs include an amplifier connected to the first data line; a control signal generation circuit that generates a charge share control signal when an operation control signal received from an external device indicates a charge share operation and generates a precharge control signal when the operation control signal indicates a precharge operation; and a switch circuit that connects the first data line and a second data line adjacent to the first data line to each other in response to the charge share control signal and supplies a predetermined precharge voltage to the first data line in response to the precharge control signal.

[0009] According to another aspect of the present invention for achieving the above-described technical problem, a display device includes a display panel including a plurality of pixels and a plurality of data lines connected to each of the pixels; a first group of source driver ICs arranged on one side of the display panel and connected to one end of the data lines to drive the data lines; a second group of source driver ICs arranged on the other side of the display panel and connected to the other end of the data lines to drive the data lines; and a timing controller for generating an operation control signal for operating the first group of source driver ICs and the second group of source driver ICs in one of a data output operation, a charge sharing operation, and a pre-charge operation, wherein each of the first group of source driver ICs and the second group of source driver ICs comprises: amplifiers respectively connected to each data line; A control signal generation circuit that receives the above-described operation control signal and generates a transmission control signal when the operation control signal instructs data output, generates a charge sharing control signal when the operation control signal instructs a charge sharing operation, and generates a precharge control signal when the operation control signal instructs a precharge operation; and a switch circuit that connects each amplifier to a corresponding data line in response to the above-described transmission control signal, connects adjacent data lines to each other in response to the charge sharing control signal, and supplies a predetermined precharge voltage to each data line in response to the precharge control signal.

[0010] According to another aspect of the present invention for achieving the above-described technical problem, a method for operating a display driving device is provided, comprising: a step of receiving an operation control signal; a step of generating a charge sharing control signal when the operation control signal instructs a charge sharing operation and a step of generating a precharge control signal when the operation control signal instructs a precharge operation; a step of performing the charge sharing operation of connecting the first data line and a second data line adjacent to the first data line to each other in response to the charge sharing control signal; and a step of performing the precharge operation of forcibly supplying a predetermined precharge voltage to the first data line in response to the precharge control signal.

[0011] According to the present invention, the source driver ICs connected to the upper and lower ends of a data line respectively selectively perform either a charge sharing operation or a precharge operation for the data line connected to the source driver ICs during a horizontal blank period, thereby reducing the difference in output signals at both ends of the data line, thereby preventing damage to the source driver IC and pixels.

[0012] FIG. 1 is a block diagram of a display device according to one embodiment of the present invention.

[0013] Figures 2 and 3 are detailed block diagrams of the display device illustrated in Figure 1.

[0014] FIG. 4 is a timing diagram of signals for explaining the operation of the display device shown in FIGS. 2 and 3.

[0015] FIG. 5 is a drawing showing the arrangement of switches when a data output operation is performed in the display device illustrated in FIGS. 2 and 3.

[0016] FIG. 6 is a drawing showing the arrangement of switches when a charge sharing operation is performed in the display device illustrated in FIGS. 2 and 3.

[0017] FIG. 7 is a drawing showing the arrangement of switches during a precharge operation performed in the display device illustrated in FIGS. 2 and 3.

[0018] FIG. 8 is a flowchart for explaining the operation of the display device illustrated in FIGS. 1 to 6.

[0019] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0020] Throughout the specification, identical reference numbers refer to substantially identical components. In the following description, detailed descriptions of components and functions not related to the core components of the present invention and those known in the art may be omitted.

[0021] In this specification, when the terms "includes," "has," and "consists of," are used, other parts may be added, unless "only" is used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0022] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0023] While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0024] The term "at least one" should be understood to include all possible combinations of one or more associated items. For example, "at least one of the first, second, and third items" can mean any combination of items that can be represented by two or more of the first, second, and third items, as well as each of the first, second, and third items.

[0025] The individual features of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical linkages and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0026] Before describing embodiments of the present invention in detail with reference to the attached drawings, the concepts of charge sharing operation and precharge operation used in this specification will be briefly described.

[0027] In this specification, the charge sharing operation refers to a phenomenon or operation in which charges existing in capacitive nodes (e.g., data lines) are redistributed when the capacitive nodes are connected to each other. For example, a data line connected to pixels may include a gate capacitance included in a capacitor or transistor.

[0028] A precharge operation means forcibly supplying a specific voltage, for example, a precharge voltage, to capacitive nodes to set the capacitive nodes to a predetermined state (e.g., an initial state) before performing a specific operation (e.g., an operation of transferring output signals of amplifiers to the capacitive nodes). Therefore, the precharge operation may include not only increasing the voltage of a pixel to a predetermined level (charging), but also decreasing the voltage of the pixel to a predetermined level (discharging). In this case, the voltage level of each capacitive node may be discharged or charged to the precharge voltage level according to the precharge operation.

[0029] For example, charge sharing operation is an operation that shares charges between data lines to adjust the voltage level between data lines, and improves the uniformity and performance of the display (e.g., reduces ghosting effects), which can be used to improve power efficiency and picture quality.

[0030] Precharge operation is the operation of minimizing the difference in voltage levels between each end of data lines in order to prepare for the light operation of the next pixel data for a specific pixel, and can be used primarily to prevent data transmission errors and maintain display consistency.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0032] FIG. 1 is a block diagram of a display device according to one embodiment of the present invention.

[0033] Referring to FIG. 1, a display device (100) according to one embodiment of the present invention includes a timing controller (110), a gate driver (130), a first data driver (200), a second data driver (300), and a display panel (400). The first data driver (200) includes a first group of source driver ICs (200_1 to 200_m, where m is a natural number greater than or equal to 2), and the second data driver (300) includes a second group of source driver ICs (300_1 to 300_m).

[0034] A timing controller (110), a gate driver (130), a first data driver (200), and a second data driver (300) constitute a display driver device.

[0035] The display device (100) may be a TV, a monitor, or a mobile device, and the mobile device may be a laptop computer, a tablet PC, a smartphone, a drone, or a wearable device.

[0036] A display panel (400) includes an active area for displaying a display image on a screen, and a pixel array including pixels (PX) is arranged in the active area. The pixel array includes a plurality of data lines (DL), a plurality of gate lines (GL), and pixels (PX) arranged in a matrix form.

[0037] Each of the pixels (PX) may include a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each of the pixels (PX) may further include a white subpixel. Each of the pixels (PX) may be an organic light-emitting diode (OLED) pixel.

[0038] The timing controller (110) controls operations (e.g., data output operation, charge sharing operation, or precharge operation, etc.) of each component (130, 200, and 300). For example, the timing controller (110) generates gate timing control signals that control the operation timing of the gate driver IC (130) and source timing control signals that control the operation timing of the source driver ICs (200_1 to 200_m, 300_1 to 300_m) based on timing signals output from a host system (or an application processor (AP)). The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and a data enable signal.

[0039] The gate driver (130) can control the on or off of at least one transistor included in each pixel (PX) according to a gate timing control signal generated by the timing controller (110). To this end, the gate driver (130) can include a plurality of gate driver ICs. The gate driver IC is also called a scan driver IC or a row driver IC.

[0040] Each of the source driver ICs of the first group (200_1 to 200_m) and the source driver ICs of the second group (300_1 to 300_m) outputs image data of each pixel to each pixel according to a source timing control signal generated by the timing controller (110) to implement the color of each pixel (PX).

[0041] Each of the source driver ICs (200_1 to 200_m) of the first group includes a digital-to-analog converter (hereinafter referred to as 'DAC', 201_1 to 201_m) and a plurality of amplifiers, and each of the source driver ICs (300_1 to 300_m) of the second group includes a DAC (301_1 to 301_m) and a plurality of amplifiers.

[0042] For example, DAC (201_i, i is a natural number, any one of 1 ≤ i ≤ m) can collectively represent DACs included in a source driver IC (200_i), and DAC (301_i) can collectively represent DACs included in a source driver IC (300_i).

[0043] The above-described source driver IC (200_1~200_m, 300_1~300_m) is also called a column driver IC or data driver IC.

[0044] FIG. 2 and FIG. 3 are detailed block diagrams of the display device illustrated in FIG. 1, and FIG. 4 is a timing diagram of signals for explaining the operation of the display device illustrated in FIG. 2 and FIG. 3.

[0045] Referring to FIGS. 1 to 4, the structure of each source driver IC (200_1 to 200_m, 300_1 to 300_m) may be manufactured differently depending on variations in PVT (Pressure, Volume, and Temperature), but for convenience of explanation, it is assumed that they are the same in this specification.

[0046] The timing and voltage level of each control signal (SSOE, SCS, SPV, and PRV) for controlling the operation of the source driver ICs of the first group (200_1 to 200_m) and each control signal (SSOE, SCS, SPV, and PRV) for controlling the operation of the source driver ICs of the second group (300_1 to 300_m) may differ depending on the PVT change, but are assumed to be the same for convenience of explanation.

[0047] Each of the source driver ICs (200_1 to 200_m) of the first group is also called a top side source driver IC, and each of the source driver ICs (300_1 to 300_m) of the second group is also called a bottom side source driver IC.

[0048] Any one of the source driver ICs (200_1 to 200_m) of the first group and any one of the source driver ICs (300_1 to 300_m) of the second group are respectively connected to the upper and lower ends of one data line (DL), and can drive the corresponding data line (DL) simultaneously. That is, according to the present invention, the paired source driver ICs (200_i and 300_i, where i is any one of 1 or more and m or less, and 1≤i≤m) can drive the data lines (DL) connected to the paired source driver ICs (200_i and 300_i) in both directions (e.g., simultaneously).

[0049] When each transmission control switch (SA_1, SD_1) is turned on or off, the output signals (T_S) of the amplifiers (212_1 and 312_1) included in the driving circuits (210_1, 310_1) connected to both ends of the first data line (DL_1) <1> , B_S <1> ) are different, a current due to the voltage level difference flows from the amplifier outputting an output signal with a high voltage level to the amplifier outputting an output signal with a low voltage level.

[0050] In addition, when one of the amplifiers (212_1, 312_1) does not operate depending on an electrostatic discharge (ESD) surge or a voltage level of a source output enable signal (SSOE) while the amplifiers (212_1, 312_1) are driving the first data line (DL_1) in both directions, another amplifier that is operating among the amplifiers (212_1, 312_1) supplies current to the amplifier that is not operating through the first data line (DL_1).

[0051] At this time, if an overcurrent is supplied to the non-operating amplifier through the first data line (DL_1), the pixels connected to the first data line (DL_1) may be damaged or the non-operating amplifier may be damaged due to the overcurrent flowing in the first data line (DL_1). In order to solve this problem, the present invention can selectively perform either the charge sharing operation or the precharge operation by the first group of source driver ICs (200_1 to 200_m) and the second group of source driver ICs (300_1 to 300_m).

[0052] For convenience of explanation, in FIGS. 2 and 3, while the source output enable signal (SSOE, also called a 'transmission control signal') maintains a second voltage level, i.e., during the horizontal blank period (SOE_OFF), the display device (100) according to the present invention is illustrated as performing a charge sharing operation (CSO) or a precharge operation (PCO) for data lines (DL_1 and DL_2) included in the display panel (400) simultaneously or in parallel using paired source driver ICs (200_1 and 300_1).

[0053] However, the display device (100) according to the present invention is not limited thereto, and as illustrated in FIGS. 6 and 7, the charge sharing operation (CSO) or precharge operation (PCO) for all data lines (DL_1 to DL_x, x is a natural number greater than or equal to 2) formed on the display panel (400) during the horizontal blank period (SOE_OFF) may be performed simultaneously or in parallel using all source driver ICs (200_1 to 200_m, and 300_1 to 300_m).

[0054] According to the charge sharing operation (CSO) or precharge operation (PCO) performed in the display device (100) according to the present invention, the difference in voltage levels at both ends of each data line (DL_1 to DL_x) is minimized, so that not only can damage to pixels (PX) connected to each data line (DL_1 to DL_x) be prevented, but also damage to amplifiers connected to both ends of each data line (DL_1 to DL_x) can be prevented.

[0055] Referring to FIGS. 2 and 3, the first upper source driver IC (200_1) includes a first channel upper driving circuit (210_1) for driving a first data line (DL_1), a second channel upper driving circuit (210_2) for driving a second data line (DL_2), a first control signal generation circuit (216), and a first precharge voltage generation circuit (220).

[0056] In FIG. 3, the first precharge voltage generation circuit (220) is described as being included in the first upper source driver IC (200_1), but this is only one example, and the first precharge voltage generation circuit (220) may be formed to be physically separate from the first upper source driver IC (200_1).

[0057] The first control signal generation circuit (216) includes a first digital logic circuit (217) and a first level shifter (218).

[0058] The first digital logic circuit (217) receives an operation control signal (OCTL) from an external circuit, for example, a timing controller (110). The first digital logic circuit (217) determines whether the operation control signal (OCTL) indicates any one of a data output operation, a charge sharing operation, and a precharge operation, and controls the activation timing or deactivation timing of each of the control signals (LSSOE, LSPV, LSCS) based on the determination result.

[0059] In one embodiment, the timing controller (110) according to the present invention can determine an instruction of either a charge sharing operation or a free charge operation based on the frequency of an image to be output through the display panel (400).

[0060] Specifically, when the frequency of the image to be output through the display panel (400) is a frequency of the first band, the timing controller (110) can instruct a charge sharing operation, and when the frequency of the image to be output through the display panel (400) is a frequency of the second band higher than the first band, the timing controller (110) can instruct a pre-charge operation.

[0061] For example, the timing controller (110) may instruct a charge sharing operation when the frequency band of an image to be output through the display panel (400) is 60 Hz, and may instruct a pre-charge operation when the frequency band of an image to be output through the display panel (400) is 120 Hz. This is because an image in a 120 Hz frequency band requires a faster response characteristic than an image in a 60 Hz frequency band, and the pre-charge operation can reduce the output signal deviation of the first upper source driver IC (200_1) and the first lower source driver IC (300_1) in a shorter period of time compared to the charge sharing operation.

[0062] In another embodiment, the timing controller (110) may determine whether to perform either a charge sharing operation or a pre-charge operation depending on the level of a lock signal. For example, the charge sharing operation may be instructed when the lock signal is at a high level, and the pre-charge operation may be instructed when the lock signal is at a low level.

[0063] In another embodiment, the timing controller (110) may instruct data output when the lock signal is at a high level, and may additionally check the frequency of an image to be output through the display panel (400) when the lock signal is at a low level, and may instruct a charge sharing operation when the frequency of the image is a frequency of the first band, and may instruct a pre-charge operation when the frequency of the image is a frequency of the second band higher than the first band.

[0064] The first level shifter (218) performs at least one of the functions of shifting the voltage level of each control signal (LSSOE, LSPV, LSCS) to a high voltage or controlling the phase of each control signal (LSSOE, LSPV, LSCS). In addition, the first level shifter (218) generates a source output enable signal (SSOE) corresponding to the first control signal (LSSOE), a precharge control signal (SPV) corresponding to the second control signal (LSPV), and a charge sharing control signal (SCS) corresponding to the third control signal (LSCS).

[0065] The waveforms of each of the source output enable signal (SSOE), precharge control signal (SPV), and charge sharing control signal (SCS) in each operating section (SOI and SOE_OFF) will be described later with reference to FIG. 4.

[0066] The first precharge voltage generation circuit (220) generates the first precharge voltage (PRV1). For example, the first precharge voltage generation circuit (220) can generate the first precharge voltage (PRV1) only in the precharge operation section of the horizontal blank section (SOE_OFF) under the control of the first control signal generation circuit (216). The first precharge voltage generation circuit (220) can be a voltage regulator, for example, an LDO (Low Dropout) voltage regulator.

[0067] The first channel upper driving circuit (210_1) includes a first pin (P1), a first DAC (211_1), a first amplifier (212_1), and a first group of switches (SA_1, SB_1, SC_1). The first channel upper driving circuit (210_1) may further include a plurality of ESD diodes (ED1, ED2) for protecting the first channel upper driving circuit (210_1) from ESD surges.

[0068] The second channel upper driving circuit (210_2) includes a second pin (P2), a second DAC (211_2), a second amplifier (212_2), and a second group of switches (SA_2, SB_2, SC_2). The second channel upper driving circuit (210_2) may further include a plurality of ESD diodes (ED3, ED4) to protect the second channel upper driving circuit (210_2) from ESD surges.

[0069] The first switch circuit (214) includes a first group of switches (SA_1, SB_1, SC_1) and a second group of switches (SA_2, SB_2, SC_2).

[0070] As illustrated in FIG. 2, the first upper source driver IC (200_1) further includes a first charge sharing line (CSL1), a first precharge line (PCL1), and a first switch circuit (214). Although FIG. 2 illustrates that the first upper source driver IC (200_1) includes the first charge sharing line (CSL1), the first precharge line (PCL1), and the first switch circuit (214), this is merely an example, and the first charge sharing line (CSL1), the first precharge line (PCL1), and the first switch circuit (214) may be disposed outside the first upper source driver IC (200_1).

[0071] The first charge sharing line (CSL1) collectively refers to the charge sharing line(s) used for charge sharing operation in the first upper source driver IC (200_1) or the first data driver (200). The first precharge line (PCL1) collectively refers to the precharge line(s) used for precharge operation in the first upper source driver IC (200_1) or the first data driver (200).

[0072] Hereinafter, for convenience of explanation, regardless of the embodiments in which the first charge sharing line (CSL1), the first precharge line (PCL1), and the first switch circuit (214) are arranged inside or outside the first upper source driver IC (200_1), a semiconductor device including the first charge sharing line (CSL1), the first precharge line (PCL1), and the first switch circuit (214) will be referred to as the first upper source driver IC (200_1).

[0073] The first pin (P1) is connected to one end of the first data line (DL_1). The first DAC (211_1) converts the first digital signal into an analog signal to generate the first input signal (IN1). The first amplifier (212_1) is connected to the power line (PL) and the ground (VSS). The first amplifier (212_1) receives and amplifies the first input signal (IN1). The first amplifier (212_1) outputs the amplified first signal (T_S <1> ) is output through the first output terminal (OT1).

[0074] The first ESD diode (ED1) is connected between the power line (PL) supplying the operating voltage and the first pin (P1), and the second ESD diode (ED2) is connected between the first pin (P1) and ground (VSS).

[0075] The second pin (P2) is connected to one end of the second data line (DL_2). The second DAC (211_2) converts the second digital signal into an analog signal to generate a second input signal (IN2). The second amplifier (212_2) is connected to the power line (PL) and the ground (VSS). The second amplifier (212_2) receives and amplifies the second input signal (IN2). The second amplifier (212_2) outputs the amplified second signal (T_S <2> ) is output through the second output terminal (OT2).

[0076] The third ESD diode (ED3) is connected between the power line (PL) and the second pin (P2), and the fourth ESD diode (ED4) is connected between the second pin (P2) and ground (VSS).

[0077] The first lower source driver IC (300_1) includes a first channel lower driving circuit (310_1) for driving a first data line (DL_1), a second channel lower driving circuit (310_2) for driving a second data line (DL_2), a second control signal generation circuit (316), and a second precharge voltage generation circuit (320).

[0078] In FIG. 3, the second precharge voltage generation circuit (320) is described as being included in the first lower source driver IC (300_1), but this is only one example, and the second precharge voltage generation circuit (320) may be formed to be physically separate from the first lower source driver IC (300_1).

[0079] The second control signal generation circuit (316) includes a second digital logic circuit (317) and a second level shifter (318).

[0080] The second digital logic circuit (317) receives an operation control signal (OCTL) output from an external circuit, for example, a timing controller (110). The second digital logic circuit (317) determines whether the operation control signal (OCTL) indicates any one of a data output operation, a charge sharing operation, and a precharge operation, and controls the activation timing or deactivation timing of each of the control signals (LSSOE, LSPV, LSCS) according to the determination result.

[0081] As described above, the timing controller (110) according to the present invention can determine an instruction for either a charge sharing operation or a pre-charge operation based on the frequency of an image to be output through the display panel (400). Since a detailed description thereof has been provided in detail in the first digital logic circuit (217) section, a detailed description thereof will be omitted.

[0082] The second level shifter (318) performs at least one of the functions of shifting the voltage level of each control signal (LSSOE, LSPV, LSCS) to a high voltage or controlling the phase of each control signal (LSSOE, LSPV, LSCS). The second level shifter (318) generates a source output enable signal (SSOE) corresponding to the first control signal (LSSOE), a precharge control signal (SPV) corresponding to the second control signal (LSPV), and a charge sharing control signal (SCS) corresponding to the third control signal (LSCS).

[0083] The waveforms of each of the source output enable signal (SSOE), precharge control signal (SPV), and charge sharing control signal (SCS) in each operating section (SOI and SOE_OFF) will be described later with reference to FIG. 4.

[0084] The second precharge voltage generation circuit (320) generates a second precharge voltage (PRV2). For example, the second precharge voltage generation circuit (320) can generate the second precharge voltage (PRV2) only in the precharge operation section of the horizontal blank section (SOE_OFF) under the control of the second control signal generation circuit (316). The second precharge voltage generation circuit (320) may be a voltage regulator, for example, an LDO voltage regulator.

[0085] In order to minimize the difference in voltage levels between the two ends of each data line (DL_1 to DL_x) by the precharge operation, the first precharge voltage (PRV1) and the second precharge voltage (PRV2) can be set to be the same.

[0086] The first channel lower driving circuit (310_1) includes a third pin (P3), a third DAC (311_1), a third amplifier (312_1), and a third group of switches (SD_1, SE_1, and SF_1). The first channel lower driving circuit (310_1) may further include a plurality of ESD diodes (ED5, ED6) for protecting the first channel lower driving circuit (310_1) from ESD surges.

[0087] The second channel lower driving circuit (310_2) includes a fourth pin (P4), a fourth DAC (311_2), a fourth amplifier (312_2), and a fourth group of switches (SD_2, SE_2, and SF_2). The second channel lower driving circuit (310_2) may further include a plurality of ESD diodes (ED7, ED8) for protecting the second channel lower driving circuit (310_2) from ESD surges.

[0088] The second switch circuit (314) includes a third group of switches (SD_1, SE_1, and SF_1) and a fourth group of switches (SD_2, SE_2, and SF_2).

[0089] The first lower source driver IC (300_1) further includes a second charge sharing line (CSL2), a second precharge line (PCL2), and a second switch circuit (314), as illustrated in FIG. 2. Although FIG. 2 illustrates that the first lower source driver IC (300_1) includes the second charge sharing line (CSL2), the second precharge line (PCL2), and the second switch circuit (314), this is merely an example, and the second charge sharing line (CSL2), the second precharge line (PCL2), and the second switch circuit (314) may be disposed outside the first lower source driver IC (300_1).

[0090] The second charge sharing line (CSL2) collectively refers to the charge sharing line(s) used for charge sharing operation in the first lower source driver IC (300_1) or the second data driver (300). The second precharge line (PCL2) collectively refers to the precharge line(s) used for precharge operation in the first lower source driver IC (300_1) or the second data driver (300).

[0091] For convenience of explanation, in the following, regardless of the embodiments in which the second charge sharing line (CSL2), the second precharge line (PCL2), and the second switch circuit (314) are arranged inside or outside the first lower source driver IC (300_1), a semiconductor device including the second charge sharing line (CSL2), the second precharge line (PCL2), and the second switch circuit (314) is referred to as a first lower source driver IC (300_1).

[0092] The third pin (P3) is connected to the other end of the first data line (DL_1). At this time, the first data line (DL_1) means the end opposite to one end of the first data line (DL_1). The third DAC (311_1) converts the third digital signal into an analog signal to generate a third input signal (IN3). The third amplifier (312_1) is connected to the power line (PL) and the ground (VSS). The third amplifier (312_1) receives and amplifies the third input signal (IN3). The third amplifier (312_1) amplifies the amplified third signal (B_S <1> ) is output through the third output terminal (OT3).

[0093] The fifth ESD diode (ED5) is connected between the power line (PL) and the third pin (P3), and the sixth ESD diode (ED6) is connected between the third pin (P3) and ground (VSS).

[0094] The fourth pin (P4) is connected to the other end of the second data line (DL_2). The fourth DAC (311_2) converts the fourth digital signal into an analog signal to generate a fourth input signal (IN4). The fourth amplifier (312_2) is connected to the power line (PL) and the ground (VSS). The fourth amplifier (312_2) receives and amplifies the fourth input signal (IN4). The fourth amplifier (312_2) amplifies the fourth signal (B_S <2> ) is output through the fourth output terminal (OT4).

[0095] In the above-described embodiments, the first to fourth pins (P1 to P4) may mean pads including circuits related to input / output of data.

[0096] The seventh ESD diode (ED7) is connected between the power line (PL) and the fourth pin (P4), and the eighth ESD diode (ED8) is connected between the fourth pin (P4) and ground (VSS).

[0097] Hereinafter, the data output operation, charge sharing operation, and pre-charge operation performed by the display device (100) will be described in more detail with additional reference to FIGS. 5 to 7.

[0098] Figure 5 is a drawing showing the arrangement of switches when the display device (100) performs a data output operation.

[0099] As illustrated in FIG. 2, the first and second switch circuits (214 and 314) include a plurality of switches, and the plurality of switches are arranged in a first switch array for transmitting the output signals of each amplifier (212_1 to 212_x, and 312_1 to 312_x) to each data line (DL_1 to DL_x) in the data output section (SOI).

[0100] At this time, the first switch arrangement means an arrangement of switches in which each transmission control switch (SA_1 to SA_x, SD_1 to SD_x) included in the first and second data driving units (200, 300) is turned on, each charge sharing switch (SB_1 to SB_x, SE_1 to SE_x) included in the first data driving unit (200, 300) is turned off, and each precharge switch (SC_1 to SC_x, SF_1 to SF_x) included in the first and second data driving units (200, 300) is turned off, as illustrated in FIG. 5.

[0101] More specifically, as illustrated in FIGS. 1 to 5, the first and second control signal generation circuits (216, 316) output a source output enable signal (SSOE) having a first voltage level (L), a precharge control signal (SPV) having a first voltage level (L), and a charge sharing control signal (SCS) having a first voltage level (L) when the operation control signal (OCTL) instructs a data output operation.

[0102] The first voltage level (L) is one of a high voltage level and a low voltage level (e.g., a low voltage level), and the second voltage level (H) is the other of a high voltage level and a low voltage level (e.g., a high voltage level).

[0103] In one embodiment, each of the transmission control switches (SA_1, SA_2, SD_1, SD_2) may be a low active transmission gate that is turned on in response to a source output enable signal (SSOE) having a first voltage level (L). Each of the charge sharing switches (SB_1, SB_2, SE_1, SE_2) may be a high active transmission gate that is turned on in response to a charge sharing control signal (SCS) having a second voltage level (H). Each of the precharge switches (SC_1, SC_2, SF_1, SF_2) may be a high active transmission gate that is turned on in response to a precharge control signal (SPV) having a second voltage level (H).

[0104] According to this embodiment, when the source output enable signal (SSOE) is at the first voltage level (L), i.e., during the data output interval (SOI), each of the transmission control switches (SA_1, SA_2, SD_1, SD_2) is turned on in response to the source output enable signal (SSOE) having the first voltage level (L). Accordingly, the output terminals (OT1, OT2, OT3, and OT4) of the first to fourth amplifiers (212_1, 212_2, 312_1, and 312_2) are connected to the first to fourth pins (P1, P2, P3, and P4).

[0105] Therefore, the driving signal (T_S) output from the first amplifier (212_1) <1> ) is supplied to one end of the first data line (DL_1), and the driving signal (B_S) output from the third amplifier (312_1) <1> ) is supplied to the other end of the first data line (DL_1). Simultaneously or in parallel, a driving signal (T_S) output from the second amplifier (212_2) <2> ) is supplied to one end of the second data line (DL_2), and the driving signal (B_S) output from the fourth amplifier (312_2) <2> ) is supplied to the other end of the second data line (DL_2).

[0106] That is, as illustrated in FIG. 5, during the data output interval (SOI), all transmission control switches (SA_1 to SA_x) included in the first data driving unit (200) and all transmission control switches (SD_1 to SD_x) included in the second data driving unit (300) are turned on, and accordingly, the first data driving unit (200) outputs driving signals output from the first group of amplifiers (212_1 to 212_x) included therein to one ends of the data lines (DL_1 to DL_x), and the second data driving unit (300) outputs driving signals output from the second group of amplifiers (312_1 to 312_x) included therein to the other ends of the data lines (DL_1 to DL_x).

[0107] Meanwhile, during the data output interval (SOI), each charge sharing switch (SB_1, SB_2, SE_1, SE_2) maintains an off state in response to a charge sharing control signal (SCS) having a first voltage level (L), and each precharge switch (SC_1, SC_2, SF_1, SF_2) maintains an off state in response to a precharge control signal (SPV) having a first voltage level (L).

[0108] Figure 6 is a drawing showing the arrangement of switches when a charge sharing operation is performed in a display device.

[0109] As illustrated in FIG. 6, the first and second switch circuits (214, 314) include a plurality of switches, and the plurality of switches are arranged as a second switch array for connecting each data line (DL_1 to DL_x) during a charge sharing operation (CSO) of a horizontal blank period (SOE_OFF).

[0110] At this time, as illustrated in FIG. 6, the second switch arrangement means an arrangement of multiple switches in which each transmission control switch (SA_1 to SA_x, SD_1 to SD_x) included in the first and second data driving units (200, 300) is turned off, each charge sharing switch (SB_1 to SB_x, SE_1 to SE_x) included in the first and second data driving units (200, 300) is turned on, and each precharge switch (SC_1 to SC_x, SF_1 to SF_x) included in the first and second data driving units (200, 300) is turned off.

[0111] More specifically, referring to FIGS. 1 to 4 and 6, the first control signal generation circuit (216) outputs a source output enable signal (SSOE) having a second voltage level (H), a precharge control signal (SPV) having a first voltage level (L), and a charge sharing control signal (SCS) having a second voltage level (H) when the operation control signal (OCTL) indicates a charge sharing operation (CSO).

[0112] In one embodiment, the charge sharing control signal (SCS) can be output in the horizontal blanking interval (SOE_OFF). That is, as illustrated in FIG. 4, a charge sharing operation (CSO) is performed during each horizontal blanking interval (SOE_OFF) between data output intervals in which corresponding plurality of display data (DATA1 and DATA2, DATA2 and DATA3, DATA3 and DATA4, and DATA4 and DATA5) are output.

[0113] The first charge sharing switches (SB_1, SB_2) are maintained in an on state to connect terminals of the data lines (DL_1 to DL_x) in response to a charge sharing control signal (SCS) having a second voltage level (H), the first precharge switches (SC_1, SC_2) are maintained in an off state in response to a precharge control signal (SPV) having a first voltage level (L), and the first transmission control switches (SA_1, SA_2) are turned off in response to a source output enable signal (SSOE) having a first voltage level (L). Accordingly, a charge sharing operation is performed between terminals of the data lines (DL_1 to DL_x).

[0114] Similarly, the second control signal generation circuit (316) outputs a source output enable signal (SSOE) having a second voltage level (H), a precharge control signal (SPV) having a first voltage level (L), and a charge sharing control signal (SCS) having a second voltage level (H) when the operation control signal (OCTL) indicates a charge sharing operation (CSO).

[0115] The second charge sharing switches (SE_1, SE_2) maintain an on state that connects the other ends of the data lines (DL_1 to DL_x) in response to a charge sharing control signal (SCS) having a second voltage level (H), the second precharge switches (SF_1, SF_2) maintain an off state in response to a precharge control signal (SPV) having a first voltage level (L), and the second transmission control switches (SD_1, SD_2) are turned off in response to a source output enable signal (SSOE) having the first voltage level (L). Accordingly, a charge sharing operation is performed between the other ends of the data lines (DL_1 to DL_x).

[0116] As described above, since all data lines (DL1_1 to DL_x) are connected to each other through charge sharing lines, a charge sharing operation (CSO) in which charges of all data lines (DL1_1 to DL_x) are redistributed can be performed.

[0117] In one embodiment, when a charge sharing operation is performed in the display device (100), the charge sharing operation performed by the first data driving unit (200) and the charge sharing operation performed by the second data driving unit (300) can be performed simultaneously.

[0118] Figure 7 is a drawing showing the arrangement of switches during a precharge operation performed in a display device.

[0119] As illustrated in FIG. 7, the first and second switch circuits (214, 314) include a plurality of switches, and the plurality of switches are arranged in a third switch array for supplying a precharge voltage (PRV) to each data line (DL_1 to DL_x) during a precharge operation (CSO) of a horizontal blank period (SOE_OFF).

[0120] At this time, as illustrated in FIG. 7, the third switch array means an array of multiple switches in which each transmission control switch (SA_1 to SA_x, SD_1 to SD_x) included in the first and second data driving units (200, 300) is turned off, each charge sharing switch (SB_1 to SB_x, SE_1 to SE_x) included in the first and second data driving units (200, 300) is turned off, and each precharge switch (SC_1 to SC_x, SF_1 to SF_x) included in the first and second data driving units (200, 300) is turned on.

[0121] More specifically, referring to FIGS. 1 to 4 and FIG. 7, the first control signal generation circuit (216) outputs a source output enable signal (SSOE) having a second voltage level (H), a precharge control signal (SPV) having a second voltage level (H), and a charge sharing control signal (SCS) having a first voltage level (L) when the operation control signal (OCTL) indicates a precharge operation (PCO).

[0122] In one embodiment, the precharge operation (PCO) can be output in a horizontal blank interval (SOE_OFF). That is, as illustrated in FIG. 4, the precharge operation (PCO) is performed during each horizontal blank interval (SOE_OFF) between data output intervals in which corresponding plurality of display data (DATA1 and DATA2, DATA2 and DATA3, DATA3 and DATA4, and DATA4 and DATA5) are output.

[0123] The first precharge switch (SC_1, SC_2) is maintained in an on state in response to a precharge control signal (SPV) having a second voltage level (H), the first charge sharing switch (SB_1, SB_2) is maintained in an off state to separate ends of the data lines (DL_1 to DL_x) in response to a charge sharing control signal (SCS) having a first voltage level (L), and the first transmission control switch (SA_1, SA_2) is turned off in response to a source output enable signal (SSOE) having a first voltage level (L).

[0124] At the same time, the first precharge voltage generation circuit (220) generates a first precharge voltage (PRV1) and supplies the first precharge voltage (PRV1) to each end of the data lines (DL1_1 to DL_x) through the first precharge line. Accordingly, the voltage of each of the data lines (DL1_1 to DL_x) can be quickly charged or discharged to the level (VL) of the first precharge voltage (PRV1).

[0125] Similarly, the second control signal generation circuit (316) outputs a source output enable signal (SSOE) having a second voltage level (H), a precharge control signal (SPV) having a second voltage level (H), and a charge sharing control signal (SCS) having a first voltage level (L) when the operation control signal (OCTL) indicates a precharge operation (PCO).

[0126] The second precharge switches (SF_1, SF_2) are maintained in an on state in response to a precharge control signal (SPV) having a second voltage level (H), the second charge sharing switches (SE_1, SE_2) are maintained in an off state to separate the other ends of the data lines (DL_1 to DL_x) in response to a charge sharing control signal (SCS) having a first voltage level (L), and the second transmission control switches (SD_1, SD_2) are turned off in response to a source output enable signal (SSOE) having a first voltage level (L).

[0127] At the same time, the second precharge voltage generation circuit (320) generates a second precharge voltage (PRV2) and supplies the second precharge voltage (PRV2) to the other end of each of the data lines (DL1_1 to DL_x) through the second precharge line. Therefore, the voltage of each of the data lines (DL1_1 to DL_x) can be quickly charged or discharged to the level (VL) of the second precharge voltage (PRV2).

[0128] Accordingly, the difference between the voltage at one end of each of the data lines (DL1_1 to DL_x) and the voltage at the other end of each of the data lines (DL1_1 to DL_x) is minimized faster than the charge sharing operation (CSO).

[0129] For example, when a precharge operation (PCO) is performed between data output sections in which corresponding multiple display data (DATA1 and DATA2, and DATA3 and DATA4) are output, the voltage of each of the data lines (DL1_1 to DL_x) can be quickly discharged to the level (VL) of the precharge voltage (PRV1 = PRV2).

[0130] In addition, when a precharge operation (PCO) is performed between data output sections in which corresponding plurality of display data (DATA2 and DATA3, and DATA4 and DATA5)) are output, the voltage of each of the data lines (DL1_1 to DL_x) can be quickly charged to the level (VL) of the precharge voltage (PRV1 = PRV2).

[0131] In the above-described embodiment, the level of the precharge voltage by the precharge operation (PCO) may be different from the level of the charge sharing by the charge sharing operation (CSO).

[0132]

[0133] Hereinafter, with reference to FIG. 8, the operating method of the display driving device according to the present invention will be described.

[0134] Figure 7 is a flowchart for explaining the operation of a display driving device according to one embodiment of the present invention.

[0135] First, the first and second control signal generation circuits (216, 316) receive an operation control signal (OCTL) from the timing controller (110) (S800).

[0136] In one embodiment, the timing controller (110) can determine an instruction of either a charge sharing operation or a pre-charge operation based on the frequency of an image to be output through the display panel (400).

[0137] Specifically, when the frequency of the image to be output through the display panel (400) is a frequency of the first band, the timing controller (110) can instruct a charge sharing operation, and when the frequency of the image to be output through the display panel (400) is a frequency of the second band higher than the first band, the timing controller (110) can instruct a pre-charge operation.

[0138] For example, the timing controller (110) may instruct a charge sharing operation when the frequency band of an image to be output through the display panel (400) is 60 Hz, and may instruct a pre-charge operation when the frequency band of an image to be output through the display panel (400) is 120 Hz. This is because an image in a 120 Hz frequency band requires a faster response characteristic than an image in a 60 Hz frequency band, and the pre-charge operation can reduce the output signal deviation of the first upper source driver IC (200_1) and the first lower source driver IC (300_1) in a shorter period of time compared to the charge sharing operation.

[0139] The first and second control signal generation circuits (216, 316) output a source output enable signal (SSOE) having a first voltage level (L), a precharge control signal (SPV) having a first voltage level (L), and a charge sharing control signal (SCS) having a first voltage level (L) when the operation control signal (OCTL) is interpreted as indicating a data output operation (YES of S810) (S820).

[0140] Each transfer control switch (SA_1, SA_2, SD_1, SD_2) is turned on in response to a source output enable signal (SSOE) having a first voltage level (L), each charge sharing switch (SB_1, SB_2, SE_1, SE_2) is maintained in an off state in response to a charge sharing control signal (SCS) having a first voltage level (L), and each precharge switch (SC_1, SC_2, SF_1, SF_2) is maintained in an off state in response to a precharge control signal (SPV) having a first voltage level (L).

[0141] That is, during the data output interval (SOI), as all transmission control switches (SA_1 to SA_x) included in the first data driving unit (200) and all transmission control switches (SD_1 to SD_x) included in the second data driving unit (300) are turned on, the first data driving unit (200) outputs driving signals output from the first group of amplifiers (212_1 to 212_x) included therein to one end of the data lines (DL_1 to DL_x), and the second data driving unit (300) outputs driving signals output from the second group of amplifiers (312_1 to 312_x) included therein to the other end of the data lines (DL_1 to DL_x) (S830).

[0142] Meanwhile, if the first and second control signal generation circuits (216, 316) determine that the operation control signal (OCTL) indicates a charge sharing operation (CSO) (YES of S810 and YES of S840), they output a source output enable signal (SSOE) having a second voltage level (H), a precharge control signal (SPV) having a first voltage level (L), and a charge sharing control signal (SCS) having a second voltage level (H) (S850).

[0143] Each transfer control switch (SA_1, SA_2, SD_1, SD_2) is turned off in response to a source output enable signal (SSOE) having a second voltage level (H), each charge sharing switch (SB_1, SB_2, SE_1, SE_2) is maintained in an on state in response to a charge sharing control signal (SCS) having a second voltage level (H), and each precharge switch (SC_1, SC_2, SF_1, SF_2) is maintained in an off state in response to a precharge control signal (SPV) having a first voltage level (L).

[0144] Accordingly, during the horizontal blank period (SOE_OFF), all data lines (DL1_1 to DL_x) are connected to each other through charge sharing lines, so a charge sharing operation (CSO) is performed in which charges of all data lines (DL1_1 to DL_x) are redistributed (S860).

[0145] Meanwhile, if the first and second control signal generation circuits (216, 316) determine that the operation control signal (OCTL) indicates a precharge operation (PCO) (YES of S810 and NO of S840), they output a source output enable signal (SSOE) having a second voltage level (H), a precharge control signal (SPV) having a second voltage level (H), and a charge sharing control signal (SCS) having a first voltage level (L) (S870).

[0146] Each transfer control switch (SA_1, SA_2, SD_1, SD_2) is turned off in response to a source output enable signal (SSOE) having a second voltage level (H), each charge sharing switch (SB_1, SB_2, SE_1, SE_2) is maintained in an off state in response to a charge sharing control signal (SCS) having a first voltage level (L), and each precharge switch (SC_1, SC_2, SF_1, SF_2) is maintained in an on state in response to a precharge control signal (SPV) having a second voltage level (H).

[0147] Accordingly, during the horizontal blank period (SOE_OFF), a first precharge voltage (PRV1) is supplied to one end of each of the data lines (DL1_1 to DL_x) through a first precharge line, and a second precharge voltage (PRV2) is supplied to the other end of each of the data lines (DL1_1 to DL_x) through a second precharge line, thereby performing a precharge operation (S780). As the precharge operation is performed, the difference between the voltage of one end of each of the data lines (DL1_1 to DL_x) and the voltage of the other end of each of the data lines (DL1_1 to DL_x) can be minimized faster than a charge sharing operation (CSO).

[0148] Those skilled in the art will appreciate that the present invention described above can be implemented in other specific forms without changing the technical idea or essential features thereof.

[0149] Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included within the scope of the present invention.

Claims

1. A first source driver IC arranged on one side of the display panel and connected to one end of the first data line; and A second source driver IC is disposed on the other side of the display panel and is connected to the other end of the first data line, The above first and second source driver ICs An amplifier connected to the first data line; A control signal generation circuit that generates a charge share control signal when an operation control signal received from an external device instructs a charge share operation, and generates a precharge control signal when the operation control signal instructs a precharge operation; A display driving device including a switch circuit that connects the first data line and the second data line adjacent to the first data line to each other in response to the charge sharing control signal, and supplies a predetermined precharge voltage to the first data line in response to the precharge control signal.

2. In paragraph 1, The charge sharing operation performed by the first source driver IC and the charge sharing operation performed by the second source driver IC are performed simultaneously, A display driving device in which the precharge operation performed by the first source driver IC and the precharge operation performed by the second source driver IC are performed simultaneously.

3. In paragraph 1, Further comprising a precharge voltage generation circuit that generates the above precharge voltage, A display driving device in which the switch circuit connects the precharge voltage generation circuit to the first data line in response to the precharge control signal.

4. In paragraph 1, A display driving device in which the precharge voltage for the precharge operation of the first source driver IC and the precharge voltage for the precharge operation of the second source driver IC are the same.

5. In the first paragraph, the switch circuit, A transmission control switch connected between the output terminal of the amplifier and the first data line; a charge sharing switch connected between the first data line and the second data line; and A display driving device including a precharge switch connected between the first data line and an output terminal of a precharge voltage generation circuit.

6. In paragraph 5, The above control signal generation circuit is a display driving device that generates a transmission control signal for turning off the transmission control switch, a charge sharing control signal for turning on the charge sharing switch, and a precharge control signal for turning off the precharge switch when the operation control signal instructs the charge sharing operation.

7. In paragraph 5, The above control signal generation circuit is a display driving device that generates a transmission control signal for turning off the transmission control switch, a charge sharing control signal for turning off the charge sharing switch, and a precharge control signal for turning on the precharge switch when the operation control signal instructs the precharge operation.

8. In paragraph 5, The above control signal generation circuit generates a transmission control signal when the above operation control signal instructs data output, A display driving device in which the switch circuit connects the amplifier to the first data line in response to the transmission control signal so that a driving signal output from the amplifier is supplied to a pixel connected to the first data line.

9. In paragraph 8, The above control signal generation circuit is a display driving device that generates, when the operation control signal instructs the data output, the transmission control signal for turning on the transmission control switch, the charge sharing control signal for turning off the charge sharing switch, and the precharge control signal for turning off the precharge switch.

10. In paragraph 1, A display driving device in which the above charge sharing operation and the above precharge operation are performed during a horizontal blank period.

11. In paragraph 1, A display driving device in which the above-described motion control signal is generated to instruct the charge sharing operation when the frequency of the image to be output through the display panel is a frequency of the first band, and is generated to instruct the pre-charge operation when the frequency of the image to be output through the display panel is a frequency of the second band higher than the first band.

12. A display panel comprising a plurality of pixels and a plurality of data lines connected to each of the pixels; A first group of source driver ICs arranged on one side of the display panel and connected to one end of the data lines to drive the data lines; A second group of source driver ICs arranged on the other side of the display panel and connected to the other ends of the data lines to drive the data lines; and A timing controller for generating an operation control signal to operate the source driver ICs of the first group and the source driver ICs of the second group in one of a data output operation, a charge sharing operation, and a pre-charge operation, Each of the source driver ICs of the first group and the source driver ICs of the second group, Amplifiers connected to each data line; A control signal generation circuit that receives the above operation control signal and generates a transmission control signal when the operation control signal instructs data output, generates a charge sharing control signal when the operation control signal instructs a charge sharing operation, and generates a precharge control signal when the operation control signal instructs a precharge operation; and A display device including a switch circuit that connects each amplifier to a corresponding data line in response to the transmission control signal, connects adjacent data lines to each other in response to the charge sharing control signal, and supplies a predetermined precharge voltage to each data line in response to the precharge control signal.

13. In paragraph 12, The source driver ICs of the first group and the source driver ICs of the second group simultaneously perform the charge sharing operation for one data line, A display device in which the source driver ICs of the first group and the source driver ICs of the second group simultaneously perform the precharge operation for one data line.

14. In paragraph 12, The above switch circuit includes a plurality of switches, The above multiple switches are, In response to the above transmission control signal, the first switch array is arranged to supply the driving signal output from each amplifier to the corresponding data lines, In response to the charge sharing control signal, the second switch array is arranged to connect the adjacent data lines to each other, A display device arranged in a third switch array to forcibly supply the precharge voltage to the corresponding data line in response to the precharge control signal.

15. In paragraph 14, The above switch circuit, A transmission control switch that connects each of the above amplifiers to the corresponding data line; a charge sharing switch connecting the adjacent data lines; and A display device including a precharge switch that connects a precharge voltage generation circuit that generates the above precharge voltage to each data line.

16. In paragraph 15, When the above-mentioned operation control signal instructs the above-mentioned charge sharing operation, the control signal generation circuit, Generating the transmission control signal to turn off the transmission control switch, Generate the charge sharing control signal to turn on the charge sharing switch, A display device that generates the precharge control signal for turning off the precharge switch.

17. In the 15th paragraph, when the operation control signal indicates a precharge operation, the control signal generation circuit, Generating the transmission control signal to turn off the transmission control switch, Generate the charge sharing control signal to turn off the charge sharing switch, A display device that generates the precharge control signal for turning on the precharge switch.

18. In paragraph 12, A display device in which the timing controller generates an operation control signal that instructs the charge sharing operation when the frequency of the image to be output through the display panel is a frequency of the first band, and generates an operation control signal that instructs the pre-charge operation when the frequency of the image to be output through the display panel is a frequency of the second band higher than the first band.

19. A method for operating a display driving device by a first source driver IC connected to one end of a first data line and a second source driver IC connected to the other end of the first data line, A step of receiving a motion control signal; A step of generating a charge sharing control signal when the above-mentioned operation control signal instructs a charge sharing operation, and generating a precharge control signal when the above-mentioned operation control signal instructs a precharge operation; and A method of operating a data drive device, comprising the steps of performing the charge sharing operation of connecting the first data line and the second data line adjacent to the first data line to each other in response to the charge sharing control signal, and performing the precharge operation of forcibly supplying a predetermined precharge voltage to the first data line in response to the precharge control signal.

20. In paragraph 19, Further comprising a step of generating a transmission control signal when the above operation control signal instructs a data output operation, In the above-mentioned performing step, A plurality of switches included in the first and second source driver ICs are arranged in a first switch array to supply driving signals output from the plurality of amplifiers to the data lines in response to the transmission control signal, In response to the charge sharing control signal, the second switch array is arranged to connect the data lines, A method of operating a data drive device arranged in a third switch array to forcibly supply the precharge voltage to the data lines in response to the precharge control signal.

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