Shift register, display substrate, and display device

Abstract

The present invention relates to the technical field of display and provides a shift register, a display substrate, and a display device, for use in solving the problems of complex structures and large occupied area of existing shift registers. The shift register of the present invention comprises: a first input sub-circuit configured to transmit a first level signal to a first node in response to a first clock signal; a second input sub-circuit configured to transmit an input signal to a second node in response to the first clock signal; a control sub-circuit configured to input a second level signal to the first node in response to a second clock signal; a protection sub-circuit configured to, when the second input sub-circuit does not operate, input a voltage of a third node to the second node, and enable a voltage of the second node to be lower than the voltage of the third node; a first output sub-circuit configured to output the second level signal in response to a voltage of the first node; and a second output sub-circuit configured to output the second clock signal in response to the voltage of the third node.

Description

Shift register, display substrate, and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a display substrate, and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the most important technologies is the mass production of Gate Driver on Array (GOA) technology.

[0003] GOA technology is used to integrate a shift register circuit composed of thin film transistors (TFTs) on the array substrate of the display substrate to form a scan drive for the display substrate, thereby eliminating the gate drive integrated circuit part. It can not only reduce product costs in terms of material costs and manufacturing processes, but also achieve an aesthetically pleasing design of the display substrate with bilateral symmetry and narrow bezels.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a display substrate, and a display device.

[0006] In a first aspect, an embodiment of the present disclosure provides a shift register, wherein the shift register comprises: a first input subcircuit, a second input subcircuit, a control subcircuit, a protection subcircuit, a first output subcircuit, and a second output subcircuit;

[0007] The first input sub-circuit is configured to transmit a first level signal to a first node in response to a first clock signal; the first node is a connection point between the first input sub-circuit, the first output sub-circuit and the control sub-circuit;

[0008] The second input subcircuit is configured to transmit the input signal to a second node in response to the first clock signal; the second node is a connection point between the second input subcircuit and the protection subcircuit;

[0009] The control subcircuit is configured to input a second level signal to the first node in response to a second clock signal;

[0010] The protection subcircuit is configured to transmit the voltage of the second node to a third node when the second input subcircuit is in operation; and to input the voltage of the third node to the second node when the second input subcircuit is in operation, so that the voltage of the second node is lower than the voltage of the third node; the third node is a connection point between the protection subcircuit and the second output subcircuit;

[0011] The first output sub-circuit is configured to output a second level signal in response to the voltage of the first node;

[0012] The second output sub-circuit is configured to output a second clock signal in response to a voltage of the third node.

[0013] Optionally, the first input sub-circuit includes: a third transistor;

[0014] The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node.

[0015] Optionally, the second input sub-circuit includes: a first transistor;

[0016] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node.

[0017] Optionally, the protection sub-circuit includes: a sixth transistor;

[0018] The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node.

[0019] Optionally, the control subcircuit includes: a second transistor;

[0020] The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node.

[0021] Optionally, the first output sub-circuit includes: a fifth transistor and a first storage capacitor;

[0022] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal;

[0023] One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line.

[0024] Optionally, the second output sub-circuit includes: a fourth transistor and a second storage capacitor;

[0025] The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal;

[0026] One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

[0027] Optionally, the transistors in each sub-circuit are all oxide thin film transistors.

[0028] Optionally, a width-to-length ratio of the second transistor is greater than a width-to-length ratio of the third transistor.

[0029] In a second aspect, an embodiment of the present disclosure provides a shift register, wherein the shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first storage capacitor, and a second storage capacitor;

[0030] The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node;

[0031] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node;

[0032] The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node;

[0033] The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node;

[0034] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal;

[0035] One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line;

[0036] The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal;

[0037] One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

[0038] In a third aspect, an embodiment of the present disclosure provides a display substrate, wherein the display substrate comprises: a base, and a plurality of shift registers provided above that are cascaded on the base.

[0039] Optionally, the display substrate further comprises: a plurality of clock signal lines and power signal lines; the clock signal lines at least comprise: a first clock signal line and a second clock signal line; the power signal lines at least comprise: a first level signal line and a second level signal line;

[0040] The plurality of clock signal lines and the power signal lines extend along a first direction and are arranged side by side along a second direction; the first direction and the second direction intersect;

[0041] The width of the clock signal line along the second direction is greater than the width of the power signal line along the second direction.

[0042] Optionally, the first transistor, the second transistor, the third transistor and the sixth transistor in each of the shift registers are divided into a first transistor group;

[0043] The active layers in the first transistor group are arranged along a first direction and are disposed side by side along the first direction.

[0044] Optionally, each active layer in the first transistor group is located between adjacent power signal lines, and a width of each active layer along the second direction is smaller than a distance between adjacent power signal lines.

[0045] Optionally, the width of each active layer in the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

[0046] Optionally, a width of the first transistor group along the second direction is smaller than a width of the clock signal line along the second direction, and is greater than or equal to a width of the power signal line along the second direction.

[0047] Optionally, the fourth transistor and the fifth transistor in each of the shift registers are divided into a second transistor group;

[0048] The active layers in the second transistor group are arranged along the first direction and arranged side by side along the second direction.

[0049] Optionally, each active layer in the second transistor group is located on a side of the power signal line away from the clock signal line.

[0050] Optionally, a width of each active layer in the second transistor group along the second direction is greater than a width of the clock signal line along the second direction.

[0051] Optionally, the orthographic projection of the first storage capacitor on the substrate is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the fourth transistor on the substrate;

[0052] The orthographic projection of the second storage capacitor on the substrate is located on a side of the orthographic projection of the fifth transistor on the substrate away from the orthographic projection of the second level signal line on the substrate.

[0053] Optionally, an orthographic projection of the first storage capacitor on the substrate at least partially overlaps with an orthographic projection of the second level signal line on the substrate.

[0054] In a fourth aspect, an embodiment of the present disclosure provides a display device, wherein the display device includes the display substrate provided as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG1 is a schematic diagram of a circuit structure of an exemplary shift register.

[0056] FIG2 is a schematic diagram of a planar structure of the shift register shown in FIG1 .

[0057] FIG3 is a schematic diagram of the circuit structure of the shift register provided in an embodiment of the present disclosure.

[0058] FIG4 is a schematic diagram of a planar structure of the shift register shown in FIG3 .

[0059] FIG5 is a timing diagram of the shift register shown in FIG3 .

[0060] FIG6 is a schematic diagram of the circuit structure of another shift register provided by an embodiment of the present disclosure.

[0061] FIG7 a is a schematic structural diagram of a first gate conductive layer in a display substrate provided by an embodiment of the present disclosure.

[0062] FIG7 b is a schematic structural diagram of the second gate conductive layer in the display substrate provided by an embodiment of the present disclosure.

[0063] FIG7 c is a schematic structural diagram of a semiconductor layer in a display substrate provided in an embodiment of the present disclosure.

[0064] FIG7 d is a schematic structural diagram of the third gate conductive layer in the display substrate provided in an embodiment of the present disclosure.

[0065] FIG7e is a schematic structural diagram of the source-drain conductive layer in the display substrate provided in an embodiment of the present disclosure.

[0066] FIG. 7 f shows the stacked structure of each film layer in FIG. 7 a to FIG. 7 e . DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0068] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "electrically connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0069] It should be noted that the transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, to distinguish the source and drain of the transistor, one of the electrodes is referred to as the first electrode, the other electrode is referred to as the second electrode, and the gate is referred to as the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. The following embodiments are described using N-type transistors. When an N-type transistor is used, the first electrode is the source of the N-type transistor and the second electrode is the drain of the N-type transistor. When the gate input is high, the source and drain are conductive, while the P-type is the opposite. It is conceivable that the use of P-type transistors is something that a person skilled in the art can easily come up with without creative effort, and therefore it is also within the scope of protection of the embodiments of the present disclosure. In addition, according to the material of the active layer in the transistor, transistors can be divided into types such as oxide thin-film transistors and low-temperature polysilicon thin-film transistors. Generally, oxide thin-film transistors are N-type transistors, and low-temperature polysilicon thin-film transistors are P-type transistors.

[0070] Among them, since the transistor used in the embodiment of the present disclosure is an N-type transistor, the working level signal, i.e., the first level signal, in the embodiment of the present disclosure is a high level signal, and the non-working level signal, i.e., the second level signal, is a low level signal; the corresponding first level signal line is a high level signal line, and the second level signal line is a low level signal line.

[0071] Typically, a display substrate includes multiple gate lines and multiple data lines. The gate lines and data lines intersect to define multiple pixel regions, each of which is provided with pixel cells. The structure of the display substrate is described below using the example of the gate lines extending in the row direction and the data lines extending in the column direction. When driving the display substrate for display, scanning signals can be written to the gate lines row by row, and data voltage signals can be written to the data lines simultaneously, so that the pixel cells in the display substrate are illuminated row by row, depending on the image to be displayed.

[0072] Among them, the scanning signal is provided by the gate driving circuit, and the data voltage signal is provided by the source driving circuit; in the related technology, the gate driving circuit can be integrated into the gate driving chip, and the source driving circuit can be integrated into the source driving chip; and currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a technology for integrating the gate driving circuit on an array substrate (Gate On Array; GOA) is provided; wherein, the gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is electrically connected to a gate line one by one, and is used to provide a scanning signal to the gate line electrically connected thereto.

[0073] In order to make it clearer how the shift register outputs the scanning signal, a specific example of the shift register is used for explanation below.

[0074] Figure 1 is a schematic diagram of the circuit structure of an exemplary shift register. As shown in Figure 1, the shift register includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first storage capacitor C1, and a second storage capacitor C2.

[0075] The gate of the first transistor T1 is electrically connected to the first clock signal line GCK, the source is electrically connected to the signal input terminal Input, and the drain is electrically connected to the first node N1; the first node N1 is the connection point between the drain of the first transistor T1, the gate of the second transistor T2, the source of the seventh transistor T7 and the source of the eighth transistor T8.

[0076] The gate of the second transistor T2 is electrically connected to the first node N1, the source is electrically connected to the first clock signal line GCK, and the drain is electrically connected to the second node N2; the second node N2 is the connection point between the drain of the second transistor T2, the drain of the third transistor T3, the gate of the sixth transistor T6, the gate of the fourth transistor T4, and one end of the first storage capacitor C1.

[0077] The third transistor T3 has a gate electrically connected to the first clock signal line GCK, a source electrically connected to the low-level signal line VGL, and a drain electrically connected to the second node N2.

[0078] The fourth transistor T4 has a gate electrically connected to the second node N2 , a source electrically connected to the high-level signal line VGH and the other end of the first storage capacitor C2 , and a drain electrically connected to the signal output end Output.

[0079] The gate of the fifth transistor T5 is electrically connected to the third node N3, the source is electrically connected to the second clock signal line GCB, and the drain is electrically connected to the signal output terminal Output and the other end of the second storage capacitor C2; the third node N3 is the connection point between the gate of the fifth transistor T5, the drain of the eighth transistor T8 and one end of the second storage capacitor C2.

[0080] The sixth transistor T6 has a gate electrically connected to the second node N2 , a source electrically connected to the high-level signal line VGH, and a drain electrically connected to the source of the seventh transistor T7 .

[0081] The gate of the seventh transistor T7 is electrically connected to the second clock signal line GCB, the source is electrically connected to the drain of the sixth transistor T6 , and the drain is electrically connected to the first node N1 .

[0082] The eighth transistor T8 has a gate electrically connected to the low-level signal line VGL, a source electrically connected to the first node N1 , and a drain electrically connected to the third node N3 .

[0083] One end of the first storage capacitor C1 is electrically connected to the first node N1 , and the other end is electrically connected to the high-level signal line VGH and the source of the fourth transistor T4 .

[0084] One end of the second storage capacitor C2 is electrically connected to the third node N3 , and the other end is electrically connected to the drain of the fifth transistor T5 and the signal output terminal Output.

[0085] The shift register shown in Figure 1 can be a first-stage shift register in a gate drive circuit, and its signal input terminal Input can be connected to the frame start signal line GSTV. When the shift register is not a first-stage shift register, its input terminal Input is cascaded with the shift registers of other stages, and a high-level signal or a second clock signal can be output from the signal output terminal Output according to a preset timing. The specific implementation process can refer to the description in the relevant technology and will not be described in detail here.

[0086] In the shift register shown in FIG1 , each transistor can be configured as a low-temperature polysilicon (LTPS) thin-film transistor to achieve higher mobility. Due to the large number of transistors, the entire shift register occupies a relatively large area. FIG2 is a schematic plan view of the shift register shown in FIG1 . As shown in FIG2 , the shift register structure is relatively complex, with a width of 266 microns along the row direction. While the width along the column direction remains constant, the shift register occupies a relatively large area, affecting the narrow-frame design of the display substrate.

[0087] In order to solve at least one of the above technical problems, the embodiments of the present disclosure provide a shift register, a display substrate and a display device. The shift register, display substrate and display device provided by the embodiments of the present disclosure will be further described in detail below in combination with the drawings and specific implementation methods.

[0088] In the first aspect, an embodiment of the present disclosure provides a shift register. Figure 3 is a schematic diagram of the circuit structure of the shift register provided by the embodiment of the present disclosure. As shown in Figure 3, the shift register includes: a first input sub-circuit 301, a second input sub-circuit 302, a control sub-circuit 303, a protection sub-circuit 304, a first output sub-circuit 305 and a second output sub-circuit 306.

[0089] The first input sub-circuit 301 is configured to transmit a first-level signal to a first node N1 in response to a first clock signal. The first node N1 is the connection point between the first input sub-circuit 301, the first output sub-circuit 305, and the control sub-circuit 302. The second input sub-circuit 302 is configured to transmit an input signal to a second node N2 in response to the first clock signal. The second node N2 is the connection point between the second input sub-circuit 302 and the protection sub-circuit 304. The control sub-circuit 303 is configured to input a second-level signal to the first node N1 in response to a second clock signal. The protection sub-circuit 304 is configured to transmit the voltage of the second node N2 to a third node N3 when the second input sub-circuit 302 is operating. When the second input sub-circuit 302 is not operating, the protection sub-circuit 304 is configured to input the voltage of the third node N3 to the second node N2, thereby lowering the voltage of the second node N2 to a lower voltage than the third node N3. The third node N3 is the connection point between the protection sub-circuit 304 and the second output sub-circuit 306. The first output sub-circuit 305 is configured to output a second level signal in response to the voltage of the first node N1 , and the second output sub-circuit 306 is configured to output a second clock signal in response to the voltage of the third node N3 .

[0090] In the shift register provided in the embodiment of the present disclosure, the signal in the first input subcircuit 301 is output through the first output subcircuit 305, and the signal in the second input subcircuit 302 is output through the second output subcircuit 306. When the display substrate is driven to display, a scanning signal can be written to the gate line row by row according to the image to be displayed, so that the pixel units in the display substrate are illuminated row by row. It can be seen that the shift register provided in the embodiment of the present disclosure has a simple structure, which can reduce the number of transistors in the shift register, thereby reducing the area occupied by the shift register, which is conducive to the narrow frame design of the display substrate, thereby improving the user experience. At the same time, the protection subcircuit 304 can transmit the voltage of the third node N3 to the second node N2 when the second input subcircuit 302 is not working, so that the voltage of the second node N2 is lower than the voltage of the third node N3, thereby preventing the voltage of the third node N3 from being directly transmitted to the second input subcircuit 302. Therefore, it can be prevented that the higher voltage will not break down the components in the second input subcircuit 302 that are in a non-working state, thereby improving the stability and service life of the components in the shift register, and further improving the display effect.

[0091] Specifically, as shown in Figure 3, the first input sub-circuit 301 includes a third transistor T3 having a gate electrically connected to the first clock signal line GCK, a source electrically connected to the high-level signal line VGH, and a drain electrically connected to the first node N1. The control sub-circuit 304 includes a second transistor T2 having a gate electrically connected to the second clock signal line GCB, a source electrically connected to the low-level signal line VGL, and a drain electrically connected to the first node N1.

[0092] When the first clock signal inputted by the first clock signal line GCK is a high-level signal and the second clock signal inputted by the second clock signal line GCB is a low-level signal, the third transistor T3 is turned on and the second transistor T2 is turned off. The high-level signal inputted by the high-level signal line VGH can be inputted to the first node N1 through the third transistor T3, charging the first node N1 and thereby pulling the voltage of the first node N1 high. When the first clock signal inputted by the first clock signal line GCK is a low-level signal and the second clock signal inputted by the second clock signal line GCB is a high-level signal, the second transistor T2 is turned on and the third transistor T3 is turned off. The low-level signal inputted by the low-level signal line VGL can be inputted to the first node N1 through the second transistor T2, thereby pulling the voltage of the first node N1 low.

[0093] Continuing with FIG3 , the second input sub-circuit 302 includes a first transistor T1 having a gate electrically connected to the first clock signal line GCK, a source electrically connected to the signal input terminal Input, and a drain electrically connected to the second node N2. The protection sub-circuit 303 includes a sixth transistor T6 having a gate electrically connected to the high-level signal line VGH, a source electrically connected to the second node N2, and a drain electrically connected to the third node N3.

[0094] When the first clock signal line GCK is a high-level signal, the first transistor T1 is turned on, and the high-level signal (which can be a frame start signal) input by the signal input terminal Input can be input to the second node N2 through the first transistor T1, charging the second node N2 to increase the voltage of the second node N2. At the same time, the sixth transistor T6 is in a normally open state under the control of the high-level signal, and the voltage of the second node N2 is transmitted to the third node N3 through the sixth transistor T6. When the first clock signal line GCK is a low-level signal, the first transistor T1 is turned off. At this time, the third node N3 has been charged for a long time and is at a higher voltage. If it is directly transmitted to the drain of the closed first transistor T1, it is easy to break down the first transistor T, causing damage to the first transistor T1. The sixth transistor T6 is in a normally open state, which has a certain impedance. It can play a good role in reducing the voltage of the third node N3 during the transmission process to the second node N2, preventing the first transistor T2 from breaking down, thereby ensuring the performance stability of the first transistor T1.

[0095] Continuing with FIG3 , the first output sub-circuit 305 includes a fifth transistor T5 and a first storage capacitor C1. The fifth transistor T5 has a gate electrically connected to the first node N1, a source electrically connected to the low-level signal line VGL, and a drain electrically connected to the signal output terminal Output. One end of the first storage capacitor C1 is electrically connected to the first node N1, and the other end is electrically connected to the low-level signal line VGL. The second output sub-circuit 306 includes a fourth transistor T4 and a second storage capacitor C2. The fourth transistor T4 has a gate electrically connected to the third node N3, a source electrically connected to the second clock signal line GCB, and a drain electrically connected to the signal output terminal Output. One end of the second storage capacitor C2 is electrically connected to the third node N3, and the other end is electrically connected to the signal output terminal Output.

[0096] When the voltage at the first node N1 is a high-level signal, the fifth transistor T5 is turned on, and the low-level signal input from the low-level signal line VGL can be output by the signal output terminal Output. At the same time, when the voltage at the third node N3 is a high-level signal, the fourth transistor T4 is turned on, and the low-level signal in the second clock signal input from the second clock signal line GCB can be output by the signal output terminal Output. At this time, the low-level signal in the second clock signal is the same as the level signal input from the low-level signal line VGL. When the voltage at the first node N1 is a level signal, the fifth transistor T5 is turned off. At the same time, when the voltage at the third node N3 is a high-level signal, the fourth transistor T4 is turned on, and the high-level signal in the second clock signal input from the second clock signal line GCB can be output by the signal output terminal Output.

[0097] In some embodiments, the width-to-length ratio of the second transistor T2 is greater than the width-to-length ratio of the third transistor T3 .

[0098] In practical applications, the width-to-length ratio of the second transistor T2 can be appropriately increased so that the second transistor T2 has higher stability and can transmit a larger current. When the second transistor T2 is turned on, the low-level signal input by the low-level signal line VGL can be stably input to the first node N1, thereby controlling the fifth transistor T5 to be completely turned off, avoiding leakage current, and thereby improving the stability of the signal output at the signal output terminal Output.

[0099] Figure 4 is a schematic planar structural diagram of the shift register shown in Figure 3. As shown in Figure 4, the shift register is provided with only six transistors, significantly reducing the number of transistors and simplifying the circuit structure compared to the shift register structures shown in Figures 1 and 2. Furthermore, the width of the shift register along the row direction is 226 microns, which is 40 microns smaller than the width of the shift register shown in Figures 1 and 2, a reduction of 15% of the original width. This facilitates the narrow-frame design of the display substrate, thereby improving user experience.

[0100] FIG5 is a timing diagram of the shift register shown in FIG3 . The working principle of the shift register provided by the embodiment of the present disclosure will be further described in detail below in conjunction with the timing diagram.

[0101] In the first phase, the signal on the first clock signal line GCK is a high-level signal, the signal on the second clock signal line GCB is a low-level signal, the first transistor T1 and the third transistor T3 are both turned on, the second transistor T2 is turned off, the high-level signal inputted by the high-level signal line VGH can charge the first node N1, and the frame start signal inputted by the signal input terminal Input can charge the second node N2 and the third node N3, so that the voltages of the first node N1, the second node N2, and the third node N3 are all high-level voltages. At this time, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the voltage of the signal output terminal Output is reset by the low-level signal inputted by the low-level signal line VGL and the low-level signal of the second clock signal line GCB.

[0102] In the second phase, the signal on the first clock signal line GCK is a low-level signal, the signal on the second clock signal line GCB is a high-level signal, the first transistor T1 and the third transistor T3 are both turned off, the second transistor T2 is turned on, and the voltage at the first node N1 is pulled low by the low-level signal input from the low-level signal line VGL, causing the fourth transistor T4 to turn off. The voltage at the third node N3 continues to remain high-level due to the action of the second storage capacitor C2, the fifth transistor T5 is turned on, and the high-level signal of the second clock signal GCB is output from the signal output terminal Output.

[0103] In the third phase, the signal on the first clock signal line GCK is a high-level signal, the signal on the second clock signal line GCB is a low-level signal, the first transistor T1 and the third transistor T3 are both turned on, the second transistor T2 is turned off, the voltage on the first node N1 is pulled high again, the fourth transistor T4 is turned on, and the low-level signal inputted by the low-level signal line VGL is outputted by the signal output terminal Output. At this time, a low-level signal is inputted to the signal input terminal Input, and the fifth transistor T5 is turned off.

[0104] In the fourth phase, the signal on the first clock signal line GCK is a low-level signal, the signal on the second clock signal line GCB is a high-level signal, the first transistor T1 and the third transistor T3 are both off, the second transistor T2 is on, and the voltage of the first node N1 is pulled low by the low-level signal input from the low-level signal line VGL, turning off the fourth transistor T4. Simultaneously, a low-level signal is input to the signal input terminal Input, turning off the fifth transistor T5, and the signal output terminal Output has no signal output and is in a noise reduction state.

[0105] In a second aspect, an embodiment of the present disclosure provides a shift register. FIG6 is a schematic diagram of the circuit structure of another shift register provided by an embodiment of the present disclosure. As shown in FIG6 , the shift register includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first storage capacitor C1, and a second storage capacitor C2. The gate of the third transistor T3 is electrically connected to the first clock signal line GCK, the source is electrically connected to the high-level signal line VGH, and the drain is electrically connected to the first node N1. The gate of the second transistor T2 is electrically connected to the second clock signal line GCB, the source is electrically connected to the low-level signal line VGL, and the drain is electrically connected to the first node N1. The gate of the first transistor T1 is electrically connected to the first clock signal line GCK, the source is electrically connected to the signal input terminal Input, and the drain is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the high-level signal line VGH, the source is electrically connected to the second node N2, and the drain is electrically connected to the third node N3. The fifth transistor T5 has a gate electrically connected to the first node N1, a source electrically connected to the low-level signal line VGL, and a drain electrically connected to the signal output terminal Output. The first storage capacitor C1 has one end electrically connected to the first node N1 and another end electrically connected to the low-level signal line VGL. The fourth transistor T4 has a gate electrically connected to the third node N3, a source electrically connected to the second clock signal line GCB, and a drain electrically connected to the signal output terminal Output. The second storage capacitor C2 has one end electrically connected to the third node N3 and another end electrically connected to the signal output terminal Output.

[0106] The shift register provided in the embodiment of the present disclosure is a specific circuit structure of the shift register provided in any of the above embodiments, and its implementation principle is the same as the implementation principle of the shift register provided in any of the above embodiments, which will not be described again here.

[0107] In a third aspect, embodiments of the present disclosure provide a display substrate comprising: a substrate (not shown) and a plurality of shift registers, as provided in any of the above embodiments, cascaded on the substrate. Figures 7a through 7f are schematic diagrams of the structures of the various film layers in the display substrate provided in embodiments of the present disclosure. The display substrate provided in embodiments of the present disclosure will be further described below in conjunction with the structures of the various film layers.

[0108] Figure 7a is a schematic structural diagram of the first gate conductive layer in the display substrate provided by an embodiment of the present disclosure. As shown in Figure 7a, the first gate conductive layer includes: first plates of the first storage capacitor C1 and the second storage capacitor C2, and connecting lines electrically connecting the first plates.

[0109] Figure 7b is a schematic diagram of the structure of the second gate conductive layer in the display substrate provided by an embodiment of the present disclosure. As shown in Figure 7b, the second gate conductive layer includes: second plates of the first storage capacitor C1 and the second storage capacitor C2, and a connecting line electrically connecting the second plates. The first and second gate conductive layers are both formed on a substrate, and the orthographic projections of the corresponding first and second plates on the substrate overlap to form the first and second storage capacitors C1 and C2.

[0110] Figure 7c is a schematic diagram of the structure of the semiconductor layer in the display substrate provided by an embodiment of the present disclosure. As shown in Figure 7c, the semiconductor layer includes the active layers of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The active layers of each transistor are made of an oxide material, such as a metal oxide such as indium gallium zinc oxide (IGZO).

[0111] Figure 7d is a schematic structural diagram of the third gate conductive layer in the display substrate provided in an embodiment of the present disclosure. As shown in Figure 7d, the third gate conductive layer includes: gates of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, as well as connecting lines electrically connecting the respective gates.

[0112] Figure 7e is a schematic structural diagram of the source-drain conductive layer in the display substrate provided in an embodiment of the present disclosure. As shown in Figure 4e, the source-drain conductive layer includes: the source and drain of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, as well as the frame start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, the high-level signal line VGH and the low-level signal line VGL, and connecting lines electrically connecting each source, drain and each signal line.

[0113] Figure 7f shows the stacked structure of the film layers in Figures 7a to 7e. The above film layers are stacked together to form a shift register in the display substrate, which has the same structure as that shown in Figure 4.

[0114] Continuing to refer to Figures 7e and 7f, the display substrate also includes: multiple clock signal lines and power signal lines; the clock signal lines include at least: a first clock signal line GCK and a second clock signal line GCB; the power signal lines include at least: a high-level signal line VGH and a low-level signal line VGL; the multiple clock signal lines and power signal lines extend along the first direction and are arranged side by side along the second direction; the second direction intersects with the first direction; the width of the clock signal lines along the second direction is greater than the width of the power signal lines along the second direction.

[0115] In the embodiment of the present disclosure, the first direction can be the row direction of the display substrate, and the second direction can be the column direction of the display substrate. The first clock signal line GCK, the second clock signal line GCB, the high-level signal line VGH and the low-level signal line VGL can extend along the same direction (first direction), that is, the column direction. Among them, the first clock signal line GCK and the second clock signal line GCB in the clock signal line transmit constantly changing voltage signals, and the high-level signal line VGH and the low-level signal line VGL in the power signal line transmit stable voltage signals. In order to avoid the clock signal line from generating a large parasitic capacitance, the width of the clock signal line along the second direction is greater than the width of the power signal line along the second direction. For example, the width of the first clock signal line GCK along the second direction is greater than the width of the high-level signal line VGH along the second direction to ensure efficient transmission of the signal. It should be noted here that, taking the first clock signal line GCK as an example, the first clock signal line GCK is not a straight line. It is generally extended along the first direction, and there may be bends at certain positions. At a certain section of the bend, the section can extend along the second direction, and the width of the first clock signal line GCK along the second direction may be the length of the section along the second direction.

[0116] 7 c , the first transistor T1 , the second transistor T2 , the third transistor T3 and the sixth transistor T6 are divided into a first transistor group; the active layers in the first transistor group are arranged along the first direction and are arranged side by side along the first direction.

[0117] The drains of the first transistor T1 and the sixth transistor T6 are connected together. In practical applications, the active layer of the first transistor T1 and the active layer of the sixth transistor T6 can be directly connected together, that is, the active layers of the two are part of a whole, so as to reduce the drilling process when forming the drain and save the manufacturing cost.

[0118] The transistors can be divided into multiple groups according to their positions relative to the power signal line in the display substrate. For example, the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6 can be divided into a first transistor group, and the fourth transistor T4 and the fifth transistor T5 can be divided into a second transistor group.

[0119] The active layer of the first transistor group can be shaped like a rectangle, with the longer sides of the rectangle arranged along the first direction, i.e., along the column direction, and the shorter sides arranged along the second direction, i.e., along the row direction. Each active layer in the first transistor group can be divided into three parts, wherein the first part is the active layer of the first transistor T1 and the sixth transistor T6, the second part is the active layer of the second transistor T2, and the third part is the active layer of the third transistor. Each active layer in the first transistor group can be arranged along the first direction and arranged side by side along the first direction, which can reduce the width occupied by each active layer in the first transistor group along the row direction, thereby reducing the width of the entire shift register in the display substrate, facilitating a narrow bezel design of the display substrate, and thereby improving user experience.

[0120] Continuing to refer to FIG7c, FIG7e and FIG7f, each active layer in the first transistor group is located between adjacent power signal lines, and the width of each active layer along the second direction is smaller than the distance between adjacent power signal lines.

[0121] Since the high-level signal line VGH and the low-level signal line VGL transmit stable voltage signals, they will not interfere with other conductive layers. Therefore, each active layer in the first transistor group can be arranged between the high-level signal line VGH and the low-level signal line VGL, and the width of each active layer along the second direction is smaller than the distance between adjacent high-level signal lines VGH and low-level signal lines VGL, so as to further reduce the width occupied by the first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 in the first transistor group along the first direction, thereby reducing the width of the entire shift register, which is conducive to the narrow-frame design of the display substrate and thus improves the user experience.

[0122] Continuing to refer to FIG7c, FIG7e and FIG7f, the width of each active layer in the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

[0123] The first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6 in the first transistor group do not directly output to the pixel circuit in the display area, and the width of their active layers along the second direction can be relatively small. For example, their width along the second direction can be smaller than the width of the clock signal line (the first clock signal line GCK or the second clock signal line GCB) along the second direction, and greater than or equal to the width of the power signal line (the high-level signal line VGH or the low-level signal line VGL) along the second direction. While ensuring the performance stability of each transistor, the width occupied by each transistor along the row direction can be reduced, thereby reducing the width of the entire shift register, which is conducive to the narrow-frame design of the display substrate and thus improves the user experience.

[0124] In some embodiments, as shown in FIG. 7 f , the width of the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

[0125] The first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6 in the first transistor group are arranged side by side along the first direction, that is, the first transistor group is arranged as a whole along the first direction. The width of the first transistor group along the second direction is the width of each transistor therein along the second direction, wherein the width of each transistor along the second direction includes not only the width of the active layer along the second direction mentioned above, but also the width of the thin film transistor along the second direction including the source, drain, gate, and other structures. If the widths of the transistors along the second direction are different, then the largest width of the transistors along the second direction is the width of the first transistor group along the second direction. For example, the width of the first transistor group along the second direction can be less than the width of the clock signal line (the first clock signal line GCK or the second clock signal line GCB) along the second direction, and greater than or equal to the width of the power signal line (the high level signal line VGH or the low level signal line VGL) along the second direction. While ensuring the performance stability of each transistor in the first transistor group, the width occupied by the first transistor group along the row direction can be reduced, thereby reducing the width of the entire shift register, which is conducive to the narrow frame design of the display substrate and thus improving the user experience.

[0126] Continuing to refer to FIG7c, FIG7e and FIG7f, the fourth transistor T4 and the fifth transistor T5 are divided into a second transistor group; the active layers in the second transistor group are arranged along the first direction and arranged side by side along the second direction.

[0127] The fourth transistor T4 and the fifth transistor T5 in the second transistor group serve as output transistors, which output directly to the pixel circuit in the display area. They can be arranged in different areas from the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6 in the first transistor group mentioned above to ensure the performance of the fourth transistor T4 and the fifth transistor T5 in the second transistor group and improve the stability of the output gate drive signal. Specifically, the active layers in the second transistor group can be arranged along the first direction and arranged side by side along the second direction to increase the area of ​​each active layer in the second transistor group. At the same time, they can be arranged on the side of the power signal line away from the clock signal line, and between the adjacent signal lines that do not need to be set, to form an active layer with a larger area to ensure the performance stability of the output transistor.

[0128] Continuing to refer to FIG7 c , FIG7 e and FIG7 f , the width of each active layer in the second transistor group along the second direction is greater than the width of the clock signal line along the second direction.

[0129] The width of each active layer in the second transistor group along the second direction is larger. For example, the width of each active layer in the second transistor group along the second direction is greater than the width of the clock signal line (the first clock signal line GCK or the second clock signal line GCB), so as to ensure that the fourth transistor T4 and the fifth transistor T5 in the second transistor group have higher overall stability, thereby improving the stability of the output gate drive signal.

[0130] Continuing to refer to Figures 7a, 7b to 7f, the orthographic projection of the first storage capacitor C1 on the substrate is located between the orthographic projection of the high-level signal line VGH on the substrate and the orthographic projection of the fourth transistor T4 on the substrate; the orthographic projection of the second storage capacitor C2 on the substrate is located on the side of the orthographic projection of the fifth transistor T5 on the substrate away from the orthographic projection of the low-level signal line VGL on the substrate.

[0131] The first storage capacitor C1 and the film layers of each transistor are all arranged in different film layers. The first storage capacitor C1 can be arranged between the high-level signal line VGH and the fourth transistor T4 to ensure stable electrical connection between it and each transistor. Similarly, the second storage capacitor C2 can be arranged on the side of the fifth transistor T5 away from the low-level signal line VGL to ensure stable electrical connection between it and each transistor.

[0132] Continuing to refer to FIG. 7 a and FIG. 7 b to FIG. 7 f , the orthographic projection of the first storage capacitor C1 on the substrate at least partially overlaps with the orthographic projection of the low-level signal line VGL on the substrate.

[0133] The first storage capacitor C1 can be disposed in a different film layer than the film layers of each transistor, and its orthographic projection on the substrate can at least partially overlap with the orthographic projection of the low-level signal line VGL on the substrate, thereby further reducing the width of the first storage capacitor C1 along the row direction, thereby reducing the width of the entire shift register, facilitating a narrow-frame design for the display substrate and thereby improving user experience. Furthermore, the first storage capacitor C1 and the second storage capacitor C2 can be rectangular or similar in shape, with the longer sides of the rectangle arranged along the first direction and the narrower sides arranged along the second direction. This can further reduce the width of the first storage capacitor C1 and the second storage capacitor C2 along the row direction, thereby reducing the width of the entire shift register, facilitating a narrow-frame design for the display substrate and thereby improving user experience.

[0134] Fourthly, embodiments of the present disclosure provide a display device comprising a shift register and a display substrate as provided in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a television, mobile phone, monitor, laptop computer, digital photo frame, or navigation system. The implementation principles of the display device are similar to those of the aforementioned shift register and display substrate and will not be further elaborated here.

[0135] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, wherein: The shift register comprises: a first input subcircuit, a second input subcircuit, a control subcircuit, a protection subcircuit, a first output subcircuit and a second output subcircuit; The first input subcircuit is configured to transmit a first level signal to a first node in response to a first clock signal; the first node is a connection point between the first input subcircuit, the first output subcircuit and the control subcircuit; The second input subcircuit is configured to transmit the input signal to a second node in response to the first clock signal; the second node is a connection point between the second input subcircuit and the protection subcircuit; The control subcircuit is configured to input a second level signal to the first node in response to a second clock signal; The protection subcircuit is configured to transmit the voltage of the second node to the third node when the second input subcircuit is working; when the second input subcircuit is not working, input the voltage of the third node to the second node and make the voltage of the second node lower than the voltage of the third node; the third node is a connection point between the protection subcircuit and the second output subcircuit; The first output subcircuit is configured to output a second level signal in response to the voltage of the first node; The second output sub-circuit is configured to output a second clock signal in response to a voltage of the third node.

2. The shift register according to claim 1, wherein: The first input subcircuit comprises: a third transistor; The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node.

3. The shift register according to claim 2, wherein: The second input subcircuit includes: a first transistor; The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node.

4. The shift register according to claim 3, wherein: The protection subcircuit comprises: a sixth transistor; The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node.

5. The shift register according to claim 4, wherein: The control subcircuit includes: a second transistor; The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node.

6. The shift register according to claim 5, wherein: The first output subcircuit includes: a fifth transistor and a first storage capacitor; The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal; One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line.

7. The shift register according to claim 6, wherein: The second output subcircuit includes: a fourth transistor and a second storage capacitor; The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal; One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

8. The shift register according to any one of claims 1 to 7, wherein: The transistors in each sub-circuit are all oxide thin film transistors.

9. The shift register according to claim 8, wherein: The width-to-length ratio of the second transistor is greater than the width-to-length ratio of the third transistor.

10. A shift register, wherein: The shift register comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first storage capacitor, and a second storage capacitor; The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node; The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node; The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal; One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line; The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal; One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

11. A display substrate, wherein: The display substrate comprises: a base, and a plurality of shift registers according to any one of claims 1 to 10 cascaded on the base.

12. The display substrate according to claim 11, wherein: The display substrate further comprises: a plurality of clock signal lines and power signal lines; the clock signal lines at least comprise: a first clock signal line and a second clock signal line; the power signal lines at least comprise: a first level signal line and a second level signal line; A plurality of the clock signal lines and the power signal lines extend along a first direction and are arranged side by side along a second direction; the first direction and the second direction intersect; The width of the clock signal line along the second direction is greater than the width of the power signal line along the second direction.

13. The display substrate according to claim 12, wherein: The first transistor, the second transistor, the third transistor and the sixth transistor in each of the shift registers are divided into a first transistor group; The active layers in the first transistor group are arranged along a first direction and are disposed side by side along the first direction.

14. The display substrate according to claim 13, wherein: Each active layer in the first transistor group is located between adjacent power signal lines, and a width of each active layer along the second direction is smaller than a distance between adjacent power signal lines.

15. The display substrate according to claim 14, wherein: The width of each active layer in the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

16. The display substrate according to claim 15, wherein: The width of the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

17. The display substrate according to claim 12, wherein: The fourth transistor and the fifth transistor in each of the shift registers are divided into a second transistor group; The active layers in the second transistor group are arranged along the first direction and are arranged side by side along the second direction.

18. The display substrate according to claim 17, wherein: Each active layer in the second transistor group is located on a side of the power signal line away from the clock signal line.

19. The display substrate according to claim 17, wherein: The width of each active layer in the second transistor group along the second direction is greater than the width of the clock signal line along the second direction.

20. The display substrate according to claim 12, wherein: The orthographic projection of the first storage capacitor on the substrate is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the fourth transistor on the substrate; The orthographic projection of the second storage capacitor on the substrate is located on a side of the orthographic projection of the fifth transistor on the substrate away from the orthographic projection of the second level signal line on the substrate.

21. The display substrate according to claim 20, wherein: An orthographic projection of the first storage capacitor on the substrate at least partially overlaps with an orthographic projection of the second level signal line on the substrate.

22. A display device, wherein: The display device comprises the display substrate according to any one of claims 11 to 21.

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