Detection device and method for manufacturing detection device

Abstract

This detection device comprises: a substrate; an organic insulating film and a barrier film laminated on the substrate; an organic light sensor in which a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and an upper electrode are laminated in this order on the barrier film in a detection region of the substrate; and a sealing film covering the organic light sensor. Side surfaces of the lower buffer layer, the active layer, and the upper buffer layer are covered with the upper electrode, and the upper electrode is covered with the sealing film.

Description

Detection device and method for manufacturing the same

[0001] The present invention relates to a detection device and a method for manufacturing a detection device.

[0002] Optical sensors capable of detecting fingerprint patterns and vein patterns are known (see, for example, Patent Document 1). Such optical sensors have multiple photodiodes (OPDs: Organic Photodiodes) that use an organic semiconductor material as an active layer. As described in Patent Document 2, the photodiodes are stacked, for example, in the following order: a lower electrode, an electron transport layer, an active layer, a hole transport layer, and an upper electrode. The electron transport layer or the hole transport layer is also called a buffer layer.

[0003] Japanese Patent Application Laid-Open No. 2009-32005 International Publication No. 2020 / 188959 Japanese Patent Application Laid-Open No. 2002-038254 Japanese Patent Application Laid-Open No. 2005-120406 Japanese Patent Application Laid-Open No. 2005-068501

[0004] In the manufacturing process of a detection device having an OPD, during the film formation process using a patterning mask, the patterning mask may come into contact with the film surface of the active layer, etc. Scratches or foreign matter on the film surface of the active layer, etc., can cause film thickness and shape variations on the outer edge of the OPD. Such film thickness and shape variations can change the state of light incident on the organic photosensor, potentially reducing detection accuracy.

[0005] Patent Documents 3 to 5 describe techniques related to masks used in forming conductive films and color filters of liquid crystal display devices. However, Patent Documents 3 to 5 do not describe a detection device having an OPD or a manufacturing method thereof.

[0006] An object of the present invention is to provide a detection device that can prevent scratches on an organic photosensor and adhesion of foreign matter thereto, and a method for manufacturing the detection device.

[0007] A detection device according to one embodiment of the present invention includes a substrate, an organic insulating film and a barrier film stacked on the substrate, an organic photosensor in a detection region of the substrate, the organic photosensor being formed by stacking a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and an upper electrode in this order on the barrier film, and a sealing film covering the organic photosensor, wherein side surfaces of the lower buffer layer, the active layer, and the upper buffer layer are covered by the upper electrode, and the upper electrode is covered by the sealing film.

[0008] A method for manufacturing a detection device according to one aspect of the present invention includes the steps of: forming an organic insulating film, a barrier film, a lower electrode, a lower buffer layer, an active layer, and an upper buffer layer on a substrate in this order; forming an upper metal layer on the upper buffer layer using a first patterning mask in a region of the substrate corresponding to a detection region, and removing the lower buffer layer, the active layer, and the upper buffer layer in regions where the upper metal layer is not provided; and forming an upper electrode on the upper metal layer using a second patterning mask, wherein in the step of forming the upper electrode, a distance between an inner wall of an opening of the second patterning mask and a side surface of the active layer is 500 μm or more, and the side surfaces of the lower buffer layer, the active layer, and the upper buffer layer are covered with the upper electrode.

[0009] A method for manufacturing a detection device according to one aspect of the present invention includes the steps of: forming, on a substrate, an organic insulating film, a barrier film, a lower electrode, a lower buffer layer, an active layer, and an upper buffer layer in that order; forming, using a first patterning mask, an upper metal layer on the upper buffer layer in a region of the substrate corresponding to a detection region, and removing the lower buffer layer, the active layer, and the upper buffer layer in regions where the upper metal layer is not provided; and forming, using a second patterning mask, an upper electrode on the upper metal layer, wherein, in the step of forming the upper electrode, the second patterning mask is supported on spacers provided on an outer edge side of the substrate, and side surfaces of the lower buffer layer, the active layer, and the upper buffer layer are covered with the upper electrode.

[0010] FIG. 1 is a plan view schematically showing a detection device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. FIG. 3 is a circuit diagram showing the detection device according to the first embodiment. FIG. 4 is a plan view schematically showing the configuration of a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and an upper electrode of a plurality of photodiodes. FIG. 5 is a cross-sectional view taken along line V-V' in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI' in FIG. 4. FIG. 7 is an explanatory diagram schematically showing a manufacturing process of the detection device according to the first embodiment. FIG. 8 is an explanatory diagram showing an enlarged view of steps ST1 and ST2 in FIG. 7. FIG. 9 is an explanatory diagram schematically showing a manufacturing process of the detection device according to a second embodiment.

[0011] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this disclosure and each figure, elements similar to those described above with reference to the previous figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0012] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0013] First Embodiment Fig. 1 is a plan view schematically showing a detection device according to a first embodiment. As shown in Fig. 1, the detection device 1 has a substrate 21, a sensor unit 10, a gate line driving circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 122, a power supply circuit 123, a first light source substrate 51, a second light source substrate 52, and light sources 53 and 54. The first light source substrate 51 is provided with a plurality of light sources 53. The second light source substrate 52 is provided with a plurality of light sources 54.

[0014] A control board 121 is electrically connected to the substrate 21 via a wiring board 71. The wiring board 71 is, for example, a flexible printed circuit board or a rigid board. The wiring board 71 is provided with a detection circuit 48. The control board 121 is provided with a control circuit 122 and a power supply circuit 123. The control circuit 122 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 122 supplies control signals to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The control circuit 122 also supplies control signals to the light sources 53 and 54 to control the lighting or non-lighting of the light sources 53 and 54. The power supply circuit 123 supplies voltage signals, such as a sensor power supply signal VDDSNS (see FIG. 3), to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16. Furthermore, the power supply circuit 123 supplies a power supply voltage to the light sources 53 and 54 .

[0015] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area where multiple photodiodes PD (see FIG. 4) of the sensor unit 10 are provided. The peripheral area GA is an area between the outer periphery of the detection area AA and the outer edge of the substrate 21, where multiple photodiodes PD are not provided.

[0016] The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line driving circuit 15 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

[0017] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is the normal direction to the main surface of the substrate 21. Furthermore, "planar view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 21.

[0018] The plurality of light sources 53 are provided on the first light source substrate 51 and arranged along the second direction Dy. The plurality of light sources 54 are provided on the second light source substrate 52 and arranged along the second direction Dy. The first light source substrate 51 and the second light source substrate 52 are electrically connected to the control circuit 122 and the power supply circuit 123 via terminal portions 124 and 125 provided on the control board 121, respectively.

[0019] For example, inorganic light emitting diodes (LEDs) or organic light emitting diodes (OLEDs) are used as the light sources 53 and 54. The light sources 53 and 54 emit light of different wavelengths.

[0020] The first light emitted from the light source 53 is mainly reflected by the surface of the object to be detected, such as a finger, and enters the sensor unit 10. As a result, the sensor unit 10 can detect a fingerprint by detecting the shape of the projections and recesses on the surface of the finger or the like. The second light emitted from the light source 54 is mainly reflected by the inside of the finger or the like or passes through the finger or the like and enters the sensor unit 10. As a result, the sensor unit 10 can detect information about the living body inside the finger or the like. The information about the living body includes, for example, the pulse wave, pulse rate, and blood vessel image of the finger or palm. In other words, the detection device 1 may be configured as a fingerprint detection device that detects fingerprints, or a vein detection device that detects blood vessel patterns such as veins.

[0021] The arrangement of the light sources 53, 54 shown in FIG. 1 is merely an example and can be changed as appropriate. The detection device 1 is provided with multiple types of light sources 53, 54 as light sources. However, this is not limited to this, and the light source may be of one type. For example, multiple light sources 53 and multiple light sources 54 may be arranged on the first light source substrate 51 and the second light source substrate 52, respectively. Furthermore, the number of light source substrates on which the light sources 53 and the light sources 54 are arranged may be one or three or more. Alternatively, it is sufficient that at least one or more light sources are arranged.

[0022] 2 is a block diagram showing an example of the configuration of a detection device according to an embodiment. As shown in FIG. 2, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Some or all of the functions of the detection control circuit 11 are included in a control circuit 122. In addition, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 122.

[0023] The sensor unit 10 has a plurality of photodiodes PD. The photodiodes PD of the sensor unit 10 output electrical signals corresponding to the incident light as detection signals Vdet to the signal line selection circuit 16. The sensor unit 10 also performs detection in accordance with a gate drive signal VGL supplied from the gate line drive circuit 15.

[0024] The detection control circuit 11 is a circuit that supplies control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals, such as a start signal STV and a clock signal CK, to the gate line drive circuit 15. The detection control circuit 11 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16. The detection control circuit 11 also supplies various control signals to the light sources 53 and 54, and controls the lighting and non-lighting of each.

[0025] The gate line driving circuit 15 is a circuit that drives a plurality of gate lines GL (see FIG. 3) based on various control signals. The gate line driving circuit 15 sequentially or simultaneously selects the plurality of gate lines GL and supplies a gate driving signal VGL to the selected gate lines GL. In this way, the gate line driving circuit 15 selects a plurality of photodiodes PD connected to the gate lines GL.

[0026] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SL (see FIG. 3 ). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected signal line SL to the detection circuit 48 based on a selection signal ASW supplied from the detection control circuit 11. As a result, the signal line selection circuit 16 outputs a detection signal Vdet of the photodiode PD to the detection unit 40.

[0027] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a memory circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 based on a control signal supplied from the detection control circuit 11 so that they operate in synchronization with each other.

[0028] The detection circuit 48 is, for example, an analog front end (AFE) circuit. The detection circuit 48 is a signal processing circuit that has at least the functions of a detection signal amplifier circuit 42 and an A / D conversion circuit 43. The detection signal amplifier circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal.

[0029] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When a finger touches or approaches the detection surface, the signal processing circuit 44 can detect unevenness on the surface of the finger or palm based on the signal from the detection circuit 48. The signal processing circuit 44 can also detect information about the living body based on the signal from the detection circuit 48. The information about the living body includes, for example, an image of the blood vessels of the finger or palm, a pulse wave, a pulse rate, and a blood oxygen concentration.

[0030] The memory circuit 46 temporarily stores the signals calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0031] The coordinate extraction circuit 45 is a logic circuit that calculates the detected coordinates of the unevenness of the surface of a finger or the like when the signal processing circuit 44 detects contact or proximity of a finger. The coordinate extraction circuit 45 is also a logic circuit that calculates the detected coordinates of the blood vessels of the finger or palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from each photodiode PD of the sensor unit 10 to generate two-dimensional information indicating the shape of the unevenness of the surface of the finger or the like and two-dimensional information indicating the shape of the blood vessels of the finger or palm. The coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output voltage Vo without calculating the detection coordinates.

[0032] Fig. 3 is a circuit diagram showing a detection device according to an embodiment. Fig. 3 also shows the circuit configuration of a detection circuit 48. As shown in Fig. 3, a sensor pixel PX includes a photodiode PD, a capacitance element Ca, and a drive transistor Tr. The capacitance element Ca is a capacitance (sensor capacitance) formed in the photodiode PD, and is equivalently connected in parallel with the photodiode PD.

[0033] 3 shows two gate lines GL(m) and GL(m+1) arranged in the second direction Dy among the multiple gate lines GL. Also, two signal lines SL(n) and SL(n+1) arranged in the first direction Dx among the multiple signal lines SL. A sensor pixel PX is an area surrounded by the gate line GL and the signal line SL.

[0034] The drive transistors Tr are provided corresponding to the respective photodiodes PD. The drive transistors Tr are configured by thin film transistors, and in this example, are configured by n-channel MOS (Metal Oxide Semiconductor) type TFTs (Thin Film Transistors).

[0035] Each of the gate lines GL is connected to the gates of a plurality of drive transistors Tr arranged in a first direction Dx. Each of the signal lines SL is connected to one of the source and drain of a plurality of drive transistors Tr arranged in a second direction Dy. The other of the source and drain of each of the drive transistors Tr is connected to the cathode of the photodiode PD and the capacitance element Ca.

[0036] A sensor power supply signal VDDSNS is supplied to the anode of the photodiode PD from the power supply circuit 123 (see FIG. 1 ). A sensor reference voltage COM, which serves as the initial potential of the signal line SL and the capacitance element Ca, is supplied to the signal line SL and the capacitance element Ca from the power supply circuit 123 via the reset transistor TrR.

[0037] When light is irradiated onto the sensor pixel PX during the exposure period, a current corresponding to the amount of light flows through the photodiode PD, causing charge to accumulate in the capacitance element Ca. When the drive transistor Tr is turned on during the readout period, a current corresponding to the charge accumulated in the capacitance element Ca flows through the signal line SL. The signal line SL is connected to the detection circuit 48 via the output transistor TrS of the signal line selection circuit 16. This allows the detection device 1 to detect a signal corresponding to the amount of light irradiated onto the photodiode PD for each sensor pixel PX.

[0038] During the readout period, the switch SSW of the detection circuit 48 is turned on and connected to the signal line SL. The detection signal amplifier circuit 42 of the detection circuit 48 converts the current or charge supplied from the signal line SL into a voltage corresponding to the current or charge. A reference potential (Vref) having a fixed potential is input to the non-inverting input terminal (+) of the detection signal amplifier circuit 42, and the signal line SL is connected to the inverting input terminal (-). In this embodiment, a signal equal to the sensor reference voltage COM is input as the reference potential (Vref) voltage. The control circuit 122 (see FIG. 1) calculates the difference between the detection signal Vdet when light is irradiated and the detection signal Vdet when light is not irradiated as the sensor output voltage Vo. The detection signal amplifier circuit 42 also includes a capacitance element Cb and a reset switch RSW. During the reset period, the reset switch RSW is turned on, resetting the charge in the capacitance element Cb.

[0039] The driving transistor Tr is not limited to an n-type TFT, but may be a p-type TFT. The pixel circuit of the sensor pixel PX shown in Fig. 3 is merely an example, and the sensor pixel PX may be provided with multiple transistors corresponding to one photodiode PD.

[0040] Next, the configuration of the photodiode PD will be described with reference to Fig. 4 to Fig. 6. Fig. 4 is a plan view schematically showing the configuration of the lower electrode, lower buffer layer, active layer, upper buffer layer, and upper electrode of a plurality of photodiodes.

[0041] 4, multiple photodiodes PD (organic photosensors) are arranged in a matrix in the detection area AA. Each of the multiple photodiodes PD has a lower electrode 31, a lower buffer layer 32, an active layer 33, an upper buffer layer 34, an upper metal layer 35M, and an upper electrode 35. The multiple lower electrodes 31 are provided spaced apart for each of the multiple photodiodes PD and arranged in a matrix in the detection area AA. The lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the upper metal layer 35M are provided continuously across the multiple photodiodes PD and are provided throughout the entire detection area AA.

[0042] The upper electrode 35 is provided continuously across the multiple photodiodes PD and is provided in the detection area AA and the peripheral area GA. The upper electrode 35 is provided to cover the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the upper metal layer 35M. The outer edge of the upper electrode 35 is located outside (toward the outer edge of the substrate 21) the outer edges of the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the upper metal layer 35M. A portion of the upper electrode 35 is connected to a contact portion CN provided in the peripheral area GA and is electrically connected to an external circuit (e.g., a control circuit 122 or a power supply circuit 123 (see FIG. 1 )) through wiring on the substrate 21.

[0043] The detection device 1 has a sealing film 90 that covers the multiple photodiodes PD. The sealing film 90 is provided across the detection area AA and the peripheral area GA, and is provided up to the outer edge side of the substrate 21. The sealing film 90 is provided to cover the multiple photodiodes PD. The outer edge of the sealing film 90 is located outside the outer edge of the upper electrode 35 (toward the outer edge of the substrate 21).

[0044] 4, the wiring substrate 71 (see FIG. 1) is not shown, but the wiring substrate 71 is connected to a terminal provided on the substrate 21 outside the upper electrode 35. Furthermore, the sealing film 90 may have an opening at the connection point between the wiring substrate 71 and the terminal, as necessary.

[0045] Next, a description will be given of the laminated structure of the multiple photodiodes PD and the sealing film 90 of the detection device 1. Fig. 5 is a cross-sectional view taken along line VV' in Fig. 4. Fig. 6 is a cross-sectional view taken along line VI-VI' in Fig. 4.

[0046] In the following description, the direction perpendicular to the surface of the substrate 21, from the substrate 21 toward the sealing film 90, will be referred to as the "upper side" or simply "upper." The direction from the sealing film 90 toward the substrate 21 will be referred to as the "lower side" or simply "lower."

[0047] 5 and 6 , the detection device 1 has a substrate 21, a TFT layer 22, an organic insulating film 26, a barrier film 27, a photodiode PD, and a sealing film 90. In the detection area AA, the TFT layer 22, the organic insulating film 26, the barrier film 27, the photodiode PD, and the sealing film 90 are stacked in this order on the substrate 21.

[0048] The substrate 21 is an insulating substrate made of a film-like resin. The TFT layer 22 is a circuit formation layer in which pixel circuits of the sensor pixels PX (see FIG. 3 ) are formed. The TFT layer 22 includes various wirings such as drive transistors Tr, gate lines GL, and signal lines SL, as well as multiple inorganic insulating films that provide insulation between layers.

[0049] The organic insulating film 26 is provided to cover the drive transistor Tr formed in the TFT layer 22. The organic insulating film 26 is a planarization film made of an organic insulating material. The barrier film 27 is provided on the organic insulating film 26. The barrier film 27 is made of an inorganic insulating material such as silicon nitride (SiN).

[0050] The photodiode PD is provided on the barrier film 27. The photodiode PD is formed by stacking a lower electrode 31, a lower buffer layer 32, an active layer 33, an upper buffer layer 34, an upper metal layer 35M, and an upper electrode 35 in this order in a direction perpendicular to the substrate 21. The photodiode PD of this embodiment is an organic photodiode (OPD) in which an organic semiconductor is used as the active layer 33.

[0051] The lower electrode 31 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). The lower buffer layer 32, the active layer 33, the upper buffer layer 34, the upper metal layer 35M, and the upper electrode 35 are provided continuously across the multiple photodiodes PD. Specifically, the lower buffer layer 32, the active layer 33, the upper buffer layer 34, the upper metal layer 35M, and the upper electrode 35 are provided to overlap the lower electrode 31 and are also provided in the region between adjacent lower electrodes 31.

[0052] The insulating film 36 is provided to cover the periphery of the lower electrode 31. The insulating film 36 insulates the lower electrodes 31 of adjacent photodiodes PD. Even if a step occurs in the lower buffer layer 32 at the periphery of the lower electrode 31, the insulating film 36 can prevent a short circuit between the active layer 33 and the lower electrode 31. In this embodiment, the insulating film 36 is made of a silicon nitride film (SiN) or a silicon oxide film (SiO ２ The insulating film 36 is formed of an inorganic insulating material such as a barrier film 27. The insulating film 36 is provided to cover the peripheral edge of the contact portion CN. The insulating film 36 is provided to cover the entire barrier film 27, but is not limited to this, and it is sufficient that the insulating film 36 is provided to cover at least the peripheral edge of the lower electrode 31 and the peripheral edge of the contact portion CN.

[0053] The characteristics (for example, voltage-current characteristics and resistance value) of the active layer 33 change depending on the light irradiated thereto. An organic material is used as the material of the active layer 33. Specifically, the active layer 33 has a bulk heterostructure in which a p-type organic semiconductor and an n-type organic semiconductor, an n-type fullerene derivative (PCBM), are mixed. For example, a low-molecular organic material, C ６０ (fullerene), PCBM (phenyl C ６１ Butyric acid methyl ester: Phenyl C 61 -butyric acid methyl ester), CuPc (Copper Phthalocyanine), F １６ CuPc (fluorinated copper phthalocyanine), rubrene (5,6,11,12-tetraphenyltetracene), PDI (a derivative of perylene), or the like can be used.

[0054] The active layer 33 can be formed by a vapor deposition (dry process) using these low molecular weight organic materials. In this case, the active layer 33 is formed by, for example, CuPc and F １６ CuPc laminated film or rubrene and C ６０ The active layer 33 may be a laminated film of the above-mentioned low molecular weight organic material and high molecular weight organic material. The active layer 33 may also be formed by a wet process. In this case, the active layer 33 is made of a material that combines the above-mentioned low molecular weight organic material and high molecular weight organic material. Examples of high molecular weight organic materials that can be used include P3HT (poly(3-hexylthiophene)) and F8BT (F8-alt-benzothiadiazole). The active layer 33 may be a film in which P3HT and PCBM are mixed, or a film in which F8BT and PDI are mixed. The active layer 33 is not limited to a bulk heterostructure and may be a PIN type.

[0055] The lower buffer layer 32 and the upper buffer layer 34 are provided to allow holes and electrons generated in the active layer 33 to easily reach the lower electrode 31 or the upper electrode 35. The lower buffer layer 32 is provided between the lower electrode 31 and the active layer 33, and is in direct contact with the lower electrode 31 and the active layer 33. The lower buffer layer 32 is also provided between adjacent lower electrodes 31, covering the barrier film 27 and the insulating film 36.

[0056] The upper buffer layer 34 is provided between the active layer 33 and the upper electrode 35. The upper metal layer 35M is provided between the upper buffer layer 34 and the upper electrode 35. The upper buffer layer 34 is in direct contact with the active layer 33 and the upper metal layer 35M.

[0057] In this embodiment, the lower electrode 31 is the cathode electrode of the photodiode PD, and the upper electrode 35 is the anode electrode of the photodiode PD. In this case, the lower buffer layer 32 is an electron transport layer, and the upper buffer layer 34 is a hole transport layer. The material of the electron transport layer is ethoxylated polyethyleneimine (PEIE). The material of the hole transport layer is a metal oxide layer. As the metal oxide layer, tungsten oxide (WO ３ ), molybdenum oxide, etc. are used.

[0058] The lower electrode 31 may be the anode electrode of the photodiode PD, and the upper electrode 35 may be the cathode electrode of the photodiode PD. In this case, the lower buffer layer 32 may be a hole transport layer, and the upper buffer layer 34 may be an electron transport layer.

[0059] The upper metal layer 35M is formed to have the same width (area) as the lower buffer layer 32, the active layer 33, and the upper buffer layer 34. The upper metal layer 35M functions as the upper electrode of the photodiode PD and also functions as a mask when patterning the lower buffer layer 32, the active layer 33, and the upper buffer layer 34. The manufacturing process of the photodiode PD will be described later with reference to FIG.

[0060] 5 and 6, the side surfaces of the photodiode PD (side surfaces 32s, 33s, 34s, and 35Ms of the lower buffer layer 32, active layer 33, upper buffer layer 34, and upper metal layer 35M) are shown schematically as being perpendicular to the surface of the substrate 21. However, in reality, the side surfaces 32s, 33s, 34s, and 35Ms of the photodiode PD have a forward tapered shape (see the enlarged view in FIG. 8).

[0061] The upper electrode 35 covers the upper surface of the upper metal layer 35M, and also covers the side surface 32s of the lower buffer layer 32, the side surface 33s of the active layer 33, the side surface 34s of the upper buffer layer 34, and the side surface 35Ms of the upper metal layer 35M. In the following description, the "side surface 32s of the lower buffer layer 32, the side surface 33s of the active layer 33, the side surface 34s of the upper buffer layer 34, and the side surface 35Ms of the upper metal layer 35M" may be referred to as the "side surfaces 32s, 33s, 34s, 35Ms of the photodiode PD."

[0062] More specifically, the upper electrode 35 includes an overlapping portion 35a, a side portion 35b, and an extending portion 35c. The overlapping portion 35a covers the upper surface of the upper metal layer 35M. The side portion 35b covers the side surfaces 32s, 33s, 34s, and 35Ms of the photodiodes PD. The upper end of the side portion 35b is connected to the overlapping portion 35a, and the lower end of the side portion 35b is connected to the extending portion 35c. The extending portion 35c extends to the peripheral region GA outside the side surfaces 32s, 33s, 34s, and 35Ms of the multiple photodiodes PD. The extending portion 35c of the upper electrode 35 is provided on the barrier film 27 and the insulating film 36 in a region that does not overlap with the multiple photodiodes PD.

[0063] The side surface 35s on the outer edge side of the upper electrode 35 (the side surface 35s of the extension portion 35c) is located closer to the outer edge of the substrate 21 than the side surfaces 32s, 33s, 34s, and 35Ms of the multiple photodiodes PD. In other words, the plane area of ​​the upper electrode 35 is larger than the plane areas of the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the upper metal layer 35M. On the outer edge side of the substrate 21, the side surface 35s of the upper electrode 35 is located closer to the detection region AA than the side surface of the barrier film 27. Also, as shown in FIG. 6 , a portion of the extension portion 35c of the upper electrode 35 extends to a region overlapping with the contact portion CN and is connected to the contact portion CN.

[0064] The upper electrode 35 is formed of a light-transmitting conductive material such as ITO or IZO. However, the upper electrode 35 may be formed of a light-non-transmitting conductive material such as silver (Ag). The upper metal layer 35M is formed of a metal material such as silver (Ag). That is, the upper metal layer 35M may be made of the same metal material as the upper electrode 35.

[0065] The sealing film 90 is provided to cover the multiple photodiodes PD. The sealing film 90 is provided to cover the overlapping portion 35a, the side portion 35b, and the extending portion 35c of the upper electrode 35. The side surface of the sealing film 90 is located closer to the outer edge of the substrate 21 than the outer edge side surface 35s of the upper electrode 35. The sealing film 90 effectively seals the photodiodes PD and can prevent moisture from entering from the outside. Furthermore, because the sealing film 90 covers the outer edge side surface 35s of the upper electrode 35, it is possible to effectively prevent moisture from entering from the outer edge side of the substrate 21 compared to when the upper electrode 35 extends to the outer edge side of the substrate 21.

[0066] The sealing film 90 is formed of an inorganic film such as a silicon nitride film or an aluminum oxide film. The sealing film 90 is not limited to a single layer film, but may be a laminated film in which a plurality of inorganic films are stacked. Alternatively, the sealing film 90 may be a laminated film in which an organic film formed of a resin film such as acrylic and an inorganic film are stacked.

[0067] As described above, in the detection device 1 of this embodiment, the side surfaces 32s, 33s, 34s, and 35Ms of the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the upper metal layer 35M are covered with the upper electrode 35. This makes it possible to suppress contact between the patterning mask and the active layer 33 when forming the upper electrode 35, compared to when the upper electrode 35 is formed in the same shape as the lower buffer layer 32, the active layer 33, and the upper buffer layer 34.

[0068] (Method of Manufacturing Detector) Next, a method of manufacturing the detector 1 of this embodiment will be described with reference to Fig. 7. Fig. 7 is an explanatory diagram that schematically shows the manufacturing process of the detector according to the first embodiment. Fig. 8 is an explanatory diagram that shows an enlarged view of steps ST1 and ST2 in Fig. 7. Note that in Fig. 7, the lower buffer layer 32 and the upper buffer layer 34 are omitted to make the drawing easier to see.

[0069] As shown in Fig. 7, a TFT layer 22, an organic insulating film 26, and a barrier film 27 are formed on a substrate 21. A lower electrode 31, an insulating film 36, a lower buffer layer 32 (see Fig. 8), an active layer 33, and an upper buffer layer 34 (see Fig. 8), which constitute a photodiode PD, are formed in this order on the barrier film 27. The lower electrode 31 is patterned in a matrix shape corresponding to the arrangement of the multiple photodiodes PD. The lower buffer layer 32, the active layer 33, and the upper buffer layer 34 are formed over the entire surface of the substrate 21, spanning the detection area AA and the peripheral area GA.

[0070] Next, a film forming apparatus (not shown) uses a first patterning mask 201 to form an upper metal layer 35M on the upper buffer layer 34 in an area corresponding to the detection area AA of the substrate 21 (step ST1). The first patterning mask 201 for forming the upper metal layer 35M is a metal mask having an opening OP1. The opening OP1 is provided at a position overlapping with the area (detection area AA) where multiple photodiodes PD are to be formed. The upper metal layer 35M is formed by a method such as sputtering, vapor deposition, or plasma CVD.

[0071] 8, in the process of depositing the upper metal layer 35M, the first patterning mask 201 is disposed above and spaced apart from the upper buffer layer 34. The upper metal layer 35M is deposited so as to extend beyond the opening OP1 of the first patterning mask 201. As a result, the side surface 35Ms of the upper metal layer 35M is formed to have a forward tapered shape.

[0072] 7, the lower buffer layer 32, the active layer 33, and the upper buffer layer 34 are removed from the region where the upper metal layer 35M is not provided (step ST2). In the removal process of step ST2, the upper metal layer 35M is used as a mask. The lower buffer layer 32, the active layer 33, and the upper buffer layer 34 in the region that does not overlap with the upper metal layer 35M are removed by dry etching. In other words, the lower buffer layer 32, the active layer 33, and the upper buffer layer 34 in the region that overlaps with the upper metal layer 35M are formed as a plurality of photodiodes PD.

[0073] 8, in the process of removing the lower buffer layer 32, the active layer 33, and the upper buffer layer 34, etching of the lower buffer layer 32, the active layer 33, and the upper buffer layer 34 first progresses in a region outside the side surface 35Ms of the upper metal layer 35M. At this time, together with the lower buffer layer 32, the active layer 33, and the upper buffer layer 34, a thin outer edge portion (a portion overlapping with the side surface 35Ms) of the upper metal layer 35M is also etched.

[0074] 8, when the outer edge portion of the upper metal layer 35M is further removed, etching of the lower buffer layer 32, the active layer 33, and the upper buffer layer 34 proceeds sequentially in the regions overlapping with the removed portion of the upper metal layer 35M. As a result, the side surfaces 32s, 33s, and 34s of the lower buffer layer 32, the active layer 33, and the upper buffer layer 34 of the photodiode PD are formed to have a forward tapered shape. In addition, the side surface 35Ms of the upper metal layer 35M is also formed to have a forward tapered shape.

[0075] Next, as shown in FIG. 7 , a film forming apparatus (not shown) forms an upper electrode 35 on the upper metal layer 35M using a second patterning mask 202 (step ST3). The second patterning mask 202 for forming the upper electrode 35 is a metal mask having an opening OP2. The opening OP2 of the second patterning mask 202 has a width W2 that is at least greater than the width W1 of the active layer 33. Here, the width W1 of the active layer 33 is defined as the maximum width between the side surfaces 33s of the active layer 33. Specifically, the active layer 33 has a forward tapered shape, and the maximum width W1 of the active layer 33 is defined as the distance between the lower end of the side surface 33s of the active layer 33 and the insulating film 36 or the barrier film 27.

[0076] The distance L1 between the inner wall of the opening OP2 of the second patterning mask 202 and the side surface 33s of the active layer 33 is 500 μm or more. More specifically, the distance L1 is the distance, in a direction parallel to the surface of the substrate 21, between the inner wall of the opening OP2 of the second patterning mask 202 and the lower end of the side surface 33s of the active layer 33, which contacts the insulating film 36 or the barrier film 27. The distance L1 varies along each side of the photodiode PD depending on the alignment accuracy of the second patterning mask 202. For example, as shown in FIG. 7 , in the portion where the contact portion CN is provided, the distance L1 between the inner wall of the opening OP2 and the side surface 33s of the active layer 33 is greater than the distance L1 on the opposite side. In this embodiment, the second patterning mask 202 is positioned so that the minimum distance L1 along the outer edge of the photodiode PD is 500 μm or more.

[0077] Furthermore, the width W2 of the opening OP2 is smaller than the width of the barrier film 27 formed on the substrate 21. The inner wall of the opening OP2 of the second patterning mask 202 overlaps with the outer edge side of the barrier film 27 formed on the substrate 21.

[0078] As a result, the upper electrode 35 is formed so as to cover the upper surface of the upper metal layer 35M, as well as the side surfaces 32s, 33s, and 34s of the photodiode PD and the side surface 35Ms of the upper metal layer 35M. The upper electrode 35 is provided so as to extend further toward the outer edge of the substrate 21 than the side surface 33s of the active layer 33. Furthermore, the side surface 35s on the outer edge side of the upper electrode 35 is formed more inward (toward the detection area AA) than the side surface of the barrier film 27.

[0079] Next, a film forming apparatus (not shown) forms a sealing film 90 covering the upper electrode 35 (step ST4). A patterning mask (not shown) for forming the sealing film 90 has an opening with a width larger than the opening OP2. As a result, the sealing film 90 is formed to cover the entire surface of the upper electrode 35. The side surface 35s on the outer edge of the upper electrode 35 is also covered with the sealing film 90. In other words, the side surface 35s on the outer edge of the upper electrode 35 is formed more inward (toward the detection area AA) than the side surface of the sealing film 90.

[0080] The detection device 1 of this embodiment is formed through the above-described steps. In this embodiment, in the step of forming the upper electrode 35 shown in step ST3, the inner wall of the opening OP2 of the second patterning mask 202 is positioned at a predetermined distance L1 from the side surface 33s of the active layer 33. This makes it possible to suppress contact between the second patterning mask 202 and the side surface 33s of the active layer 33, compared to when the upper electrode 35 is formed in the same shape as the lower buffer layer 32, the active layer 33, and the upper buffer layer 34, i.e., when the side surface 35s of the upper electrode 35 is positioned so as to overlap the side surfaces 32s, 33s, 34s, and 35Ms of the photodiode PD.

[0081] 8, even if the side surfaces 32s, 33s, and 34s of the lower buffer layer 32, the active layer 33, and the upper buffer layer 34 have a forward tapered shape, it is possible to prevent the second patterning mask 202 from contacting the side surfaces 32s, 33s, and 34s. Therefore, in this embodiment, it is possible to prevent scratches and foreign matter from adhering to the outer edge of the photodiode PD.

[0082] 7 and 8 are merely schematic illustrations of the manufacturing process of the detection device 1 and can be modified as appropriate. For example, the stacked structure and the forward tapered shapes of the side surfaces 32s, 33s, and 34s shown in Fig. 8 are exaggerated for ease of understanding, and the film thickness, the inclination, and the width of the side surfaces 32s, 33s, and 34s may be different.

[0083] Second Embodiment Fig. 9 is an explanatory diagram schematically showing the manufacturing process of a detection device according to a second embodiment. In the following description, the same components as those described in the above-mentioned embodiment are denoted by the same reference numerals, and redundant description will be omitted. In Fig. 9, the lower buffer layer 32 and the upper buffer layer 34 are omitted, as in Fig. 7.

[0084] The manufacturing process shown in Fig. 9 corresponds to the process (step ST3) of forming the upper electrode 35 in Fig. 7. In the second embodiment, the processes of forming the upper metal layer 35M, removing the active layer 33, and forming the sealing film 90 are similar to the processes of steps ST1, ST2, and ST4 described above in Fig. 7, and therefore repeated explanations will be omitted.

[0085] 9, in the second embodiment, the second patterning mask 202 is supported on spacers 203 provided on the outer edge side of the substrate 21. The height of the spacers 203 is greater than the total height of the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the upper metal layer 35M. The spacers 203 are resin tapes made of a resin material such as polyimide.

[0086] The second patterning mask 202 is disposed above the upper metal layer 35M. More specifically, the lower surface of the second patterning mask 202 is disposed at a distance from the upper surface of the upper metal layer 35M in a direction perpendicular to the substrate 21. The width W2 of the opening OP2 of the second patterning mask 202 is greater than at least the width W1 of the active layer 33. However, in this embodiment, the inner wall of the opening OP2 of the second patterning mask 202 may be positioned so as to overlap the side surface 33s of the active layer 33. That is, the distance L1 (see FIG. 7 ) between the inner wall of the opening OP2 of the second patterning mask 202 and the side surface 33s of the active layer 33 may be 500 μm or less.

[0087] A film forming apparatus (not shown) forms the upper electrode 35 on the upper metal layer 35M using the second patterning mask 202 (step ST3A). In this embodiment, the upper electrode 35 is formed between the lower surface of the second patterning mask 202 and the upper surface of the upper metal layer 35M. As a result, the upper electrode 35 is formed so as to cover the upper surface of the upper metal layer 35M, as well as the side surfaces 32s, 33s, and 34s of the photodiode PD and the side surface 35Ms of the upper metal layer 35M.

[0088] In this embodiment, the second patterning mask 202 is supported by the spacers 203 during the film formation process of the upper electrode 35, thereby preventing the second patterning mask 202 from contacting the respective side surfaces 32s, 33s, and 34s of the lower buffer layer 32, the active layer 33, and the upper buffer layer 34.

[0089] Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each of the above-described embodiments and modifications.

[0090] REFERENCE SIGNS LIST 1 Detector 10 Sensor section 21 Substrate 22 TFT layer 26 Organic insulating film 27 Barrier film 31 Lower electrode 32 Lower buffer layer 33 Active layer 34 Upper buffer layer 35 Upper electrode 35M Upper metal layer 40 Detector 90 Sealing film 201 First patterning mask 202 Second patterning mask 203 Spacer AA Detecting region GA Peripheral region PD Photodiode

Claims

1. A detection device comprising: a substrate; an organic insulating film and a barrier film laminated on the substrate; an organic photosensor having a lower electrode, a lower buffer layer, an active layer, an upper buffer layer and an upper electrode laminated in this order on the barrier film in a detection region of the substrate; and a sealing film covering the organic photosensor, wherein side surfaces of the lower buffer layer, the active layer and the upper buffer layer are covered by the upper electrode, and the upper electrode is covered by the sealing film.

2. The detection device according to claim 1, wherein, on the outer edge side of the substrate, the side surface of the upper electrode is positioned closer to the detection region than the side surface of the barrier film.

3. The detection device according to claim 1, wherein the side surface of the organic light sensor is forward tapered.

4. The detection device according to claim 1, further comprising an upper metal layer provided between said upper buffer layer and said upper electrode.

5. The detection device according to claim 4, wherein the side surface of the upper metal layer is forward tapered.

6. A method for manufacturing a detection device, comprising the steps of: forming an organic insulating film, a barrier film, a lower electrode, a lower buffer layer, an active layer, and an upper buffer layer on a substrate in that order; forming an upper metal layer on the upper buffer layer using a first patterning mask in a region of the substrate corresponding to a detection region, and removing the lower buffer layer, the active layer, and the upper buffer layer in a region where the upper metal layer is not provided; and forming an upper electrode on the upper metal layer using a second patterning mask, wherein in the step of forming the upper electrode, a distance between an inner wall of an opening of the second patterning mask and a side surface of the active layer is 500 μm or more, and the sides of the lower buffer layer, the active layer, and the upper buffer layer are covered with the upper electrode.

7. A method for manufacturing a detection device, comprising the steps of: forming an organic insulating film, a barrier film, a lower electrode, a lower buffer layer, an active layer, and an upper buffer layer on a substrate in that order; forming an upper metal layer on the upper buffer layer using a first patterning mask in a region of the substrate corresponding to a detection region, and removing the lower buffer layer, the active layer, and the upper buffer layer in regions where the upper metal layer is not provided; and forming an upper electrode on the upper metal layer using a second patterning mask, wherein in the step of forming the upper electrode, the second patterning mask is supported on a spacer provided on the outer edge side of the substrate, and side surfaces of the lower buffer layer, the active layer, and the upper buffer layer are covered with the upper electrode.

Images