Semiconductor device, manufacturing method therefor, and electronic apparatus
By forming bit lines through flip-chip bonding and etching processes, the problem of open-circuit bit lines in vertical channel transistors is solved, improving electrical performance and simplifying the fabrication process.
Patent Information
- Application Number
- PCT/CN2024/078831
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-06-26
- Filing Date
- 2024-02-27
- Publication Date
- 2026-01-22
AI Technical Summary
In the fabrication process of vertical channel transistor semiconductor devices, open circuits are prone to occur in the bit lines, which affects device performance and complicates the fabrication process.
The metal silicide thin films on two silicon substrates are bonded together using flip-chip bonding to form a metal silicide layer. Bit lines are then formed through etching, and chemical mechanical polishing and annealing processes are combined to ensure the flatness and tightness of the bit lines.
This solved the bit line open circuit problem, improved the electrical performance of the bit line and semiconductor pillar, ensured the height uniformity of the semiconductor pillar, and simplified the fabrication process.
Smart Images
Figure CN2024078831_22012026_PF_FP_ABST
Abstract
Description
A semiconductor device and its manufacturing method, and an electronic device.
[0001] This application claims priority to Chinese Patent Application No. 202310753427.8, filed on June 26, 2023, entitled "A Semiconductor Device and a Method for Manufacturing the Same Thereof, and an Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field
[0002] This disclosure relates to, but is not limited to, the field of storage technology, specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0003] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM has the advantages of simpler structure, lower manufacturing cost, and higher capacity density. With the development of technology, the application of DRAM is becoming increasingly widespread.
[0004] In the fabrication of semiconductor devices containing vertical channel transistors (VCTs), such as DRAM, the bit lines need to be buried under the channel, requiring processes such as atomic layer deposition, etching, and high-temperature annealing. Furthermore, the fabrication process involves first digging trenches in the substrate and then depositing the material within the trenches, making the fabrication process complex. Moreover, the resulting bit lines are prone to open circuits, which severely affects the performance of the semiconductor device.
[0005] Summary of the Invention
[0006] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.
[0007] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising:
[0008] A first metal silicide thin film is formed on a first silicon substrate;
[0009] A second metal silicide thin film is formed on a second silicon substrate;
[0010] Using flip-chip bonding, the first metal silicide film on the first silicon substrate and the second metal silicide film on the second silicon substrate are bonded together to form a metal silicide layer.
[0011] The metal silicide layer is etched into linear bit lines using an etching process.
[0012] The first silicon substrate is used to form a semiconductor pillar.
[0013] In an exemplary embodiment, forming a first metal silicide thin film on the first silicon substrate includes:
[0014] A first metal thin film is deposited on the first silicon substrate;
[0015] An annealing process is used to form a first metal silicide thin film on the first silicon substrate;
[0016] The surface of the first metal silicide film is planarized using a chemical mechanical polishing process.
[0017] In an exemplary embodiment, the first metal thin film includes at least one of a transition metal and a transition metal alloy.
[0018] In an exemplary embodiment, forming a second metal silicide thin film on the second silicon substrate includes:
[0019] A second metal thin film is deposited on the second silicon substrate;
[0020] A second metal silicide thin film is formed on the second silicon substrate by an annealing process;
[0021] The surface of the second metal silicide film is planarized using a chemical mechanical polishing process.
[0022] In an exemplary embodiment, the second metal thin film includes at least one of a transition metal and a transition metal alloy.
[0023] In an exemplary embodiment, the first metal silicide film and the second metal silicide film are made of the same material.
[0024] In an exemplary embodiment, etching the metal silicide layer to form linear bit lines includes:
[0025] Through an etching process, trenches are formed in the first silicon substrate and the metal silicide layer, and the metal silicide layer is etched to form a plurality of linear bit lines. The trenches are provided between adjacent bit lines, and the trenches extend from the surface of the first silicon substrate away from the second silicon substrate to the second silicon substrate.
[0026] In an exemplary embodiment, after forming a semiconductor pillar on the first silicon substrate, the method further includes:
[0027] An etching process is used to expose the sidewalls of the semiconductor pillar;
[0028] An atomic deposition process is used to form a gate insulating layer on the sidewall of the semiconductor pillar;
[0029] An atomic deposition process is used to form a gate electrode on the gate insulating layer, and the gate electrode and the gate insulating layer are arranged around the sidewall of the semiconductor pillar.
[0030] Secondly, embodiments of this disclosure also provide a semiconductor device, including a memory cell disposed on a substrate. The memory cell includes a bit line disposed on the substrate and a semiconductor pillar disposed on the side of the bit line away from the substrate. The semiconductor pillar includes a first electrode, a channel, and a second electrode sequentially disposed along a direction away from the substrate. The first electrode is electrically connected to the bit line. The bit line includes a first metal silicide layer and a second metal silicide layer, and the first metal silicide layer and the second metal silicide layer are bonded together.
[0031] In an exemplary embodiment, the first metal silicide layer and the second metal silicide layer are made of the same material and are connected as one piece.
[0032] In an exemplary embodiment, the bit line is linear, and the bit line includes a bottom surface located near the substrate and a top surface located away from the substrate, both the bottom surface and the top surface being flat surfaces in the extension direction of the bit line.
[0033] In an exemplary embodiment, the memory cell further includes a gate insulating layer and a gate electrode, the gate electrode and the gate insulating layer being disposed around the sidewall of the channel of the semiconductor pillar.
[0034] Thirdly, embodiments of this disclosure also provide an electronic device, including the aforementioned semiconductor device.
[0035] The semiconductor device manufacturing method of this application adopts a flip chip bonding method to bond metal silicide thin films on two silicon substrates to form a metal silicide layer. Subsequently, an etching process is used to form bit lines in the metal silicide layer, so that the bit lines have a uniform and dense internal structure, solving problems such as bit line open circuits and poor contact between bit lines and semiconductor pillars, and ensuring the uniformity of the height of multiple semiconductor pillars formed on the silicon substrate.
[0036] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.
[0037] Overview of the attached figures
[0038] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0039] Figure 1 is a schematic diagram of the planar structure of a semiconductor device according to an embodiment of this application;
[0040] Figure 2 is a cross-sectional structural schematic diagram of a semiconductor device according to an embodiment of this application;
[0041] Figure 3 is a cross-sectional structural schematic diagram of the semiconductor device according to an embodiment of this application;
[0042] Figure 4a is a schematic diagram showing the formation of the first doped layer and the second doped layer during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0043] Figure 4b is a schematic diagram showing the formation of a metal silicide layer during the manufacturing process of a semiconductor device according to an embodiment of this application;
[0044] Figure 4c is a schematic diagram of the bonding between the metal silicide layer and the substrate during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0045] Figure 5a is a cross-sectional view in the second direction after the semiconductor pillars are formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0046] Figure 5b is a cross-sectional view in the first direction after the semiconductor pillars are formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0047] Figure 6 is a cross-sectional view in the second direction after the second insulating film is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0048] Figure 7a is a cross-sectional view in the second direction after the third insulating film is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0049] Figure 7b is a cross-sectional view in the first direction after the third insulating film is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0050] Figure 8a is a cross-sectional view in the second direction after the second electrode is exposed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0051] Figure 8b is a cross-sectional view in the first direction after the second electrode is exposed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0052] Figure 9a is a cross-sectional view in the second direction after the second barrier layer is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0053] Figure 9b is a cross-sectional view in the first direction after the second barrier layer is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0054] Figure 10a is a cross-sectional view in the second direction after the channel is exposed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0055] Figure 10b is a cross-sectional view in the first direction after the channel is exposed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0056] Figure 11a is a cross-sectional view in the second direction after the gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0057] Figure 11b is a cross-sectional view in the first direction after the gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0058] Figure 12a is a cross-sectional view in the second direction after the gate electrode is formed during the manufacturing process of the semiconductor device according to an embodiment of this application;
[0059] Figure 12b is a cross-sectional view in the first direction after the gate electrode is formed during the manufacturing process of the semiconductor device according to an embodiment of this application.
[0060] Detailed Explanation
[0061] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0062] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values shown in the drawings.
[0063] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.
[0064] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.
[0065] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.
[0066] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (also called the drain terminal, drain region, or drain electrode) and the source electrode (also called the source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.
[0067] In this specification, the first electrode mentioned below can be the drain electrode and the second electrode can be the source electrode, or both can be either. In practical applications, which electrode is the source and which is the drain depends on the direction of current flow; generally, current flows from the source electrode to the drain electrode. However, in cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.
[0068] In this specification, "electrical connection" includes situations where components are connected together by elements that have some electrical function, such as physical connections or signal connections. There are no particular limitations on the term "elements that have some electrical function," as long as they can facilitate electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0069] In this specification, the terms "parallel" and "perpendicular" as used below refer to approximately parallel and approximately perpendicular lines within the tolerance range. "Parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes angles greater than -5° and less than 5°. Similarly, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes angles greater than 85° and less than 95°.
[0070] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."
[0071] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.
[0072] This application provides a method for manufacturing a semiconductor device, the method comprising:
[0073] A first metal silicide thin film is formed on a first silicon substrate;
[0074] A second metal silicide thin film is formed on a second silicon substrate;
[0075] Using flip-chip bonding, the first metal silicide film on the first silicon substrate and the second metal silicide film on the second silicon substrate are bonded together to form a metal silicide layer.
[0076] The metal silicide layer is etched into linear bit lines using an etching process.
[0077] The first silicon substrate is used to form a semiconductor pillar.
[0078] In an exemplary embodiment, forming a first metal silicide thin film on the first silicon substrate includes:
[0079] A first metal thin film is deposited on the first silicon substrate;
[0080] An annealing process is used to form a first metal silicide thin film on the first silicon substrate;
[0081] The surface of the first metal silicide film is planarized using a chemical mechanical polishing process.
[0082] In an exemplary embodiment, the first metal thin film includes at least one of a transition metal and a transition metal alloy.
[0083] In an exemplary embodiment, forming a second metal silicide thin film on the second silicon substrate includes:
[0084] A second metal thin film is deposited on the second silicon substrate;
[0085] A second metal silicide thin film is formed on the second silicon substrate by an annealing process;
[0086] The surface of the second metal silicide film is planarized using a chemical mechanical polishing process.
[0087] In an exemplary embodiment, the second metal thin film includes at least one of a transition metal and a transition metal alloy.
[0088] In an exemplary embodiment, the first metal silicide film and the second metal silicide film are made of the same material.
[0089] The following examples illustrate the solution of this embodiment.
[0090] Figure 1 is a schematic diagram of the planar structure of a semiconductor device according to an embodiment of this application. In an exemplary embodiment, as shown in Figure 1, the semiconductor device according to an embodiment of this application includes a plurality of spaced-apart memory cells 11 disposed on a substrate. Each memory cell 11 includes a word line 12 extending along a first direction D1, a bit line 13 extending along a second direction D2, a semiconductor pillar 14 extending along a direction perpendicular to the substrate, and a gate electrode that surrounds a channel of the semiconductor pillar 14 and is mutually insulated. The gate electrode is electrically connected to the word line 12.
[0091] In an exemplary embodiment, as shown in FIG1, a plurality of mutually spaced memory cells 11 are arranged at intervals along a first direction D1 to form a memory cell row. A word line 12 is electrically connected to the gate electrode of all memory cells 11 in a memory cell row. All memory cells 11 in a memory cell row can share a word line 12.
[0092] In an exemplary embodiment, as shown in FIG1, a plurality of mutually spaced memory cells 11 are arranged at intervals along a second direction D2 to form a memory cell column. A bit line 13 is electrically connected to the semiconductor pillars 14 of all memory cells 11 in a memory cell column. All memory cells 11 in a memory cell column can share a bit line 13.
[0093] In an exemplary embodiment, the material of bit line 13 may be a metal silicide. For example, titanium silicon compound, cobalt silicon compound, or platinum-nickel silicon compound.
[0094] In this embodiment of the application, the bit line 13 in the semiconductor device is made of metal silicide, which can form an ohmic contact with the electrode of the semiconductor pillar 14, reduce the contact resistance of the bit line 13, and solve the problem of poor contact between the bit line and the electrode of the semiconductor pillar 14.
[0095] In an exemplary embodiment, the metal silicide comprises transition metal ions. For example, the transition metal ions include at least one selected from titanium ions, cobalt ions, platinum ions, and nickel ions.
[0096] In an exemplary embodiment, the orthographic projection of the semiconductor pillar 14 onto the substrate can take various shapes, such as regular or irregular shapes like circles, ellipses, rectangles, rhombuses, triangles, pentagons, and hexagons.
[0097] The semiconductor device in this application embodiment can be a vertical channel transistor. This semiconductor device can serve as a read transistor and / or write transistor in a dynamic random access memory (DRAM), thereby reducing the memory area and increasing storage density.
[0098] In some embodiments, the semiconductor device of this application may also be other memory structures that bury bit lines in the channel near the substrate side, which will not be described in detail here.
[0099] Figure 2 is a cross-sectional view of the semiconductor device according to an embodiment of this application, and Figure 3 is a cross-sectional view of the semiconductor device according to an embodiment of this application. Figure 2 can be a cross-sectional view along the a-a' direction in Figure 1; Figure 3 can be a cross-sectional view along the c-c' direction in Figure 1. In an exemplary embodiment, as shown in Figures 2 and 3, in a direction perpendicular to the substrate, the memory cell 11 includes a bit line 13 disposed on a second silicon substrate 101, and a semiconductor pillar 50 disposed on the side of the bit line 13 away from the second silicon substrate 101. The semiconductor pillar 50 includes a first electrode 51, a channel 52, and a second electrode 53 sequentially disposed along a direction away from the substrate. The channel 52 is located between the first electrode 51 and the second electrode 53. Both the first electrode 51 and the second electrode 53 are electrically connected to the channel 52. The first electrode 51 is located on the side of the channel 52 closer to the second silicon substrate 101 and is electrically connected to the bit line 13; the second electrode 53 is located on the side of the channel 52 away from the second silicon substrate 101.
[0100] In an exemplary embodiment, the bit line 13 includes a first metal silicide layer and a second metal silicide layer, with the second metal silicide layer located on the side of the first metal silicide layer near the second silicon substrate 101. The first metal silicide layer and the second metal silicide layer are bonded together.
[0101] In an exemplary embodiment, the first metal silicide layer and the second metal silicide layer may be made of the same material and are connected as one piece.
[0102] In an exemplary embodiment, the first metal silicide layer and the second metal silicide layer may be made of different materials.
[0103] In an exemplary embodiment, the bit line 13 is linear and includes a bottom surface located near the second silicon substrate 101 and a top surface located away from the second silicon substrate 101. Both the bottom surface and the top surface are flat surfaces in the extension direction of the bit line 13.
[0104] In this embodiment of the semiconductor device, the bit line is formed by first forming a first metal silicide thin film on a first silicon substrate and a second metal silicide thin film on a second silicon substrate. Then, the first and second metal silicide thin films are bonded together by flip chip bonding to form a metal silicide layer. Finally, the metal silicide layer forms the bit line, which is transferred between the bottom of the semiconductor pillar and the surface of the second silicon substrate. This makes the top and bottom surfaces of the bit line 13 flat and the interior uniform and dense, thus ensuring the electrical performance of the bit line 13.
[0105] In an exemplary embodiment, as shown in Figures 2 and 3, the memory cell 11 further includes a gate electrode 30, which is disposed around the outside of the channel 52. The gate electrode 30 extends on the sidewall of the channel 52 to form an annular conductive layer extending in a direction perpendicular to the second silicon substrate 101. A gate insulating layer 31 is disposed between the gate electrode 30 and the channel 52, separating the gate electrode 30 from the channel 52 and thus insulating the gate electrode 30 from the channel 52.
[0106] In an exemplary embodiment, the gate insulating layer 31 may be selected from a material with a wide bandgap and high dielectric constant, or a material suitable for fabricating extremely small devices, such as hafnium dioxide. The gate insulating layer 31 may be a single-layer dielectric material, such as an oxide or nitride; or, the gate insulating layer 31 may be a multilayer dielectric material, such as a combination of oxides and nitrides.
[0107] In an exemplary embodiment, as shown in Figures 2 and 3, the gate electrode 30 is insulated from the first electrode 51, the second electrode 53, and the bit line 13.
[0108] In an exemplary embodiment, as shown in Figures 2 and 3, the gate electrode 30 is disposed opposite to the channel 52, and the gate electrode 30 does not cover the first electrode 51 and the second electrode 53. The gate electrode 30 may surround part or all of the channel 52 to form a ring gate structure. For example, the gate electrode 30 may be ring-shaped, surrounding the perimeter of the channel 52.
[0109] In an exemplary embodiment, the gate electrode 30 material may be a metal. For example, the gate electrode 30 material may be a conductive metal such as tin or tungsten.
[0110] The transistor ring gate structure in this application embodiment has strong gate control, which can increase the area of the channel region and improve the hold time. Furthermore, the ring gate structure can reduce the area of the semiconductor device.
[0111] In an exemplary embodiment, as shown in Figures 2 and 3, the semiconductor device further includes a first isolation layer 81. The first isolation layer 81 is disposed on the side of the semiconductor pillar 50 away from the substrate and contacts the second electrode 53 of the semiconductor pillar 50. The orthogonal projection of the first isolation layer 81 onto the substrate covers the orthogonal projection of the semiconductor pillar 50 onto the substrate. The first isolation layer 81 is used to isolate the surface of the second electrode 53 of the semiconductor pillar 50, preventing any impact on the semiconductor pillar 50 during the formation of the gate electrode 30. The material of the first isolation layer 81 can be an inorganic material; for example, the material of the first isolation layer 81 can be silicon dioxide.
[0112] In an exemplary embodiment, as shown in Figures 2 and 3, the semiconductor device further includes a second isolation layer 82. The second isolation layer 82 is disposed around the sidewall of the second electrode 53 of the semiconductor pillar 50. The second isolation layer 82 is used to isolate the sidewall of the second electrode 53 of the semiconductor pillar 50, preventing it from affecting the semiconductor pillar 50 during the formation of the gate electrode 30. The material of the second isolation layer 82 can be an inorganic material; for example, the material of the second isolation layer 82 can be silicon dioxide.
[0113] In an exemplary embodiment, as shown in FIG2, a first trench 61 is provided between the semiconductor pillars 50 of adjacent memory cells in the second direction D2, and the first trench 61 extends along the first direction D1. In a direction perpendicular to the second silicon substrate 101, the first trench 61 extends to the bit line 13, and the bottom wall of the first trench 61 is the surface of the bit line 13 away from the substrate. The first direction D1 intersects the second direction D2; for example, the first direction D1 is perpendicular to the second direction D2.
[0114] In an exemplary embodiment, as shown in FIG2, the semiconductor device further includes a first insulating layer 21 and a second insulating layer 22. Both the first insulating layer 21 and the second insulating layer 22 are disposed in a first trench 61. In the second direction D2, the first insulating layer 21 is located between the gate electrodes 30 of adjacent memory cells 11, isolating the gate electrodes 30 of adjacent memory cells 11 and thus insulating the gate electrodes 30 and the second electrodes 53 of adjacent memory cells 11 from each other. In a direction perpendicular to the substrate, the second insulating layer 22 is located between the gate electrode 30 of a memory cell 11 and the bit line 13 of that memory cell 11, isolating the gate electrode 30 from the bit line 13 and thus insulating the gate electrode 30 from the bit line 13 from each other. The materials of the first insulating layer 21 and the second insulating layer 22 can be inorganic materials.
[0115] In an exemplary embodiment, as shown in FIG2, the semiconductor device further includes a third insulating layer 23, which is disposed on the side of the first insulating layer 21 away from the substrate, and is located between the first isolation layers 81 on adjacent memory cells 11. The material of the third insulating layer 23 may be an inorganic material.
[0116] In an exemplary embodiment, as shown in FIG3, a second trench 62 is provided between the semiconductor pillars 50 of adjacent memory cells in the first direction D1, and the second trench 62 extends along the second direction D2. In a direction perpendicular to the second silicon substrate 101, the second trench 62 extends to the second silicon substrate 101, and the bottom wall of the second trench 62 is the surface of the second silicon substrate 101. A gate electrode 30 and a gate insulating layer 31 are disposed in the second trench 62.
[0117] In an exemplary embodiment, the second trench 62 is used to form the bit line 13; the first trench 61 and the second trench 62 are used to form the semiconductor pillar 50.
[0118] In an exemplary embodiment, as shown in FIG3, the second insulating layer 22 is located in the second trench 62. In the first direction D1, the second insulating layer 22 is located between the bit lines 13 of adjacent memory cells 11, isolating the bit lines 13 of adjacent memory cells 11 and insulating the bit lines 13 of adjacent memory cells 11 from the first electrode 51. In a direction perpendicular to the substrate, the second insulating layer 22 is located between the gate electrode 30 and the second silicon substrate 101.
[0119] In an exemplary embodiment, as shown in FIG3, the portion of the third insulating layer 23 near the substrate is located in the second trench 62 and disposed on the side of the gate electrode 30 away from the substrate. The portion of the third insulating layer 23 away from the substrate is located above the second trench 62 and disposed between the first isolation layers 81 on adjacent memory cells 11.
[0120] In an exemplary embodiment, as shown in Figures 2 and 3, the semiconductor device further includes a cover layer 90 located on the side of the semiconductor pillar 50 and the third insulating layer 23 away from the substrate. The cover layer 90 can cover one or more semiconductor pillars 50 to protect the semiconductor pillars 50.
[0121] The technical solution of this embodiment is further illustrated below through the fabrication process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."
[0122] In an exemplary embodiment, the semiconductor device includes a memory cell disposed on a substrate. The memory cell includes a bit line and a semiconductor pillar disposed sequentially along a direction away from the substrate. The semiconductor pillar includes a first electrode, a channel, and a second electrode disposed sequentially along a direction away from the substrate. The first electrode is electrically connected to the bit line.
[0123] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:
[0124] (S101) A first silicon substrate 71 is provided. Through an ion implantation process, P-type doping (doping with B) and N-type doping (doping with P) are performed at different depths in the first silicon substrate 71. Subsequently, lattice repair is performed through heat treatment. A first doped layer 72 is formed in the P-type doped region of the first silicon substrate 71, and a second doped layer 73 is formed in the N-type doped region. The second doped layer 73 is interconnected with the first doped layer 72, as shown in Figure 4a. The first silicon substrate 71 is used to subsequently form semiconductor pillars, the first doped layer 72 is used to subsequently form channels, and the second doped layer 73 is used to subsequently form the first electrode.
[0125] (S102) A first metal silicide thin film 77 is formed on the second doped layer 73 of the first silicon substrate 71, as shown in FIG4b. The first metal silicide thin film 77 is used for subsequent bit line formation.
[0126] In one exemplary embodiment, forming the first metal silicide thin film 77 includes:
[0127] A first metal thin film is deposited on the first silicon substrate;
[0128] An annealing process is used to form a first metal silicide thin film on the first silicon substrate;
[0129] The surface of the first metal silicide film is planarized using a chemical mechanical polishing process.
[0130] The first metal film comprises at least one selected from transition metals and transition metal alloys. For example, the transition metal comprises at least one selected from titanium and cobalt, and the transition metal alloy comprises a platinum-nickel alloy.
[0131] (S103) A second silicon substrate 101 is provided. A second metal silicide thin film is formed on the second silicon substrate 101. The second silicon substrate 101 is used as a substrate for subsequent formation, and the second metal silicide thin film is used for subsequent formation of bit lines.
[0132] In one exemplary embodiment, forming a second metal silicide thin film on a second silicon substrate 101 includes:
[0133] A second metal thin film is deposited on the second silicon substrate 101;
[0134] A second metal silicide thin film is formed on the second silicon substrate by an annealing process;
[0135] The surface of the second metal silicide film is planarized using a chemical mechanical polishing process.
[0136] The second metal film comprises at least one of a transition metal and a transition metal alloy. For example, the transition metal comprises at least one of titanium and cobalt, and the transition metal alloy comprises a platinum-nickel alloy.
[0137] In one exemplary embodiment, the first metal silicide film and the second metal silicide film are made of the same material. For example, both the first metal silicide film and the second metal silicide film are made of titanium silicon compound.
[0138] Subsequently, using flip-chip bonding, the first metal silicide thin film of the first silicon substrate 71 is bonded to the second metal silicide thin film of the second silicon substrate 101; thus forming a metal silicide layer 78 between the first metal silicide thin film and the second metal silicide thin film, with the second silicon substrate 101 serving as the substrate.
[0139] Subsequently, the portion of the first silicon substrate 71 away from the first doped layer 72 is subjected to N-type doping (P doping), forming a third doped layer 74 in the N-type doped region of the first silicon substrate 71, as shown in Figure 4c. The third doped layer 74 is used to form the second electrode in the subsequent process.
[0140] S104) Forming a semiconductor pillar. Forming the semiconductor pillar includes: etching the first doped layer 72, the second doped layer 73, the third doped layer 74, and the metal silicide layer 78 of the first silicon substrate 71 by an etching process on a substrate having the aforementioned pattern. A second trench 62 is formed in the first doped layer 72, the second doped layer 73, the third doped layer 74, and the metal silicide layer 78, so that the metal silicide layer 78 is etched to form a plurality of linear bit lines 13; each bit line 13 extends along a second direction D2, the plurality of bit lines 13 are arranged at intervals along a first direction D1, and a second trench 62 is provided between adjacent bit lines 13; the second trench 62 extends along the second direction D2, the second trench 62 extends to the second silicon substrate 101, and the bottom wall of the second trench 62 is the surface of the second silicon substrate 101;
[0141] Subsequently, a first insulating film 91 is filled into the second trench 62. A portion of the first insulating film 91 fills the second trench 62, and a portion of the first insulating film 91 is located on the surface of the semiconductor pillar 50 away from the second silicon substrate 101.
[0142] Subsequently, a first trench 61 is formed in the first doped layer 72, the second doped layer 73, and the third doped layer 74. The first trench 61 extends along the first direction D1 to the bit line 13, and the bottom wall of the first trench 61 is the surface of the bit line 13 away from the substrate. The first trench 61 and the second trench 62 form a semiconductor pillar 50 on the first silicon substrate 71. Specifically, the first trench 61 and the second trench 62 form a second electrode 53 in the third doped layer 74, a channel 52 in the first doped layer 72, and a first electrode 51 in the second doped layer 73. The second electrode 53, the channel 52, and the first electrode 51 form the semiconductor pillar 50, as shown in Figures 5a and 5b.
[0143] (S105) On the substrate having the aforementioned pattern, an atomic deposition process is used to form a second insulating film 92 on the sidewall of the first trench 61, as shown in Figure 6.
[0144] (S106) On a substrate having the aforementioned pattern, a third insulating film 93 is formed on the side of the semiconductor pillar 50 away from the second silicon substrate 101 by chemical deposition. A portion of the third insulating film 93 fills the first trench 61, and a portion of the third insulating film 93 covers the first insulating film 91 on one or more semiconductor pillars 50, as well as the first insulating film 91 in the second trench 62, as shown in Figures 7a and 7b.
[0145] (S107) On a substrate having the aforementioned pattern, a grinding process is used to remove a portion of the third insulating film 93 away from the second silicon substrate 101 and the first insulating film 91 on the semiconductor pillar 50, exposing the surface of the second electrode 53 of the semiconductor pillar 50; subsequently, an etching process is used to etch away a portion of the second insulating film 92 and a portion of the first insulating film 91 of the second trench 62, exposing the sidewalls of the second electrode 53 of the semiconductor pillar 50; the remaining third insulating film 93 forms the first insulating layer 21, as shown in Figures 8a and 8b.
[0146] (S108) On a substrate having the aforementioned pattern, an atomic deposition process is used to form a second isolation layer 82 on the exposed sidewall of the second electrode 53. The second isolation layer 82 is disposed around the sidewall of the second electrode 53, as shown in Figures 9a and 9b.
[0147] (S109) On the substrate having the aforementioned pattern, an etching process is used to remove a portion of the second insulating film 92 and a portion of the first insulating film 91 to form a cavity 110 surrounding the sidewall of the channel 52. The cavity 110 exposes the sidewall of the channel 52 of the semiconductor pillar 50, and the retained first insulating film 91 and the retained second insulating film 92 form a second insulating layer 22, as shown in Figures 10a and 10b.
[0148] Figure 11a is a cross-sectional view in the second direction after the gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application; Figure 11b is a cross-sectional view in the first direction after the gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application.
[0149] S110) On a substrate having the aforementioned pattern, an atomic deposition process is used to form a gate insulating layer 31 on the exposed sidewall of the channel 52, the gate insulating layer 31 being disposed around the sidewall of the channel 52; a first isolation layer 81 is formed on the surface of the second electrode 53 of the semiconductor pillar 50 on the side away from the second silicon substrate 101; as shown in Figures 11a and 11b.
[0150] S111) On a substrate having the aforementioned pattern, an atomic deposition process is used to form a gate electrode 30 on a gate insulating layer 31. The gate electrode 30 is disposed around the sidewall of the channel 52 through the gate insulating layer 31, as shown in Figures 12a and 12b.
[0151] S112) On a substrate having the aforementioned pattern, a third insulating layer 23 is formed on the side of the first insulating layer 21 away from the substrate and on the side of the gate electrode 30 away from the substrate; subsequently, a capping layer 90 is formed on the side of the first isolation layer 81 away from the substrate and the side of the third insulating layer 23 away from the substrate on the semiconductor pillar 50, as shown in Figures 2 and 3.
[0152] The semiconductor device manufacturing method of this application has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.
[0153] The semiconductor device manufacturing method of this application adopts a flip chip bonding method to bond metal silicide thin films on two silicon substrates to form a metal silicide layer. Subsequently, an etching process is used to form bit lines in the metal silicide layer, so that the bit lines have a uniform and dense internal structure, solving problems such as bit line open circuits and poor contact between bit lines and semiconductor pillars, and ensuring the uniformity of the height of multiple semiconductor pillars formed on the silicon substrate.
[0154] This application also provides an electronic device, including any of the semiconductor devices described above. This application does not impose any special limitations on the specific form of the described electronic device.
[0155] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.
[0156] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.
Claims
1. A method for manufacturing a semiconductor device, the method comprising: forming a first metal silicide film on a first silicon substrate; forming a second metal silicide film on a second silicon substrate; bonding the first metal silicide film of the first silicon substrate and the second metal silicide film of the second silicon substrate by flip-chip bonding, so that the first metal silicide film and the second metal silicide film form a metal silicide layer; etching the metal silicide layer to form a linear bit line by an etching process; forming a semiconductor pillar from the first silicon substrate.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming a first metal silicide film on a first silicon substrate, comprising: depositing a first metal film on the first silicon substrate; forming a first metal silicide film on the first silicon substrate by an annealing process; planarizing a surface of the first metal silicide film by a chemical mechanical polishing process.
3. The method of manufacturing a semiconductor device according to claim 2, wherein The first metal film comprises at least one of a transition metal and a transition metal alloy.
4. The method of manufacturing a semiconductor device according to claim 1, wherein forming a second metal silicide film on a second silicon substrate, comprising: depositing a second metal film on the second silicon substrate; forming a second metal silicide film on the second silicon substrate by an annealing process; planarizing a surface of the second metal silicide film by a chemical mechanical polishing process.
5. The method of manufacturing a semiconductor device according to claim 4, wherein The second metal film comprises at least one of a transition metal and a transition metal alloy.
6. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein The first metal silicide film and the second metal silicide film are of the same material.
7. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein etching the metal silicide layer to form a linear bit line, comprising: forming a groove in the first silicon substrate and the metal silicide layer by an etching process, so that the metal silicide layer is etched to form a plurality of linear bit lines, and a groove is arranged between adjacent bit lines, the groove extending from a surface of the first silicon substrate away from the second silicon substrate to the second silicon substrate.
8. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein After forming a semiconductor pillar from the first silicon substrate, the method further comprises: exposing a sidewall of the semiconductor pillar by an etching process; forming a gate insulating layer on the sidewall of the semiconductor pillar by an atomic deposition process; forming a gate electrode on the gate insulating layer by an atomic deposition process, the gate electrode and the gate insulating layer being arranged around the sidewall of the semiconductor pillar. 9.A semiconductor device, comprising a memory cell arranged on a substrate, the memory cell comprising a bit line arranged on the substrate, and a semiconductor pillar arranged on a side of the bit line away from the substrate, the semiconductor pillar comprising a first electrode, a channel, and a second electrode arranged in sequence in a direction away from the substrate, the first electrode being electrically connected to the bit line; the bit line comprising a first metal silicide layer and a second metal silicide layer, the first metal silicide layer and the second metal silicide layer being bonded together.
10. The semiconductor device of claim 9, wherein, The first metal silicide layer and the second metal silicide layer are of the same material and are connected together.
11. The semiconductor device of claim 9, wherein, The bit line is linear, and includes a bottom surface located close to one side of the substrate and a top surface located away from the substrate, both the bottom surface and the top surface being flat surfaces in the extension direction of the bit line.
12. The semiconductor device of claim 9, wherein, The storage unit further includes a gate insulating layer and a gate electrode, the gate electrode being disposed around the sidewall of the channel of the semiconductor pillar.
13. An electronic device comprising the semiconductor device according to any one of claims 9 to 12.