Method for marking erroneous code block, and electronic device and computer-readable storage medium

Abstract

Provided in the present application are a method for marking an erroneous code block, and an electronic device and a computer-readable storage medium. The method comprises: performing first processing on a code stream that is received from an Ethernet interface, so as to obtain a first code stream, wherein the first processing at least comprises first forward error correction (FEC) decoding, and the first code stream is a 257B code stream; in respect of an error that cannot be corrected by means of FEC during FEC decoding, performing error marking on n 257B code blocks in the first code stream, so as to obtain a second code stream, wherein n is an integer greater than or equal to 1; and performing second processing on the second code stream, so as to map the second code stream into a signal container of an optical transport network (OTN).

Description

Error code block marking method, electronic device, and computer-readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202310788406.X and application date June 29, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to an error code block marking method, an electronic device, and a computer-readable storage medium. Background Art

[0004] The Optical Transport Network (OTN) is a transport network that implements the transmission, multiplexing, routing, and monitoring of service signals within the optical domain, while ensuring their performance and survivability. With the rapid growth of network service throughput, bandwidth requirements for communication equipment are also rapidly increasing. OTN has evolved from 400 Gigabit Ethernet (GE) to support access and transmission of 800GE services. Compared to Ethernet services at 400GE and below (400GE / 200GE / 100GE / 10GE), to conserve transmission bandwidth, narrow the gap between Ethernet service rates and OTN rates, and increase the possibility of using the same modules for both Ethernet and OTN services, the 800GE to OTN mapping reference point has been changed from a 66B data stream to a 257B data stream. However, the current error marking function of the OTN Ethernet interface is for 66B code streams. When the mapping reference point is changed to 257B code streams, the error marking function of the OTN Ethernet interface is not effective for 257B code streams, which will cause the mean time to false packet acceptance (MTTFPA) problem.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide an error code block marking method, an electronic device, and a computer-readable storage medium, which are intended to solve the problem that an OTN node cannot implement an error marking function for Ethernet services using a 257B reference point.

[0007] In a first aspect, an embodiment of the present application provides an error code block marking method, the method comprising: performing a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing includes decoding a first forward error correction code (FEC), and the first code stream is a 257B code stream; for an FEC uncorrectable error occurring during the FEC decoding process, performing error marking on n 257B code blocks in the first code stream to obtain a second code stream, wherein n is an integer greater than or equal to 1; and performing a second processing on the second code stream to map the second code stream to a signal container of an optical transport network (OTN).

[0008] In a second aspect, an embodiment of the present application provides an error code block marking device, the device comprising: a first processing module, configured to perform a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing includes decoding a first forward error correction code FEC, and the first code stream is a 257B code stream; an error marking module, configured to perform an error marking on n 257B code blocks in the first code stream for an FEC uncorrectable error occurring during the FEC decoding process, to obtain a second code stream, wherein n is an integer greater than or equal to 1; and a second processing module, configured to perform a second processing on the second code stream to map the second code stream to a signal container of an optical transport network OTN.

[0009] In a third aspect, an embodiment of the present application provides an electronic device comprising: one or more processors; a memory on which one or more programs are stored, and when the one or more programs are executed by the one or more processors, the one or more processors implement the error code block marking method described in the first aspect above.

[0010] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the error code block marking method as described in the first aspect above.

[0011] In an embodiment of the present application, a code stream received from an Ethernet interface is first processed to obtain a first code stream using 257B encoding, wherein the first processing includes FEC decoding. In response to an FEC uncorrectable error occurring during the FEC decoding process, n 257B code blocks in the first code stream are error-marked to obtain a second code stream carrying the error mark. The second code stream is then mapped to a signal container of an optical transport network (OTN), thereby enabling the second code stream to be transmitted to an Ethernet sink node via the OTN. This solves the problem that the OTN node cannot implement an error marking function for Ethernet services using a 257B reference point, and can improve the MTTFPA problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram of a process in which a 400GE service is transmitted to a peer Ethernet node via an OTN in the related art;

[0013] FIG2 is a schematic diagram of a process in which an 800GE service is transmitted to a peer Ethernet node via an OTN in the related art;

[0014] FIG3 is a flow chart of a method for marking an error code block according to an embodiment of the present application;

[0015] FIG4 a is a schematic diagram of the format of a type A 257B error code block provided in an embodiment of the present application;

[0016] FIG4 b is a schematic diagram of the format of a Type B 257B error code block provided in an embodiment of the present application;

[0017] FIG5 is a schematic diagram of an optional process of transmitting an 800GE service to a peer Ethernet node via an OTN according to an embodiment of the present application;

[0018] FIG6 is a schematic diagram of an optional process of transmitting an 800GE service to a peer Ethernet node via an OTN according to an embodiment of the present application;

[0019] 7 is a schematic diagram of an error marking processing method for an 800GE service transmitted to a peer Ethernet node via an OTN according to an embodiment of the present application;

[0020] FIG8 is a schematic diagram of an error code block marking device provided in an embodiment of the present application;

[0021] FIG9 is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solution of the present application, the error code block marking method, electronic device and computer-readable storage medium provided by the present application are described in detail below with reference to the accompanying drawings.

[0023] Hereinafter, example embodiments will be described more fully in conjunction with the accompanying drawings, but the described example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these examples are provided so that this application will be thorough and complete and will fully enable those skilled in the art to understand the scope of this application.

[0024] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] The terms used herein are used only to describe specific embodiments and are not intended to limit this application. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, they specify the presence of features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0026] In the description of the embodiments of the present application, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0027] In the description of the embodiments of this application, any embodiment or design scheme using "exemplary," "for example," or "for example" should not be understood as being more preferred or advantageous than other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0029] In order to facilitate understanding of the solutions of the embodiments of the present application and to provide a clear and concise description of the following embodiments, a brief introduction to the relevant technologies is first given.

[0030] (1) Optical Transport Network (OTN) refers to a transmission network that implements the transmission, multiplexing, routing, and monitoring of service signals in the optical domain and ensures their performance indicators and survivability.

[0031] OTN is divided into the client signal layer, optical payload unit (OPU), optical data unit (ODU), optical transport unit (OTU), optical channel layer (OCh), optical multiplex section layer (OMS), and optical transmission section layer (OTS). Each of these layers serves as the client layer, while the other serves as the service layer. The client signal layer refers to the signal to be carried by the OTN network, such as SDHQ, Ethernet, and IP services. The optical channel payload unit (OPU) is mainly used to adapt the client signal to make it suitable for transmission on the optical channel, that is, it is the "container" that carries the client signal. The overhead of this layer is mainly used to indicate the process of mapping the client signal to the OTN signal. The optical channel data unit (ODU) is composed of the related overhead of the OPU layer and the ODU layer. The overhead of this layer can support end-to-end detection of the transmission signal quality. The optical channel transport unit (OTU) is the basic unit structure for transmitting information on the optical path and is composed of the related overhead of the ODU layer and the OTU layer. The optical channel layer (OCh) is an optical signal with a specific wavelength and a special frame format, where the special frame format is defined by the OTU layer. The optical multiplexing section layer (OMS) is a multi-wavelength optical signal that has been combined. The optical transmission section layer (OTS) is an optical signal that has been processed by amplifiers (OAs).

[0032] When an Ethernet data packet arrives at the OTN, it encapsulates and converts it. The specific processing flow includes the following: At the transmitting end, the Ethernet data packet is connected to the OTN through the client board and converted into an OPU, that is, the Ethernet data packet is encapsulated into an OPU optical signal. The OPU is the most basic transmission unit in the OTN, which includes the data packet and some control information. Next, the OTN further encapsulates the OPU optical signal and converts it into an ODU optical signal. The ODU optical signal is connected to the line board and converted into an OTU optical signal. The multiple OTU optical signals are multiplexed together through a combiner and transmitted on the same optical fiber. The optical signal is regenerated and amplified by an OA optical amplifier along the optical fiber transmission path to ensure long-distance transmission. At the receiving end, the optical signal is demultiplexed by a wavelength splitter, and multiple optical signals are separated. After processing by the line board and the client board, the Ethernet service signal is output.

[0033] (2) Forward Error Correction (FEC) refers to the pre-encoding of signals before transmission. Encoding refers to the sending end sending error-correcting codes. The receiving end automatically corrects errors that occur during transmission based on the received codes and decoding rules, thereby achieving the purpose of identifying and correcting errors. Forward error correction methods include Reed-Solomon Forward Error Correction (RS-FEC). RS-FEC can be used for the coding schemes of 100GE, 200GE, 400GE, and 800GE Ethernet services.

[0034] (3) Mean Time to False Package Acceptance (MTTFPA) refers to the average time to failure. MTTF can be used to measure the probability and frequency of system failures. Generally speaking, the longer the MTTF, the higher the system stability.

[0035] (4) 66B code stream refers to a code stream using the 66B encoding format, consisting of multiple 66-bit blocks (66B blocks). Each 66-bit block contains 66 bits and uses the 64B / 66B encoding format. The first two bits of a 66-bit block can be called a synchronization header. A 66-bit block with a synchronization header of 01 can be called a 64B / 66B data coding block, indicating that the last 64 bits of the 66-bit block are all data information; a 66-bit block with a synchronization header of 10 can be called a 64B / 66B control coding block, indicating that the last 64 bits of the 66-bit block are a mixture of data information and control information, or all control information. When the values ​​of the two bits in the synchronization header are the same (the synchronization header is 00 or 11), the synchronization header is an invalid synchronization header, and the 66-bit block with an invalid synchronization header is an error code block.

[0036] (5) 257B code stream refers to a code stream using the 257B encoding format, which consists of multiple 257-bit blocks. Each 257-bit block contains 257 bits.

[0037] With the rapid growth of network service throughput, the bandwidth requirements of communication equipment are also growing rapidly. OTN has been upgraded from 400GE to support the access and transmission of 800GE services. When services with speeds below 400G (including 400GE, 200GE, 100GE, and 10GE services) are mapped to OTN, the OTN reference point is a 66B stream. For services with speeds above 400G, in this embodiment of the application, 800GE services, when mapped to OTN, the OTN reference point is a 257B stream.

[0038] Please refer to Figure 1, which is a schematic diagram of the process of transmitting 400GE services to the opposite Ethernet node via OTN in the related art. The network shown in Figure 1 includes Ethernet node 1, OTN node 1, OTN node 2, and Ethernet node 2. Ethernet node 1 and OTN node 1 are connected via a 400G Attachment Unit Interface (AUI), and OTN node 2 and Ethernet node 2 are connected via a 400G AUI. OTN node 1 and OTN node 2 are connected via an OTN link, which can include multiple OTN nodes. In the example in Figure 1, an 800G Ethernet service stream needs to be transmitted from Ethernet node 1 to Ethernet node 2 via the OTN link. Ethernet node 1 performs RS-FEC encoding on the 400G Ethernet service stream and sends the RS-FEC-encoded stream to OTN node 1 through the 400G AUI. Since the mapping reference point of the 400GE service in the OTN is a 66B stream, after receiving the 400G stream from the 400G AUI interface, OTN node 1 first performs RS-FEC decoding and 257B to 66B transcoding on the stream. When an uncorrectable error occurs during the FEC decoding process, the 66B code block corresponding to the 20*257B code block involved in the RS-FEC codeword is marked as an error during the 257B to 66B transcoding process. The error marking method can be to replace the synchronization header of the 66B code block with an invalid synchronization header (the synchronization header after replacement is 00 or 11); then, the 66B code stream is mapped into the signal container ODU flex and transmitted to OTN node 2 through the OTN link. After receiving the 66B code stream, OTN node 2 performs 66B synchronization to locate the 66B code block and demap the 66B code block from the ODU flex frame. The 66B code block marked as invalid will be converted into an Ethernet local fault (Local False, LF) code blocks or idle (Idle) code blocks, and perform 66B to 257B transcoding processing, and send a 257B code stream to Ethernet node 2. During this process, LF code blocks or Idle code blocks will be filtered to ensure that these code blocks that may contain errors are not passed to the MAC layer of Ethernet node 2.

[0039] Please refer to Figure 2, which is a schematic diagram of the process of transmitting 800GE services to a peer Ethernet node via OTN in the related art. The network shown in Figure 1 includes Ethernet node 1, OTN node 1, OTN node 2, and Ethernet node 2. Ethernet node 1 and OTN node 1 are connected via an 800G AUI, and OTN node 2 and Ethernet node 2 are connected via an 800G AUI. OTN node 1 and OTN node 2 are connected via an OTN link, which can include multiple OTN nodes. In the example of Figure 2, an 800G Ethernet service stream needs to be transmitted from Ethernet node 1 via the OTN link to Ethernet node 2. The 800G Ethernet service stream is split into two 400G streams for PCS / FEC processing. The related art uses the same FEC error marking method as 400GE services. To avoid MTTFPA issues for the MAC, when an 800GAUI interface detects an uncorrectable error during the RS-FEC process, it still uses the 400GE FEC error marking method of replacing the invalid synchronization header during 257B to 66B transcoding. This method is effective when Ethernet services are transmitted only over Ethernet links without passing through OTN links. However, if Ethernet services need to be transmitted over OTN links, this error marking function will be invalid. When mapping 800GE to ODUflex, 800GE is mapped to the OTN reference point as a 257B code stream. Therefore, OTN node 1 performs RS-FEC decoding and 257B-to-66B transcoding on the two service code streams at the 800GAUI interface. Following the same FEC error marking method as for 400GE services, the synchronization header of the 66B code block is replaced with an invalid one. The 66B code stream is then transcoded into a 257B code stream for mapping into the ODUflex. However, the 66B code blocks marked invalid cannot be transcoded to 275B. Consequently, these invalidated 66B code blocks are not transmitted over the OTN link. This means that the existing Ethernet FEC error marking function cannot guarantee effective error marking, causing MTTFPA issues on this Ethernet link.

[0040] 1.6TE services are also distributed using 257B code blocks. After being output by the MAC, the 1.6TE service code stream is split into four 400G 257B code streams at the PCS layer. Because the 257B code stream has a more compressed overhead than the 66B code stream, it is less robust than the 66B code stream. When using a 257B code stream that passes through a physical interface that could introduce errors, error marking must be supported. FEC error marking on Ethernet interfaces is accomplished by replacing the 66B code block with an invalid synchronization header during 257B to 66B transcoding. The mapping reference point for B400G Ethernet services (800GE / 1.6TE) to OTN has changed from 66B to 257B. This inevitably prevents the error marking function on Ethernet interfaces from taking effect when carrying B400G Ethernet services over OTN links, leading to MTTFPA issues.

[0041] In view of this, embodiments of the present application provide an error code block marking method, an electronic device, and a computer-readable storage medium, which are suitable for error marking of services (including 800GE and 1.6TE services) mapped to OTN using 257B as a reference point. This aims to solve the problem that OTN nodes cannot implement the error marking function for Ethernet services using the 257B reference point.

[0042] Please refer to Figure 3, which is a flow chart of a method for marking an error code block provided by an embodiment of the present application. The error code block marking method is applied to an OTN node and includes the following steps:

[0043] In step S110, the OTN node performs a first processing on the code stream received from the Ethernet interface to obtain a first code stream, wherein the first processing at least includes decoding a first forward error correction code FEC, and the first code stream is a 257B code stream.

[0044] In an exemplary embodiment, Ethernet node 1 (e.g., a routing device or gateway device) sends an 800GE service stream to OTN node 1 via an Ethernet interface, for transmission to Ethernet node 2 at the other end via the OTN. The 800GE service stream is split into two parallel 400G streams at the PCS layer and enters OTN node 1. Both of these parallel 400G streams are in 275B format. After receiving the two parallel 400G streams from the Ethernet interface, OTN node 1 performs a first processing on each stream to obtain a first stream after the first processing.

[0045] It should be noted that the first processing in the embodiment of the present application includes at least FEC decoding. In addition to FEC decoding, the first processing may also include one or more of the following processing: multi-channel alignment, alignment marker AM locking, channel de-skew, channel sorting, and FEC codeword deinterleaving.

[0046] In an exemplary embodiment, after the code stream enters the OTN node through the Ethernet interface, the following first processing steps are sequentially performed: multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword deinterleaving, and FEC decoding.

[0047] In step S120 , the OTN node marks n 257B code blocks in the first code stream as errors in response to an FEC uncorrectable error occurring during the FEC decoding process, thereby obtaining a second code stream, where n is an integer greater than or equal to 1.

[0048] It should be noted that if an uncorrectable FEC error (i.e., an FEC codeword cannot be corrected) occurs during FEC decoding of the codestream by the OTN node, n 257B code blocks in the first codestream are marked as errors. The specific value of n is determined by the number of FEC codewords and whether related codewords affect each other. After the first codestream is marked as an error, the second codestream can be obtained.

[0049] In an exemplary embodiment, in response to an FEC uncorrectable error occurring during FEC decoding, n 257B code blocks in the first code stream may be replaced with 257B error code blocks to obtain a second code stream. In other words, n 257B code blocks in the first code stream may be directly replaced with 257B error code blocks.

[0050] Please refer to Figure 4a, which shows a schematic diagram of the format of a Type A 257B error code block provided in an embodiment of the present application. As shown in Figure 4a, the Type A 257B error code block includes 257 bits, of which bit 0 is 0, bits 1 to 4 are 0xF (i.e., 0b1111), and bits 5 to 256 are 252 bits of information. The 252 bits of information can be any information, and the embodiments of the present application do not specifically limit the information content contained in the 252 bits of information.

[0051] Please refer to Figure 4b, which shows a format diagram of a B-type 257B error code block provided by an embodiment of the present application. As shown in Figure 4b, the B-type 257B error code block includes 257 bits, wherein the value of the 0th bit of the B-type 257B error code block is 0, the 1st bit to the 4th bit are all 0, the 5th to the 8th bits are 0xE, the 1st bit to the 8th bit are 0x0E (i.e. 0b00001110), the 9th bit to the 64th bit are 56 bits of information, and the 65th bit to the 72nd bit are 0x0E (i.e. 0b00001110). The 73rd to 128th bits are 56 bits of information, the 129th to 136th bits are 0x1E (i.e., 0b00011110), the 137th to 192th bits are 56 bits of information, the 193rd to 200th bits are 0x1E (i.e., 0b00011110), and the 201st to 256th bits are 56 bits of information. The 56-bit information can be any information, and the embodiments of the present application do not specifically limit the information content contained in the 56-bit information. In one example, the 56-bit information includes an error control code block / E / .

[0052] It should be noted that, in a specific implementation process, the n 257B code blocks in the first code stream may be replaced by any one of the above-mentioned A-type 257B error code blocks and B-type 257B error code blocks.

[0053] In an exemplary embodiment, the first code stream can be transcoded from 257B to 66B to obtain a third code stream, where the third code stream is a 66B code stream. In response to an FEC uncorrectable error occurring during FEC decoding, m 66B code blocks in the third code stream are replaced with 66B invalid code blocks to obtain a fourth code stream, where m is greater than or equal to 4 and is a multiple of 4. The fourth code stream is transcoded from 66B to 257B, and every four 66B invalid code blocks in the fourth code stream are replaced with one 257B error code block to obtain a second code stream.

[0054] That is, the first code stream in 275B format is transcoded into a third code stream in 66B format. Then, in response to FEC uncorrectable errors occurring during the FEC decoding process, m 66B code blocks in the third code stream that are associated with n 257B code blocks that need to be error-marked are error-marked. The 66B code blocks are error-marked by setting the synchronization header of the 66B code blocks to "00" or "11," that is, replacing the relevant 66B code blocks with invalid 66B code blocks, thereby obtaining a fourth code stream. The fourth code stream is then transcoded from 66B to 257B, and during the transcoding process, every four invalid 66B code blocks are replaced with one 257B error code block, thereby obtaining a second code stream.

[0055] In an exemplary embodiment, replacing every four 66B invalid code blocks with one 257B error code block includes: replacing every four 66B invalid code blocks with one Type A 257B error code block. Specifically, bit 0 of the corresponding 257B code block can be set to 0 (a total of 1 bit), bits 1 to 4 can be set to 0xF (i.e., Ob1111, a total of 4 bits), the values ​​of bits 2 to 5 and bits 10 to 65 of the first 66B code block are placed in bits 5 to 64 of the 257B code block (a total of 60 bits), and bits 2 to 65 of the second, third, and fourth 66B code blocks are placed in bits 65 to 256 of the 257B code block (a total of 192 bits), respectively.

[0056] In an exemplary embodiment, each of four 66B invalid code blocks is replaced with one 257B error code block, including: each of four 66B invalid code blocks is replaced with one B-type 257B error code block. Specifically, the 0th bit of the corresponding 257B code block can be set to 0, the 1st to 8th bits of the 257B code block can be set to 0x0E (i.e., 0b00001110), the 56-bit information of the first 66B invalid code block can be placed in the 9th to 64th bits of the 257B code block, the 65th to 72nd bits of the 257B code block can be set to 0x1E (i.e., 0b00011110), and the 56-bit information of the second 66B invalid code block can be placed in the 73rd bit of the 257B code block. The 129th to 136th bits of the 257B code block are set to 0x1E (i.e., 0b00011110), the 56-bit information of the third 66B invalid code block is placed from the 137th to 192th bits of the 257B code block, the 193th to 200th bits of the 257B code block are set to 0x1E (i.e., 0b00011110), and the 56-bit information of the fourth 66B invalid code block is placed from the 201st to the 256th bits of the 257B code block.

[0057] In an exemplary embodiment, an error mark enable signal may be output for FEC uncorrectable errors occurring during the FEC decoding process; during the duration of the error mark enable signal, a 257B code block in the first code stream is replaced with a 257B error code block to obtain a second code stream.

[0058] For example, when an uncorrectable error is detected in the FEC decoding, an error flag enable signal is set to indicate all 257B blocks involved in the FEC codeword. The duration of the error flag enable signal is aligned with the 257B codeword. When the error flag enable signal is asserted, the corresponding 257B codeblock is replaced with a 257B error codeblock.

[0059] It should be noted that the 257B code block is replaced by a 257B error code block, specifically, it can be replaced by an A-type 257B error code block or it can be replaced by a B-type 257B error code block.

[0060] In an exemplary embodiment, the first code stream can be transcoded from 257B to 66B to obtain a third code stream, wherein the third code stream is a 66B code stream; in response to an FEC uncorrectable error occurring during the FEC decoding process, an error flag enable signal is output; within the duration of the error flag enable signal, the 66B code blocks in the third code stream are replaced with 66B invalid code blocks; the third code stream is transcoded from 66B to 257B, and every four 66B invalid code blocks in the third code stream are replaced with one 257B error code block to obtain a second code stream.

[0061] For example, a first code stream in 257B format is transcoded to obtain a third code stream in 66B format. During the transcoding process, an error flag enable signal is set for the uncorrectable 275 code blocks involved in FEC decoding, so that during the effective period of the error flag enable signal, the relevant 275 code blocks are converted into four 66B invalid code blocks respectively. Next, the third code stream with error marking is transcoded to obtain a second code stream in 275B format, and every four 66B invalid code blocks in the third code stream are replaced with one 257B error code block to obtain the second code stream.

[0062] In an exemplary embodiment, replacing every four 66B invalid code blocks with one 257B error code block includes: replacing every four 66B invalid code blocks with one Type A 257B error code block. Specifically, bit 0 of the corresponding 257B code block can be set to 0 (a total of 1 bit), bits 1 to 4 can be set to 0xF (a total of 4 bits), the values ​​of bits 2 to 5 and bits 10 to 65 of the first 66B code block are placed in bits 5 to 64 of the 257B code block (a total of 60 bits), and bits 2 to 65 of the second, third, and fourth 66B code blocks are placed in bits 65 to 256 of the 257B code block (a total of 192 bits), respectively.

[0063] In an exemplary embodiment, each of four 66B invalid code blocks is replaced with one 257B error code block, including: each of four 66B invalid code blocks is replaced with one B-type 257B error code block. Specifically, the 0th bit of the corresponding 257B code block can be set to 0, the 1st to 8th bits of the 257B code block can be set to 0x0E (i.e., 0b00001110), the 56-bit information of the first 66B invalid code block can be placed in the 9th to 64th bits of the 257B code block, the 65th to 72nd bits of the 257B code block can be set to 0x1E (i.e., 0b00011110), and the 56-bit information of the second 66B invalid code block can be placed in the 73rd bit of the 257B code block. The 129th to 136th bits of the 257B code block are set to 0x1E (i.e., 0b00011110), the 56-bit information of the third 66B invalid code block is placed from the 137th to 192th bits of the 257B code block, the 193th to 200th bits of the 257B code block are set to 0x1E (i.e., 0b00011110), and the 56-bit information of the fourth 66B invalid code block is placed from the 201st to the 256th bits of the 257B code block.

[0064] Step S130: The OTN node performs a second process on the second code stream to map the second code stream into a signal container of the optical transport network OTN.

[0065] In an exemplary embodiment, the second process includes code stream interleaving and rate compensation.

[0066] In an exemplary embodiment, the second code stream is subjected to a second processing to map the second code stream into a signal container of an optical transport network (OTN), specifically including: interleaving the second code stream with one or three fifth code streams to obtain a sixth code stream; and performing rate compensation on the sixth code stream and mapping it into the OTN signal container, wherein both the fifth code stream and the sixth code stream are 257B code streams.

[0067] For example, 800GE services are divided into two streams, flow0 and flow1. Flow0 and flow1 enter the OTN node through the Ethernet interface. The OTN node performs the first processing on flow0 and flow1, respectively, to generate flow0' and flow1'. Flow0 encounters an uncorrectable error during the FEC decoding process included in the first processing. Therefore, flow0' is marked as an error and becomes flow0", while flow1 does not encounter any uncorrectable errors during the FEC decoding process. Flow0" and flow1' are interleaved to form a single stream. This interleaved stream is rate compensated to adapt to the rate of the OTN signal container, and then mapped into the OTN signal container.

[0068] For example, a 1.6TE service is divided into four streams: flow0, flow1, flow2, and flow3. These streams enter the OTN node through an Ethernet interface. The OTN node performs the first processing on flow0, flow1, flow2, and flow3, respectively, generating flow0', flow1', flow2', and flow3'. Because flow0 encounters an uncorrectable error during the FEC decoding process included in the first processing, flow0' is marked as an error and becomes flow0", while flows1, flow2, and flow3 do not encounter uncorrectable errors during the FEC decoding process. Flow0" is interleaved with flow1', flow2', and flow3 to form a single stream. This interleaved stream is rate-compensated to match the rate of the OTN signal container, and the rate-compensated stream is mapped into the OTN signal container.

[0069] It should be noted that the OTN signal container refers to an OTN transmission frame. The OTN transmission frame can be a flexible optical service unit (OSU flex) frame, an optical data unit k (ODUk), ODUCn, or ODUflex frame, an optical transport unit k (OTUk), OTUCn, or a flexible OTN (FlexO) frame. In the following description, the signal container uses ODUflex as an example.

[0070] It should be noted that rate compensation for the code stream can be achieved by adding / deleting idle code blocks, so that the transmission rate of the code stream finally mapped to the ODUflex matches the rate of the ODUflex payload area.

[0071] The solutions provided in the embodiments of the present application are described in detail below through specific examples.

[0072] Example 1

[0073] Please refer to FIG. 5 , which is a schematic diagram of an optional process for transmitting an 800GE service to a peer Ethernet node via an OTN according to an embodiment of the present application. This embodiment includes the following steps:

[0074] In step S1001, Ethernet node 1 sends an 800GE service stream to OTN node 1 via the 800GE AUI. The 800GE service stream is split into two 400G streams that enter OTN node 1. These two streams are referred to as flow 0 and flow 1, both of which are 257B streams.

[0075] Step S1002: OTN node 1 performs multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword deinterleaving, and FEC decoding on flow 0 and flow 1 respectively.

[0076] Step S1003: If an uncorrectable error occurs in flow 0 during the FEC decoding process, OTN node 1 replaces the relevant uncorrectable 275B code block in flow 0 with a type A 275B error code block or a type B 275B error code block.

[0077] Step S1004: If an uncorrectable error occurs in flow 1 during the FEC decoding process, OTN node 1 replaces the relevant uncorrectable 275B code block in flow 1 with a type A 275B error code block or a type B 275B error code block.

[0078] Step S1005: OTN node 1 interleaves flow 0 and flow 1, which have undergone the first processing and error marking, into a 275B code stream, performs rate compensation on the interleaved code stream, and maps it into an ODUflex. The ODUflex is then transmitted to OTN node 2 via the OTN link.

[0079] Step S1006: OTN node 2 demaps two 257B code streams, flow 0 and flow 1, from the ODU flex, and sends flow 0 and flow 1 to Ethernet node 2.

[0080] Step S1007: Ethernet node 2 receives two 275B code streams, flow 0 and flow 1, and transcodes flow 0 and flow 1 into 66B code streams, respectively. Each 275B error code block in flow 0 and flow 1 is converted into four 66B invalid code blocks.

[0081] In step S1008, Ethernet node 2 filters out the 66B invalid code blocks in flow 0 and flow 1 through sequence detection, and then transmits them to the MAC layer.

[0082] Example 2

[0083] Please refer to FIG. 6 , which is a schematic diagram of an optional process for transmitting an 800GE service to a peer Ethernet node via an OTN according to an embodiment of the present application. This embodiment includes the following steps:

[0084] In step S2001, Ethernet node 1 sends an 800GE service stream to OTN node 1 via the 800GE AUI. The 800GE service stream is split into two 400G streams that enter OTN node 1. These two streams are referred to as flow 0 and flow 1, both of which are 257B streams.

[0085] In step S2002, OTN node 1 performs multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword deinterleaving, and FEC decoding on flow 0 and flow 1 respectively.

[0086] In step S2003, an uncorrectable error occurs in flow 0 during the FEC decoding process. OTN node 1 identifies the uncorrectable 275B code blocks in flow 0, transcodes flow 0 into a 66B code stream, replaces each uncorrectable 275B code block with the corresponding four 66B invalid code blocks, then transcodes flow 0 into a 275B code stream and replaces each four 66B invalid code blocks with one Type B 275B error code block.

[0087] In step S2004, an uncorrectable error occurs in flow 1 during the FEC decoding process. OTN node 1 determines the uncorrectable 275B code blocks in flow 1, transcodes flow 1 into a 66B code stream, replaces each uncorrectable 275B code block with the corresponding four 66B invalid code blocks, then transcodes flow 0 into a 275B code stream and replaces each four 66B invalid code blocks with one B-type 275B error code block.

[0088] In step S2005, OTN node 1 interleaves flow 0 and flow 1 into a 275B code stream, performs rate compensation on the interleaved code stream, and maps it into an ODUflex. The ODUflex is then transmitted to OTN node 2 via the OTN link.

[0089] Step S2006: OTN node 2 demaps two 257B streams, flow 0 and flow 1, from the ODU flex, and sends flow 0 and flow 1 to Ethernet node 2.

[0090] Step S2007: Ethernet node 2 receives two 275B code streams, flow 0 and flow 1, and transcodes flow 0 and flow 1 into 66B code streams respectively. Each 275B error code block in flow 0 and flow 1 is converted into four 66B invalid code blocks respectively.

[0091] In step S2008, Ethernet node 2 filters out the 66B invalid code blocks in flow 0 and flow 1 through sequence detection, and then transmits them to the MAC layer.

[0092] Example 3

[0093] Please refer to Figure 7, which is a schematic diagram of an error marking processing method for an 800GE service transmitted to a peer Ethernet node via OTN provided by an embodiment of the present application. OTN node 1 receives two code streams of an 800GE service from Ethernet node 1 through an Ethernet interface, performs the first processing and OTN FEC error marking on the two code streams. The two code streams after error marking are shown as flow 0 and flow 1 in Figure 7. The two code streams are interleaved with the error-marked code streams flow 0 and flow 1 to form one code stream and mapped into the ODUflex. The ODUflex is transmitted to OTN node 2 through the OTN link. OTN node 2 performs a cyclic redundancy check (CRC) on the ODUflex and marks the ODUflex errors in the CRC to obtain ODUflex'. OTN node 2 demaps the ODUflex' into two code streams flow 0' and flow 1'. Flow 0' and flow 1' have both OTN FEC error markings and CRC error markings. Ethernet node 2 receives flow 0' and flow 1' through the OTN interface and performs FEC decoding on flow 0' and flow 1'. During the FEC decoding process, it is found that flow 0' and flow 1' have both OTN FEC error markings and CRC error markings. 1', and Ethernet FEC error marking is performed on flows 0' and 1', resulting in flows 0" and 1". Some OTN FEC error marks in flows 0" and 1" are replaced by Ethernet FEC error marks. In this way, possible error code blocks introduced by the source Ethernet interface, OTN interface, and sink Ethernet interface links are all correctly marked and will not conflict. In other words, even if the error marking function of the OTN link segment is enabled, it will not affect the error code block marking method of the embodiment of the present application, ultimately ensuring the complete error marking function of the entire Ethernet source interface link, OTN link, and Ethernet sink interface link.

[0094] Example 4

[0095] In an optional implementation of transmitting the 1.6TE service to the peer Ethernet node via the OTN provided in the embodiment of the present application, the following steps are included:

[0096] In step S4001, Ethernet node 1 sends a 1.6TE service stream to OTN node 1 through a 1.6TE Ethernet interface. The 800GE service stream is split into four 400G streams that enter OTN node 1. These four streams are designated as flow 0, flow 1, flow 2, and flow 3. Flow 0, flow 1, flow 2, and flow 3 are all 257B streams.

[0097] In step S4002, OTN node 1 performs multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword deinterleaving, and OTN FEC decoding on flows 0, 1, 2, and 3, respectively. Uncorrectable errors occur in flows 0 and 1 during the OTN FEC decoding process, while no uncorrectable errors occur in flows 2 and 3.

[0098] Step S4003: In response to uncorrectable errors occurring in flow 0 during the OTN FEC decoding process, OTN node 1 determines the 275B code blocks in flow 0 that cannot be corrected, transcodes flow 0 into a 66B code stream, replaces the uncorrectable 275B code blocks with the corresponding four 66B invalid code blocks, then transcodes flow 0 into a 275B code stream and replaces every four 66B invalid code blocks in flow 0 with a Type B 275B error code block.

[0099] Step S4004: In response to uncorrectable errors occurring in flow 1 during the OTN FEC decoding process, OTN node 1 determines the 275B code blocks in flow 1 that cannot be corrected, transcodes flow 1 into a 66B code stream, replaces the uncorrectable 275B code blocks with the corresponding four 66B invalid code blocks, then transcodes flow 1 back into a 275B code stream and replaces every four 66B invalid code blocks in flow 1 with type B 275B error code blocks.

[0100] In step S4005, OTN node 1 interweaves flows 0, 1, 2, and 3 into a 275B code stream, performs rate compensation on the interwoven code stream, and maps it into an ODUflex. The ODUflex is then transmitted to OTN node 2 via the OTN link.

[0101] In step S4006, OTN node 2 performs CRC detection on the ODUflex and marks CRC errors for the error code blocks found in the CRC detection. It then demaps the ODUflex into four 257B code streams, flow 0, flow 1, flow 2, and flow 3, and sends flow 0, flow 1, flow 2, and flow 3 to Ethernet node 2.

[0102] In step S4007, Ethernet node 2 receives four 275B code streams (flow 0, flow 1, flow 2, and flow 3) and performs Ethernet FEC decoding and 275B-to-66B transcoding on each of them. During the transcoding process, if uncorrectable errors occur during Ethernet FEC decoding, the relevant 275B code blocks in the code stream are converted into four 66B invalid code blocks. It is worth noting that the 275B code blocks that cannot be corrected during Ethernet FEC decoding may overlap with the 275B code blocks that cannot be corrected during the previous OTN FEC decoding process. Regardless of the 275B code block's uncorrectable errors, it will ultimately be converted into four 66B invalid code blocks and filtered out before entering the MAC layer, ensuring complete error marking for the entire Ethernet source interface link, OTN link, and Ethernet sink interface link.

[0103] It should be noted that although operations are described in a specific order in some embodiments and figures of the present application, this should not be construed as requiring that these operations be performed in the specific order shown or in a serial order, or that all of the operations shown be performed to obtain the desired result. In certain circumstances, multitasking and parallel processing may be advantageous.

[0104] According to the solution of the embodiment of the present application, the problem that the OTN node cannot implement the error marking function for Ethernet services using the 257B reference point can be effectively solved, and the MTTFPA problem can be improved.

[0105] Referring to FIG8 , FIG8 is a schematic diagram of an error code block marking device provided in an embodiment of the present application. As shown in FIG8 , the error code block marking device 200 includes:

[0106] A first processing module 201 is configured to perform a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing at least includes decoding a first forward error correction code (FEC), and the first code stream is a 257B code stream;

[0107] An error marking module 202 is configured to mark n 257B code blocks in the first code stream as errors if an FEC uncorrectable error occurs during the FEC decoding process, thereby obtaining a second code stream, where n is an integer greater than or equal to 1.

[0108] The second processing module 203 is configured to perform a second processing on the second code stream so as to map the second code stream into a signal container of the optical transport network OTN.

[0109] In a possible embodiment, the error marking module 202 specifically includes a code block replacement unit, which is used to: when an FEC uncorrectable error occurs during the FEC decoding process, replace n 257B code blocks in the first code stream with 257B error code blocks to obtain a second code stream.

[0110] In one possible embodiment, the error marking module 202 specifically includes an enabling unit and a code block replacement unit, wherein the enabling unit is used to output an error marking enable signal when an FEC uncorrectable error occurs during the FEC decoding process; the code block replacement unit is used to replace the 257B code block in the first code stream with a 257B error code block within the duration of the error marking enable signal to obtain a second code stream.

[0111] In a possible embodiment, replacing the 257B code block with a 257B error code block specifically includes: replacing the 257B code block with a type A 257B error code block or a type B 257B error code block; wherein, the value of the 0th bit of the type A 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252-bit information; the value of the 0th bit of the type B 257B error code block is 0, the 1st to 8th bits are 0x0E, the 9th to 64th bits are 56-bit information, the 65th to 72nd bits are 0x1E, the 73rd to 128th bits are 56-bit information, the 129th to 136th bits are 0x1E, the 137th to 192th bits are 56-bit information, the 193th to 200th bits are 0x1E, and the 201st to 256th bits are 56-bit information.

[0112] In one possible embodiment, the error marking module 202 specifically includes a 66B transcoding unit, a 275B transcoding unit, and a code block replacement unit. The 66B transcoding unit is configured to perform 257B-to-66B transcoding on the first code stream to obtain a third code stream, wherein the third code stream is a 66B code stream. The code block replacement unit is configured to replace m 66B code blocks in the third code stream with 66B invalid code blocks in response to an FEC uncorrectable error occurring during FEC decoding, thereby obtaining a fourth code stream, wherein m is greater than or equal to 4 and is a multiple of 4. The 275B transcoding unit is configured to perform 66B-to-257B transcoding on the fourth code stream, and replace every four 66B invalid code blocks in the fourth code stream with one 257B error code block, thereby obtaining a second code stream.

[0113] In one possible embodiment, the error marking module 202 specifically includes an enabling unit, a 66B transcoding unit, a 275B transcoding unit, and a code block replacement unit, wherein the 66B transcoding unit is used to perform 257B to 66B transcoding processing on the first code stream to obtain a third code stream, wherein the third code stream is a 66B code stream; the enabling unit is used to output an error marking enable signal when an FEC uncorrectable error occurs during the FEC decoding process; the code block replacement unit is used to replace the 66B code blocks in the third code stream with 66B invalid code blocks within the duration of the error marking enable signal; and the 275B transcoding unit is used to perform 66B to 257B transcoding processing on the third code stream, and replace every four 66B invalid code blocks in the third code stream with one 257B error code block to obtain a second code stream.

[0114] In one possible embodiment, each of the four 66B invalid code blocks in the fourth code stream is replaced with one 257B error code block, specifically including: each of the four 66B invalid code blocks in the fourth code stream is replaced with one A-type 257B error code block or one B-type 257B error code block; wherein the A-type 257B error code block is obtained by converting four 66B error code blocks, the 0th bit of the A-type 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252 bits. Special information: The value of the 0th bit of the B-type 257B error code block is 0, the 1st to 8th bits are 0x0E, the 9th to 64th bits are 56 bits of information, the 65th to 72nd bits are 0x1E, the 73rd to 128th bits are 56 bits of information, the 129th to 136th bits are 0x1E, the 137th to 192th bits are 56 bits of information, the 193th to 200th bits are 0x1E, and the 201st to 256th bits are 56 bits of information.

[0115] In a possible embodiment, the first process further includes one or more of the following processes: multi-channel alignment, alignment marker AM locking, channel de-skew, channel sorting, and FEC codeword de-interleaving.

[0116] In a possible embodiment, the second code stream is subjected to a second processing to map the second code stream into a signal container of an optical transport network (OTN), including: interleaving the second code stream with one or three fifth code streams to obtain a sixth code stream; and performing rate compensation on the sixth code stream and then mapping it into the OTN signal container, wherein both the fifth code stream and the sixth code stream are 257B code streams.

[0117] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0118] Referring to FIG9 , FIG9 is a schematic diagram of an electronic device provided in an embodiment of the present application. The electronic device 900 includes but is not limited to:

[0119] at least one processor 901;

[0120] At least one memory 902, configured to store at least one program;

[0121] When at least one program is executed by at least one processor 901 , the error code block marking method described in any of the above embodiments is executed.

[0122] It should be understood that the processor 901 and the memory 902 may be connected via a bus or other means.

[0123] It should be understood that the processor 901 can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. Alternatively, the processor 901 uses one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0124] Memory 902, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs, such as the error code block marking method described in any embodiment of this application. Processor 901 implements the error code block marking method described above by executing the non-transitory software program and instructions stored in memory 902.

[0125] The memory 902 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store the error code block marking method for executing the above-mentioned method. In addition, the memory 902 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 902 may optionally include a memory remotely arranged relative to the processor 901, and these remote memories may be connected to the processor 901 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0126] The non-transient software programs and instructions required to implement the above-mentioned error code block marking method are stored in the memory 902. When executed by one or more processors 901, the error code block marking method provided by any embodiment of the present application is executed.

[0127] An embodiment of the present application also provides a computer-readable storage medium, which stores a program executable by a processor. When the program executable by the processor is executed by the processor, it is used to implement the error code block marking method described in any of the above embodiments.

[0128] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media.Computer-readable media can be computer-readable signal media or computer-readable storage media.Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or components, or any combination thereof.More specific examples (non-exhaustive list) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0129] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0130] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0131] Computer program code for performing the operations of the present application can be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (such as through the Internet using an Internet service provider).

[0132] The above is a specific description of the implementation of this application, but this application is not limited to the above implementation methods. Technical personnel familiar with this field can also make various equivalent modifications or substitutions under the sharing conditions that do not violate the essence of this application. These equivalent modifications or substitutions are all included in the scope defined by this application.

Claims

1. A method for marking an error code block, comprising: Performing a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing at least includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream; In response to an FEC uncorrectable error occurring during the FEC decoding process, marking n 257B code blocks in the first code stream as errors to obtain a second code stream, where n is an integer greater than or equal to 1; The second code stream is subjected to a second processing so as to map the second code stream into a signal container of an optical transport network OTN.

2. The method according to claim 1, wherein: The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: In response to an FEC uncorrectable error occurring during the FEC decoding process, the n 257B code blocks in the first code stream are replaced with 257B error code blocks to obtain the second code stream.

3. The method according to claim 1, wherein: The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: Outputting an error flag enable signal in response to an FEC uncorrectable error occurring during the FEC decoding process; During the duration of the error mark enable signal, the 257B code blocks in the first code stream are replaced with 257B error code blocks to obtain the second code stream.

4. The method according to claim 2 or 3, wherein: Replacing the 257B code block with a 257B error code block includes: replacing the 257B error code block with an A-type 257B error code block or a B-type 257B error code block; wherein, The value of the 0th bit of the A-type 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252 bits of information; The value of the 0th bit of the B-type 257B error code block is 0, the 1st to 4th bits are all 0, the 5th to 8th bits are 0xE, the 9th to 64th bits are 56 bits of information, the 65th to 72nd bits are 0x1E, the 73rd to 128th bits are 56 bits of information, the 129th to 136th bits are 0x1E, the 137th to 192th bits are 56 bits of information, the 193rd to 200th bits are 0x1E, and the 201st to 256th bits are 56 bits of information.

5. The method according to claim 1, wherein: The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: Performing 257B to 66B transcoding on the first bitstream to obtain a third bitstream, wherein the third bitstream is a 66B bitstream; In response to an FEC uncorrectable error occurring during the FEC decoding process, m of the 66B code blocks in the third code stream are replaced with 66B invalid code blocks to obtain a fourth code stream, wherein m is greater than or equal to 4 and is a multiple of 4; The fourth code stream is transcoded from 66B to 257B, and every four 66B invalid code blocks in the fourth code stream are replaced with one 257B error code block to obtain the second code stream.

6. The method according to claim 1, wherein: The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: Performing 257B to 66B transcoding on the first bitstream to obtain a third bitstream, wherein the third bitstream is a 66B bitstream; Outputting an error flag enable signal in response to an FEC uncorrectable error occurring during the FEC decoding process; During the duration of the error mark enable signal, the 66B code block in the third code stream is replaced with a 66B invalid code block; The third code stream is transcoded from 66B to 257B, and every four 66B invalid code blocks in the third code stream are replaced with one 257B error code block to obtain the second code stream.

7. The method according to claim 5 or 6, wherein: The replacing each of the four 66B invalid code blocks in the fourth code stream with one 257B error code block includes: replacing each of the four 66B invalid code blocks in the fourth code stream with one A-type 257B error code block or one B-type 257B error code block; The A-type 257B error code block is obtained by converting four of the 66B error code blocks, the 0th bit of the A-type 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252 bits of information; The 0th bit of the B-type 257B error code block is 0, the 1st bit to the 4th bit are all 0, the 5th bit to the 8th bit are 0xE, the 9th bit to the 64th bit are 56 bits of information, the 65th bit to the 72nd bit are 0x1E, the 73rd bit to the 128th bit are 56 bits of information, the 129th bit to the 136th bit are 0x1E, the 137th bit to the 192nd bit are 56 bits of information, the 193rd bit to the 200th bit are 0x1E, and the 201st bit to the 256th bit are 56 bits of information.

8. The method according to claim 1, wherein: The first processing also includes one or more of the following processing: multi-channel alignment, alignment marker AM locking, channel de-skew, channel sorting and FEC codeword de-interleaving.

9. The method according to claim 1, wherein: The performing a second processing on the second code stream to map the second code stream to a signal container of an optical transport network OTN includes: Interleaving the second code stream with one or three fifth code streams to obtain one sixth code stream; The sixth code stream is rate compensated and then mapped into the signal container of the OTN, wherein both the fifth code stream and the sixth code stream are 257B code streams.

10. An error code block marking device, comprising: A first processing module, configured to perform a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing at least includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream; an error marking module, configured to mark the n 257B code blocks in the first code stream as errors in response to an FEC uncorrectable error occurring during the FEC decoding process, so as to obtain a second code stream, wherein n is an integer greater than or equal to 1; The second processing module is used to perform second processing on the second code stream to map the second code stream into a signal container of an optical transport network OTN.

11. An electronic device, comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the error code block marking method as described in any one of claims 1-9.

12. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the error code block marking method according to any one of claims 1 to 9 is implemented.

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