Method and apparatus for data check, and device, medium and product

Abstract

The embodiments of the present disclosure relate to a method and apparatus for a data check, and a device, a medium and a product. The method comprises: acquiring N groups of data from a memory, wherein each group of data among the N groups of data comprises a check bit, N being a positive integer greater than or equal to 2. The method further comprises: performing aggregation on the N groups of data to obtain aggregated data, and performing error correction code (ECC) encoding on the aggregated data to obtain encoded data, wherein the aggregated data comprises an aggregated check bit, and the aggregated check bit is an aggregation of the check bits of the N groups of data. The method further comprises: decomposing the encoded data into N groups of encoded data, among which each group of data comprises a check bit, and respectively writing the N groups of encoded data into the memory. Therefore, a plurality of single groups of data, which are read from a memory in unit, are aggregated to obtain a larger encoding unit, such that a memory ECC function with stronger error detection and error correction capabilities can be supported under the same hardware condition.

Description

Method, device, equipment, medium and product for data verification

[0001] This application claims priority to Chinese patent application number 202310792806.8 filed with the China Patent Office on June 29, 2023 and entitled “A method for correcting data errors”, and Chinese patent application number 202311126669.0 filed with the China Patent Office on August 31, 2023 and entitled “Methods, devices, equipment, media and products for data verification”, the entire contents of which are incorporated into this application by reference. Technical Field

[0002] Embodiments of the present application relate to the field of memory technology, and more specifically, to methods, devices, equipment, media, and products for verifying data in a memory. Background Art

[0003] In computationally intensive applications like artificial intelligence (AI), the demand for high-performance, integrated central processing unit (CPU) and graphics processing unit (GPU) computing power has led to the rapid development of high-performance computing (HPC) systems with computing power exceeding exascale (1018 floating-point operations per second). These high-performance systems place high demands on memory bandwidth, which in turn has driven the widespread use of high-bandwidth memory (HBM) in HPC systems.

[0004] HBM is a high-performance dynamic random access memory (DRAM) based on 3D stacking technology. HBM stacks multiple Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM, or DDR for short) chips in three dimensions to create a large-capacity, high-bit-width memory array. HBM supports multi-channel parallel access to the memory, significantly improving read speeds.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a data verification solution.

[0007] In a first aspect, a method for data verification is provided. The method includes: obtaining N groups of data from a memory, each group of the N groups of data including a check bit, wherein N is a positive integer greater than or equal to 2; aggregating the N groups of data to obtain aggregated data, the aggregated data including an aggregated check bit, the aggregated check bit being an aggregation of the check bits of the N groups of data; performing error correction code (ECC) encoding on the aggregated data to obtain coded data; decomposing the coded data into N groups of coded data, each group of the N groups of coded data including a check bit; and writing the N groups of coded data into a memory respectively. Thus, multiple groups of data read from the memory unit can be aggregated to obtain a larger coding unit for ECC encoding. Therefore, under the same hardware conditions such as redundancy ratio, this method can support memory ECC functions with stronger error detection and correction capabilities than traditional technologies, and meet higher error correction and error detection requirements.

[0008] In some embodiments of the first aspect, acquiring N groups of data from the memory includes reading data from N channels or N memory bank groups of the memory, where data from each channel or each memory bank constitutes a group of data. Thus, data serving as coding units can be aggregated from a spatial dimension to obtain larger coding units.

[0009] In some embodiments of the first aspect, acquiring N sets of data from a memory includes reading data from M channels or M memory bank groups of the memory in L time slices, where N=L*M, and where a time slice is the duration of a burst transmission of data read from the memory. Thus, data can be aggregated as encoded data from both temporal and spatial dimensions to obtain a larger encoding unit.

[0010] In some embodiments of the first aspect, performing ECC encoding on the aggregated data includes: determining a method for obtaining N groups of data from a memory according to a preset encoding method; and performing ECC encoding on the aggregated data according to the preset encoding method. This provides a flexible, configurable, and customizable ECC error detection and correction function, which can provide multiple ECC encoding and decoding methods to meet different user needs under the same hardware environment.

[0011] In some embodiments of the first aspect, performing ECC encoding on the aggregated data according to a preset encoding method includes presetting the encoding method based on user input, the input including an ECC performance requirement for a memory, thereby automatically determining an optimal encoding method under hardware conditions based on the ECC performance requirement.

[0012] In some embodiments of the first aspect, the method further includes: in response to the encoding scheme being updated, retrieving data from a memory according to the updated encoding scheme to update a check digit of the retrieved data. In this way, relevant configurations can be dynamically updated as needs change without requiring a reboot, thereby avoiding service interruptions caused by configuration updates.

[0013] In some embodiments of the first aspect, the encoding method includes Reed-Solomon (RS) encoding. RS encoding can detect and correct multi-bit errors, significantly improving the error detection and correction capabilities of the generated ECC code.

[0014] In some embodiments of the first aspect, the method further comprises: determining a corresponding decoding method based on the encoding method; and when reading data from the memory for use, generating error-corrected data bits for the data based on the parity bits of the read data according to the decoding method. Thus, the method can be combined with an ECC encoding process that aggregates multiple sets of data, thereby achieving an ECC function with stronger error detection and correction capabilities and performance compared to traditional methods under the same hardware conditions.

[0015] In some embodiments of the first aspect, the method further includes: determining the number of bits that differ between the corrected data bits and the read data bits; and if the number of bits satisfies a threshold condition, generating a prompt indicating that an error may exist in the corrected data bits. This allows for more cautious error correction results and allows the decision of whether to use risky data to be delegated to upper-layer applications, thereby minimizing the risk of miscorrection while ensuring business continuity.

[0016] In a second aspect, a device for data verification is provided, which includes: an acquisition module, configured to acquire N groups of data from a memory, each group of the N groups of data including a check bit, wherein N is a positive integer greater than or equal to 2; an aggregation module, configured to aggregate the N groups of data to obtain aggregated data, the aggregated data including an aggregated check bit, which is an aggregation of the check bits of the N groups of data; an encoding module, configured to perform error correction code ECC encoding on the aggregated data to obtain encoded data; a decomposition module, configured to decompose the encoded data into N groups of encoded data, each group of the N groups of encoded data including a check bit; and a writing module, which writes the N groups of encoded data into the memory respectively.

[0017] In some embodiments of the second aspect, the acquisition module includes a first reading module, which is configured to read data from N channels or N memory bank groups of the memory, where data in each channel or each memory bank constitutes a group of data.

[0018] In some embodiments of the second aspect, the acquisition module includes a second read module, which is configured to read data from M channels or M memory bank groups of the memory in L time slices, where N=L*M, and the time slice is the duration of a burst transmission of reading data from the memory.

[0019] In some embodiments of the second aspect, the encoding module includes: a determination module, configured to determine a method for obtaining N groups of data from a memory according to a preset encoding method; and an ECC encoding module, configured to perform ECC encoding on the aggregated data according to a preset encoding method.

[0020] In some embodiments of the second aspect, the ECC encoding module includes: pre-setting the encoding method according to user input, where the input includes ECC performance requirements for the memory.

[0021] In some embodiments of the second aspect, the apparatus further includes an updating module configured to: in response to the encoding scheme being updated, obtain data from the memory according to the updated encoding scheme to update a check bit of the obtained data.

[0022] In some embodiments of the second aspect, the encoding scheme includes Reed-Solomon encoding.

[0023] In some embodiments of the second aspect, the device further includes: a decoding method determination module, configured to determine a corresponding decoding method according to an encoding method; and an error correction module, configured to generate error-corrected data bits for the data based on a check bit of the read data according to the decoding method when reading data from the memory for use.

[0024] In some embodiments of the second aspect, the device further includes: a difference bit number determination module, which determines the number of different bits between the error-corrected data bits and the data bits of the read data; and a prompt module, which is configured to generate a prompt when the different number of bits meets a threshold condition, and the prompt indicates that there may be an error in the error-corrected data bits.

[0025] In a third aspect, an electronic device is provided, comprising a processor and a memory, wherein the memory stores computer instructions, and when the computer instructions are executed by the processor, the electronic device performs the actions according to the method of the first aspect or any embodiment thereof.

[0026] In a fourth aspect, a computer-readable storage medium is provided, wherein computer-executable instructions are stored on the computer-readable storage medium, and when executed by an electronic device, the electronic device performs the operation according to the method of the first aspect or any embodiment thereof.

[0027] In a fifth aspect, a computer program product is provided, which is tangibly stored on a computer-readable medium and includes computer-executable instructions that, when executed, implement the operations of the method according to the first aspect or any embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features, advantages and aspects of the embodiments of the present application will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0029] FIG1 is a schematic diagram illustrating an example environment in which various embodiments of the present application can be implemented;

[0030] FIG2 shows a flow chart of an example method for data verification according to some embodiments of the present application;

[0031] FIG3 shows a schematic diagram of a non-limiting example of reading data for aggregation according to some embodiments of the present application;

[0032] FIG4 is a schematic diagram showing a non-limiting example of aggregating multiple groups of data for ECC encoding according to some embodiments of the present application;

[0033] FIG5 is a schematic diagram showing a non-limiting example of decomposing and writing ECC-encoded aggregated data into a memory according to some embodiments of the present application;

[0034] FIG6 shows a flowchart of an example method for performing error detection and correction on data according to some embodiments of the present application;

[0035] FIG7 shows a flowchart of an example method for data verification according to some embodiments of the present application;

[0036] FIG8 shows a schematic block diagram of a message transmission device according to some embodiments of the present application; and

[0037] FIG9 shows a schematic block diagram of an example device that can be used to implement embodiments of the present application. DETAILED DESCRIPTION

[0038] The following describes embodiments of the present application in more detail with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of protection of the present application.

[0039] In the description of the embodiments of this application, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment." The terms "first," "second," etc. can refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0040] HBM, based on 3D stacking technology, provides multi-channel parallel access to memory. HBM is widely used in HPC applications due to the high memory bandwidth requirements of high-computing systems. HBM's structure lacks individual redundant chips, resulting in a lower redundancy ratio than standard DDR. Due to this limited redundancy ratio and other factors, conventional HBM supports relatively simple ECC algorithms and has limited error detection and correction capabilities. For example, for 128 bits of data, 8-bit Hamming code ECC can detect and correct a single bit error. To detect a two-bit error, 9-bit Hamming code ECC is required.

[0041] Some HBM providers provide 16 redundant bits for ECC check bits for 128-bit data. This redundancy ratio supports 8 basic Hamming code check bits and 8 parity bits, where each parity bit is calculated for 16 of the 128-bit data. This method can achieve single-bit error correction, but the error correction requires multiple trial calculations, resulting in significant latency. Furthermore, to implement this method, the memory redundancy ratio must be increased to 8:1, which increases hardware costs. Furthermore, Hamming code-based ECC cannot correct multi-bit errors. If errors occur in more than two bits, missed detection or false correction will still occur, meaning it cannot achieve the multi-bit error correction capability required to cope with hard failures.

[0042] On the other hand, as memory technology advances, the amount of charge stored in a cell decreases, increasing the probability that transient errors may lead to multi-bit errors. Furthermore, the memory design and manufacturing process may also introduce factors that increase the probability of multi-bit errors. Furthermore, the HPC field, where HBM is often used, has very high requirements for data reliability and latency. Therefore, the capabilities and performance of traditional simple HBM encoding methods may not meet application requirements. Furthermore, an increasing number of specialized chips integrate the CPU and HBM memory into a single system-on-chip (SoC). High memory failure rates can directly lead to the return of the entire SoC, resulting in high after-sales costs and service risks. Therefore, improving the ECC error correction and detection capabilities and performance of HBM and other memories within the constraints of limited hardware redundancy and certain latency requirements presents a challenge.

[0043] In order to solve the above problems and other problems, an embodiment of the present disclosure provides a data verification scheme. The scheme aggregates multiple groups of data read from memory units (for example, from dimensions such as space and time) to obtain larger coding units for ECC encoding. Thus, under the same hardware conditions such as redundancy ratio, the scheme can support ECC-related functions for memory with stronger error detection and correction capabilities than traditional technologies, thereby significantly improving the reliability of ECC error detection and correction of memory and reducing uncorrectable errors, meeting higher error correction and error detection requirements. It should be understood that although HBM may be used as an example in the description herein, the scheme according to the embodiment of the present application is also applicable to various other memory forms, such as DDR, mobile DDR, and storage class memory (SCM).

[0044] First, reference is made to FIG1 , which shows a schematic diagram of an example environment 100 in which multiple embodiments of the present application can be implemented. Example environment 100 includes a computing device 110. Computing device 110 includes a processor 120 and a memory 130. Processor 120 may include a CPU, a GPU, various types of dedicated computing units (such as AI chips, etc.), various controllers, or appropriate combinations of the foregoing items. Processor 120 can perform various processing actions according to computer program instructions stored in or loaded into memory 130.

[0045] The memory 130 may be a random access memory (RAM), such as a dynamic random access memory (DRAM), which can support fast random reads and writes from the processor 120, thereby directly supporting the calculations of the processor 120. That is, given a random address in the memory 130, the processor 120 can quickly read data from or write data to that address. Therefore, when the processor 120 executes a process, it can read data required for execution (such as instructions and / or calculation parameters) from the memory 130 and write data (such as calculation output) to the memory 130.

[0046] The computing device 110 also includes (a plurality of) memory controllers 140 as part of the processor 120. The memory controller 140 is a component of the computing device 110 that controls and manages data transfer between a computing unit such as a CPU or GPU and the memory 130. The processor 120 reads and writes data from the memory 130 via the memory controller 140. Each memory controller 140 can be implemented as a separate chip or integrated into another larger chip, such as a controller built into a CPU or a north bridge.

[0047] In some embodiments of the present disclosure, data can be transmitted between the processor 120 and the memory 130 in a burst transmission manner. The burst transmission has a certain burst length. During the duration of a burst transmission (hereinafter also referred to as a data cycle), the memory controller 140 can continuously read / write a number of consecutive storage units equal to the burst length according to a specified starting address without continuously providing addresses. As a non-limiting example, when a unit burst length is capable of reading 64 bits of data from the memory 130 via a single channel, during a data cycle with a burst length equal to 2, the processor 120 can read 128 bits of data from the storage area via a single channel.

[0048] In some embodiments, multiple parallel communication channels exist between the memory 130 and the memory controller 140, enabling the processor 120 to read / write data simultaneously via the multiple channels in parallel. For example, the memory 130 may include multiple bank groups, each of which can be independently read and written, enabling data to be read / written from multiple bank groups simultaneously. For example, the memory 130 may be an HBM based on 3D stacking technology, in which multiple bank groups are stacked together in a three-dimensional manner.

[0049] In some such embodiments, there may be multiple memory controllers 140, each of which controls data transmission for a portion of the memory bank groups and can read data from the multiple memory bank groups in parallel via multiple channels. In some such embodiments, the memory 130 also supports virtual channels. Virtual channel technology can split each physical channel into multiple virtual channels, so that the number of single data that can be transmitted in parallel between the processor 120 and the memory 130 is greater than the number of physical channels. The embodiments of the present application are not limited to a specific number of memory controllers, memory bank groups, or channels / virtual channels.

[0050] In an embodiment of the present application, the memory 130 supports an error-correcting code (ECC) check function. In this case, for a group of data bits to be written to the memory 130, the processor 120 can, for example, use the memory controller 140 to calculate the corresponding ECC. When the group of data bits is written to the memory 130, the calculated ECC is also written to the memory 130 as a check bit. Later, when the group of data bits is read back for use by the processor 120, the corresponding check bit is also read.

[0051] The memory controller 140 then recalculates the ECC for the read data bits and compares it with the ECC in the read check bits. If the two do not match, the memory controller 140 can determine that there is an error in the read data bits. In this case, the memory controller 140 can perform further error correction decoding on the data bits to determine which one or more bits are incorrect. The erroneous bits are then corrected. For binary data bits, this correction may mean flipping the erroneous bit. Correcting the data enables the processor 120 to correctly execute subsequent tasks, thereby ensuring the normal operation of the computing device 110.

[0052] To achieve this functionality, the memory 130 may optionally include a data portion 150 specifically storing actual data bits and a check portion 160 storing check bits. The processor 120 may write the check bits of the data bits into the check portion 160 based on corresponding read and write specifications. It should be understood that the data portion 150 and the check portion 160 are shown only as examples. In some embodiments, the memory 130 may not have a separate cell storing the check bits. The memory 130 may also store the data bits and corresponding check bits in other appropriate structures.

[0053] In addition, the processor 120 includes a paired ECC encoding circuit and decoding circuit (not shown), for example, in the memory controller 140 or in another part thereof. A pair of encoding circuits can implement the encoding and decoding functions of a specific ECC algorithm, for example, a Hamming code algorithm, a Reed-Solomon encoding algorithm, etc. The encoding circuit can be used to calculate the ECC of the data bits. The decoding circuit can decode the calculated ECC to determine the error bits in the corresponding data bits and correct them. In some embodiments, the memory controller 140 may include multiple pairs of encoding circuits and decoding circuits, and switch between different circuits according to the system settings to perform the ECC function using different algorithms.

[0054] The data unit targeted by ECC encoding is called a codeword. Each codeword consists of actual data bits and redundant check bits, including ECC. To achieve a certain error correction capability, the number of check bits must meet certain requirements, which are generally limited by the achievable hardware redundancy ratio between the capacity of the data portion 150 and the check portion 160. Taking the ECC function of basic Hamming code with a hardware redundancy ratio of 16:1 as an example, for a codeword consisting of 128 data bits, a maximum of 8 additional check bits can support the detection and correction of a single-bit error. If reliable detection of two-bit errors is required, the redundancy ratio must be increased. If two-bit errors are to be detected and one-bit errors corrected, 9 bits of ECC are required for 128 bits of data. In this case, a higher hardware redundancy ratio can be provided, namely, the capacity of the check portion 160 can be increased while the capacity of the data portion 150 remains unchanged. This approach will increase hardware costs. To avoid increasing hardware costs, the size of the coding unit must be increased. For example, the processor 120 can increase the size of the coding unit according to the methods of the embodiments of the present application, as described in detail below.

[0055] It should be understood that the architecture and functions in the example environment 100 are described only for illustrative purposes and do not imply any limitation on the scope of the present application. In addition, other devices, systems or components not shown may also exist in the example environment 100. In addition, the embodiments of the present application may also be applied to other environments with different and / or other functions. For example, in some high-performance computing systems, the processor 120 and the memory 130 may be packaged in the same SoC. For example, the read, write and data verification actions for the memory 130 may also be performed by the base die. The embodiments of the present application will be generally described below in the context of the computing device 110 utilizing the processor 120 to perform actions.

[0056] Reference is now made to FIG2 , which illustrates a flow chart of an example method 200 for data verification according to some embodiments of the present application. Example method 200 may be performed, for example, by computing device 110 as shown in FIG1 . It should be understood that method 200 may also include additional actions not shown, and the scope of the present application is not limited in this respect. Method 200 is described in detail below in conjunction with example environment 100 of FIG1 .

[0057] At 210, N sets of data are retrieved from a memory, each of which includes a check bit. N is an integer greater than or equal to 2. For example, the computing device 110 may read N sets of data from the memory 130 to the processor 120 via the memory controller 140, each of which includes actual data bits and a check bit. The check bit may be used to store an ECC check code for the data bits. At this point, the check bit may be empty or may need to be updated.

[0058] In some embodiments, the processor 120 can read N sets of data in parallel from N memory bank groups or N channels of the memory 130. In some embodiments, the N channels can be virtual channels. The N sets of data read in parallel can be aggregated for encoding as described below. Compared with performing ECC encoding on a single set of data obtained from each channel, this reading method can obtain a larger number of encoding units without increasing latency.

[0059] In some embodiments, the processor 120 can read N sets of data from M channels or M memory bank groups of the memory in L time slices, where L and M are integers, and N = L*M. Each of the L time slices is the duration of a burst transfer of data from the memory. As known to those skilled in the art, this burst transfer has a certain burst length. When the hardware capabilities and burst length are determined, the duration of a burst transfer can be used as a unit time for configuration. An example of reading data from multiple channels and / or multiple time slices for ECC encoding will be described in more detail below in conjunction with FIG.

[0060] Continuing with reference to FIG2 , at 220 , the N sets of data are aggregated to obtain aggregated data, where the aggregated data includes an aggregated check bit, where the aggregated check bit is an aggregate of the check bits of the N sets of data. For example, the processor 120 may aggregate the N sets of data obtained at 210 to obtain aggregated data, where the aggregated data includes an aggregated check bit that aggregates the check bits of the N sets of data.

[0061] In some embodiments, the processor 120 may concatenate the data bits of N groups of data and the parity bits of N groups of data to obtain aggregated data. It should be understood that such aggregation may be logical aggregation, as long as the processor 120 is able to know which bits in the aggregated data are data bits and which bits are parity bits.

[0062] At 230, ECC encoding is performed on the aggregated data to obtain encoded data. For example, processor 120 may perform ECC encoding on the aggregated data obtained at 220 to obtain encoded data. In some embodiments, the ECC encoding may be Hamming code or its variants. For example, processor 120 may calculate a Hamming code for the aggregated data, calculate a parity check bit for each of multiple segments of the aggregated data, and use both as part of the check bits of the encoded data. In some embodiments, the ECC encoding may be Reed-Solomon code, which has stronger error correction and detection capabilities. An example of ECC encoding for aggregating N groups of data will be described in more detail below in conjunction with FIG. 4 .

[0063] Continuing with FIG2 , at 240 , the coded data is decomposed into N groups of coded data, each of which includes a check digit. For example, the processor 120 may decompose the coded data obtained at 230 into N groups of coded data, each of which includes a check digit. Similarly, this decomposition may be a logical decomposition, as long as the processor 120 is able to correctly process (e.g., transmit) the N groups of coded data in groups.

[0064] At 250, N groups of coded data are written to the memory separately. For example, the processor 120 may write the N groups of coded data decomposed at 240 to the memory 130 separately. The processor 120 may write data to the memory 130 in a manner corresponding to the manner in which the data is read from the memory 130 at 210. In some embodiments, the processor 120 may write the N groups of data to N memory bank groups or N channels (or virtual channels) in parallel. In some embodiments, the processor 120 may write the N groups of data to M channels or M memory bank groups in L time slices, where L and M are integers and N=L*M. An example of decomposing coded data will be described in more detail below in conjunction with FIG. 5 .

[0065] Using method 200, multiple single groups of data read from the memory unit are aggregated from dimensions such as space and time, and a larger coding unit can be obtained for ECC encoding. Thus, under the same hardware conditions, method 200 can support memory ECC functions with stronger error detection and correction capabilities (such as RS encoding, which is more powerful than Hamming code) compared to traditional methods, thereby significantly improving the reliability of memory ECC error detection and correction functions and reducing the occurrence of uncorrectable errors (UCE). In addition, method 200 can also meet the increased demand for memory ECC error correction and error detection by aggregating data without changing hardware characteristics such as hardware redundancy ratio after the error correction and error detection requirements of memory ECC increase.

[0066] Reference is now made to FIG3 , which illustrates a non-limiting example diagram 300 of reading data for aggregation according to some embodiments of the present application. Diagram 300 shows a processor 310 in communication with an HBM 320 supporting multiple channels. Processor 310 and HBM 320 may be example implementations of processor 120 and memory 130, respectively, in FIG1 , and the actions described in FIG3 may be example implementations of action 210 in method 200 of FIG2 .

[0067] In schematic 300, processor 310 reads data in parallel via multiple controllers 330-1 through 330-I (individually or collectively referred to as controllers 330). For illustration purposes, controller 330-1 is used as an example, capable of controlling data transmissions in channels 340-1 and 340-2. During each data cycle of a burst transmission, controller 330-1 can read a set of unit data from each of channels 340-1 and 340-2 into its own buffer. The duration of a data cycle depends on the burst length of the burst transmission and the hardware conditions of the relevant components. Therefore, this set of unit data can be considered as data read in a unit time slice.

[0068] As shown in the figure, in the first time slice, controller 330-1 can read data 311 from channel 340-1 and data 312 from channel 340-2. In the second time slice, controller 330-1 can read data 313 from channel 340-1 and data 314 from channel 340-2. Each set of data 311 to 314 includes a check bit in addition to the actual data bits. It should be understood that, depending on the scenario, the check bit can be a null value reserved for later writing to HBM 320.

[0069] Traditionally, the controller 330-1 can treat each piece of data as a codeword to calculate the check bit separately, then for the 128+8-bit example codeword, Hamming code encoding for detecting and correcting single-bit errors can be used. However, in the example of Figure 3, the controller 330-1 can aggregate the data 311 to 314 into a longer codeword for ECC encoding. Thus, in this example, the longer codeword includes 32 check bits, thereby being able to support 4 RS8 redundant encodings. RS encoding is widely used on DDR4 and DDR5. It is a symbol-based algorithm that can be used to correct errors in one or more symbols, each symbol can be 8 bits, for example.

[0070] According to the Reed-Solomon theorem, using RS8 redundant coding based on finite field arithmetic to calculate these 32-bit parity bits can correct errors in up to two random RS symbols, meaning it can correct 16-bit errors. This covers more error-prone failure modes. This significantly improves the memory's error detection and correction capabilities and reduces the occurrence of UCE.

[0071] In this non-limiting example, processor 310 aggregates data based on the data read in parallel by each controller 330. It should be understood that this is for illustrative purposes only. In some embodiments, a computing device (e.g., computing device 110) may determine how to retrieve N sets of data from memory for aggregation based on a pre-set encoding method. For example, the number of channels that should be used to read data in parallel and / or the number of time slices over which data read should be aggregated may be pre-set.

[0072] In some embodiments, the computing device can set the configuration information of the encoding method based on parameter values ​​input by the user (e.g., the number of channels and the number of time slices). In some such embodiments, the input includes ECC performance requirements for the memory. For example, the correctable rate, expected error correction delay, and expected missed detection rate. The computing device can then adapt the configuration parameters of the encoding method based on these performance requirements and the hardware conditions of the memory 130.

[0073] Reference is now made to FIG. 4 , which illustrates a non-limiting example of aggregating multiple sets of data for ECC encoding according to some embodiments of the present application. FIG. 400 illustrates multiple sets of data 411 to 414 read in multiple time slices and / or from multiple channels. The actions depicted in FIG. 4 may be example implementations of actions 220 and 230 in method 200 of FIG. 2 , and multiple sets of data 411 to 414 may be examples of data 311 to 314 read from HBM 320 in the example of FIG. 3 . For illustrative purposes, FIG. 4 will be described below in the context of actions performed by processor 310 in FIG. 3 .

[0074] As shown in FIG4 , each set of data 411 to 414 includes a set of data bits and a set of check bits, such as data bit 425 and check bit 435 of data 411. In some embodiments, the check bits may be left blank. In some embodiments, the check bits may be placeholders added by the processor based on the hardware redundancy ratio of the memory.

[0075] Instead of calculating the value of the check bit separately for each set of data, processor 310 can aggregate data 411 to 414 before performing the calculation. In the example of FIG4 , to aggregate the data, processor 310 concatenates the data bits of data 411 to 414 together to form a collection of data bits 445, and concatenates the check bits of data 411 to 414 together to form a collection of check bits 455. Furthermore, collection of data bits 445 and collection of check bits 455 are aggregated (in this example, concatenated) to form final aggregated data 465. Aggregated data 455 includes aggregated data bits 475 and aggregated check bits 485.

[0076] Then, the processor 310 can perform ECC encoding on the aggregated data 465 to obtain encoded data. Specifically, the processor 310 can calculate the value of the check bit of the aggregated data 465 according to a pre-set ECC encoding method, and put it into the aggregate check bit 485. In some embodiments, the processor 310 can perform ECC encoding on the aggregated data 465 according to a pre-set encoding method. For example, the processor 310 can configure its ECC encoding circuit according to the parameters in the encoding setting to perform ECC encoding for the aggregated data. In some embodiments, the encoding method can be RS encoding with specific parameters, which specify various properties of the RS encoding algorithm and codewords. In some embodiments, the processor 310 may include multiple ECC encoding circuits. According to the pre-set encoding method, the processor 310 can switch to the corresponding encoding circuit and configure the encoding circuit according to the set parameters to perform ECC encoding for the aggregated data.

[0077] Reference is now made to FIG5 , which illustrates a non-limiting example of decomposing and writing ECC-encoded aggregated data to a memory according to some embodiments of the present application. The actions described in FIG5 may be an example implementation of actions 240 and 250 in method 200 of FIG2 , and aggregated data 565 may be an example of aggregated data 465 in the example of FIG4 . For ease of explanation, FIG5 will be described below in the context of actions performed by processor 310 in FIG3 .

[0078] After performing ECC encoding on the aggregated data 565, the processor 310 also needs to write the data bits and parity bits of the encoded aggregated data 565 to the corresponding addresses. Therefore, the processor 310 can perform the reverse process of the above aggregation process and rewrite the encoded data (e.g., via the controller 330) to the HBM 320 in a manner similar to reading N groups of data from the HBM.

[0079] As shown in FIG5 , aggregated data 565 can be aggregated from multiple sets of data (e.g., data 411 to 414 in FIG4 ), with data bits 575 comprising multiple portions from the multiple sets of data, such as portion 545. Furthermore, the number of check bits 585 of aggregated data 565 is also equal to the number of the multiple sets of check bits from the multiple sets of data. After the processor has ECC-encoded aggregated data 565 as a long codeword, check bits 585 comprise the ECC values ​​calculated for data bits 575. Check bits 575 can be considered to comprise multiple portions, such as 555, corresponding to the check bits of each set of data from the multiple sets of data.

[0080] Based on this, the processor 310 can re-decompose the data bits 575 into multiple groups of data bits and decompose the check bits 585 into multiple groups of check bits. The processor 310 can then combine each group of data bits in the multiple groups of data bits with the corresponding check bits to re-obtain multiple groups of data, in this example, data 511 to 514. Each group of data 511 to 514 has the same structure as the multiple groups of data previously obtained by the processor 310 and includes a portion of the calculated check bits 585.

[0081] In this way, processor 310 can rewrite N sets of data into HBM 320 according to the corresponding read and write specifications, similar to the previous method of reading multiple sets of data. Taking Figure 3 as an example, as shown in the figure, controller 330-1 of processor 310 can write data 511 to 514 into HBM 320 in parallel via channel 340-1 and channel 340-2 in two time slices.

[0082] It should be understood that the data structures of the aggregation and decomposition described in Figures 4 and 5 are only logical examples. Various implementation variations that meet such logical structures also fall within the scope of the present application, as long as the processor can correctly operate and transmit the corresponding bits of data. It should also be understood that the number of controllers, time slices, and channels shown in Figures 3 to 5 are only examples, and they can be determined based on the input parameters and / or performance requirements for the coding configuration as described above, and the coding configuration can be changed. The example of the ECC coding configuration being changed will be described in more detail below in conjunction with Figure 7.

[0083] After the data in the memory is ECC encoded, when the processor 120 subsequently needs to obtain the ECC-encoded data for use (for example, by an application process running on the processor 120), it can use the check bits of the encoded data to detect whether an error occurred in the actual data bits of the encoded data when being written and correct the error. Now refer to Figure 6, which shows a flowchart of an example method 600 for error detection and correction of data according to some embodiments of the present application. The example method 600 can be performed, for example, by the computing device 110 as shown in Figure 1. It should be understood that the method 600 may also include additional actions not shown, and some actions in the method 600 may be omitted, and the scope of the present application is not limited in this respect. The method 600 is described in detail below in conjunction with the example environment 100 of Figure 1.

[0084] At 610, for example, based on instructions from an application program, the processor 120 may read a corresponding amount of encoded data from the memory 130 into a cache line thereof, such as a cache line of the controller 140. The encoded data includes data bits to be used by the program and corresponding check bits. When these data bits were previously written, the check bits may be generated by the processor 120 based on the method of an embodiment of the present application (e.g., the method described with respect to FIG. 2 to FIG. 5 ).

[0085] Based on the currently configured ECC encoding mode, the processor 120 can determine the corresponding decoding mode. For example, when the computing device 110 is started, the processor 120 can configure the corresponding ECC encoding and decoding path based on the current ECC encoding configuration information. The processor 120 can then read the amount of encoded data suitable for the current decoding mode to perform decoding based on the decoding mode. For example, the processor 120 can read multiple sets of encoded data from (multiple) channels and / or (multiple) time slices in a manner similar to the above-mentioned acquisition of multiple sets of data to combine into codewords suitable for the current decoding mode.

[0086] The processor 120 may perform error detection on the encoded data read and, if necessary, attempt to generate error-corrected data bits for the data based on the read check bits. Specifically, at 615, the processor 120 may generate check bits for the data bits of the encoded data read based on the current decoding method. Then, at 620, the processor 120 may compare the check bits generated at 615 with the check bits of the encoded data read at 610 to determine whether the two sets of check bits match.

[0087] If the two sets of check bits match, processor 120 can determine that the data bits of the encoded data read are consistent with when these data bits were written, that is, there are no errors in these data bits. In this case, method 600 can proceed to 625, where the tested data is provided to the application process for further use. Then, method 600 can return to 610, where processor 120 can read the next batch of data of the decoding unit size and its check bits.

[0088] If the two sets of parity bits do not match, processor 120 may determine that an error exists in the data bits. In this case, processor 120 may attempt to perform error correction on the data bits to correct the erroneous bits. Therefore, method 600 proceeds to 630, where processor 120 may decode the read parity bits according to the currently active ECC decoding path (e.g., the RS decoding circuit path). This decoding process is intended to determine the location of the erroneous bits in the corresponding data bits for correction.

[0089] Different ECC algorithms with different parameters have different error correction capabilities. In some cases, data errors may be uncorrectable, i.e., there is an Uncorrected Corruption (UCE) in the data. If processor 120 detects an UCE at 635, method 600 proceeds to 640, where processor 120 may trigger an UCE interrupt. If no UCE is detected, method 600 proceeds to 645, where processor 120 may generate an error correction result. In other words, processor 120 may correct the errors in the detected data bits based on the results of decoding the check bits to generate error-corrected data bits. For a binary erroneous data bit in the data bits, this may mean a reversal of the value.

[0090] As mentioned above, a specific ECC decoding method has a certain error detection and correction capability. When the number of errors in the data bits it detects exceeds its capability, not only will ECC errors occur, but miscorrections may also occur. In other words, using the current decoding method to perform ECC decoding on the check code may produce a certain result, but in fact, this result may contain errors.

[0091] In some cases, method 600 may further test the reliability of the error-corrected data. At 650, processor 120 may determine whether to perform a reliability test on the error-corrected data. For example, processor 120 may enable or disable this feature based on a pre-configured configuration, thereby implementing two different error correction modes. If reliability testing is determined not to be performed, method 600 proceeds to 655, where processor 120 may provide the error-corrected data to the application process for further use. At 655, processor 120 may also record a relevant error correction log. Method 600 may then return to 610.

[0092] If a reliability check is determined, method 600 proceeds to 660, where processor 120 may determine the difference between the error-corrected data bits generated at 645 and the read data bits. In some embodiments, processor 120 may determine the number of bits that differ between the error-corrected data bits and the read data bits. In some embodiments, processor 120 may also determine the distribution of these differing bits among the data bits. Then, at 665, processor 120 may determine whether the difference satisfies a threshold condition.

[0093] In some embodiments, processor 120 may determine that the number of bits that differ between the error-corrected data bits and the data bits of the read data exceeds a threshold. The threshold is associated with the maximum number of bits that can be corrected by the ECC encoding and decoding method used in a group of data bits. For example, if an ECC method that can detect at most one bit of data generates a correction result that corrects two bits, then the result meets the threshold condition, i.e., the correction result may include an error.

[0094] In some embodiments, the threshold condition is also related to the distribution of erroneous bits. For example, if the ECC method can reliably detect j consecutive bit errors, but if the erroneous bits are discontinuous, it can only reliably detect k fewer bit errors. If the error-corrected data bits correct i discontinuous bit errors, processor 120 may still determine that the result meets the threshold condition.

[0095] If the difference does not meet the threshold condition, the method proceeds to 655. If the difference does meet the threshold condition, the method proceeds to 670, where the processor 120 may generate a hint indicating that an error may exist in the error-corrected data bit. Then, at 675, the processor 120 may provide the error-corrected data along with the hint (e.g., as an additional marker) to the application process for use. The processor 120 may also record the relevant error correction log for tracking and analysis. Then, the method 600 may return to 610.

[0096] In this way, more cautious error correction results can be provided to upper-level applications, and the decision of whether to use risky data can be handed over to upper-level applications, thereby taking into account the risk of miscorrection while also ensuring the continuous operation of the business as much as possible. For example, when the data is an image to be displayed by an application, errors involving several pixels may not affect the display. Therefore, the application can choose to use the data. As another example, when the application has high requirements for data correctness, it can discard the error-corrected data that is marked as possibly erroneous. In other embodiments of the present application, for example, in a security server where the correctness of the data is very important, in order to ensure the reliability of the data as much as possible, after determining that there may be an error in the error-corrected data bit, instead of generating a prompt at 670, the processor 120 can trigger an interrupt.

[0097] Method 600 can be used in conjunction with the ECC encoding process described above with reference to Figures 2 to 5 , thereby achieving ECC functionality with enhanced error detection and correction performance compared to conventional methods under the same hardware conditions. Furthermore, the aforementioned process for detecting and indicating the reliability of error-corrected data can also be used independently with other ECC decoding processes to provide the aforementioned related benefits.

[0098] As previously described, computing device 110 can read data and perform ECC functions on the data according to pre-set encoding schemes. Furthermore, these encoding schemes can be updated due to changes in ECC requirements for computing device 110. In some embodiments, encoding scheme updates can occur during system operation, and the update takes effect without requiring a system restart.

[0099] The setting and updating of the encoding scheme will now be described with reference to FIG7 . FIG7 illustrates a flow chart of an example method 700 for data verification according to some embodiments of the present application, wherein the ECC encoding configuration used for data verification is updated during system operation. Example method 700 can be executed, for example, by computing device 110 as shown in FIG1 . It should be understood that method 700 may also include additional actions not shown, and some actions in method 700 may be omitted, and the scope of the present application is not limited in this respect. Method 700 is described in detail below in conjunction with example environment 100 of FIG1 .

[0100] Method 700 begins when the system on computing device 110 is booted at 710. Here, computing device 110 may configure components that perform ECC encoding and decoding based on a pre-set encoding scheme to initialize ECC error correction and detection functions. For example, computing device 110 may perform configuration based on a configuration file that stores parameters related to the encoding scheme. These parameters may have default values ​​that have not been changed or restored, or values ​​previously entered by a user.

[0101] In some embodiments, the configuration parameters may include the number of channels that should be used to read data in parallel and / or the number of time slices over which the data should be aggregated. For example, the computing device 110 may configure its ECC encoding function to encode N groups of data read in parallel from M channels or M memory bank groups over L time slices, as described above with respect to method 200.

[0102] In some embodiments, for example, as part of processor 120, computing device 110 may include multiple ECC encoding circuits and corresponding decoding circuits, such as circuits implementing a Hamming code algorithm and circuits implementing a RS algorithm. Based on the encoding algorithm specified in the configuration file, computing device 110 may enable and configure the corresponding circuits to perform ECC-related functions.

[0103] It should be understood that in addition to the configurations affecting the encoding method described above, the computing device 110 may also perform other ECC-related configurations. For example, based on requirements such as the missed detection rate for ECC decoding, the computing device 110 may include a function for enabling or disabling reliability testing of error-corrected data after it is generated, as described in detail above with respect to method 600.

[0104] At 720, the processor 120 of the computing device 110 begins running various system and application processes and continuously communicates with the memory 130 to read and write data, etc. During this period, the configured ECC-related functions are utilized. The processor 120 (for example, in its internal buffer) can perform ECC encoding on the data to be written to the memory 130 and write the data bits of the data together with the calculated check bits to the memory 130 according to the corresponding read and write specifications. Furthermore, when reading the encoded data for use, the processor 120 can utilize the configured ECC-related functions to read the data bits and corresponding check bits of the data for decoding, thereby performing ECC error correction and error detection on the data.

[0105] Computing device 110 can perform ECC encoding and corresponding ECC decoding on the aggregated long codewords based on the configured ECC error correction and detection functions, according to the method actions described above with respect to Figures 2 to 6, which will not be further described here. Depending on the implementation, this process can be performed by memory controller 140 or another component of the processor. Although not shown in Figure 7, if a UCE is detected during the decoding process, computing device 110 performs relevant error handling actions, such as triggering an interrupt.

[0106] During system operation, at 730, the computing device 110 may receive an update indication for the ECC encoding method, for example, via a user interface. The update indication may include update information for one or more parameters, such as the number of channels for reading the data to be aggregated in parallel, the number of time slices for reading the data to be aggregated, and the encoding algorithm. In response to receiving the update indication, at 740, the computing device 110 may configure the relevant components according to the update to switch to the new encoding method. For example, the computing device 110 may switch the encoding circuit to another encoding circuit, and correspondingly switch the decoding circuit to a decoding circuit paired with the other encoding circuit. After switching to the new encoding method, the processor 120 of the computing device 110 may perform subsequent ECC encoding and decoding actions according to the new encoding method.

[0107] When the encoding scheme is updated during system operation, after the update, data encoded with parity bits using the scheme before the update may exist in memory 130. If processor 120 accesses this data for error detection and correction, it will use the updated decoding scheme to perform these operations. This may produce erroneous results or no results at all. To address this issue, at 750, computing device 110 may cause processor 120 to update the parity bits of the encoded data in memory 130 using the updated encoding scheme.

[0108] To this end, the processor 120 can read the encoded data from the memory 130 into its buffer according to the updated encoding method to update the check bits of the data. According to the ECC encoding process described above, the processor 120 can use the number of channels and time slices indicated in the updated configuration to read and aggregate the long codeword for ECC encoding, and use the updated encoding method to calculate the check bits of the long codeword. The processor 120 can then write the data bits and check bits of the long codeword back to the corresponding addresses, thereby leaving the data bits unchanged and overwriting the previous check bits. The processor 120 can continue to read and aggregate the next long codeword to update the check bits until the required update is completed.

[0109] Method 700 provides customizable ECC error detection and correction functions that are flexibly configurable in multiple dimensions, such as space, time, and encoding algorithms. In this way, multiple ECC encoding and decoding methods that meet different user needs can be provided under the same hardware environment. Moreover, the relevant configuration can be dynamically updated without restarting as demand changes, thereby avoiding business interruptions caused by updating ECC-related function configurations. This method can be used, for example, for operational configuration optimization in data centers. Multiple ECC-related function configurations can be adopted and tested for a period of time to clarify the most important memory failure modes and determine the optimal configuration parameters.

[0110] As described above, given the hardware limitations of a memory system (e.g., the supported redundancy ratio of data bits to check bits, etc.), users can configure ECC-related functions based on the memory error detection and correction requirements of their application scenarios. In some embodiments, users can directly enter parameter values ​​to configure parameters based on their needs.

[0111] For example, when the processor 120 includes multiple pairs of encoding and decoding circuits, for scenarios requiring 1-bit error correction, the user can configure the encoding algorithm to a Hamming code encoding algorithm for cost considerations. For example, for higher error detection requirements, the user can configure the encoding algorithm to a more capable RS encoding algorithm and encode on the basis of aggregated long codewords to achieve error correction capabilities for multiple consecutive symbols. As another non-limiting example, the user can enter a configuration value to specify RS8 encoding based on the aggregation of two time slice data read in parallel from two channels. However, if less latency is to be achieved without changing the encoding algorithm, the user can modify the configuration to aggregate the data of one time slice read in parallel from four channels for RS8 encoding.

[0112] In other embodiments, instead of directly inputting parameter values, the user input may include ECC performance requirements for the memory 130. The computing device 110 may automatically adapt the parameters of the encoding method that can meet the performance requirements and comply with hardware and other limitations based on these ECC performance requirements and the hardware limitations of the memory 130, and use these parameters to set or update ECC-related functional configurations. In some embodiments, these performance requirements may include the expected delay caused by ECC error correction, and the expected reliability indicators of the corresponding data using the generated verification data, such as the expected missed detection rate or the false correction rate. In some embodiments, the hardware limitations of the memory 130 may include the redundancy ratio between the capacity of the memory 130 used to store original data and the capacity used to store verification data.

[0113] In some embodiments, the computing device 110 can provide a plurality of preset parameter combinations, as well as mapping rules from corresponding requirements to these plurality of parameter combinations. In this way, the computing device 110 can provide corresponding parameter combinations based on the mapping rules to configure ECC-related functions. In some embodiments, the computing device 110 can implement a configuration planning function. This function takes performance requirements and constraints as input and outputs optimal configuration parameters for extreme reliability that meet various constraints, such as the number of channels and time slices on which the aggregated data is based and the ECC encoding algorithm to be used. The optimal configuration parameters can then be used to configure ECC-related functions.

[0114] FIG8 shows a schematic block diagram of a data verification apparatus 800 according to some embodiments of the present application. Apparatus 800 may be implemented as or included in computing device 110 of FIG1 . Apparatus 800 may include multiple modules for performing corresponding actions in, for example, methods 200, 600, and 700.

[0115] As shown in the figure, the device 800 includes the following modules: an acquisition module 810, configured to acquire N groups of data from a memory, each group of data in the N groups of data includes a check bit, where N is a positive integer greater than or equal to 2; an aggregation module 820, configured to aggregate the N groups of data to obtain aggregated data, the aggregated data including an aggregated check bit, which is an aggregation of the check bits of the N groups of data; an encoding module 830, configured to perform error correction code ECC encoding on the aggregated data to obtain encoded data; a decomposition module 840, configured to decompose the encoded data into N groups of encoded data, each group of encoded data in the N groups of encoded data including a check bit; and a writing module 850, configured to write the N groups of encoded data into the memory respectively.

[0116] In some embodiments, the acquisition module 810 includes a first reading module configured to read data from N channels or N memory bank groups of the memory, wherein data of each channel or each memory bank constitutes a group of data.

[0117] In some embodiments, the acquisition module 810 includes a second read module, which is configured to read data from M channels or M storage memory groups of the memory in L time slices, where N=L*M, and the time slice is the duration of a burst transmission of reading data from the memory.

[0118] In some embodiments, the encoding module 830 includes: a determination module configured to determine a method for obtaining N groups of data from a memory according to a preset encoding method; and an ECC encoding module configured to perform ECC encoding on the aggregated data according to a preset encoding method.

[0119] In some embodiments, the ECC encoding module includes: presetting the encoding method according to user input, where the input includes ECC performance requirements for the memory.

[0120] In some embodiments, the apparatus 800 further includes an updating module, where the updating module is configured to: in response to the encoding method being updated, obtain data from the memory according to the updated encoding method to update the check bit of the obtained data.

[0121] In some embodiments, the encoding scheme includes Reed-Solomon encoding.

[0122] In some embodiments, the device 800 also includes: a decoding method determination module, configured to determine a corresponding decoding method according to an encoding method; and an error correction module, configured to generate error-corrected data bits for the data based on the check bits of the read data according to the decoding method when reading data from the memory for use.

[0123] In some embodiments, the device 800 also includes: a difference bit number determination module, which determines the number of different bits between the corrected data bits and the data bits of the read data; and a prompt module, which is configured to generate a prompt when the different number of bits meets a threshold condition, and the prompt indicates that there may be an error in the corrected data bits.

[0124] FIG9 shows a schematic block diagram of an example device 900 that can be used to implement an embodiment of the present application. Device 900 can be used to implement the functions of the computing device 110 shown in FIG1 . As shown, device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to computer program instructions stored in a random access memory (RAM) 903 and / or a read-only memory (ROM) 902 or computer program instructions loaded from a storage unit 908 into the RAM 903 and / or ROM 902. In RAM 903 and / or ROM 902, various programs and data required for the operation of device 900 can also be stored. As a non-limiting example, computing unit 901 and RAM 903 can respectively implement the functions of the processor 120 and memory 130 shown in FIG1 . Computing unit 901 and RAM 903 and / or ROM 902 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0125] Various components in the device 900 are connected to the I / O interface 905, including an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a magnetic disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0126] The computing unit 901 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. It can implement the functions of the processor 120 in Figure 1. Some examples of the computing unit 901 include, but are not limited to, a CPU, a GPU, various dedicated AI computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as methods 200, 600, and 700. For example, in some embodiments, methods 200, 600, and 700 can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 900 via RAM and / or ROM and / or the communication unit 909. When the computer program is loaded into the RAM and / or ROM and executed by the computing unit 901, one or more steps of the methods 200, 600, or 700 described above can be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to execute the method 200 , 600 , or 700 in any other appropriate manner (eg, by means of firmware).

[0127] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or terminal, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a server or terminal or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, and a tape, etc.), an optical medium (e.g., a digital video disk (DVD), etc.), or a semiconductor medium (e.g., a solid-state drive, etc.).

[0128] In addition, although adopting specific order to describe each operation, this should be understood as requiring such operation to be carried out with shown specific order or with sequential order, or requiring all illustrated operations to be carried out to obtain desired result.Under certain environment, multitasking and parallel processing may be advantageous.Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the application.Some features described in the context of independent embodiment can also be implemented in a single implementation in combination.On the contrary, the various features described in the context of independent implementation also can be implemented in a plurality of implementations individually or in the mode of any suitable subcombination.

[0129] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for data verification, comprising: Acquire N groups of data from a memory, each group of data in the N groups of data includes a check bit, wherein N is a positive integer greater than or equal to 2; Aggregating the N groups of data to obtain aggregated data, where the aggregated data includes an aggregated check bit, where the aggregated check bit is an aggregation of check bits of the N groups of data; Performing error correction code (ECC) encoding on the aggregated data to obtain encoded data; Decomposing the coded data into N groups of coded data, each group of the N groups of coded data including a check bit; and The N groups of encoded data are written into the memory respectively.

2. The method according to claim 1, characterized in that: Getting N sets of data from the memory includes: Data are read from N channels or N memory bank groups of the memory, wherein data of each channel or each memory bank group constitutes a group of data.

3. The method according to claim 1, characterized in that Getting N sets of data from the memory includes: Data is read from M channels or M memory bank groups of the memory in L time slices, where N=L*M, and the time slice is the duration of one burst transmission of reading data from the memory.

4. The method according to claim 1, characterized in that: Performing error correction code (ECC) encoding on the aggregated data includes: Determining a method for acquiring the N groups of data from the memory according to a preset encoding method; and The aggregated data is ECC-encoded according to the preset encoding method.

5. The method according to claim 4, characterized in that Performing ECC encoding on the aggregated data according to the preset encoding method includes: The encoding mode is preset according to a user input, wherein the input includes an ECC performance requirement for the memory.

6. The method according to claim 4, characterized in that Also includes: In response to the encoding method being updated, data is retrieved from the memory according to the updated encoding method to update a check bit of the retrieved data.

7. The method according to claim 4, characterized in that The encoding method includes Reed-Solomon encoding.

8. The method according to claim 4, characterized in that Also includes: Determine a corresponding decoding method according to the encoding method; as well as When data is read from the memory for use, error-corrected data bits for the data are generated based on the parity bits of the read data according to the decoding method.

9. The method according to claim 8, characterized in that Also includes: determining the number of bits that differ between the error-corrected data bits and the read data bits of the data; If the number of bits satisfies a threshold condition, an indication is generated indicating that there is likely an error in the error-corrected data bits.

10. A device for data verification, characterized in that: include: An acquisition module is configured to acquire N groups of data from a memory, each group of data in the N groups of data includes a check bit, wherein N is a positive integer greater than or equal to 2; an aggregation module, configured to aggregate the N groups of data to obtain aggregated data, wherein the aggregated data includes an aggregated check bit, and the aggregated check bit is an aggregation of check bits of the N groups of data; An encoding module, configured to perform error correction code (ECC) encoding on the aggregated data to obtain encoded data; a decomposition module configured to decompose the coded data into N groups of coded data, each group of coded data in the N groups of coded data including a check bit; and The N groups of data are written into the memory respectively, wherein N is a positive integer greater than or equal to 2.

11. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory stores computer instructions, and when the computer instructions are executed by the processor, the electronic device executes the method according to any one of claims 1 to 9.

12. A computer storage medium, characterized in that: The computer-readable storage medium stores instructions, which, when executed by an electronic device, cause the electronic device to perform the method according to any one of claims 1 to 9.

13. A computer program product, characterized in that The computer program product comprises instructions, which, when executed by an electronic device, cause the electronic device to perform the method according to any one of claims 1 to 9.

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