Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate has a display region, and a binding region which is located on one side of the display region. The display substrate comprises a plurality of pixel circuits, a plurality of data lines, and a first fan-out wire and a second fan-out wire, which are disposed in the display region, wherein at least one of the plurality of data lines is a set data line, and the second fan-out line is closer to the center line of the binding region in a second direction than the set data line; the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns, and one column of pixel circuits is electrically connected to one data line; and one end of the first fan-out line is electrically connected to the set data line, and the other end of the first fan-out line is electrically connected to the second fan-out line. The display substrate further comprises a plurality of pixels, wherein at least one of the pixels is a set pixel; each pixel comprises at least three sub-pixels, and each sub-pixel comprises a pixel circuit; and the second fan-out line passes through the pixel circuits of two adjacent sub-pixels in the set pixel corresponding to the second fan-out line, or passes through an outer side of the pixel circuit, which is located on an outer side, in the set pixel corresponding to the second fan-out line, and extends to the binding region.

Description

Display substrate and display device

[0001] This application claims priority to Chinese patent application No. 202310805085.X filed on June 30, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic Light-Emitting Diode (OLED) displays have gradually become a mainstream product in the display industry due to their superior performance, including self-luminescence, high contrast, wide viewing angle, fast response time, compatibility with flexible panels, wide operating temperature range, and relatively simple structure and manufacturing process. OLED display substrates are widely used in end products such as smartphones, tablets, televisions, and wearable devices (such as watches). High pixel density (PPI) and narrow bezels are currently key development trends for OLED displays.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided. The display substrate comprises a display area and a binding area, the binding area being located on one side of the display area along a second direction. The display substrate includes: a plurality of pixel circuits, a plurality of data lines, and a first fan-out line and a second fan-out line disposed in the display area. At least one of the plurality of data lines is a set data line, and the second fan-out line is located closer to a centerline of the binding area along the second direction than the set data line.

[0006] Multiple pixel circuits are arranged in multiple rows and columns, with a row of pixel circuits arranged along a first direction and a column of pixel circuits arranged along a second direction, with the first direction and the second direction intersecting. A data line extends along the second direction, and a column of pixel circuits is electrically connected to a data line. A first fan-out line extends along the first direction, and a second fan-out line extends along the second direction. One end of the first fan-out line is electrically connected to a predetermined data line, and the other end is electrically connected to the second fan-out line.

[0007] In which, the display substrate includes multiple pixels, each pixel includes at least three sub-pixels, and each sub-pixel includes a pixel circuit; at least one of the multiple pixels is a setting pixel, and each setting pixel is correspondingly provided with at least one second fan-out line, and the second fan-out line passes between the pixel circuits of two adjacent sub-pixels in the corresponding setting pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding setting pixel, and extends to the binding area.

[0008] In some embodiments, the display substrate further includes a first voltage signal line extending along the second direction. Each set pixel is provided with at least one first voltage signal line, and the first voltage signal line passes between pixel circuits of two adjacent sub-pixels in the corresponding set pixel, or passes outside of a pixel circuit located outside the corresponding set pixel.

[0009] In some embodiments, among the at least one second fan-out line and the at least one first voltage signal line corresponding to the pixel, one second fan-out line passes between the pixel circuits of a pair of adjacent sub-pixels, and one first voltage signal line passes between the pixel circuits of another pair of adjacent sub-pixels.

[0010] In some embodiments, a pixel includes three sub-pixels. A second fan-out line and a first voltage signal line are provided for each pixel. The second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels among the three sub-pixels, and the first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels among the three sub-pixels.

[0011] In some embodiments, among the second fan-out lines and the first voltage signal lines corresponding to the set pixels, one first voltage signal line and one second fan-out line pass between pixel circuits of a same pair of adjacent sub-pixels.

[0012] In some embodiments, a pixel includes three sub-pixels. A second fan-out line and a first voltage signal line are correspondingly provided to the pixel, and the second fan-out line and the first voltage signal line pass between pixel circuits of a same pair of adjacent sub-pixels among the three sub-pixels.

[0013] In some embodiments, the second fan-out line is provided with a second break, which divides the second fan-out line into an active portion and a redundant portion. One end of the active portion of the second fan-out line is electrically connected to the first fan-out line, and the other end extends to the binding area. The display substrate further includes a first connecting portion, through which the first voltage signal line and the redundant portion of the second fan-out line are electrically connected.

[0014] In some embodiments, the first voltage signal line and the second fan-out line passing through the pixel circuits of the same pair of adjacent sub-pixels are arranged adjacent to each other, and the first voltage signal line, the second fan-out line and the first connecting portion are arranged in the same layer and are integrally formed.

[0015] In some embodiments, the first fan-out line is provided with a first break, which divides the first fan-out line into an active portion and a redundant portion. One end of the active portion of the first fan-out line is electrically connected to the set data line, and the other end is electrically connected to the active portion of the second fan-out line. The display substrate further includes: a second connecting portion, one end of the second connecting portion being electrically connected to the redundant portion of the first fan-out line; a via is provided along the thickness direction of the display substrate between the second connecting portion and the redundant portion of the second fan-out line, and the other end of the second connecting portion is electrically connected to the redundant portion of the second fan-out line through the via.

[0016] In some embodiments, the second connection portion and the redundant portion of the first fan-out line are provided in the same layer and are integrally formed.

[0017] In some embodiments, the display substrate further includes: a plurality of reference voltage signal lines extending along the second direction, wherein a column of pixel circuits is electrically connected to a reference voltage signal line. In two adjacent columns of pixel circuits, the reference voltage signal line connected to one column of pixel circuits and the data line connected to the other column of pixel circuits are arranged adjacent to each other. The second fan-out line is arranged between the adjacent reference voltage signal line and the data line.

[0018] In some embodiments, the first voltage signal line of the display substrate is disposed between the reference voltage signal line and the data line which are disposed close to each other.

[0019] In some embodiments, the display substrate further comprises: a substrate, a semiconductor layer disposed on the substrate, and a plurality of auxiliary reference voltage signal lines disposed on a side of the semiconductor layer away from the substrate. The auxiliary reference voltage signal lines extend along a first direction and are electrically connected to the reference voltage signal lines. A first fan-out line is disposed on a side of the auxiliary reference voltage signal lines away from the substrate; in an orthographic projection onto the substrate, the first fan-out line overlaps the auxiliary reference voltage signal lines and partially overlaps the semiconductor layer.

[0020] In some embodiments, the display substrate further comprises: a plurality of second voltage signal lines extending along a second direction, wherein a column of pixel circuits is electrically connected to a second voltage signal line. The film layer containing the plurality of second voltage signal lines is located on a side of the film layer containing the first fan-out line away from the substrate, and in an orthographic projection onto the substrate, the second voltage signal line covers the first break of the first fan-out line.

[0021] In some embodiments, the display substrate further comprises: a multi-layer source-drain conductive layer. A pair of adjacent source-drain conductive layers in the multi-layer source-drain conductive layer is respectively a first designated source-drain conductive layer and a second designated source-drain conductive layer, wherein the first designated source-drain conductive layer is closer to the substrate than the second designated source-drain conductive layer. The first fan-out line is provided in the first designated source-drain conductive layer, and the data line and the second fan-out line are provided in the second designated source-drain conductive layer.

[0022] In some embodiments, the display substrate further includes: a gate signal line, an enable signal line, an auxiliary first voltage signal line, and an auxiliary second voltage signal line, all extending along the first direction. The pixel circuit is electrically connected to the gate signal line and the enable signal line; the auxiliary first voltage signal line is electrically connected to the first voltage signal line, and the auxiliary second voltage signal line is electrically connected to the second voltage signal line.

[0023] The first set source-drain conductive layer is provided with at least one of a gate signal line, an enable signal line, an auxiliary first voltage signal line, and an auxiliary second voltage signal line. In an orthographic projection onto the substrate, at least one of the gate signal line, the enable signal line, the auxiliary first voltage signal line, and the auxiliary second voltage signal line overlaps the second break of the second fan-out line.

[0024] In some embodiments, the first voltage signal line, the second voltage signal line, and the reference voltage signal line of the display substrate are all disposed in the second set source-drain conductive layer.

[0025] In some embodiments, the display substrate further includes a first gate layer and a second gate layer. The semiconductor layer, the first gate layer, and the second gate layer of the display substrate are sequentially arranged in a direction away from the substrate and located between the substrate and the multi-layer source / drain conductive layer. An auxiliary reference voltage signal line of the display substrate is provided in the second gate layer.

[0026] In some embodiments, the multi-layer source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer, the first source-drain conductive layer is a first set source-drain conductive layer, and the second source-drain conductive layer is a second set source-drain conductive layer.

[0027] In some embodiments, the multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the first source-drain conductive layer is a first set source-drain conductive layer, and the second source-drain conductive layer is a second set source-drain conductive layer.

[0028] In some embodiments, the multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the second source-drain conductive layer is a first set source-drain conductive layer, and the third source-drain conductive layer is a second set source-drain conductive layer.

[0029] In some embodiments, the set data line is further away from the center line of the binding area along the second direction than other data lines in the plurality of data lines. The set data line is entirely located in the display area, and ends of other data lines extend to the binding area.

[0030] In another aspect, a display device is provided, comprising: a display substrate as described in any one of the above embodiments, and a circuit board electrically connected to the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0032] FIG1 is a structural diagram of a display device according to some embodiments;

[0033] FIG2 is another structural diagram of a display device according to some embodiments;

[0034] FIG3 is a structural diagram of a pixel circuit according to some embodiments;

[0035] FIG4 is a structural diagram of a pixel circuit according to some other embodiments;

[0036] FIG5 is a partially enlarged structural diagram of a display area AA of a display substrate according to some embodiments;

[0037] FIG6 is an enlarged structural diagram of area D in FIG5 ;

[0038] FIG7 is an enlarged structural diagram of area F in FIG5 ;

[0039] FIG8 is a structural diagram of a first source-drain conductive layer to a second source-drain conductive layer of a display substrate according to some embodiments;

[0040] FIG9 is an enlarged structural diagram of the first source-drain conductive layer of the display substrate according to some embodiments, based on the region E in FIG8 ;

[0041] FIG10 is an enlarged structural diagram of the second source-drain conductive layer of the display substrate according to some embodiments, based on the region E in FIG8 ;

[0042] FIG11 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0043] FIG12 is a cross-sectional structural diagram of a display substrate according to some embodiments;

[0044] FIG13 is a structural diagram of a semiconductor layer of a display substrate according to some embodiments;

[0045] FIG14 is a structural diagram of a display substrate from a semiconductor layer to a second gate layer according to some embodiments;

[0046] FIG. 15 is a structural diagram of a display substrate from a semiconductor layer to a first source-drain conductive layer according to some embodiments. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0054] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0055] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0056] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0057] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0058] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] In an embodiment of the present disclosure, Figures 1 and 2 are planar structural diagrams of a display device 1000. In order to clearly describe the connection method between the display substrate 100 and the circuit board 200, the circuit board 200 is shown in Figure 2 on the same side of the display area AA of the display substrate 100. It should be noted that in the final display substrate 100, the circuit board 200 is bent to the other side.

[0061] To clearly illustrate the relative positional relationship between the second fan-out line FIP2, the first voltage signal line VSS, and the pixel circuit 10, Figures 3 and 4 only illustrate the structure of a portion of the pixel circuit 10 on the display substrate 100. The number of pixel circuits 10 included in the actual display substrate 100 is not limited to that shown in the figures. Furthermore, the film layer structure included in the display substrate 100 includes, but is not limited to, the film layer structure shown in the figures.

[0062] To clearly illustrate the data signal transmission paths between the set data line DL1, the first fan-out line FIP1, and the second fan-out line FIP2, Figure 5 shows a partially enlarged view of the display area AA. The vertical arrows in Figure 5 indicate the data signal transmission paths within the binding area BB via the second fan-out line FIP2. The horizontal arrows in Figure 5 indicate the data signal transmission paths from the second fan-out line FIP2 to the first fan-out line FIP1. Figure 5 identifies the data signal transmission paths for the three set data lines DL1. Figure 6 shows an enlarged structural diagram of area D in Figure 5, and Figure 7 shows an enlarged structural diagram of area F in Figure 5.

[0063] To clearly illustrate the connection between the redundant portion FIP12 of the first fan-out line FIP1 and the redundant portion FIP22 of the second fan-out line FIP2 and the first voltage signal line VSS, Figure 8 only shows the structure of the first source-drain conductive layer to the second source-drain conductive layer. Figure 9 is an enlarged structural diagram of the first source-drain conductive layer according to area E in Figure 8, and Figure 10 is an enlarged structural diagram of the second source-drain conductive layer according to area E in Figure 8.

[0064] Figure 11 is an equivalent circuit diagram of a pixel circuit according to some embodiments. Figure 12 is a cross-sectional structural diagram of a display substrate according to some embodiments.

[0065] Figure 13 is a planar structural diagram of a semiconductor layer of a display substrate according to some embodiments. Figure 14 is a structural diagram of a display substrate from the semiconductor layer to the second gate layer according to some embodiments. Figure 15 is a structural diagram of a display substrate from the semiconductor layer to the first source and drain conductive layer according to some embodiments.

[0066] It should be noted that, in order to facilitate a clear description of the patterned design of each film layer structure and the corresponding relationship between each film layer, Figures 3 to 10, and Figures 13 to 15 only show enlarged structural schematic diagrams of partial areas corresponding to some sub-pixels in each film layer structure of the display substrate. The actual film layer structure of the display substrate 100 may also include other film layer structures, and the patterned design of each film layer structure includes but is not limited to that shown in the figure, and may also include other designs.

[0067] In order to facilitate a clear description of the connection method between the functional film layers, the insulating dielectric layer ILD and the first planarization layer 61 shown in Figures 3, 4, 6 to 8, 14 and 15 are vias on the insulating dielectric layer ILD and the first planarization layer 61. In the actual film layer structure, the insulating dielectric layer ILD and the first planarization layer 61 are the film layers that entirely cover the display substrate 100, and vias are set on the insulating dielectric layer ILD and the first planarization layer 61 at the positions shown in the figures, so that the parts that need to be electrically connected between the second gate layer 32 and the first source-drain conductive layer 41, and between the first source-drain conductive layer 41 and the second source-drain conductive layer 42 can be connected correspondingly through the vias.

[0068] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is contemplated that the embodiments described can be implemented in or associated with a variety of electronic devices, including but not limited to televisions, mobile phones, wearable devices, PDAs (Personal Digital Assistants), AR (Augmented Reality) devices, VR (Virtual Reality) devices, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, clocks, calculators, television monitors, flat-panel displays, computer monitors, in-vehicle displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. For example, as shown in FIG1 , the display device 1000 may be a mobile phone.

[0069] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an OLED (Organic Light-Emitting Diode, or Organic Electroluminescence Display, organic light-emitting semiconductor) display device, a QLED (Quantum Dot Light Emitting Diodes, quantum dot electroluminescent diode) display device, an MLED (Mini Light Emitting Diodes, or Micro Light Emitting Diodes, micro light-emitting diode) display device, etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. There is no limitation on this, and adaptive design can be performed according to actual needs.

[0070] The following uses a rectangular and planar organic light-emitting diode display device as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation methods of the present disclosure include but are not limited to this, and any other display device can also be considered as long as the same technical concept is applied.

[0071] 2 , the display device 1000 includes a display substrate 100 and a circuit board 200 . The circuit board 200 is electrically connected to the display substrate 100 .

[0072] Exemplarily, the circuit board 200 is configured to transmit a driving signal to the display substrate 100 to drive the display substrate 100 to realize image display.

[0073] For example, the circuit board 200 may include a timing controller (TCON), a power management chip DC / DC, an adjustable resistor divider circuit (generating Vcom), and other driving circuits. The circuit board 200 may also include other circuit structures, which are not listed here one by one.

[0074] In some embodiments, the display device 1000 may further include an under-screen camera and an under-screen fingerprint sensor, so that the display device 1000 can realize a variety of different functions such as taking photos, recording videos, fingerprint recognition, or face recognition. There is no limitation to this, and adaptive design can be performed according to actual needs.

[0075] 2 , the display substrate 100 includes a display area AA and a peripheral area AN located at least on one side of the display area AA along the second direction Y. The display substrate 100 includes a plurality of pixels P disposed in the display area AA, each pixel P including at least three sub-pixels P(x).

[0076] Exemplarily, the plurality of pixels P are arranged in a plurality of rows and columns.

[0077] Exemplarily, as shown in FIG2 , the display area AA is an area on the display substrate 100 for displaying images, the sub-pixel P(x) is the smallest light-emitting unit on the display substrate 100 , and the sub-pixel P(x) is used to display images.

[0078] In some examples, multiple sub-pixels P(x) emit light of the same color, and the display substrate 100 may further include a color filter layer arranged on the light-emitting side of the multiple sub-pixels P(x), that is, the display substrate 100 adopts a COE (CF On Encapsulation) structure.

[0079] For example, multiple sub-pixels P(x) all emit white light, red light, green light, blue light or other color light. In this case, the color light emitted by the sub-pixel P(x) remains the same color light after passing through the color filter layer, or is converted into other color light and emitted. Therefore, when multiple sub-pixels P(x) emit the same color light, the display substrate 100 can achieve multi-color light output.

[0080] In other examples, multiple sub-pixels P(x) emit light of different colors. For example, multiple sub-pixels P(x) include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, thereby realizing multi-color light output of the display substrate 100.

[0081] It should be noted that each pixel P includes at least three sub-pixels P(x), that is, each pixel P may include three, four or more sub-pixels P(x), and the multiple sub-pixels P(x) included in each pixel P may be a row, a column or a group of sub-pixels P(x), and a group of sub-pixels P(x) may be multiple sub-pixels P(x) adjacent to each other, and the adjacent multiple sub-pixels P(x) are arranged in a row, a column, an L-shape, a rectangle or a diamond, etc.

[0082] At the same time, the luminous areas of the multiple sub-pixels P(x) included in each pixel P may be the same or different. The above is only an exemplary description and is not intended to limit the present disclosure. The specific adaptive design can be made according to actual needs.

[0083] The following description will be made by taking an example where a plurality of sub-pixels P(x) included in each pixel P are arranged in a row along the first direction X.

[0084] In some embodiments, as shown in FIG. 2 , a peripheral area AN is disposed around the display area AA. A gate driver circuit (e.g., Gate on Array, GOA for short), control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.), and a bound driver chip (e.g., Source Driver IC) may be disposed in the peripheral area AN. Functions of the peripheral area AN include but are not limited to the foregoing.

[0085] For example, as shown in FIG. 2 , the peripheral area AN includes a binding area BB located on one side of the display area AA along the second direction Y. The binding area BB is adjacent to a side edge of the display area AA, for example, adjacent to a lower edge of the display area AA. The display substrate 100 is connected to an external driver within the binding area BB.

[0086] For example, the bonding area BB is configured to lead out signal lines (e.g., data lines DL, first voltage signal lines VSS, and reference voltage signal lines VRef1) and bond them to a driver circuit board (e.g., circuit board 200) or a driver chip. That is, the bonding area BB is located on the side of the display substrate 100 that is bonded to the driver circuit board or driver chip.

[0087] In some embodiments, as shown in FIG2 , a display substrate 100 includes: a plurality of pixel circuits 10 and a plurality of light-emitting devices 20. The plurality of pixel circuits 10 are arranged in multiple rows and columns. A row of pixel circuits 10 is arranged along a first direction X, and each row of pixel circuits 10 includes a plurality of pixel circuits 10 spaced apart along the first direction X. A column of pixel circuits 10 is arranged along a second direction Y, and each column of pixel circuits 10 includes a plurality of pixel circuits 10 spaced apart along the second direction Y. In other words, the first direction X is the row direction of the plurality of pixel circuits 10, and the second direction Y is the column direction of the plurality of pixel circuits 10. The first direction X and the second direction Y intersect.

[0088] Exemplarily, the first direction X is perpendicular to the second direction Y.

[0089] Exemplarily, each pixel circuit 10 is connected to a light emitting device 20 , and the pixel circuit 10 is configured to drive the light emitting device 20 connected thereto to emit light.

[0090] Exemplarily, the light-emitting device 20 includes, but is not limited to, OLED (Organic Light-Emitting Diode), Mini LED (Mini Light-Emitting Diode), Micro LED (Micro Light-Emitting Diode), and the like.

[0091] In some embodiments, as shown in Figures 2 and 3, the display substrate 100 further includes a plurality of data lines DL, a first fan-out line FIP1, and a second fan-out line FIP2. The data lines DL extend along the second direction Y, and a column of pixel circuits 10 is electrically connected to a data line DL. At least one of the plurality of data lines DL is a set data line DL1, and the second fan-out line FIP2 is located closer to the centerline of the bonding area BB along the second direction Y than the set data line DL1.

[0092] The first fan-out line FIP1 and the second fan-out line FIP2 are provided in the display area AA. The first fan-out line FIP1 extends along the first direction X, and the second fan-out line FIP2 extends along the second direction Y. One end of the first fan-out line FIP1 is electrically connected to the set data line DL1, and the other end is electrically connected to the second fan-out line FIP2.

[0093] As shown in FIG2 , at least one of the plurality of pixels P is a setting pixel PP, and each setting pixel PP is provided with at least one second fan-out line FIP2. The second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP, or passes outside the pixel circuit 10 located outside the corresponding setting pixel PP, and extends to the bonding area BB.

[0094] 2 , compared to other data lines DL among the plurality of data lines DL, the set data line DL1 is further away from the center line of the binding area BB along the second direction Y. The set data line DL1 is entirely located in the display area AA, and the ends of the other data lines DL extend to the binding area BB.

[0095] For example, as shown in Figure 2, the data lines DL may include a first data line DL1 and a second data line DL2. The first data line DL1 is a setting data line DL1. The setting data line DL1 is located within the display area AA and does not extend to the bonding area BB. The second fan-out line FIP2 and the second data line DL2 extend to the bonding area BB. The setting data line DL1, the first fan-out line FIP1, and the second fan-out line FIP2 are sequentially connected, with each first fan-out line FIP1 electrically connected to a setting data line DL1 and a second fan-out line FIP2.

[0096] In other words, the second data line DL2 extends directly to the bonding area BB, and the data line DL1 is set as the data line DL in the display substrate 100 that needs to be sequentially led to the bonding area BB through the first fan-out line FIP1 and the second fan-out line FIP2. This configuration can be called FIP (Fanout In Pixel).

[0097] As shown in FIG2 , the width of the bezel on the side of the display substrate 100 used for bonding the driver, for example, the width of the portion of the peripheral area AN below the display area AA shown in FIG2 is d1, and the dimension of the bonding area BB along the second direction Y is d2, where d1 ≥ d2. This design can reduce the dimension d1 of the side of the peripheral area AN where the bonding area BB is provided, thereby facilitating a narrow bezel for the display device 1000.

[0098] By inserting a second fan-out line FIP2 within a pixel P or between adjacent pixels P, the data line DL1 is routed to the bonding area BB via the first and second fan-out lines FIP1 and FIP2. This increases the number of signal lines used to transmit data signals within the display area AA, thereby increasing the density of these signal lines. This reduces the overall resistance of the signal lines transmitting data signals, facilitating stable and reliable data signal transmission. Furthermore, inserting the newly added second fan-out line FIP2 between adjacent pixel circuits 10 ensures the uniformity of the film structure of the display substrate 100, thereby enhancing the display quality of the display substrate 100.

[0099] Exemplarily, as shown in FIG2 , the set pixel PP includes, for example, three sub-pixels P(x) arranged in sequence along the first direction X, for example, from the left side to the right side in FIG2 , namely, the first sub-pixel PP(1), the second sub-pixel PP(2) and the third sub-pixel PP(3).

[0100] In some examples, as shown in FIG2 , a second fan-out line FIP2 is correspondingly provided for a setting pixel PP in the display substrate 100 . The second fan-out line FIP2 passes through the outer side of the pixel circuit 10 located outside the corresponding setting pixel PP and extends to the binding area BB.

[0101] For example, the second fan-out line FIP2 passes through a side of the pixel circuit 10 of the first sub-pixel PP( 1 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ) and extends to the bonding area BB.

[0102] For another example, the second fan-out line FIP2 passes through the side of the pixel circuit 10 of the third sub-pixel PP(3) away from the pixel circuit 10 of the second sub-pixel PP(2), and extends to the bonding area BB.

[0103] In other examples, as shown in FIG3 , a second fan-out line FIP2 is correspondingly provided for a set pixel PP in the display substrate 100 . The second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding set pixel PP and extends to the binding area BB.

[0104] For example, the second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2) and extends to the binding area BB; or, as shown in FIG3 , the second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3) and extends to the binding area BB.

[0105] In some other examples, two second fan-out lines FIP2 are correspondingly provided for a setting pixel PP in the display substrate 100 . The second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.

[0106] For example, one second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; another second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB.

[0107] In some other examples, a setting pixel PP in the display substrate 100 is correspondingly provided with three setting data lines DL1 and a second fan-out line FIP2. The second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.

[0108] For example, a second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2) and extends to the binding area BB; another second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3) and extends to the binding area BB; another second fan-out line FIP2 passes from the outside of the pixel circuit 10 located on the outside of the corresponding set pixel PP and extends to the binding area BB.

[0109] In some other examples, a set pixel PP in the display substrate 100 is correspondingly provided with four second fan-out lines FIP2, wherein, along the first direction X, the first second fan-out line FIP2 passes from the side of the pixel circuit 10 of the first sub-pixel PP(1) away from the second sub-pixel PP(2) and extends to the binding area BB; the second second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2) and extends to the binding area BB; the third second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3) and extends to the binding area BB; the fourth second fan-out line FIP2 passes from the side of the pixel circuit 10 of the third sub-pixel PP(3) away from the second sub-pixel PP(2) and extends to the binding area BB.

[0110] It is understood that, when the setting pixel PP includes three sub-pixels P(x), and the setting pixel PP is adjacent to other pixels P on both sides along the first direction X, one or two second fan-out lines FIP2 may be included between two adjacent pixels P (one of which is the setting pixel PP). When two adjacent pixels P are both setting pixels PP, and the number of second fan-out lines FIP2 corresponding to one setting pixel PP is less than or equal to the number of sub-pixels P(x) included in the setting pixel PP, and when one second fan-out line FIP2 corresponding to a first setting pixel PP is located between the two setting pixels PP, any one of the second fan-out lines FIP2 corresponding to the second setting pixel PP may be located between the two setting pixels PP, or between sub-pixels P(x) within the second setting pixel PP, or on the side of the second setting pixel PP away from the first setting pixel PP.

[0111] By setting a first fan-out line FIP and a second fan-out line FIP2, the data line DL corresponding to at least a portion of the multiple sub-pixels P(x) included in the set pixel PP is led out from the peripheral area AN to the binding area BB, and is instead led out from the display area AA to the binding area BB through the second fan-out line FIP2, thereby reducing the wiring area of ​​the data line DL in the peripheral area AN and reducing the dimension d1 along the second direction Y on the side of the peripheral area AN where the binding area BB is set, thereby achieving a narrowed frame of the display device 1000.

[0112] It should be noted that the outer side of the pixel circuit 10 located outside the setting pixel PP refers to the area between the setting pixel PP and another pixel P adjacent to the setting pixel PP, and the other pixel P may also be the setting pixel PP.

[0113] The above is merely an exemplary description and does not limit the present disclosure. Each set pixel PP may also include four, five, or more sub-pixels P(x). In some examples, the number of second fan-out lines FIP2 corresponding to each set pixel PP is less than or equal to the number of sub-pixels P(x) included therein, and the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding set pixel PP, or passes outside the pixel circuit 10 located on the outside of the corresponding set pixel PP, and extends to the binding area BB. In other examples, the number of second fan-out lines FIP2 corresponding to each set pixel PP is greater than the number of sub-pixels P(x) included therein, and a portion of the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding set pixel PP, and another portion passes outside the pixel circuit 10 located on the outside of the corresponding set pixel PP, and extends to the binding area BB.

[0114] Exemplarily, as shown in FIG2 , the data line DL needs to extend to the binding area BB and be bound and connected to a driver (such as a driver circuit board or a driver chip, etc.) in the binding area BB. The driver transmits a data signal to the data line DL so that the pixel circuit 10 can drive the light-emitting device 20 to emit light.

[0115] As shown in Figure 2 , along the first direction X, the size of the binding area BB is, for example, smaller than the size of the display area AA. Furthermore, along the second direction Y, the binding area BB may be located opposite the central region of the display area AA. The data lines DL located at the edges of the display area AA along the first direction X are designated as the designated data lines DL1 (first data lines DL1), while the data lines DL located in the central region of the display area AA along the first direction X are designated as the second data lines DL2.

[0116] In some embodiments, the display substrate does not include the first fan-out line FIP1 and the second fan-out line FIP2. The data line DL1 is configured to extend from one end of the display substrate 100 near the bonding area BB toward the peripheral area AN and converge toward the bonding area BB. Referring to FIG. 2 , along the first direction X, the bonding area BB is smaller than the display area AA in the display substrate 100. Consequently, the portion of the data line DL1 located within the peripheral area AN and extending into the bonding area BB occupies space within the peripheral area AN, resulting in a larger portion of the peripheral area AN on the side where the bonding area BB is located along the second direction Y. This results in a larger border width on the side of the display substrate 100 used for driver bonding.

[0117] In other embodiments, as shown in FIG2 , the second data line DL2 is disposed opposite the binding area BB along the second direction Y, and the setting data line DL1 is located on both sides of the second data line DL2 along the first direction X. Thus, along the first direction X, the first data line DL1 located on both sides of the binding area BB is led to the binding area BB via the first fan-out line FIP1 and the second fan-out line FIP2, while the second data line DL2 disposed opposite the binding area BB is directly led to the binding area BB.

[0118] With the design shown in FIG2 , multiple data lines DL (set data line DL1 and second data line DL2) are led out from the display area AA to the binding area BB. The data lines DL do not occupy the space in the peripheral area AN, which helps to reduce the dimension d2 of the portion of the peripheral area AN on one side where the binding area BB is set along the second direction Y, thereby achieving a narrow frame of the display device 1000.

[0119] It should be noted that the display substrate 100 may include multiple binding areas BB. For example, in a large-scale display device (such as a television or computer), the display substrate 100 may include multiple binding areas BB. The data lines DL arranged opposite the binding areas BB along the second direction Y may be considered as second data lines DL2, and the remaining data lines DL may be considered as first data lines DL1 (set data lines DL1). Of course, the method of distinguishing the first data lines DL1 from the second data lines DL2 is not limited to this. The first data lines DL1 and the second data lines DL2 may also be arranged in different areas as needed.

[0120] In some embodiments, as shown in FIG3 , the display substrate 100 further includes a first voltage signal line VSS extending along the second direction Y. At least one first voltage signal line VSS is provided corresponding to each setting pixel PP. The first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP, or passes outside the pixel circuit 10 located outside the corresponding setting pixel PP.

[0121] The following description is made by taking an example where the pixel PP includes a first sub-pixel PP(1), a second sub-pixel PP(2) and a third sub-pixel PP(3) sequentially arranged along the first direction X.

[0122] In some examples, a first voltage signal line VSS is correspondingly provided to a setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes through the outside of the pixel circuit 10 located outside the corresponding setting pixel PP.

[0123] For example, the first voltage signal line VSS passes through a side of the pixel circuit 10 of the first sub-pixel PP( 1 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ).

[0124] For another example, the first voltage signal line VSS passes through the pixel circuit 10 of the third sub-pixel PP(3) at a side away from the pixel circuit 10 of the second sub-pixel PP(2).

[0125] In other examples, as shown in FIG3 , a setting pixel PP in the display substrate 100 is correspondingly provided with a first voltage signal line VSS, and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.

[0126] For example, as shown in FIG3 , the first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); or, the first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3).

[0127] In some other examples, two first voltage signal lines VSS are correspondingly provided to one setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.

[0128] For example, a first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); another first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3).

[0129] In some further examples, three first voltage signal lines VSS are correspondingly provided for one setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.

[0130] For example, a first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); another first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3); and another first voltage signal line VSS passes from the outside of the pixel circuit 10 located on the outside in the corresponding set pixel PP.

[0131] In some other examples, a set pixel PP in the display substrate 100 is correspondingly provided with four first voltage signal lines VSS, wherein, along the first direction X, the first first voltage signal line VSS passes from the side of the pixel circuit 10 of the first sub-pixel PP(1) away from the second sub-pixel PP(2); the second first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); the third first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3); and the fourth first voltage signal line VSS passes from the side of the pixel circuit 10 of the third sub-pixel PP(3) away from the second sub-pixel PP(2).

[0132] It is understood that, when the setting pixel PP includes three sub-pixels P(x), and the setting pixel PP is adjacent to other pixels P on both sides along the first direction X, one or two first voltage signal lines VSS may be included between the two adjacent pixels P (one of which is the setting pixel PP). When the two adjacent pixels P are both setting pixels PP, and the number of first voltage signal lines VSS corresponding to the setting pixels PP is less than or equal to the number of sub-pixels P(x) included in the setting pixel PP, and when one first voltage signal line VSS corresponding to a first setting pixel PP is located between the two setting pixels PP, any one of the first voltage signal lines VSS corresponding to the second setting pixel PP may be located between the two setting pixels PP, or between the sub-pixels P(x) within the second setting pixel PP, or on a side of the second setting pixel PP away from the first setting pixel PP.

[0133] By inserting the first voltage signal line VSS in the setting pixel PP, or between the setting pixel PP and the adjacent pixel P (or another setting pixel PP), the number of wiring lines of the first voltage signal line VSS in the display area AA is increased, and the density of the first voltage signal line VSS in the display area AA is increased, thereby reducing the overall resistance of the first voltage signal line VSS, which is beneficial to reducing the voltage drop of the first voltage signal line VSS and ensuring the transmission stability and reliability of the first voltage signal.

[0134] In some embodiments, as shown in FIG3 , among the at least one second fan-out line FIP2 and the at least one first voltage signal line VSS corresponding to the pixel PP, one second fan-out line FIP2 passes between the pixel circuits 10 of a pair of adjacent sub-pixels P(x), and one first voltage signal line VSS passes between the pixel circuits 10 of another pair of adjacent sub-pixels P(x).

[0135] By inserting the second fan-out line FIP2 and the first voltage signal line VSS between the pixel circuits 10 of adjacent sub-pixels P(x) within the set pixel PP, the density of the signal lines for transmitting the first voltage signal and the data signal within the display area AA is increased, thereby reducing the overall resistance of the first voltage signal line VSS and the data line DL, which is beneficial to reducing the voltage drop of the first voltage signal line VSS and the data line DL, and ensuring the transmission stability and reliability of the first voltage signal and the data signal.

[0136] For example, as shown in FIG3 , each pixel P includes three sub-pixels P(x). Each pixel PP is provided with a second fan-out line FIP2 and a first voltage signal line VSS. The second fan-out line FIP2 passes between the pixel circuits 10 of a pair of adjacent sub-pixels P(x) among the three sub-pixels P(x), and the first voltage signal line VSS passes between the pixel circuits 10 of another pair of adjacent sub-pixels P(x) among the three sub-pixels P(x).

[0137] For example, as shown in FIG3 , a pixel PP is set to include a first sub-pixel P(1), a second sub-pixel P(2), and a third sub-pixel P(3) sequentially arranged along a first direction X. A first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2), and a second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3), and extends to the bonding area BB.

[0138] It should be noted that, in the case where each pixel P includes three sub-pixels P(x), the second fan-out line FIP2 may pass between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2) and extend to the binding area BB; the first voltage signal line VSS may pass between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3).

[0139] In some embodiments, as shown in FIG. 4 , among the second fan-out lines FIP2 and the first voltage signal lines VSS corresponding to the pixel PP, one first voltage signal line VSS and one second fan-out line FIP2 pass between the pixel circuits 10 of the same pair of adjacent sub-pixels P(x).

[0140] By way of example, the pixel circuit 10 includes, for example, a plurality of thin film transistors (TFTs), at least one capacitor, and at least one connection node. Some of the connection nodes (e.g., the fifth node N5 shown in FIG11 ) play a key role in the operation of the pixel circuit 10. The detailed structure of the pixel circuit 10 will be described later and will not be further described here.

[0141] By setting a first voltage signal line VSS and a second fan-out line FIP2 corresponding to the set pixel PP to pass through the pixel circuits 10 of the same pair of adjacent sub-pixels P(x), the wiring density of the signal lines for transmitting the first voltage signal in the display area AA is increased, the resistance of the signal lines for transmitting the first voltage signal in the display area AA is reduced, and the voltage drop of the first voltage signal is reduced.

[0142] At the same time, the first voltage signal line VSS serves as a constant voltage signal line, which can play a signal shielding effect, preventing the data signal transmitted by the second fan-out line FIP2 passing through the pixel circuits 10 of adjacent sub-pixels P(x) from generating signal crosstalk with the nodes within the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.

[0143] 4 , a pixel P includes three sub-pixels P(x). Each pixel PP is provided with a second fan-out line FIP2 and a first voltage signal line VSS. The second fan-out line FIP2 and the first voltage signal line VSS pass between the pixel circuits 10 of the same pair of adjacent sub-pixels P(x) among the three sub-pixels P(x).

[0144] For example, as shown in FIG4 , a pixel PP is set to include a first sub-pixel P(1), a second sub-pixel P(2), and a third sub-pixel P(3) sequentially arranged along a first direction X. The first voltage signal line VSS and the second fan-out line FIP2 both pass between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2).

[0145] It should be noted that, when each pixel P includes three sub-pixels P(x), the first voltage signal line VSS and the second fan-out line FIP2 may also pass between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3).

[0146] In some embodiments, as shown in FIG6 , the second fan-out line FIP2 is provided with a second break DK2 that divides the second fan-out line FIP2 into an active portion FIP21 and a redundant portion FIP22. The active portion FIP21 of the second fan-out line FIP2 has one end electrically connected to the first fan-out line FIP1 and the other end extending to the bonding area BB.

[0147] Exemplarily, as shown in FIG6 , the second break DK2 divides the second fan-out line FIP2 into an effective portion FIP21 and a redundant portion FIP22 that are electrically insulated from each other. Referring to FIG2 and FIG5 , one end of the effective portion FIP21 of the second fan-out line FIP2 (e.g., the lower end shown in FIG2 ) extends to the binding area BB, and the other end is connected to the first fan-out line FIP1. The effective portion FIP21 of the second fan-out line FIP2 is electrically insulated from the redundant portion FIP22 of the second fan-out line FIP2 on the side away from the binding area BB. That is, the first fan-out line FIP1 is electrically connected to the effective portion FIP21 of the second fan-out line FIP2, and extends to the binding area BB through the effective portion FIP21 of the second fan-out line FIP2.

[0148] The second fan-out line FIP2 is divided by a second break DK2 into an effective portion FIP21 and a redundant portion FIP22, which are electrically insulated from each other. The data signal is emitted from the driver bound in the binding area BB and is transmitted to the corresponding sub-pixel P(x) via the effective portion FIP21 of the second fan-out line FIP2, the first fan-out line FIP1, and the set data line DL1. In this way, the transmission path of the data signal does not pass through the redundant portion FIP22 of the second fan-out line FIP2, which helps shorten the transmission path of the data signal on the second fan-out line FIP2, thereby reducing the voltage drop of the data signal during transmission on the second fan-out line FIP2, preventing signal distortion caused by the voltage drop, and ensuring the accuracy of data signal transmission.

[0149] It should be noted that the redundant portion FIP22 of the second fan-out line FIP2 may be configured not to transmit signals, or configured to transmit signals other than data signals.

[0150] In some embodiments, as shown in Figures 8 and 10, the display substrate 100 further includes a first connection portion LJ1, through which the first voltage signal line VSS and the redundant portion FIP22 of the second fan-out line FIP2 are electrically connected. The redundant portion FIP22 of the second fan-out line FIP2 is configured to transmit the first voltage signal.

[0151] The redundant portion FIP22 of the second fan-out line FIP2 is connected to the first voltage signal line VSS through the first connection portion LJ1. In this way, the wiring area of ​​the first voltage signal line VSS in the display area AA is increased, so that the density of the first voltage signal line VSS in the display area AA is increased, which is beneficial to reducing the resistance of the first voltage signal line VSS and further reducing the voltage drop of the first voltage signal line VSS.

[0152] In some embodiments, as shown in Figures 4, 8 and 10, the first voltage signal line VSS and the second fan-out line FIP2 passing through the pixel circuits 10 of the same pair of adjacent sub-pixels P(x) are arranged adjacent to each other, and the first voltage signal line VSS, the second fan-out line FIP2 and the first connection part LJ1 are arranged on the same layer and are integrally formed.

[0153] For example, during the fabrication of the display substrate 100, a conductive structural layer is first formed, for example, by sputtering. Subsequently, the conductive structural layer is patterned, for example, by etching, to form the connected first voltage signal line VSS, first connector LJ1, and second fan-out line FIP2. In this way, the first voltage signal line VSS, second fan-out line FIP2, and first connector LJ1 are simultaneously formed in the same fabrication step. The first voltage signal line VSS, first connector LJ1, and second fan-out line FIP2 are connected to form an integrated structure, eliminating the need for additional structures to connect the three. While the first connector LJ1 and second fan-out line FIP2 are added, no additional fabrication steps are required for the display substrate 100, thereby reducing production costs.

[0154] It should be noted that the preparation process of the first voltage signal line VSS, the first connection portion LJ1 and the second fan-out line FIP2 may also adopt other methods, which are only illustrative and not intended to limit the present disclosure.

[0155] In some embodiments, as shown in FIG6 , the first fan-out line FIP1 is provided with a first break DK1, which divides the first fan-out line FIP1 into an active portion FIP11 and a redundant portion FIP12. The active portion FIP11 of the first fan-out line FIP1 is electrically connected to the set data line DL1 at one end, and to the active portion FIP21 of the second fan-out line FIP2 at the other end.

[0156] Exemplarily, as shown in FIG6 , the first break DK1 divides the first fan-out line FIP1 into an effective portion FIP11 and a redundant portion FIP12 that are electrically insulated from each other. Referring to FIG2 and FIG5 , one end of the effective portion FIP11 of the first fan-out line FIP1 (e.g., the lower end shown in FIG2 ) extends to the binding area BB, and the other end is connected to the second fan-out line FIP2. The effective portion FIP21 of the first fan-out line FIP1 is electrically insulated from the redundant portion FIP12 of the first fan-out line FIP1 on the side away from the binding area BB. That is, the effective portion FIP11 of the first fan-out line FIP1 is electrically connected to the effective portion FIP21 of the second fan-out line FIP2, and extends to the binding area BB through the effective portion FIP21 of the second fan-out line FIP2.

[0157] The first fan-out line FIP1 is divided by a first break DK1 into an effective portion FIP11 and a redundant portion FIP12, which are electrically insulated from each other. A data signal is emitted from the driver bound within the binding area BB and transmitted sequentially through the effective portion FIP21 of the second fan-out line FIP2, the effective portion FIP11 of the first fan-out line FIP1, and the set data line DL1 to the corresponding sub-pixel P(x). In this way, the data signal transmission path does not pass through the redundant portion FIP22 of the second fan-out line FIP2 or the redundant portion FIP12 of the first fan-out line FIP1. This helps shorten the data signal transmission path on the first fan-out line FIP1 and the second fan-out line FIP2, thereby reducing the voltage drop of the data signal during transmission on the first fan-out line FIP1 and then the second fan-out line FIP2, preventing signal distortion caused by the voltage drop and ensuring the accuracy of data signal transmission.

[0158] In some embodiments, as shown in Figures 8 and 9 , the display substrate 100 further includes a second connection portion LJ2. A via K is provided between the second connection portion LJ2 and the redundant portion FIP22 of the second fan-out line FIP2 along the thickness direction of the display substrate 100. One end of the second connection portion LJ2 is electrically connected to the redundant portion FIP12 of the first fan-out line FIP1, and the other end of the second connection portion LJ2 is electrically connected to the redundant portion FIP22 of the second fan-out line FIP2 through the via K.

[0159] Exemplarily, the first fan-out line FIP1 and the second fan-out line FIP2 are located in different film layer structures, that is, along the thickness direction of the display substrate 100 , the distances between the film layer structures where the first fan-out line FIP1 and the second fan-out line FIP2 are located and the display substrate 100 are different.

[0160] An insulating spacer layer, such as a planarization layer 6, may be provided between the first fan-out line FIP1 and the second fan-out line FIP2 to electrically insulate the first fan-out line FIP1 from the second fan-out line FIP2. A via K is provided on the planarization layer 6 corresponding to the portion between the redundant portion FIP22 of the second fan-out line FIP2 and the end proximate to the second connection portion LJ2, thereby connecting one end of the second connection portion LJ2 to the redundant portion FIP22 of the second fan-out line FIP2 through the via K. In this manner, the redundant portion FIP12 of the first fan-out line FIP1 and the redundant portion FIP22 of the second fan-out line FIP2 are connected via the second connection portion LJ2, thereby increasing the wiring area of ​​the first voltage signal line VSS within the display area AA and increasing the density of the first voltage signal line VSS within the display area AA. The parallel arrangement of the redundant portion FIP12 of the first fan-out line FIP1 and the redundant portion FIP22 of the second fan-out line FIP2 facilitates reducing the resistance of the first voltage signal line VSS, thereby reducing the voltage drop across the first voltage signal line VSS.

[0161] In some embodiments, as shown in FIG. 9 , the second connection portion LJ2 and the redundant portion FIP12 of the first fan-out line FIP1 are provided in the same layer and are integrally formed.

[0162] For example, during the fabrication of the display substrate 100, a conductive structural layer is first formed, for example, by sputtering. Subsequently, the conductive structural layer is patterned, for example, by etching, to form the redundant portion FIP12 and the second connection portion LJ2 of the first fan-out line FIP1, which are connected to each other. In this way, the redundant portion FIP12 and the second connection portion LJ2 of the first fan-out line FIP1 are formed simultaneously in the same fabrication step. Furthermore, the second connection portion LJ2 and the redundant portion FIP12 of the first fan-out line FIP1 are integrally connected, eliminating the need for additional structures to connect them. While the redundant portion FIP12 and the second connection portion LJ2 of the first fan-out line FIP1 are added, no additional fabrication steps are required for the display substrate 100, thereby reducing production costs.

[0163] It should be noted that the redundant portion FIP12 of the first fan-out line FIP1 and the second connection portion LJ2 may also be prepared using other methods, which are only illustrative and not intended to limit the present disclosure.

[0164] In some embodiments, as shown in Figures 3 and 4, the display substrate 100 further includes a plurality of reference voltage signal lines VRef1. The reference voltage signal lines VRef1 extend along the second direction Y, and each column of pixel circuits 10 is electrically connected to a reference voltage signal line VRef1. In two adjacent columns of pixel circuits 10, the reference voltage signal line VRef1 connected to one column of pixel circuits 10 and the data line DL connected to the other column of pixel circuits 10 are arranged adjacent to each other. The second fan-out line FIP2 is arranged between the adjacent reference voltage signal line VRef1 and the data line DL.

[0165] For example, as shown in Figures 3 and 4 , each column of pixel circuits 10 is electrically connected to a data line DL and a reference voltage signal line VRef1. A column of pixel circuits 10 extends along the second direction Y, and the data line DL and the reference voltage signal line VRef1 corresponding to the column of pixel circuits 10 are located on both sides of the pixel circuit 10 along the first direction X. A second fan-out line FIP2 is inserted between two adjacent columns of pixel circuits 10 to lead the set data line DL1 from the display area AA to the binding area BB.

[0166] In some embodiments, as shown in FIG. 3 and FIG. 4 , the first voltage signal line VSS of the display substrate 100 is disposed between the reference voltage signal line VRef1 and the data line DL, which are disposed adjacent to each other.

[0167] For example, as shown in FIG3 and FIG4 , the data lines DL and the reference voltage signal line VRef1 corresponding to a column of pixel circuits 10 are located on both sides of the pixel circuit 10 along the first direction X. Inserting a first voltage signal line VSS between two adjacent columns of pixel circuits 10 increases the density of the first voltage signal lines VSS in the display area AA, thereby reducing the overall resistance of the first voltage signal lines VSS, facilitating reduction of the voltage drop of the first voltage signal lines VSS, and ensuring the transmission stability and reliability of the first voltage signal.

[0168] In some embodiments, as shown in FIG. 11 , the pixel circuit 10 includes a plurality of transistors TFTs and at least one capacitor.

[0169] For example, the pixel circuit 10 may be a "3T1C" circuit, a "7T1C" circuit, an "8T1C" circuit, or a "9T2C" circuit, where "T" refers to a TFT, and the number before "T" refers to the number of TFTs; "C" refers to a capacitor, and the number before "C" refers to the number of capacitors. In the embodiments of the present disclosure, the pixel circuit 10 is illustrated as a "9T2C" circuit, but the embodiments of the present disclosure are not limited thereto, and any other pixel circuit 10 may also be considered as long as the same technical concept is applied.

[0170] For example, as shown in FIG11 , an equivalent circuit diagram of a pixel circuit 10 in a 9T2C mode is shown. In this case, the pixel circuit 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and signal lines electrically connected to the pixel circuit 10 (e.g., a data signal line DL, a first enable signal line EM1, a second enable signal line EM2, an initialization signal line Vinit, a first voltage signal line VSS, a second voltage signal line VDD, etc.).

[0171] For example, as shown in FIG11 , each pixel circuit 10 is correspondingly connected to three gate signal lines GL, namely a first gate signal line GL1 , a second gate signal line GL2 and a third gate signal line GL3 .

[0172] A gate of the first transistor T1 is electrically connected to the third gate signal line GL3 , a first electrode of the first transistor T1 is electrically connected to the first initialization signal line Vinit1 , and a second electrode of the first transistor T1 is electrically connected to the first node N1 .

[0173] A gate of the second transistor T2 is electrically connected to the second gate signal line GL2 , a first electrode of the second transistor T2 is electrically connected to the first node N1 , and a second electrode of the second transistor T2 is electrically connected to the third node N3 .

[0174] A gate of the third transistor T3 is electrically connected to the first node N1 , a first electrode of the third transistor T3 is electrically connected to the second node N2 , and a second electrode of the third transistor T3 is electrically connected to the third node N3 .

[0175] A gate of the fourth transistor T4 is electrically connected to the first gate signal line GL1 , a first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5 .

[0176] A gate of the fifth transistor T5 is electrically connected to the first enable signal line EM1 , a first electrode of the fifth transistor T5 is electrically connected to the second voltage signal line VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2 .

[0177] A gate of the sixth transistor T6 is electrically connected to the second enable signal line EM2 , a first electrode of the sixth transistor T6 is electrically connected to the third node N3 , and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4 .

[0178] A gate of the seventh transistor T7 is electrically connected to the scan signal line Scan, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0179] A gate of the eighth transistor T8 is electrically connected to the scan signal line Scan, a first electrode of the eighth transistor T8 is electrically connected to the second reference voltage signal line VRef2, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0180] A gate of the ninth transistor T9 is electrically connected to the second gate signal line GL2 , a first electrode of the ninth transistor T9 is electrically connected to the first reference voltage signal line VRef1 , and a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5 .

[0181] The first plate C11 of the first capacitor C1 is electrically connected to the fifth node N5 , and the second plate C12 of the first capacitor C1 is electrically connected to the first node N1 .

[0182] A first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5 , and a second plate C22 of the second capacitor C2 is electrically connected to the second voltage signal line VDD.

[0183] The fifth node N5 is electrically connected to the first capacitor C1 and the second capacitor C2 , and a voltage change of the fifth node N5 may cause a change in the stored voltages of the first capacitor C1 and the second capacitor C2 .

[0184] In some embodiments, as shown in FIG12 , a display substrate 100 includes a substrate 1, a semiconductor layer 2, a multi-layer gate layer 3, and a multi-layer source / drain conductive layer 4. The multi-layer source / drain conductive layer 4 can be collectively referred to as a functional film layer in the display substrate 100. Each functional film layer has a predetermined conductive pattern, and adjacent functional film layers are separated by an insulating film structure.

[0185] For example, the substrate 1 may be a rigid substrate, the material of which includes, but is not limited to, glass. Alternatively, the substrate 1 may be a flexible substrate, the material of which includes, but is not limited to, any one of PI (Polyimide), PC (Polycarbonate), or PVC (Polyvinyl Chloride).

[0186] 12 and 13 , the semiconductor layer 2 includes an active layer pattern. As shown in FIG13 , the active layer pattern includes an active layer 21 of each transistor TFT.

[0187] In some examples, the thin film transistor TFT may be a low-temperature polysilicon thin film transistor, that is, the semiconductor layer 2 is made of low-temperature polysilicon.

[0188] In some other examples, the thin film transistor TFT may also be an oxide thin film transistor, that is, the semiconductor layer 2 is made of metal oxide, such as indium gallium zinc oxide or indium gallium tin oxide.

[0189] In some embodiments, as shown in FIG. 12 , the multi-layer gate layer 3 includes a first gate layer 31 and a second gate layer 32 sequentially disposed from one side of the substrate 1 .

[0190] Exemplarily, as shown in FIG14 , the first gate layer 31 includes a first gate conductive pattern, which overlaps with the orthographic projection of the active layer pattern on the substrate 1 , and the overlapping portion of the first gate conductive pattern and the active layer pattern serves as the gate of each transistor TFT.

[0191] In some examples, as shown in FIG. 14 , the first gate conductive pattern includes a scan signal line Scan extending along a first direction X, and the scan signal line Scan is configured to transmit a scan signal to the transistor TFT.

[0192] In some embodiments, as shown in FIG. 12 and FIG. 14 , the second gate layer 32 includes a second gate conductive pattern, and the second gate conductive pattern includes the auxiliary reference voltage signal line VRef11 .

[0193] Exemplarily, as shown in FIG. 14 , the auxiliary reference voltage signal line VRef11 extends along the first direction X and is connected to the reference voltage signal line VRef1 .

[0194] For example, as shown in FIG14 , the second gate conductive pattern includes a plurality of signal lines extending along a first direction X, such as an auxiliary reference voltage signal line VRef11, a second reference voltage signal line VRef2, a first initialization signal line Vinit1, a second enable signal line EM2, and a repair signal line Repair. The first initialization signal line Vinit1 is configured to transmit an initialization signal to the transistor TFT. The second enable signal line EM2 is configured to transmit a light emission control signal to the transistor TFT.

[0195] In some embodiments, as shown in FIG12 , the display substrate 100 further includes a multi-layer gate insulating layer 5 . The multi-layer gate insulating layer 5 includes a first gate insulating layer 51 disposed between the semiconductor layer 2 and the first gate layer 1 , and a second gate insulating layer 52 disposed between the first gate layer 31 and the second gate layer 32 .

[0196] In some embodiments, as shown in FIG14 , the first gate conductive pattern includes a first plate pattern, which includes the first plates (e.g., the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2) of the capacitors (e.g., the first capacitor C1 and the second capacitor C2) of each pixel circuit 10. The second gate layer 32 also includes a second plate pattern, which includes the second plates (e.g., the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2) of each pixel circuit 10.

[0197] As shown in FIG14 , the orthographic projections of the first plate pattern and the second plate pattern on the substrate 1 overlap. The second plate C12 of the first capacitor C1 overlaps with the first plate C11 to form the first capacitor C1, and the second plate C22 of the second capacitor C2 overlaps with the first plate C21 to form the second capacitor C2.

[0198] In some embodiments, as shown in Figures 3, 4, and 12, a pair of adjacent source-drain conductive layers 4 in the multi-layer source-drain conductive layer 4 are respectively a first designated source-drain conductive layer and a second designated source-drain conductive layer, wherein the first designated source-drain conductive layer is closer to the substrate 1 than the second designated source-drain conductive layer. The first fan-out line FIP1 is provided in the first designated source-drain conductive layer, and the data line DL and the second fan-out line FIP2 are provided in the second designated source-drain conductive layer.

[0199] Exemplarily, as shown in Figure 15, an insulating dielectric layer ILD is provided between the second gate layer 32 and the first source-drain conductive layer 41, the second gate layer 32 is electrically insulated from the first source-drain conductive layer 41, and a via is provided on the insulating dielectric layer ILD. The second gate conductive pattern in the second gate layer 32 and the part of the first conductive pattern in the first source-drain conductive layer 41 that needs to be connected are electrically connected through the via on the insulating dielectric layer ILD.

[0200] Exemplarily, an insulating spacer layer (e.g., planarization layer 6) is further provided between the first set source-drain conductive layer and the second set source-drain conductive layer. The first set source-drain conductive layer and the second set source-drain conductive layer are electrically insulated. Vias are provided in the insulating spacer layer, and portions of the first set source-drain conductive layer and the second set source-drain conductive layer that need to be connected can be electrically connected through the vias in the insulating spacer layer. One end of the first fan-out line FIP1 is connected to the set data line DL1 through a via, and the other end is connected to the second fan-out line FIP2 through another via.

[0201] The first set source-drain conductive layer includes a first fan-out line FIP1 extending along a first direction X, and may also include other signal lines extending along the first direction X. The second set source-drain conductive layer includes a second fan-out line FIP2 and a data line DL extending along a second direction Y, and may also include other signal lines extending along the second direction Y. With this design, the multiple signal lines included in each source-drain conductive layer can all extend in the same direction, simplifying the structure of the conductive pattern within, thereby simplifying the fabrication process of the source-drain conductive layer.

[0202] At the same time, the data lines DL (set data lines DL1) located on both sides of the display area AA along the first direction X can be led out from the display area AA to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2, thereby reducing the width of the peripheral area AN of the display substrate 100 on the side of the binding area BB, and further reducing the border width of the side of the display device 1000 used for binding the driver.

[0203] As shown in Figures 14 and 15 , the first fan-out line FIP1 is provided in the first set source-drain conductive layer, and the auxiliary reference voltage signal line VRef11 is located in the second gate layer 32. Along the thickness direction of the display substrate 100, the auxiliary reference voltage signal line VRef11 is located above the fifth node N5. The first fan-out line FIP1 is also located above the auxiliary reference voltage signal line VRef11. In other words, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1.

[0204] The auxiliary reference voltage signal line VRef11 is configured to transmit a reference voltage signal, which is a constant voltage signal. In this way, the auxiliary reference voltage line VRef11 between the fifth node N5 and the first fan-out line FIP1 can play a shielding effect, preventing signal crosstalk between the data signal transmitted on the first fan-out line FIP and the fifth node N5, thereby ensuring the normal operation of the pixel circuit 10.

[0205] In some embodiments, as shown in Figures 3 and 4, the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41 and a second source-drain conductive layer 42. The first source-drain conductive layer 41 is a first set source-drain conductive layer, and the second source-drain conductive layer 42 is a second set source-drain conductive layer.

[0206] Exemplarily, the first fan-out line FIP1 is disposed in the first source-drain conductive layer 41 , and the data line DL and the second fan-out line FIP2 are disposed in the second source-drain conductive layer 42 .

[0207] 15 , the first source-drain conductive layer 41 includes a first source-drain conductive pattern, which includes a source electrode 411 and a drain electrode 412 of each transistor TFT. The source electrode 411 and the drain electrode 412 may be structurally identical, and thus the source electrode 411 and the drain electrode 412 of the transistor TFT may be interchangeable.

[0208] 15 , the first source-drain conductive pattern further includes a first gate line GL1, a second gate line GL2, a third gate line GL3, a first fan-out line FIP1, an auxiliary second voltage signal line DIP, an auxiliary first voltage signal line SIP, and a first enable signal line EM1 extending along a first direction X. The first enable signal line EM1 is configured to transmit a light emission control signal to the transistor TFT.

[0209] 14 and 15 , an opening is provided on the second electrode plate C22 of the second capacitor C2, and the first source-drain conductive layer 41 further includes a connecting line LX, one end of the connecting line LX is connected to the first electrode plate C21 of the second capacitor C2 through the opening, and the other end is connected to the fifth node N5 in the dotted box in FIG. 14 .

[0210] 14 and 15 , the auxiliary reference voltage signal line VRef11 is located above the fifth node N5, and the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11 along the thickness direction of the display substrate 100. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1.

[0211] The auxiliary reference voltage signal line VRef11 is configured to transmit a reference voltage signal, which is a constant voltage signal. In this way, the auxiliary reference voltage line VRef11 between the fifth node N5 and the first fan-out line FIP1 can play a shielding effect, preventing signal crosstalk between the data signal transmitted on the first fan-out line FIP and the fifth node N5, thereby ensuring the normal operation of the pixel circuit 10.

[0212] Exemplarily, as shown in FIG12 , the display substrate 100 further includes a multi-layer planarization layer 6, which includes a first planarization layer 61 and a second planarization layer 62. The first planarization layer 61 is disposed between the first source-drain conductive layer 41 and the second source-drain conductive layer 42, and the second planarization layer 62 is disposed on a side of the second source-drain conductive layer 42 away from the first source-drain conductive layer 41.

[0213] In some embodiments, as shown in FIG. 3 and FIG. 4 , the second source-drain conductive layer 42 includes a data line DL extending along the second direction Y, a first voltage signal line VSS, a second voltage signal line VDD, a second fan-out line FIP2 , and a reference voltage signal line VRef1 .

[0214] For example, as shown in FIG8 , a plurality of vias are provided on the first planarization layer 61, and the first voltage signal line VSS is electrically connected to the auxiliary first voltage signal line SIP through the vias on the first planarization layer 61, thereby increasing the number of signal lines for transmitting the first voltage signal in the display area AA without increasing the film layer structure, increasing the wiring density of the signal lines for transmitting the first voltage signal in the display area AA, and reducing the resistance of the first voltage signal line VSS.

[0215] Exemplarily, as shown in Figure 8, the second voltage signal line VDD is electrically connected to the auxiliary first voltage signal line DIP through a via on the first planarization layer 61, thereby increasing the number of signal lines for transmitting the second voltage signal in the display area AA without increasing the film layer structure, increasing the wiring density of the signal lines for transmitting the second voltage signal in the display area AA, and reducing the resistance of the second voltage signal line VDD.

[0216] In some embodiments, the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41 , a second source-drain conductive layer 42 and a third source-drain conductive layer 43 , wherein the first source-drain conductive layer 41 is a first set source-drain conductive layer and the second source-drain conductive layer 42 is a second set source-drain conductive layer.

[0217] Exemplarily, the first fan-out line FIP1 is disposed in the first source-drain conductive layer 41 , and the data line DL and the second fan-out line FIP2 are disposed in the second source-drain conductive layer 42 .

[0218] Exemplarily, as shown in FIG. 12 , the multi-layer planarization layer 6 further includes a third planarization layer 63 , which is disposed on a side of the third source-drain conductive layer 43 away from the second source-drain conductive layer 42 .

[0219] In some embodiments, the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41, a second source-drain conductive layer 42 and a third source-drain conductive layer 43, the second source-drain conductive layer 42 is a first set source-drain conductive layer, and the third source-drain conductive layer 43 is a second set source-drain conductive layer.

[0220] Exemplarily, the second source-drain conductive layer 42 is a first set source-drain conductive layer, and the third source-drain conductive layer 43 is a second set source-drain conductive layer. The first fan-out line FIP1 is provided in the second source-drain conductive layer 42, and the data line DL and the second fan-out line FIP2 are provided in the third source-drain conductive layer 43.

[0221] It should be noted that the display substrate 100 may include two semiconductor layers, wherein the material of one semiconductor layer includes, for example, low-temperature polysilicon, and the material of the other semiconductor layer includes, for example, metal oxide. The active layers of the multiple transistors TFT included in the pixel circuit 10 are respectively located in the two semiconductor layers. In this way, the multiple transistors TFT included in the pixel circuit 10 include some low-temperature polysilicon thin-film transistors and some oxide thin-film transistors.

[0222] In some embodiments, as shown in Figures 14 and 15 , the display substrate 100 further includes a plurality of auxiliary reference voltage signal lines VRef11 disposed on a side of the semiconductor layer 2 away from the substrate 1. The auxiliary reference voltage signal lines VRef11 extend along a first direction X and are electrically connected to the reference voltage signal line VRef1. A first fan-out line FIP1 is disposed on a side of the auxiliary reference voltage signal line VRef11 away from the substrate 1. In an orthographic projection onto the substrate 1, the first fan-out line FIP1 overlaps the auxiliary reference voltage signal line VRef11 and partially overlaps the semiconductor layer 2.

[0223] Along the thickness direction of the display substrate 100, the auxiliary reference voltage signal line VRef11 is located above the fifth node N5, and the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1. As such, the auxiliary reference voltage signal transmitted by the auxiliary reference voltage signal line VRef11 is a constant voltage signal, which provides a shielding effect, preventing signal crosstalk between the data signal transmitted on the first fan-out line FIP and the fifth node N5, thereby ensuring normal operation of the pixel circuit 10.

[0224] It should be noted that the first fan-out line FIP1 extends along the first direction X, and a shielding structure is provided between the first fan-out line FIP1 and the fifth node N5 of the adjacent row of pixel circuits 10 to prevent signal crosstalk between the data signal transmitted by the first fan-out line FIP1 and the fifth node N5 of the pixel circuits 10. The shielding structure may be an auxiliary reference voltage signal line VRef11 located between the first fan-out line FIP1 and the fifth node N5 along the thickness direction of the display substrate 100, or may be another signal line that transmits a constant voltage signal.

[0225] 6 and 7 , the display substrate 100 further includes a plurality of second voltage signal lines VDD extending along the second direction Y. A column of pixel circuits 10 is electrically connected to a second voltage signal line VDD.

[0226] The film layer where the plurality of second voltage signal lines VDD are located is located on the side of the film layer where the first fan-out line FIP1 is located away from the substrate 1 . In the orthographic projection onto the substrate 1 , the second voltage signal line VDD covers the first break DK1 of the first fan-out line FIP1 .

[0227] For example, as shown in Figures 6 and 7 , the first fan-out line FIP1 is located on the first source-drain conductive layer 41, and the second voltage signal line VDD is located on the second source-drain conductive layer 42. The orthographic projection of the first break DK1 on the first fan-out line FIP1 on the display substrate 100 falls within the range of the orthographic projection of the second voltage signal line VDD on the display substrate 100. That is, the first break DK1 is blocked by the second voltage signal line VDD. When ambient light from the side of the substrate 1 away from the first source-drain conductive layer 41 is emitted toward the substrate 1, the portion of the ambient light emitted toward the first fan-out line FIP1 without the break DK1 can be blocked and reflected by the first fan-out line FIP1, while the portion of the ambient light emitted toward the first break DK1 can be blocked and reflected by the second voltage signal line VDD. This reduces the difference in light reflectivity between the first source-drain conductive layer 41 at the first break DK1 and at the portion without the first break DK1, effectively mitigating the screen-off mura phenomenon caused by the first break DK1.

[0228] Exemplarily, the number of the second breaks DK2 on the second fan-out line FIP2 is greater than or equal to the number of the first breaks DK1 on the first fan-out line FIP1.

[0229] In some examples, as shown in Figures 5, 6, and 7, in a first fan-out line FIP1 and a second fan-out line FIP2 connected to a data line DL1, the number of second breaks DK2 on the second fan-out line FIP2 is half the number of first breaks DK1 on the first fan-out line FIP1. For example, each first fan-out line FIP1 is provided with two first breaks DK1, and each second fan-out line FIP2 is provided with one second break DK2.

[0230] In other examples, in a first fan-out line FIP1 and a second fan-out line FIP2 connected to the data line DL1, the number of second breaks DK2 on the second fan-out line FIP2 is equal to the number of first breaks DK1 on the first fan-out line FIP1. For example, each first fan-out line FIP1 is provided with a first break DK1, and each second fan-out line FIP2 is provided with a second break DK2.

[0231] It will be understood that, referring to Figures 3 and 5 , the length of the first fan-out line FIP1 along the first direction X is, for example, the same or substantially the same as the length of the display area AA along the first direction X, and the length of the second fan-out line FIP1 along the second direction Y is, for example, the same or substantially the same as the length of the display area AA along the second direction Y. One end of the active portion FIP21 of the second fan-out line FIP2 extends to the binding area BB, and the other end extends along the second direction Y toward the display area AA and is connected to one end of the active portion FIP11 of the first fan-out line FIP1. The other end of the active portion FIP11 of the first fan-out line FIP1 is connected to a set data line DL1.

[0232] When no other signal line is disposed between the setting data line DL1 and the boundary of the display area AA extending along the second direction Y, a first break DK1 may be disposed on the first fan-out line FIP1 connected to the setting data line DL1 .

[0233] When other signal lines, such as the first voltage line VSS or the second voltage line VDD, are provided between the set data line DL1 and the boundary of the display area AA extending along the second direction Y, two first breaks DK1 can be provided on the first fan-out line FIP1 connected to the set data line DL1. The two first breaks DK1 are located on either side of the set data line DL1 along the first direction X. In this way, the first fan-out line FIP1 has two redundant portions FIP12. These two redundant portions FIP12 can be respectively connected to two signal lines (e.g., the first voltage signal line VSS or the second voltage signal line VDD), thereby increasing the wiring density of the signal lines connected thereto within the display area AA, thereby reducing the resistance of the connected signal lines.

[0234] The specific design of the fractures on the first fan-out line FIP1 and the second fan-out line FIP2 can be adaptively designed according to actual needs, which is only an example description and does not limit the present disclosure.

[0235] In some embodiments, as shown in Figures 3, 4, and 6, the display substrate 100 further includes: a gate signal line GL1, an enable signal line EM, an auxiliary first voltage signal line SIP, and an auxiliary second voltage signal line DIP, all extending along a first direction X. The pixel circuit 10 is electrically connected to the gate signal line GL1 and the enable signal line EM. The auxiliary first voltage signal line SIP is electrically connected to the first voltage signal line VSS, and the auxiliary second voltage signal line DIP is electrically connected to the second voltage signal line VDD.

[0236] The first set source / drain conductive layer includes at least one of a gate signal line GL1, an enable signal line EM, an auxiliary first voltage signal line SIP, and an auxiliary second voltage signal line DIP. In an orthographic projection onto substrate 1, at least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP, and the auxiliary second voltage signal line DIP overlaps a second break DK2 of the second fan-out line FIP2.

[0237] Exemplarily, the enable signal line EM includes a first enable signal line EM1 and a second enable signal line EM2 , and the pixel circuit 10 is electrically connected to the first enable signal line EM1 and the second enable signal line EM2 .

[0238] When the display substrate 100 includes two source-drain conductive layers 4, the first set source-drain conductive layer is the first source-drain conductive layer 41. When the display substrate 100 includes three source-drain conductive layers 4, the first set source-drain conductive layer is the first source-drain conductive layer 41 or the second source-drain conductive layer 42. The following description takes the first set source-drain conductive layer as the first source-drain conductive layer 41 and the second set source-drain conductive layer as the second source-drain conductive layer 42 as an example.

[0239] At least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP is located in the first set source-drain conductive layer, the second fan-out line FIP2 is located in the second set source-drain conductive layer, and the first set source-drain conductive layer is located between the second set source-drain conductive layer and the substrate 1. In this way, when at least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP in the first set source-drain conductive layer covers the second break DK2 of the second fan-out line FIP2, it can achieve a signal shielding effect, thereby avoiding the data signal transmitted by the second fan-out line FIP2 passing through the pixel circuits 10 of adjacent sub-pixels P(x) from generating signal crosstalk with the nodes in the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.

[0240] As shown in FIG6 , the transverse signal line in the first source / drain conductive layer 41 overlapping the second break DK2 may be at least one of the gate signal line GL1 , the enable signal line EM, the auxiliary first voltage signal line SIP, or the auxiliary second voltage signal line DIP.

[0241] In some embodiments, as shown in FIG. 12 and FIG. 15 , the first voltage signal line VSS, the second voltage signal line VDD, and the reference voltage signal line VRef1 of the display substrate 100 are all disposed in the second set source-drain conductive layer.

[0242] The first voltage signal line VSS, the second voltage signal line VDD and the reference voltage signal line VRef1 in the second set source-drain conductive layer can block the first break DK1 on the first fan-out line FIP1 in the first set source-drain conductive layer, thereby preventing the data signal transmitted by the first fan-out line FIP1 from generating signal crosstalk between the first break DK1 position and the node in the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.

[0243] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising a display area and a binding area, wherein the binding area is located on one side of the display area along a second direction; The display substrate comprises: A plurality of pixel circuits, wherein the plurality of pixel circuits are arranged in a plurality of rows and columns, wherein a row of pixel circuits is arranged along a first direction, and a column of pixel circuits is arranged along a second direction, and the first direction and the second direction intersect; a plurality of data lines, the data lines extending along the second direction, a column of pixel circuits being electrically connected to one of the data lines; A first fan-out line and a second fan-out line are provided in the display area; the first fan-out line extends along the first direction, and the second fan-out line extends along the second direction; at least one of the plurality of data lines is a setting data line, and the second fan-out line is closer to a center line of the binding area along the second direction than the setting data line; one end of the first fan-out line is electrically connected to the setting data line, and the other end is electrically connected to the second fan-out line; Wherein, the display substrate comprises a plurality of pixels, each pixel comprises at least three sub-pixels, and each sub-pixel comprises one pixel circuit; At least one of the multiple pixels is a setting pixel, and one of the setting pixels is correspondingly provided with at least one second fan-out line, and the second fan-out line passes between pixel circuits of two adjacent sub-pixels in the corresponding setting pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding setting pixel, and extends to the binding area.

2. The display substrate according to claim 1, wherein: The display substrate further comprises: A first voltage signal line extends along the second direction; one of the set pixels is correspondingly provided with at least one of the first voltage signal lines, and the first voltage signal line passes between pixel circuits of two adjacent sub-pixels in the corresponding set pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding set pixel.

3. The display substrate according to claim 2, wherein: Among the at least one second fan-out line and at least one first voltage signal line corresponding to the set pixel, one second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels, and one first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels.

4. The display substrate according to claim 3, wherein: The pixel includes three sub-pixels; The setting pixel is correspondingly provided with a second fan-out line and a first voltage signal line, the second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels among the three sub-pixels, and the first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels among the three sub-pixels.

5. The display substrate according to claim 2, wherein: Among the second fan-out lines and the first voltage signal lines corresponding to the setting pixel, one first voltage signal line and one second fan-out line pass between pixel circuits of the same pair of adjacent sub-pixels.

6. The display substrate according to claim 5, wherein: The pixel includes three sub-pixels; The setting pixel is correspondingly provided with one of the second fan-out lines and one of the first voltage signal lines, and the second fan-out line and the first voltage signal line pass between pixel circuits of a same pair of adjacent sub-pixels among the three sub-pixels.

7. The display substrate according to claim 5 or 6, wherein: The second fan-out line is provided with a second break, and the second break divides the second fan-out line into a valid part and a redundant part; one end of the valid part of the second fan-out line is electrically connected to the first fan-out line, and the other end extends to the binding area; The display substrate further includes a first connection portion, through which the first voltage signal line and a redundant portion of the second fan-out line are electrically connected.

8. The display substrate according to claim 7, wherein: The first voltage signal line and the second fan-out line passing through the pixel circuits of the same pair of adjacent sub-pixels are arranged adjacent to each other, and the first voltage signal line, the second fan-out line and the first connecting portion are arranged in the same layer and are integrally formed.

9. The display substrate according to claim 7 or 8, wherein: The first fan-out line is provided with a first break, and the first break divides the first fan-out line into a valid part and a redundant part; one end of the valid part of the first fan-out line is electrically connected to the set data line, and the other end is electrically connected to the valid part of the second fan-out line; The display substrate further includes: a second connection portion, one end of which is electrically connected to a redundant portion of the first fan-out line; A via hole is provided between the second connection portion and the redundant portion of the second fan-out line along the thickness direction of the display substrate, and the other end of the second connection portion is electrically connected to the redundant portion of the second fan-out line through the via hole.

10. The display substrate according to claim 9, wherein: The second connection portion and the redundant portion of the first fan-out line are arranged in the same layer and are integrally formed.

11. The display substrate according to any one of claims 1 to 10, wherein: The display substrate further comprises: A plurality of reference voltage signal lines, wherein the reference voltage signal lines extend along the second direction, and one column of pixel circuits is electrically connected to one of the reference voltage signal lines; in two adjacent columns of pixel circuits, the reference voltage signal line connected to one column of pixel circuits and the data line connected to the other column of pixel circuits are arranged close to each other; Wherein, the second fan-out line is arranged between the reference voltage signal line and the data line which are arranged close to each other.

12. The display substrate according to claim 11, wherein: The first voltage signal line of the display substrate is arranged between the reference voltage signal line and the data line which are arranged close to each other.

13. The display substrate according to claim 11 or 12, wherein: The display substrate further comprises: substrate; a semiconductor layer disposed on the substrate; A plurality of auxiliary reference voltage signal lines are provided on a side of the semiconductor layer away from the substrate, the auxiliary reference voltage signal lines extend along the first direction and are electrically connected to the reference voltage signal lines; The first fan-out line is arranged on a side of the auxiliary reference voltage signal line away from the substrate; in an orthographic projection onto the substrate, the first fan-out line overlaps with the auxiliary reference voltage signal line and partially overlaps with the semiconductor layer.

14. The display substrate according to any one of claims 1 to 13, wherein: The display substrate further comprises: a plurality of second voltage signal lines, wherein the second voltage signal lines extend along the second direction, and a column of pixel circuits is electrically connected to one of the second voltage signal lines; The film layer where the plurality of second voltage signal lines are located is located at a position away from the substrate where the film layer where the first fan-out line is located. On one side, in an orthographic projection onto the substrate, the second voltage signal line covers the first break of the first fan-out line.

15. The display substrate according to any one of claims 1 to 14, wherein: The display substrate further comprises: A plurality of source-drain conductive layers, wherein a pair of adjacent source-drain conductive layers in the plurality of source-drain conductive layers are respectively a first set source-drain conductive layer and a second set source-drain conductive layer, and the first set source-drain conductive layer is closer to the substrate than the second set source-drain conductive layer; The first fan-out line is arranged in the first set source-drain conductive layer, and the data line and the second fan-out line are arranged in the second set source-drain conductive layer.

16. The display substrate according to claim 15, wherein: The display substrate further comprises: a gate signal line, an enable signal line, an auxiliary first voltage signal line and an auxiliary second voltage signal line, all extending along the first direction; the pixel circuit is electrically connected to the gate signal line and the enable signal line; the auxiliary first voltage signal line is electrically connected to the first voltage signal line, and the auxiliary second voltage signal line is electrically connected to the second voltage signal line; The first set source-drain conductive layer is provided with at least one of the gate signal line, the enable signal line, the auxiliary first voltage signal line and the auxiliary second voltage signal line; in the orthographic projection onto the substrate, at least one of the gate signal line, the enable signal line, the auxiliary first voltage signal line and the auxiliary second voltage signal line covers the second break of the second fan-out line.

17. The display substrate according to claim 15 or 16, wherein: The first voltage signal line, the second voltage signal line and the reference voltage signal line of the display substrate are all arranged on the second set source-drain conductive layer.

18. The display substrate according to any one of claims 15 to 17, wherein: The display substrate further comprises: a first gate layer and a second gate layer; the semiconductor layer of the display substrate, the first gate layer and the second gate layer are sequentially arranged in a direction away from the substrate and are located between the substrate and the multi-layer source-drain conductive layer; The auxiliary reference voltage signal line of the display substrate is arranged on the second gate layer.

19. The display substrate according to any one of claims 15 to 18, wherein: The multi-layer source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer, the first source-drain conductive layer is the first set source-drain conductive layer, and the second source-drain conductive layer is the second set source-drain conductive layer; or, The multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the first source-drain conductive layer is the first set source-drain conductive layer, and the second source-drain conductive layer is the second set source-drain conductive layer; or, The multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the second source-drain conductive layer is the first set source-drain conductive layer, and the third source-drain conductive layer is the second set source-drain conductive layer.

20. The display substrate according to any one of claims 1 to 19, wherein: Compared with other data lines in the plurality of data lines, the set data line is farther away from a center line of the binding area along the second direction; the set data line is entirely located in the display area, and ends of the other data lines extend to the binding area.

21. A display device, comprising: The display substrate according to any one of claims 1 to 20; A circuit board is electrically connected to the display substrate.

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