Pixel circuit and driving method therefor, display panel, and display device

Abstract

A pixel circuit, comprising a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit and a storage sub-circuit. The driving sub-circuit is configured to control the connection and disconnection of a circuit between a second node and a third node under the control of the voltage of a first node. The compensation sub-circuit is configured to, in response to a first scanning signal received by a first scanning signal end, control the connection and disconnection of a circuit between the first node and the third node. The reset sub-circuit is configured to, in response to a reset signal received by a reset signal end, transmit to the first node a first initialization signal received by a first initialization signal end. The storage sub-circuit is coupled to a first voltage signal end, the first node and the second node. The storage sub-circuit is configured to store the voltages of the first node and the second node.

Description

Pixel circuit and driving method thereof, display panel, and display device

[0001] This application claims priority to Chinese patent application No. 202310799140.9, filed on June 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0003] With the rapid development of display technology, display devices have become increasingly ubiquitous in people's lives. Organic Light Emitting Diodes (OLEDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response, high contrast, and flexible display.

[0004] Summary of the Invention

[0005] In one aspect, a pixel circuit is provided, comprising a driving subcircuit, a compensation subcircuit, a reset subcircuit, and a storage subcircuit.

[0006] The driving sub-circuit is coupled to a first node, a second node, and a third node and is configured to control the conduction and cutoff of a circuit between the second node and the third node under the control of the voltage of the first node.

[0007] The compensation subcircuit is coupled to the first scan signal terminal, the first node, and the third node, and is configured to control the conduction and cutoff of the circuit between the first node and the third node in response to a first scan signal received at the first scan signal terminal.

[0008] The reset subcircuit is coupled to a first initialization signal terminal, a reset signal terminal, and the first node. The reset subcircuit is configured to transmit a first initialization signal received at the first initialization signal terminal to the first node in response to an operating voltage of the reset signal received at the reset signal terminal.

[0009] The storage sub-circuit is coupled to the first voltage signal terminal, the first node, and the second node, and is configured to store the voltages of the first node and the second node.

[0010] In some embodiments, the storage subcircuit includes a first storage capacitor and a second storage capacitor, wherein a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the first node. A first plate of the second storage capacitor is connected to the first voltage signal terminal, and a second plate of the second storage capacitor is connected to the second node.

[0011] In some embodiments, the compensation sub-circuit includes a first sub-transistor and a second sub-transistor connected in series, wherein the first terminal of the first sub-transistor is connected to the first node, the second terminal of the first sub-transistor and / or the first terminal of the second sub-transistor are connected to a fourth node, the second terminal of the second sub-transistor is connected to the third node, and the control electrodes of the first sub-transistor and the second sub-transistor are connected to the first scan signal terminal. The pixel circuit further includes a leakage prevention sub-circuit coupled to a control signal terminal, a constant voltage terminal, and the fourth node. The leakage prevention sub-circuit is configured to transmit a constant voltage signal received at the constant voltage terminal to the fourth node in response to an operating voltage of a control signal received at the control signal terminal.

[0012] In some embodiments, the pixel circuit further includes a light emission control subcircuit coupled to a first voltage signal terminal, an enable signal terminal, the second node, the third node, and a fifth node. The fifth node is connected to an anode of the light-emitting device. The light emission control subcircuit is configured to, in response to an enable signal received at the enable signal terminal, control the conduction and cutoff of a circuit between the first voltage signal terminal and the second node; and control the conduction and cutoff of a circuit between the third node and the fifth node. The signals received at the enable signal terminal and the control signal terminal are the same.

[0013] In some embodiments, the pixel circuit further includes a data writing subcircuit coupled to the data signal terminal, the second scan signal terminal, and the second node. The data writing subcircuit is configured to, in response to a first operating voltage of the second scan signal received at the second scan signal terminal, transmit the data signal received at the data signal terminal to the second node; and, in response to a second operating voltage of the second scan signal received at the second scan signal terminal, transmit a data refresh signal received at the data signal terminal to the second node; the data refresh signal is a data signal received by pixel circuits in other rows.

[0014] In some embodiments, the cutoff time of the first operating voltage of the second scanning signal is before the cutoff time of the operating voltage of the first scanning signal. Furthermore, the time interval between the cutoff time of the first operating voltage of the second scanning signal and the cutoff time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period. The row scanning period is the duration of one operating voltage of the second scanning signal.

[0015] In some embodiments, the start time of the first operating voltage of the second scanning signal is after the end time of the operating voltage of the reset signal. Furthermore, the time interval between the start time of the first operating voltage of the second scanning signal and the end time of the operating voltage of the reset signal is greater than or equal to one horizontal scanning period. The horizontal scanning period is the duration of one operating voltage of the second scanning signal.

[0016] In some embodiments, the transistor included in the compensation subcircuit is a P-type transistor. The duration of the operating voltage of the first scanning signal is greater than or equal to four horizontal scanning periods. The voltage of the first horizontal scanning period after the first scanning signal is activated is greater than the voltage of the second horizontal scanning period after the first scanning signal is activated. The horizontal scanning period is the duration of an operating voltage of the second scanning signal. The duration of the first operating voltage of the second scanning signal coincides with the 2Nth horizontal scanning period of the operating voltage of the first scanning signal, where N ≥ 2 and N is an integer.

[0017] In some embodiments, the start and end times of the second operating voltage of the second scanning signal are between the end time of the operating voltage of the first scanning signal and the start time of the operating voltage of the enable signal. Furthermore, the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period. The time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scanning period. The row scanning period is the duration of one operating voltage of the second scanning signal.

[0018] In some embodiments, the data writing sub-circuit is further configured to transmit the data holding signal received at the data signal terminal to the second node in response to a third operating voltage of the second scan signal received at the second scan signal terminal.

[0019] In some embodiments, the reset sub-circuit is further coupled to the second initialization signal terminal, the third scan signal terminal, and the fifth node. The reset sub-circuit is further configured to transmit the second initialization signal received at the second initialization signal terminal to the fifth node under control of the operating voltage of the third scan signal received at the third scan signal terminal.

[0020] In some embodiments, the reset signal's operating voltage starts before the first scan signal's operating voltage starts. Furthermore, the time interval between the start time of the reset signal's operating voltage and the start time of the first scan signal's operating voltage is greater than or equal to three horizontal scan periods. And / or, the reset signal's operating voltage ends after the first scan signal's operating voltage starts. Furthermore, the time interval between the cutoff time of the reset signal's operating voltage and the start time of the first scan signal's operating voltage is greater than or equal to two horizontal scan periods.

[0021] In another aspect, a method for driving a pixel circuit is provided. The method for driving a pixel circuit is used to drive the pixel circuit according to any of the above embodiments. A display frame includes a refresh frame, and the refresh frame includes a first reset phase and a second reset phase.

[0022] During the first reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal at the reset signal terminal. Furthermore, the storage subcircuit stores the voltage of the second node after the previous frame. During the second reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal at the reset signal terminal. The compensation subcircuit transmits the voltage of the first node to the third node in response to the operating voltage of the first scan signal received at the first scan signal terminal. Furthermore, the drive subcircuit transmits the voltage of the third node to the second node under control of the voltage of the first node.

[0023] In some embodiments, the pixel circuit further includes a data writing sub-circuit, and the refresh frame further includes a first data writing phase and a second data writing phase.

[0024] During the first data writing phase, the data writing sub-circuit transmits the data signal received at the data signal terminal to the second node in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal, and writes the data signal into the storage sub-circuit. The driving sub-circuit transmits the voltage of the second node to the third node under the control of the voltage of the first node. The compensation sub-circuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scanning signal received at the first scanning signal terminal.

[0025] During the second data writing phase, the storage sub-circuit discharges and transmits the stored data signal to the second node. The driving sub-circuit transmits the voltage of the second node to the third node under the control of the voltage of the first node. The compensation sub-circuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal terminal.

[0026] In some embodiments, the transistors included in the compensation subcircuit are P-type transistors; the second reset phase includes at least three horizontal scanning periods. During the second reset phase, the voltage during the first horizontal scanning period after the first scanning signal is activated is greater than the voltage during the second horizontal scanning period after the first scanning signal is activated. The first data writing phase occurs after the second reset phase and coincides with the 2Nth horizontal scanning period after the start of the second reset phase, where N ≥ 2 and N is an integer.

[0027] In some embodiments, the pixel circuit includes a data writing subcircuit, and the refresh frame further includes a third reset phase and a first light-emitting phase, wherein the third reset phase is located between the second data writing phase and the first light-emitting phase. During the third reset phase, the data writing subcircuit transmits a data refresh signal received at the data signal terminal to the second node in response to the second operating voltage of the second scan signal received at the second scan signal terminal.

[0028] In some embodiments, the difference between the start time of the third reset phase and the end time of the second data writing phase is greater than or equal to one row scanning period. And / or the difference between the end time of the third reset phase and the start time of the first light-emitting phase is greater than or equal to one row scanning period.

[0029] In some embodiments, a difference between a start time of the first reset phase and a start time of a frame in which the first reset phase is located is greater than or equal to two row scanning periods.

[0030] In some embodiments, the pixel circuit includes a data writing subcircuit, a leakage prevention subcircuit, and a light emission control subcircuit. The pixel circuit has a first refresh frequency and a second refresh frequency, wherein the second refresh frequency is less than the first refresh frequency. At the first refresh frequency, a display frame includes one refresh frame; at the second refresh frequency, a display frame includes one refresh frame and at least one hold frame. The hold frame includes a black insertion phase, a fourth reset phase, and a second light emission phase.

[0031] During the black insertion phase, the light emitting control subcircuit is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal.

[0032] In the fourth reset phase, the data writing sub-circuit transmits the data holding signal received at the data signal terminal to the second node in response to the third operating voltage of the second scan signal received at the second scan signal terminal.

[0033] In the second light-emitting stage, the light-emitting control subcircuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the operating voltage of the enable signal received at the enable signal terminal; the driving subcircuit generates a driving current signal based on the voltage of the first node and the voltage of the second node; and the light-emitting control subcircuit transmits the driving current signal to the light-emitting device in response to the operating voltage of the enable signal received at the enable signal terminal; the leakage prevention subcircuit transmits the constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of the control signal received at the control signal terminal.

[0034] In some embodiments, a difference between an end time of the fourth resetting phase and a start time of the second light-emitting phase is greater than or equal to one row scanning period.

[0035] In another aspect, a display panel is provided. The display device includes a plurality of pixel circuits according to any of the above embodiments. The plurality of pixel circuits are arranged in M ​​rows and N columns, with each row including N pixel circuits arranged along a first direction, and each column including M pixel circuits arranged along a second direction, where M>1, N>1, and both M and N are integers.

[0036] In some embodiments, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0037] The display panel also includes a first gate drive circuit, which includes M+Q cascaded first shift registers. From the first stage of the first shift register to the last stage of the first shift register, the M+Q first shift registers are the 1st to the M+Qth first shift registers, respectively. Each first shift register includes a first signal output terminal. The first scan signal terminal of the pixel circuit in the Pth row is connected to the first signal output terminal of the P+Qth first shift register; the reset signal terminal of the pixel circuit in the Pth row is connected to the first output terminal of the Pth first shift register; P ≤ M, Q > 0, and P and Q are both integers.

[0038] In some embodiments, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0039] The display panel also includes a second gate drive circuit and a third gate drive circuit. The second gate drive circuit includes M cascaded second shift registers, from the first stage second shift register to the last stage second shift register, and the M second shift registers are respectively the first to the Mth second shift registers. Each second shift register includes a second signal output terminal. The first scanning signal terminal of the pixel circuit in the Pth row is connected to the second signal output terminal of the Pth second shift register, where P≤M, and P is an integer.

[0040] The third gate drive circuit includes M cascaded third shift registers, with the M third shift registers being the first to the Mth third shift registers, respectively, from the first to the last third shift register. Each of the third shift registers includes a third signal output terminal. The reset signal terminal of the pixel circuit in the Pth row is connected to the third signal output terminal of the Pth third shift register, where P ≤ M, and P is an integer.

[0041] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0043] FIG1 is a structural diagram of a display device according to some embodiments;

[0044] FIG2 is a structural diagram of another display device according to some embodiments;

[0045] FIG3 is a cross-sectional view taken along section line AA′ in FIG1 ;

[0046] FIG4 is a structural diagram of a display panel according to some embodiments;

[0047] FIG5 is a cross-sectional view taken along section line CC' in FIG4;

[0048] FIG6 is a structural block diagram of a pixel circuit according to some embodiments;

[0049] FIG7 is a circuit diagram of the pixel circuit shown in FIG6 ;

[0050] FIG8A is a block diagram of another pixel circuit according to some embodiments;

[0051] FIG8B is a structural block diagram of yet another pixel circuit according to some embodiments;

[0052] FIG9A is a circuit diagram of the pixel circuit shown in FIG8A ;

[0053] FIG9B is a circuit diagram of the pixel circuit shown in FIG8B ;

[0054] FIG10 is a structural diagram of a gate driving circuit of a display panel according to some embodiments;

[0055] FIG11 is a structural diagram of another gate driving circuit of a display panel according to some embodiments;

[0056] FIG12 is a structural diagram of a gate driving circuit of another display panel according to some embodiments;

[0057] FIG13 is a timing diagram of a pixel circuit according to some embodiments;

[0058] FIG14 is another timing diagram of a pixel circuit according to some embodiments;

[0059] FIG. 15 is yet another timing diagram of a pixel circuit according to some embodiments. DETAILED DESCRIPTION

[0060] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0061] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0062] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0063] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0064] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0065] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0066] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0067] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0068] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0069] As used herein, "about," "approximately," or "substantially" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0070] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0071] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0072] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0073] In this specification, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that, unless expressly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted as an ideal or overly formal meaning.

[0074] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0075] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0076] In the embodiments of the present disclosure, the transistors used may be thin film transistors (TFT), metal oxide semiconductors (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0077] In the embodiments of the present disclosure, the control electrode of each thin film transistor used is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0078] In the embodiments of the present disclosure, the capacitor may be a capacitive device fabricated separately through a process, for example, by fabricating specialized capacitive electrodes, each of which may be implemented through a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor may also be a parasitic capacitor between transistors, or implemented through the transistor itself and other devices or circuits, or through the parasitic capacitance between circuits within the circuit itself.

[0079] In the embodiments of the present disclosure, the first node, the second node, the first control node, the second control node and other nodes do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes that are equivalent to the junction points of related electrical connections in the circuit diagram.

[0080] In the embodiments of the present disclosure, “operating voltage” refers to a voltage that can turn on the operated transistor included therein; correspondingly, “non-operating voltage” refers to a voltage that cannot turn on the operated transistor included therein.

[0081] In the embodiments of the present disclosure, "low level" refers to a voltage that can turn on the operated P-type transistor included therein, but cannot turn on the operated N-type transistor included therein (i.e., the N-type transistor is turned off); accordingly, "high level" refers to a voltage that can turn on the operated N-type transistor included therein, but cannot turn on the operated P-type transistor included therein (i.e., the P-type transistor is turned off).

[0082] As shown in FIG. 1 and FIG. 2 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 may be any device that displays an image, whether in motion (eg, video) or fixed (eg, still image), and whether textual or graphic.

[0083] For example, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.

[0084] For example, as shown in FIG1 , the display device 1000 may be a portable display product; for example, the display device 1000 may be the mobile phone shown in FIG1 . For another example, referring to FIG2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be the watch shown in FIG2 .

[0085] In the following, some embodiments of the present disclosure are schematically described by taking the display device 1000 as the mobile phone shown in FIG. 1 as an example, but the implementation manner of the present disclosure is not limited thereto.

[0086] In some embodiments, referring to FIG. 3 , a display device 1000 includes a display panel 100 .

[0087] The display panel 100 includes a light-emitting side and a non-light-emitting side that are opposite to each other. The light-emitting side is the side of the display panel 100 used for display, that is, the upper side in FIG3 .

[0088] For example, as shown in FIG3 , the display device 1000 may further include a housing 200 , a cover plate 300 , a circuit board 400 , and other electronic components.

[0089] 3 , the cover plate 300 may be a single-layer glass cover plate, or may include a stack of multiple sub-cover plates, which is not specifically limited in the embodiment of the present disclosure.

[0090] As shown in FIG3 , the longitudinal cross-section of the housing 200 may be, for example, U-shaped. The display panel 100 and the circuit board 400 are disposed within the housing 200, and the cover plate 300 is disposed at the opening of the housing 200. The circuit board 400 is disposed on a side of the display panel 100 away from the cover plate 300, and is connected to the display panel 100 to provide the display panel 100 with the required display signals.

[0091] The display panel 100 may be of various types and may be selected according to actual needs.

[0092] For example, the display panel 100 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, etc., which is not specifically limited in the embodiments of the present disclosure.

[0093] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0094] In some embodiments, referring to FIG. 5 , a display panel 100 includes a display substrate 110 and an encapsulation layer 120 for encapsulating the display substrate 110 .

[0095] The encapsulation layer 120 may be an encapsulation film or an encapsulation substrate, which is not specifically limited in the embodiment of the present disclosure.

[0096] In some embodiments, referring to FIG. 4 , the display panel 100 has a display area A, which is a region for displaying images and is configured to dispose a plurality of sub-pixels P.

[0097] Exemplarily, referring to FIG. 4 , the display panel 100 includes a substrate 11 and a plurality of sub-pixels P disposed on one side of the substrate 11 and located in a display area A.

[0098] There are many types of substrates 11, which can be selected according to actual needs.

[0099] For example, the substrate 11 may be a rigid substrate, such as a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0100] For another example, the substrate 11 may be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0101] 4 and 5 , each sub-pixel P includes a light emitting device 10 and a pixel circuit 20 . The pixel circuit 20 includes a plurality of thin film transistors 30 .

[0102] As shown in FIG. 5 , the thin film transistor 30 includes a semiconductor channel 31 , a source electrode 32 , a drain electrode 33 , and a gate electrode 34 . The source electrode 32 and the drain electrode 33 are both in contact with the semiconductor channel 31 .

[0103] As shown in Figure 5, the light-emitting device 10 includes a first electrode 11, a light-emitting functional layer 12 and a second electrode 13. The first electrode 11 is electrically connected to the source 32 or drain 33 of a thin-film transistor 30. Figure 5 shows the electrical connection between the first electrode 11 and the drain 33 of the thin-film transistor 30 as an example.

[0104] It should be noted that the above-mentioned light-emitting functional layer 12 may include only a light-emitting layer, or, in addition to the light-emitting layer, may also include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL) and a hole injection layer (HIL).

[0105] Currently, display devices use variable refresh rate display panels to meet user demands for low power consumption and high refresh rates. However, when displaying at a low frequency, the frame rate of the display panel decreases, making the human eye more sensitive to the flicker of the display panel, resulting in the human eye being able to perceive flicker on the display screen.

[0106] Research has found that the channel of the driving transistor in the pixel circuit itself exhibits a significant hysteresis effect due to the large number of defect states, resulting in the image of the previous moment (the previous frame cycle) often being retained in the image display of the next moment, causing the display screen to flicker.

[0107] It should be noted that the hysteresis effect refers to an uncertainty in the electrical characteristics of the driving transistor under a certain bias voltage, that is, the magnitude of the current of the driving transistor is not only related to the current bias voltage, but also to the bias state in the previous period.

[0108] Based on this, referring to FIG. 6 , some embodiments of the present disclosure provide a pixel circuit 20 , which includes a driving sub-circuit 21 , a compensation sub-circuit 22 , a reset sub-circuit 23 , and a storage sub-circuit 24 .

[0109] In some examples, as shown in FIG6 , the driver sub-circuit 21 is coupled to the first node N1, the second node N2, and the third node N3. The driver sub-circuit 21 is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the voltage of the first node N1; and to generate a drive current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0110] Exemplarily, as shown in Figure 7, the driving sub-circuit 21 includes an eighth transistor T8 (i.e., the driving transistor mentioned above), the first electrode of the eighth transistor T8 is connected to the second node N2, the second electrode of the eighth transistor T8 is connected to the third node N3, and the control electrode of the eighth transistor T8 is connected to the first node N1.

[0111] In some examples, as shown in FIG6 , the compensation sub-circuit 22 is coupled to the first scan signal terminal GATE1, the first node N1, and the third node N3. The compensation sub-circuit 22 is configured to control the conduction and cutoff of the circuit between the first node N1 and the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1.

[0112] Exemplarily, referring to Figure 7, the compensation sub-circuit 22 includes a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series, the first end of the first sub-transistor T1-1 is connected to the first node N1, the second end of the first sub-transistor T1-1 and / or the first end of the second sub-transistor T1-2 is connected to the fourth node N4, the second end of the second sub-transistor is connected to the third node N3, and the control electrodes of the first sub-transistor T1-1 and the second sub-transistor T1-2 are connected to the first scan signal terminal GATE1.

[0113] It should be noted that there may be other transistors connected in series between the first sub-transistor T1-1 and the second sub-transistor T1-2, that is, the compensation sub-circuit 22 may also include three, four or more transistors connected in series, which is not specifically limited in the embodiment of the present disclosure.

[0114] Below, some embodiments of the present disclosure are schematically illustrated by taking the compensation sub-circuit 22 including the first sub-transistor T1-1 and the second sub-transistor T1-2 connected in series as an example, but the implementation of the present disclosure is not limited to this, and it can also be considered that the compensation sub-circuit 22 includes three, four or more transistors connected in series, as long as the same technical concept is applied.

[0115] In some examples, as shown in FIG6 , the reset sub-circuit 23 is coupled to the first initialization signal terminal VINIT1, the reset signal terminal RESET, and the first node N1. The reset sub-circuit 23 is configured to, in response to the operating voltage of the reset signal received at the reset signal terminal RESET, transmit the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 to reset the voltage of the first node N1.

[0116] Exemplarily, referring to FIG7 , the reset sub-circuit 23 includes a plurality of fifth transistors T5 connected in series, one end of the plurality of fifth transistors T5 is connected to the first initialization signal terminal VINIT1, the other end is connected to the first node N1, and the control electrode of each fifth transistor T5 is connected to the reset signal terminal RESET.

[0117] For example, as shown in FIG. 7 , the reset sub-circuit 23 includes two fifth transistors T5 connected in series. The two fifth transistors T5 form a dual-gate transistor to reduce leakage current.

[0118] 13, 14, and 15, the reset signal's operating voltage starts before the first scan signal's operating voltage starts, and the interval between the reset signal's operating voltage and the first scan signal's operating voltage starts is greater than or equal to three row scan periods. FIG. 13 illustrates an example in which the interval between the reset signal's operating voltage and the first scan signal's operating voltage starts is eight row scan periods.

[0119] Furthermore, referring to Figures 13, 14, and 15, the reset signal's operating voltage cutoff time is after the first scan signal's operating voltage start time. Furthermore, the time interval between the reset signal's operating voltage cutoff time and the first scan signal's operating voltage start time is greater than or equal to two horizontal scanning periods. Figure 13 illustrates an example in which the time interval between the reset signal's operating voltage cutoff time and the first scan signal's operating voltage start time is three horizontal scanning periods.

[0120] 6 , the storage sub-circuit 24 is coupled to the first voltage signal terminal VDD, the first node N1, and the second node N2. The storage sub-circuit 24 is configured to store the voltages of the first node N1 and the second node N2.

[0121] Exemplarily, as shown in FIG7 , the storage sub-circuit 24 includes a first storage capacitor C1 and a second storage capacitor C2. The first plate of the first storage capacitor C1 is connected to the first voltage signal terminal VDD, and the second plate of the first storage capacitor C1 is connected to the first node N1. The first plate of the second storage capacitor C2 is connected to the first voltage signal terminal VDD, and the second plate of the second storage capacitor C2 is connected to the second node N2.

[0122] In this case, after a frame of display begins, the storage subcircuit 24 can store the voltage at the second node N2 after the previous frame of display ends, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal, thereby causing the first node N1 and the third node N3 of the driving subcircuit 21 to generate a stable and large bias voltage, improving the hysteresis characteristics of the driving subcircuit 21, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of flickering on the display screen that can be perceived by the human eye.

[0123] That is, after a frame of display begins, the second storage capacitor C2 can store the voltage at the second node N2 (i.e., the first electrode of the eighth transistor T8) after the previous frame of display ends, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal, thereby causing the first electrode (the second node N2) and the control electrode (the third node N3) of the eighth transistor T8 to generate a stable and large bias voltage, thereby improving the hysteresis characteristics of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of flickering on the display screen that can be perceived by the human eye.

[0124] In some embodiments, as shown in FIG. 8A , the pixel circuit 20 further includes a leakage prevention sub-circuit 25 .

[0125] In some examples, as shown in Figures 8A and 9B, the leakage prevention sub-circuit 25 is coupled to the control signal terminal K, the constant voltage terminal VC, and the fourth node N4. The leakage prevention sub-circuit 25 is configured to transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.

[0126] The voltage of the constant voltage signal is -7V to 7V. For example, the voltage of the constant voltage signal is any one of -7V, -6V, -5V, -4V, -3V, -2V, -1V, 0V, 1V, 2V, 3V, 4V, 5V, 6V, and 7V. Specifically, based on experimental tests, a voltage value with a better leakage prevention effect can be obtained as the actual voltage value of the constant voltage signal, which is not specifically limited in the embodiments of the present disclosure.

[0127] 9B , the leakage prevention sub-circuit 25 includes a second transistor T2 , a first electrode of the second transistor T2 is connected to the constant voltage terminal VC, a second electrode of the second transistor T2 is connected to the fourth node N4 , and a control electrode of the second transistor T2 is connected to the control signal terminal K.

[0128] In this case, during the light-emitting stage, the anti-leakage sub-circuit 25 can respond to the operating voltage of the control signal received at the control signal terminal K, and transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, so as to reduce the voltage difference between the fourth node N4 and the first node N1, reduce the risk of leakage of the first node N1, thereby reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering in the display screen.

[0129] In some embodiments, as shown in FIG. 8A , the pixel circuit 20 further includes a light emission control subcircuit 26 .

[0130] In some examples, as shown in FIG8A , the light emission control subcircuit 26 is coupled to the first voltage signal terminal VDD, the enable signal terminal EM, the second node N2, the third node N3, and the fifth node N5. The light emission control subcircuit 26 is configured to control the conduction and cutoff of the circuit between the first voltage signal terminal VDD and the second node N2, and to control the conduction and cutoff of the circuit between the third node N3 and the fifth node N5 in response to the enable signal received at the enable signal terminal EM.

[0131] Here, the first voltage signal may be a signal of the positive electrode of a DC power supply. For example, the first voltage signal may be 5V.

[0132] It should be noted that the fifth node N5 is connected to the anode of the light emitting device 10 so that the driving current signal can be transmitted to the light emitting device 10 .

[0133] For example, as shown in FIG9B , the light-emission control subcircuit 26 includes a third transistor T3 and a fourth transistor T4. A first electrode of the third transistor T3 is connected to the first voltage signal terminal VDD, a second electrode of the third transistor T3 is connected to the second node N2, and a control electrode of the third transistor T3 is connected to the enable signal terminal EM. A first electrode of the fourth transistor T4 is connected to the third node N3, a second electrode of the fourth transistor T4 is connected to the fifth node N5, and a control electrode of the fourth transistor T4 is connected to the enable signal terminal EM.

[0134] On this basis, as shown in FIG9B , the signals received at the enable signal terminal EM and the control signal terminal K are the same. In this way, the enable signal terminal EM and the control signal terminal K can be connected to the same signal line, such as a gate line mentioned below, to simplify the circuit structure. That is, during the light-emitting phase, the leakage prevention sub-circuit 25 transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the enable signal terminal EM, thereby reducing the voltage difference between the fourth node N4 and the first node N1, reducing the risk of leakage at the first node N1, and thereby reducing the flicker value of the display panel 100, thereby alleviating the problem of flickering on the display screen that can be perceived by the human eye.

[0135] In some embodiments, as shown in FIG. 8A , the pixel circuit 20 further includes a data writing sub-circuit 27 .

[0136] In some examples, as shown in FIG8A , the data write sub-circuit 27 is coupled to the data signal terminal DATA, the second scan signal terminal GATE2, and the second node N2. The data write sub-circuit 27 is configured to transmit the data signal received at the data signal terminal DATA to the second node N2 in response to a first operating voltage of the second scan signal received at the second scan signal terminal GATE2; and to transmit the data refresh signal received at the data signal terminal DATA to the second node N2 in response to a second operating voltage of the second scan signal received at the second scan signal terminal GATE2. The data refresh signal is a data signal received by pixel circuits 20 in another row, such as a data signal received by pixel circuits 20 in the next adjacent row.

[0137] It should be noted that the first operating voltage and the second operating voltage of the second scanning signal may be the same in magnitude, but the timings of the first operating voltage and the second operating voltage are different.

[0138] For example, referring to Figures 13, 14, and 15, the cutoff time of the first operating voltage of the second scanning signal is before the cutoff time of the operating voltage of the first scanning signal. Furthermore, the time interval between the cutoff time of the first operating voltage of the second scanning signal and the cutoff time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period H.

[0139] It should be noted that the row scanning period H is the duration of one operating voltage of the second scanning signal.

[0140] For example, as shown in FIG13 , the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is 5 row scanning periods H.

[0141] For example, referring to Figures 13, 14, and 15, the start time of the first operating voltage of the second scanning signal is after the end time of the operating voltage of the reset signal. Furthermore, the time interval between the start time of the first operating voltage of the second scanning signal and the end time of the operating voltage of the reset signal is greater than or equal to one row scanning period H.

[0142] For example, as shown in FIG13 , the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is 2 row scanning periods H.

[0143] In some embodiments, referring to FIG. 9B , the transistors included in the compensation sub-circuit 22 are P-type transistors. Furthermore, in conjunction with FIG. 13 , FIG. 14 , and FIG. 15 , the duration of the operating voltage of the first scanning signal is greater than or equal to four horizontal scanning periods H. The voltage during the first horizontal scanning period H after the first scanning signal is operating is greater than the voltage during the second horizontal scanning period H after the first scanning signal is operating. The horizontal scanning period H is the duration of one operating voltage of the second scanning signal. In other words, the stability of the first scanning signal output during even-numbered horizontal scanning periods H is greater than the stability during odd-numbered horizontal scanning periods H.

[0144] In the present disclosure, the voltage of the first row scanning period H after the first scanning signal is working can be understood as the first period after the effective level of the first scanning signal starts to be input, that is, the first row scanning period H after the first falling edge of the first scanning signal terminal GATE1 in Figure 13, that is, the first row scanning period H counted from left to right in the second reset stage P12; or, it can be understood as the first period after the level used to turn on the first sub-transistor T1-1 in Figure 9A is input.

[0145] In the present disclosure, the voltage of the second row scanning period H after the first scanning signal is working can be understood as the second period after the effective level of the first scanning signal starts to be input, that is, the second row scanning period H after the first falling edge of the first scanning signal terminal GATE1 in Figure 13, that is, the second row scanning period H counted from left to right in the second reset stage P12; or, it can be understood as the second period after the level for turning on the first sub-transistor T1-1 in Figure 9A is input.

[0146] On this basis, the time of the first working voltage of the second scanning signal coincides with the 2Nth row scanning period H of the working voltage of the first scanning signal, where N≥2, and N is an integer.

[0147] Exemplarily, as shown in FIG13 , the duration of the working voltage of the first scanning signal is 11 row scanning periods H, and the time of the first working voltage of the second scanning signal coincides with the 6th row scanning period H of the working voltage of the first scanning signal, that is, N=3.

[0148] In addition, referring to FIG. 13 , FIG. 14 and FIG. 15 , the start and end times of the second operating voltage of the second scan signal are between the end time of the operating voltage of the first scan signal and the start time of the operating voltage of the enable signal.

[0149] Furthermore, the time interval between the start time of the second operating voltage of the second scan signal and the end time of the operating voltage of the first scan signal is greater than or equal to one row scan period H. The time interval between the end time of the second operating voltage of the second scan signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scan period H.

[0150] For example, as shown in FIG13 , the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is two row scanning periods H. The time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is one row scanning period H.

[0151] In some embodiments, as shown, the data writing sub-circuit 27 is further configured to transmit the data holding signal received at the data signal terminal DATA to the second node N2 in response to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2.

[0152] Here, the voltage range of the data hold signal is 0V to V GMP Among them, V GMP It refers to the black state voltage of the sub-pixel P. When the target grayscale of a sub-pixel P is 0, the black state voltage is directly used as the driving voltage corresponding to the sub-pixel P, so that the corresponding sub-pixel does not emit light.

[0153] Illustratively, the voltage of the data hold signal ranges from 0 V to 7 V, for example, the voltage of the data hold signal is any one of 0 V, 1 V, 2 V, 3 V, 4 V, 5 V, 6 V, and 7 V. The voltage value of the data hold signal can be determined based on experimental testing, with a voltage value having a lower flicker value being used as the actual voltage value of the data hold signal. This is not specifically limited in the present embodiment.

[0154] It should be noted that the first operating voltage, the second operating voltage and the third operating voltage of the second scan signal may be the same in magnitude, but the timings of the first operating voltage, the second operating voltage and the third operating voltage are different.

[0155] In some embodiments, as shown in FIG9B , the data writing sub-circuit 27 includes a seventh transistor T7 , a first electrode of the seventh transistor T7 is connected to the data signal terminal DATA, a second electrode of the seventh transistor T7 is connected to the second node N2 , and a control electrode of the seventh transistor T7 is connected to the second scan signal terminal GATE2 .

[0156] In some embodiments, as shown in FIG8A , the reset sub-circuit 23 is further coupled to the second initialization signal terminal VININT2, the third scan signal terminal GATE3, and the fifth node N5. The reset sub-circuit 23 is further configured to, under the control of the operating voltage of the third scan signal received at the third scan signal terminal GATE3, transmit the second initialization signal received at the second initialization signal terminal VINIT to the fifth node N5 to reset the anode (fifth node N5) of the light-emitting device 10.

[0157] 9A , the reset sub-circuit 23 further includes a sixth transistor T6 , a first electrode of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2 , a second electrode of the sixth transistor VINIT2 is connected to the fifth node N5 , and a control electrode of the sixth transistor T6 is connected to the third scan signal terminal GATE3 .

[0158] In this case, the control electrode of the sixth transistor T6 that resets the anode (fifth node N5) of the light-emitting device 10 can be controlled by the third scan signal terminal GATE3, so as to reset the anode (fifth node N5) of the light-emitting device 10 and improve the light-emitting efficiency.

[0159] In addition, the third scan signal terminal GATE3 can be connected to the same signal line as the second scan signal terminal GATE2, that is, the signals received by the third scan signal terminal GATE3 and the second scan signal terminal GATE2 can be the same, and the third scan signal terminal GATE3 can also be called the second scan signal terminal GATE2.

[0160] At this time, as shown in FIG8B , the reset sub-circuit 23 is coupled to the second initialization signal terminal VININT2, the second scan signal terminal GATE2, and the fifth node N5. The reset sub-circuit 23 is configured to, under the control of the operating voltage of the third scan signal received at the second scan signal terminal GATE2, transmit the second initialization signal received at the second initialization signal terminal VINIT to the fifth node N5 to reset the anode (fifth node N5) of the light-emitting device 10.

[0161] For example, as shown in FIG9B , the reset sub-circuit 23 further includes a sixth transistor T6 , a first electrode of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2 , a second electrode of the sixth transistor VINIT2 is connected to the fifth node N5 , and a control electrode of the sixth transistor T6 is connected to the second scan signal terminal GATE2 .

[0162] In this case, the control electrode of the sixth transistor T6 for resetting the anode (fifth node N5) of the light-emitting device 10 and the control electrode of the seventh transistor T7 can both be controlled by the second scanning signal terminal GATE2, so that during the data writing process, the anode (fifth node N5) of the light-emitting device 10 is reset at the same time, simplifying the circuit structure.

[0163] The following takes the example where the third scan signal terminal GATE3 and the second scan signal terminal GATE2 are connected to the same signal line to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0164] In some embodiments, as shown in FIG4 , all pixel circuits 20 are arranged in multiple rows and columns, where each row includes multiple pixel circuits 20 arranged along a first direction X, and each column includes multiple pixel circuits 20 arranged along a second direction Y. The first direction X is substantially perpendicular to the second direction Y.

[0165] It should be noted that the first direction X may be, for example, a row direction in which the plurality of pixel circuits 20 are arranged, and the second direction Y may be, for example, a column direction in which the plurality of pixel circuits 20 are arranged.

[0166] The following uses an example in which all pixel circuits 20 are arranged in multiple rows and columns to illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. Furthermore, a plurality of pixel circuits 20 arranged along a first direction X is referred to as a row of pixel circuits 20, and a plurality of pixel circuits 20 arranged along a second direction Y is referred to as a column of pixel circuits 20.

[0167] On this basis, the display panel 100 further includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of first power lines VDL, a plurality of first initialization signal lines VL1, a plurality of second initialization signal lines VL2, and a plurality of constant voltage signal lines VCL.

[0168] As shown in FIG4 , each gate line GL extends substantially along a first direction X and is configured to transmit any one of a first scan signal, a second scan signal, a reset signal, and an enable signal (control signal). For example, one gate line GL may be connected to any one of a first scan signal terminal GATE1, a second scan signal terminal GATE2, a reset signal terminal RESET, and an enable signal terminal EN (control signal terminal K) of a row of pixel circuits 20.

[0169] 4 , the data lines DL extend substantially along the second direction Y and are configured to transmit data signals. For example, one data line DL may be connected to a data signal terminal DATA of a column of pixel circuits 20 .

[0170] 4 , the first power line VDL extends substantially along the second direction Y and is configured to transmit a first power voltage signal. For example, one first power line VDL may be connected to the first voltage signal terminal VDD of a column of pixel circuits 20 .

[0171] 4 , the first initialization signal line VL1 extends substantially along the first direction X and is configured to transmit a first initialization signal. One first initialization signal line VL1 may be connected to the first initialization signal terminal VINIT1 of a row of pixel circuits 20 , for example.

[0172] 4 , the second initialization signal line VL2 extends substantially along the first direction X and is configured to transmit a second initialization signal. For example, one second initialization signal line VL2 may be connected to the second initialization signal terminal VINIT2 of a row of pixel circuits 20 .

[0173] 4 , the constant voltage signal line VCL extends substantially along the second direction Y and is configured to transmit a constant voltage signal. One constant voltage signal line VCL may be connected to the constant voltage signal terminals VC of a row of pixel circuits 20 , for example.

[0174] As shown in Figure 5, along the direction perpendicular to the substrate 11 and away from the substrate 11, the display panel 100 includes a substrate 11, a semiconductor layer ACT, a first gate insulation layer GI1, a first gate conductive layer GT1, a second gate insulation layer GI2, a second gate conductive layer GT2, an interlayer insulating layer ILD, a first source and drain conductive layer SD1, a first planar layer PLN1, a second source and drain conductive layer SD2 and a second planar layer PLN2.

[0175] On this basis, referring to Figures 4 and 5 , the semiconductor channel 31 of the transistor can be, for example, located in the semiconductor layer ACT, and the gate line GL, the gate 34 of the transistor, and the first plates of the capacitors (first capacitor C1 and second capacitor C2) can be, for example, located in the first gate conductive layer GT1. The second plates of the capacitors (first capacitor C1 and second capacitor C2), the first initialization signal line VL1 and the second initialization signal line can be, for example, located in the second gate conductive layer GT2. The source 32, drain 33, first power line VDL, and constant voltage signal line VCL of the transistor can be, for example, located in the first source-drain conductive layer SD1. The data line DL can be, for example, located in the second source-drain conductive layer SD2.

[0176] In some embodiments, as shown in FIG. 5 , the display panel 100 further includes a pixel defining layer (PDL). The pixel defining layer (PDL) is provided with a plurality of openings, and one light emitting device 10 is located in one opening.

[0177] In some embodiments, as shown in FIG5 , the display panel 100 further includes a spacer PS, which can be disposed between the pixel defining layer PDL and the first electrode 11 of the light-emitting device 10 to support the mask during the process so that the gap between the mask and the pixel defining layer PDL is uniform.

[0178] 4 , the display panel 100 further includes a peripheral region B, which is disposed on at least one side of the display region A. FIG4 illustrates an example in which the peripheral region B surrounds the display region A.

[0179] As shown in Figure 4, the peripheral area B includes a first border area B1, a second border area B2, a third border area B3 and a fourth border area B4. Along the first direction X, the first border area B1 and the second border area B2 are located on opposite sides of the display area A, and along the second direction Y, the third border area B3 and the fourth border area B4 are located on the other opposite sides of the display area A.

[0180] The peripheral area B is a region where no image is displayed and is configured to set up a gate driving circuit 130 and a source driving circuit 140 .

[0181] In some embodiments, referring to Figures 9B and 10, the gate driving circuit 130 includes a first gate driving circuit 131, the first gate driving circuit 131 includes a plurality of cascaded first shift registers RS1, each first shift register RS1 includes a first signal output end, and the first signal output end of each first shift register RS1 is connected to the first scan signal end GATE1 and / or the reset signal end RESET of at least one row of pixel circuits 20.

[0182] For example, as shown in FIG9B and FIG10 , a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, with each row including N pixel circuits 20 arranged along a first direction X, and each column including M pixel circuits 20 arranged along a second direction Y, where M>1, N>1, and both M and N are integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. FIG10 illustrates 2480 rows of pixel circuits 20 as an example.

[0183] The first gate drive circuit 131 includes M+Q cascaded first shift registers RS1. From the first stage of the first shift register RS1 to the last stage of the first shift register RS1, the M+Q first shift registers RS1 are respectively the 1st to the M+Qth first shift registers RS1. FIG10 illustrates the example where Q is 8.

[0184] On this basis, the first scanning signal terminal GATE1 of the pixel circuit 20 in the Pth row is connected to the first signal output terminal of the P+Qth first shift register RS1. The reset signal terminal RESET of the pixel circuit 20 in the Pth row is connected to the first signal output terminal of the Pth first shift register RS1. Furthermore, P ≤ M, Q > 0, and both P and Q are integers.

[0185] In this case, the first gate driver circuit 131 can provide a first scan signal and a reset signal to the first scan signal terminal GATE1 and the reset signal terminal RESET of all pixel circuits 20, respectively. In other words, the first scan signal terminal GATE1 and the reset signal terminal RESET of one pixel circuit 20 can share one gate driver circuit 130, which is beneficial to a narrow-frame design of the display device 1000 (see FIG. 1 ).

[0186] In some examples, as shown in FIG10 , along the first direction X, the first gate driving circuit 131 is disposed on one side of the display area A (see FIG4 ), and drives each row of pixel circuits 20 row by row from a single side of the display area A (see FIG4 ), i.e., unilateral driving.

[0187] In other examples, as shown in FIG11 , along the first direction X, two first gate driving circuits 131 are arranged on opposite sides of the display area A (see FIG4 ), and through the two first gate driving circuits 131 , each row of pixel circuits 20 is driven row by row from opposite sides of the display area A (see FIG4 ) at the same time, i.e., double-sided driving.

[0188] In some other embodiments, referring to FIG. 12 , the gate driving circuit 130 includes a second gate driving circuit 132 and a third gate driving circuit 133 .

[0189] 9B and 12 , the second gate drive circuit 132 includes a plurality of cascaded second shift registers RS2 , each second shift register RS2 includes a second signal output terminal, and the second signal output terminal of each second shift register RS2 is connected to the first scan signal terminal GATE1 of at least one row of pixel circuits 20 .

[0190] For example, as shown in FIG12 , a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, with each row including N pixel circuits 20 arranged along a first direction X, and each column including M pixel circuits 20 arranged along a second direction Y, where M>1, N>1, and both M and N are integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. FIG12 illustrates 2480 rows of pixel circuits 20 as an example.

[0191] The second gate driving circuit 132 includes M cascaded second shift registers RS2, from the first stage second shift register RS2 to the last stage second shift register RS2, the M second shift registers RS2 are respectively the first to the Mth second shift registers RS2. Each second shift register RS2 includes a second signal output terminal.

[0192] On this basis, the first scanning signal terminal GATE1 of the pixel circuit 20 in the P-th row is connected to the second signal output terminal of the P-th second shift register RS2, where P≤M, and P is an integer.

[0193] In addition, as shown in Figures 9B and 12, the third gate drive circuit 133 includes a plurality of cascaded third shift registers RS3, each third shift register RS3 includes a third signal output terminal, and the third signal output terminal of each third shift register RS3 is connected to the reset signal terminal RESET of at least one row of pixel circuits 20.

[0194] For example, as shown in FIG12 , a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, with each row including N pixel circuits 20 arranged along a first direction X, and each column including M pixel circuits 20 arranged along a second direction Y, where M>1, N>1, and both M and N are integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. FIG12 illustrates 2480 rows of pixel circuits 20 as an example.

[0195] The third gate driving circuit 133 includes M cascaded third shift registers RS3, from the first stage third shift register RS3 to the last stage third shift register RS3, and the M third shift registers RS3 are respectively the first to the Mth third shift registers RS3. Each third shift register RS3 includes a third signal output terminal.

[0196] On this basis, the reset signal terminal RESET of the pixel circuit in the P-th row is connected to the third signal output terminal of the P-th third shift register RS3, where P≤M, and P is an integer.

[0197] In this case, the second gate driver circuit 132 can provide the first scan signal to the first scan signal terminal GATE1 of all pixel circuits 20, and the third gate driver circuit 133 can provide the reset signal to the reset signal terminal RESET of all pixel circuits 20. In this case, the ratio of the duration of the first scan signal received by the first scan signal terminal GATE1 of the pixel circuit 20 to the duration of the reset signal received by the reset signal terminal RESET can be arbitrarily adjusted, which is conducive to improving afterimage performance, reducing flicker, and thus improving display quality.

[0198] In some examples, as shown in FIG12 , along the first direction X, the second gate driving circuit 132 and the third gate driving circuit 133 are respectively arranged on opposite sides of the display area A (see FIG4 ), that is, the second gate driving circuit 132 and the third gate driving circuit 133 are respectively arranged in the first border area B1 (see FIG4 ) and the second border area B2 (see FIG4 ), and each row of pixel circuits 20 are driven row by row from a single side of the display area A (see FIG4 ), which is beneficial to reducing the border of the display device 1000 (see FIG1 ) and improving the screen-to-body ratio.

[0199] In some embodiments, referring to FIG. 10 to FIG. 12 , the gate driving circuit 130 further includes a fourth gate driving circuit 134 .

[0200] 9B and 10 , the fourth gate drive circuit 134 includes a plurality of cascaded fourth shift registers RS4 , each fourth shift register RS4 includes a fourth signal output terminal, and the fourth signal output terminal of each fourth shift register RS4 is connected to the enable signal terminal EM of at least one row of pixel circuits 20 .

[0201] For example, as shown in FIG10 , a plurality of pixel circuits 20 are arranged in M ​​rows and N columns. Each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y. M>1, N>1, and both M and N are integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the first to Mth rows of pixel circuits 20, respectively. FIG10 illustrates 2480 rows of pixel circuits 20 as an example.

[0202] The fourth gate driving circuit 134 includes M cascaded fourth shift registers RS4, from the first stage fourth shift register RS4 to the last stage fourth shift register RS4, and the M fourth shift registers RS4 are respectively the first to the Mth fourth shift registers RS4. Each of the fourth shift registers RS4 includes a fourth signal output terminal.

[0203] On this basis, the enable signal terminal EM of the pixel circuit 20 in the Pth row is connected to the fourth signal output terminal of the Pth fourth shift register RS4 of the fourth gate driving circuit 134, where P≤M, and P is an integer.

[0204] As shown in Figure 10, when the display panel 100 includes a first gate driving circuit 131, the first gate driving circuit 131 and the fourth gate driving circuit 134 are respectively arranged in the first border area B1 (see Figure 4) and the second border area B2 (see Figure 4), which is conducive to the narrow border design of the display device 1000 (see Figure 1).

[0205] As shown in Figure 11, when the display panel 100 includes two first gate driving circuits 131, and the two first gate driving circuits 131 are respectively arranged in the first border area B1 and the second border area B2, the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 can be respectively arranged in the first border area B1 and the second border area B2 to form cross-driving, so as to make full use of the areas of the first border area B1 and the second border area B2 and improve the uniformity of the picture display.

[0206] As shown in Figure 12, when the display panel 100 includes a second gate driving circuit 132 and a third gate driving circuit 133, the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 are respectively arranged in the first border area B1 and the second border area B2 to form a cross drive, so as to make full use of the areas of the first border area B1 and the second border area B2 and improve the uniformity of the picture display.

[0207] In some embodiments, referring to FIG. 10 to FIG. 12 , the gate driving circuit 130 further includes a fifth gate driving circuit 135 .

[0208] 9B and 12 , the fifth gate drive circuit 135 includes a plurality of cascaded fifth shift registers RS5 , each fifth shift register RS5 includes a fifth signal output terminal, and the fifth signal output terminal of each fifth shift register RS5 is connected to the second scan signal terminal GATE2 of at least one row of pixel circuits 20 .

[0209] For example, as shown in FIG12 , a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, with each row including N pixel circuits 20 arranged along a first direction X, and each column including M pixel circuits 20 arranged along a second direction Y, where M>1, N>1, and both M and N are integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. FIG12 illustrates 2480 rows of pixel circuits 20 as an example.

[0210] The fifth gate driving circuit 135 includes M cascaded fifth shift registers RS5, from the first stage fifth shift register RS5 to the last stage fifth shift register RS5, and the M fifth shift registers RS5 are respectively the first to the Mth fifth shift registers RS5. Each fifth shift register RS5 includes a fifth signal output terminal.

[0211] On this basis, the enable signal terminal EM of the pixel circuit 20 in the Pth row is connected to the fourth signal output terminal of the Pth fifth shift register RS5 of the fourth gate driving circuit 134, where P≤M, and P is an integer.

[0212] In some examples, as shown in Figures 10 to 12, the display panel 100 includes two fifth gate drive circuits 135, which are respectively arranged in the first border area B1 (see Figure 4) and the second border area B2 (see Figure 4). That is, the second scan signal terminal GATE2 of the P-th row of pixel circuits 20 is connected to the fifth signal output terminal of the P-th fifth shift register RS5 of the two fifth gate drive circuits 135 to form a double-sided drive, P≤M, and P is an integer. In this way, the effect of the voltage drop on the second scan signal can be reduced, thereby improving the brightness uniformity of the display screen.

[0213] Some embodiments of the present disclosure further provide a driving method of a pixel circuit 20 , for driving the pixel circuit 20 as in any of the above embodiments.

[0214] As shown in FIG. 13 , a display frame F includes a refresh frame F1 , and the refresh frame F1 includes a first reset phase P11 and a second reset phase P12 .

[0215] During the first reset phase P11, the reset sub-circuit 23 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the operating voltage of the reset signal at the reset signal terminal RESET, thereby resetting the first node N1. Furthermore, the storage sub-circuit 24 stores the voltage of the second node N2 after the previous frame, so that the second node N2 can form a relatively stable potential (the voltage of the second voltage signal).

[0216] 9B , the fifth transistor T5 is turned on under the control of the reset signal received at the reset signal terminal RESET, transmitting the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1. Furthermore, the second storage capacitor C2 stores the voltage of the second node N2 after the previous frame ends.

[0217] At this time, in the first reset stage P11, a large bias voltage can be formed between the second node N2 and the first node N1, so that a stable and large bias voltage is generated between the source terminal and the control terminal of the eighth transistor T8, thereby improving the hysteresis characteristics of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of flickering on the display screen that can be perceived by the human eye.

[0218] It should be noted that the difference between the start time of the first reset stage P11 and the start time of the frame F in which the first reset stage P11 is located is greater than or equal to two row scanning periods H, so as to avoid the rising edge and falling edge of each signal of the first reset stage P11 being interlaced at the end of the previous frame F, thereby affecting the first reset stage P11.

[0219] During the second reset phase P12, the reset sub-circuit 23 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the operating voltage of the reset signal at the reset signal terminal RESET. The compensation sub-circuit 22 transmits the voltage of the first node N1 to the third node N3 in response to the operating voltage of the first scan signal received at the first scan signal terminal GATE1. Furthermore, the driving sub-circuit 21, under control of the voltage of the first node N1, transmits the voltage of the third node N3 to the second node N2, thereby resetting the third node N3 and the second node N2 in sequence.

[0220] 9B , the first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the first scan signal received at the first scan signal terminal GATE1, and transmit the voltage of the first node N1 to the third node N3. Furthermore, the eighth transistor T8 is turned on under the control of the voltage of the first node N1, and transmits the voltage of the third node N3 to the second node N2.

[0221] At this time, in the second reset phase P12, the second node N2 and the third node N3 may be reset to reduce the influence of the residual voltage of the previous frame on the data writing of this frame, thereby improving the brightness uniformity of the display screen.

[0222] In some embodiments, as shown in FIG. 13 , the refresh frame F1 further includes a first data writing phase P21 and a second data writing phase P22 .

[0223] In the first data writing phase P21, the data writing sub-circuit 27 transmits the data signal received at the data signal terminal DATA to the second node N2 in response to the first operating voltage of the second scan signal received at the second scan signal terminal GATE2, and writes the data signal into the storage sub-circuit 24. Under the control of the voltage of the first node N1, the driving sub-circuit 21 transmits the voltage of the second node N2 to the third node N3. The compensation sub-circuit 22 transmits the voltage of the third node N3 to the first node N1 in response to the operating voltage of the first scan signal received at the first scan signal terminal GATE1.

[0224] 9B , the seventh transistor T7 is turned on under the control of the first operating voltage of the second scan signal received at the second scan signal terminal GATE2, and transmits the data signal received at the data signal terminal DATA to the second node N2. The second storage capacitor C2 stores the voltage of the data signal written to the second node N2.

[0225] Furthermore, the eighth transistor T8 is turned on under the control of the voltage of the first node N1, transmitting the voltage of the third node N3 to the second node N2. The first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the operating voltage of the first scan signal received at the first scan signal terminal GATE1, transmitting the voltage of the third node N3 to the first node N1.

[0226] At this time, in the first data writing phase P21 , the data signal may be written into the first node N1 and the second storage capacitor C2 .

[0227] During the second data writing phase P22, the storage sub-circuit 24 discharges and transmits the stored data signal to the second node N2. The driver sub-circuit 21, under the control of the voltage of the first node N1, transmits the voltage of the second node N2 to the third node N3. The compensation sub-circuit 22 transmits the voltage of the third node N3 to the first node N1 in response to the operating voltage of the first scan signal received at the first scan signal terminal GATE1.

[0228] That is, as shown in Figure 9B, the second storage capacitor C2 discharges, transmitting the data signal written in the first data writing phase P21 to the second node N2. The eighth transistor T8 is turned on under the control of the voltage of the first node N1, transmitting the voltage of the third node N3 to the second node N2. The first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the operating voltage of the first scan signal received at the first scan signal terminal GATE1, transmitting the voltage of the third node N3 to the first node N1.

[0229] At this time, in the second data writing phase P22 , the second storage capacitor C2 can be continuously discharged to continuously write the data signal to the first node N1 , thereby increasing the data writing time, thereby facilitating improvement in brightness uniformity of the display screen and enhancing the display effect.

[0230] In some embodiments, as shown in FIG9B and FIG13 , the transistors included in the compensation sub-circuit 22 are P-type transistors, and the second reset phase P12 includes at least three row scanning periods H.

[0231] In the second reset phase P12, the voltage of the first horizontal scanning period H after the first scanning signal is activated is greater than the voltage of the second horizontal scanning period H after the first scanning signal is activated. That is, the stability of the first scanning signal H output in the even-numbered horizontal scanning period H is greater than the stability in the odd-numbered horizontal scanning period H.

[0232] Illustratively, the first scanning signal of the first signal output terminal of the first shift register RS1 is output by the clock signal line. During the first row scanning period H of the second reset phase P12, the first signal output terminal outputs a high-level signal of the clock signal line. During the second row scanning period H of the second reset phase P12, the first signal output terminal outputs a low-level signal of the clock signal line.

[0233] Furthermore, during the remaining odd-numbered horizontal scanning periods H in the second reset phase P12, the first signal output terminal is in a floating state. During the remaining even-numbered horizontal scanning periods H in the second reset phase P12, the first signal output terminal outputs a low-level signal of the clock signal line. At this time, the stability of the first scanning signal output during the even-numbered horizontal scanning periods H is greater than that during the odd-numbered horizontal scanning periods H.

[0234] On this basis, the first data writing phase P21 is located after the second reset phase P12 and coincides with the 2Nth row scanning period H after the start time of the second reset phase P12, where N≥2 and N is an integer.

[0235] In this case, performing the first data writing phase P21 during the even-numbered row scanning period H, when the stability of the first scanning signal is relatively high, can improve the accuracy of data signal writing, thereby improving the brightness uniformity of the display screen. In particular, when the display panel 100 includes the first gate driver circuit 131, the risk of the last few rows of sub-pixels P being brighter than other sub-pixels P can be reduced, thereby improving the brightness uniformity of the display screen.

[0236] 13 , the second reset phase P12 includes three row scanning periods H. At this time, the first data writing phase P21 coincides with the sixth row scanning period H after the start time of the second reset phase P12, i.e., the first scan signal is more stable during the sixth row scanning period H.

[0237] Moreover, the falling edge of the second scanning signal and the rising edge of the reset signal can be staggered by two row scanning periods H, so as to avoid the second reset phase P12 affecting data writing, and the brightness uniformity of the display screen is higher.

[0238] In some embodiments, as shown in FIG. 13 , the refresh frame F further includes a first light emitting phase P3 .

[0239] During the first light-emitting phase P3, the light-emitting control subcircuit 26 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The driver subcircuit 21 generates a drive current signal based on the voltages at the first node N1 and the second node N2.

[0240] Furthermore, the light emitting control sub-circuit 26 transmits the driving current signal to the light emitting device 10 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The leakage prevention sub-circuit 25 transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.

[0241] 9B , the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The eighth transistor T8 generates a drive current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0242] Furthermore, the third transistor T3 and the fourth transistor T4 are both turned on under the control of the enable signal received at the enable signal terminal EM, and transmit the drive current signal to the light-emitting device 10 to drive the light-emitting device 10 to emit light. The second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, thereby reducing the leakage current of the first node N1, thereby improving the brightness uniformity of the display screen.

[0243] On this basis, as shown in FIG13 , the refresh frame F may further include a third reset phase P13 , and the third reset phase P13 is located between the second data writing phase P22 and the first light emitting phase P3 .

[0244] In the third reset phase P13 , the data writing sub-circuit 27 transmits the data refresh signal received at the data signal terminal DATA to the second node N2 in response to the second operating voltage of the second scan signal received at the second scan signal terminal GATE2 .

[0245] That is, as shown in FIG9B , the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2, and transmits the data refresh signal received at the data signal terminal DATA to the second node N2. In this way, the data signals received by the pixel circuits 20 in other rows can be reused, and the second node N2 and the fourth node N4 can be reset again to improve the brightness uniformity of the display screen without changing the circuit structure, and the structure is simple.

[0246] In some examples, referring to Figures 13, 14 and 15, the difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is greater than or equal to 1 row scanning period H, so as to reduce the risk of the rising edge and falling edge of each signal in the third reset phase P13 and the second data writing phase P22 being interleaved, thereby affecting data writing or resetting.

[0247] For example, as shown in Figure 13, the difference between the start time of the third reset stage P13 and the end time of the second data writing stage P22 is 2 row scanning periods H, so as to avoid the rising edge and falling edge of each signal in the third reset stage P13 and the second data writing stage P22 from being interlaced, which affects data writing or resetting.

[0248] In some examples, referring to Figures 13, 14 and 15, the difference between the end time of the third reset stage P13 and the start time of the first light-emitting stage P3 is greater than or equal to a row scanning period H, so as to avoid the rising edge and falling edge of each signal in the third reset stage P13 and the first light-emitting stage P3 from interlacing, thereby affecting data writing or light emission.

[0249] For example, as shown in Figure 13, the difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is 1 row scanning period H, so as to avoid the rising edge and falling edge of each signal in the third reset phase P13 and the second data writing phase P22 from being interlaced, which may affect data writing or resetting.

[0250] In some embodiments, referring to FIG9B and FIG13 , the pixel circuit 20 has a first refresh frequency and a second refresh frequency, wherein the second refresh frequency is lower than the first refresh frequency. At the first refresh frequency, a display frame F includes a refresh frame F1. At the second refresh frequency, a display frame F includes a refresh frame F1 and at least one hold frame F2.

[0251] At this time, the display panel 100 can display high and low frequency conversion at 30 Hz, 40 Hz, 60 Hz and 120 Hz, or at 40 Hz, 55 Hz, 82 Hz and 165 Hz, for example, but the embodiments of the present disclosure are not limited thereto.

[0252] As shown in FIG13 , the holding frame F2 includes a black insertion phase P4 , a fourth reset phase P5 and a second light emitting phase P6 .

[0253] In the black insertion phase P4 , the light emitting control sub-circuit 26 is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal EM.

[0254] That is, as shown in FIG. 9B , the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal received at the enable signal terminal EM, thereby controlling the circuit for transmitting the driving current signal to be turned off.

[0255] At this time, after the first light-emitting stage P3 of the refresh frame F1, a black screen can be inserted to provide a rest time for the light-emitting device 10, thereby avoiding abnormal light emission of the light-emitting device 10 caused by long-term bias, improving the image display effect and extending the service life of the light-emitting device 10.

[0256] In the fourth reset phase P5 , the data writing sub-circuit 27 transmits the data holding signal received at the data signal terminal DATA to the second node N2 in response to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2 .

[0257] It should be noted that the voltage range of the data hold signal is 0V to V GMP Among them, V GMP Refers to the black state voltage of the sub-pixel P. The black state voltage is when the target grayscale of a sub-pixel P is 0, and the black state voltage is directly used as the driving voltage corresponding to the sub-pixel P, so that the corresponding sub-pixel does not emit light. Exemplarily, the voltage range of the data hold signal is 0V to 7V, such as the voltage of the data hold signal is any one of 0V, 1V, 2V, 3V, 4V, 5V, 6V and 7V. Here, the voltage value of the data hold signal can be specifically based on experimental testing, and the voltage value with a lower flicker value can be used as the actual voltage value of the data hold signal. The embodiments of the present disclosure do not specifically limit this.

[0258] 9B , the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2 and transmits the data holding signal received at the data signal terminal DATA to the second node N2 to reset the second node N2.

[0259] During the second light-emitting phase P6, the light-emitting control sub-circuit 26 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The driver sub-circuit 21 generates a drive current signal based on the voltages at the first node N1 and the second node N2.

[0260] Furthermore, the light emitting control sub-circuit 26 transmits the driving current signal to the light emitting device 10 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The leakage prevention sub-circuit 25 transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.

[0261] 9B , the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The eighth transistor T8 generates a drive current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0262] Furthermore, the third transistor T3 and the fourth transistor T4 are both turned on under the control of the enable signal received at the enable signal terminal EM, and transmit the drive current signal to the light-emitting device 10 to drive the light-emitting device 10 to emit light. The second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, thereby reducing the leakage current of the first node N1, thereby improving the brightness uniformity of the display screen.

[0263] In some examples, referring to Figures 13, 14 and 15, the difference between the end time of the fourth reset stage P5 and the start time of the second light-emitting stage P6 is greater than or equal to one row scanning period H, so as to avoid the rising edge and falling edge of each signal in the fourth reset stage P5 and the second light-emitting stage P6 from interlacing, which affects the reset or light-emitting.

[0264] For example, as shown in FIG13 , the difference between the end time of the fourth reset stage P5 and the start time of the second light-emitting stage P6 is a row scanning period H, so as to avoid the rising edge and falling edge of each signal in the fourth reset stage P5 and the second light-emitting stage P6 from interlacing, thereby affecting the reset or light-emitting.

[0265] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel circuit, comprising: a driving subcircuit coupled to the first node, the second node and the third node; The driving subcircuit is configured to control the conduction and cutoff of the circuit between the second node and the third node under the control of the voltage of the first node; a compensation subcircuit coupled to the first scan signal terminal, the first node and the third node; the compensation subcircuit is configured to control the conduction and cutoff of the circuit between the first node and the third node in response to the first scan signal received at the first scan signal terminal; a reset subcircuit coupled to the first initialization signal terminal, the reset signal terminal and the first node; the reset subcircuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the first node in response to the working voltage of the reset signal received at the reset signal terminal; The storage sub-circuit is coupled to the first voltage signal terminal, the first node and the second node; the storage sub-circuit is configured to store the voltages of the first node and the second node.

2. The pixel circuit according to claim 1, wherein: The storage sub-circuit comprises: a first storage capacitor, wherein a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the first node; A second storage capacitor, wherein a first plate of the second storage capacitor is connected to the first voltage signal terminal, and a second plate of the second storage capacitor is connected to the second node.

3. The pixel circuit according to claim 1 or 2, wherein: The compensation subcircuit comprises: a first sub-transistor and a second sub-transistor connected in series, wherein a first end of the first sub-transistor is connected to the first node, a second end of the first sub-transistor and / or a first end of the second sub-transistor is connected to a fourth node, a second end of the second sub-transistor is connected to the third node, and control electrodes of the first sub-transistor and the second sub-transistor are connected to the first scan signal terminal; The pixel circuit further includes: An anti-leakage subcircuit is coupled to the control signal terminal, the constant voltage terminal and the fourth node; the anti-leakage subcircuit is configured to transmit the constant voltage signal received at the constant voltage terminal to the fourth node in response to the working voltage of the control signal received at the control signal terminal.

4. The pixel circuit according to claim 3, further comprising: A light emitting control subcircuit, coupled to the first voltage signal terminal, the enable signal terminal, the second node, the third node and the fifth node; The fifth node is connected to the anode of the light emitting device; The light-emitting control subcircuit is configured to, in response to an enable signal received at the enable signal terminal, control the conduction and cutoff of the circuit between the first voltage signal terminal and the second node; and control the conduction and cutoff of the circuit between the third node and the fifth node; wherein the signals received at the enable signal terminal and the control signal terminal are the same.

5. The pixel circuit according to any one of claims 1 to 4, further comprising: a data writing subcircuit coupled to the data signal terminal, the second scanning signal terminal and the second node; the data writing subcircuit is configured to transmit the data signal received at the data signal terminal to the second node in response to a first operating voltage of the second scanning signal received at the second scanning signal terminal; And, in response to the second operating voltage of the second scanning signal received at the second scanning signal terminal, the data refresh signal received at the data signal terminal is transmitted to the second node; the data refresh signal is a data signal received by other row pixel circuits.

6. The pixel circuit according to claim 5, wherein: The cut-off time of the first working voltage of the second scanning signal is before the cut-off time of the working voltage of the first scanning signal; Moreover, the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is greater than or equal to a row scanning period; the row scanning period is the duration of a working voltage of the second scanning signal.

7. The pixel circuit according to claim 5 or 6, wherein: The start time of the first working voltage of the second scanning signal is after the end time of the working voltage of the reset signal; Moreover, the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is greater than or equal to one row scanning period; the row scanning period is the duration of one working voltage of the second scanning signal.

8. The pixel circuit according to any one of claims 5 to 7, wherein: The compensation subcircuit includes a transistor which is a P-type transistor; The duration of the working voltage of the first scanning signal is greater than or equal to 4 row scanning periods; the voltage of the first row scanning period after the first scanning signal works is greater than the voltage of the second row scanning period after the first scanning signal works; the row scanning period is the duration of one working voltage of the second scanning signal; The time of the first working voltage of the second scanning signal coincides with the 2Nth row scanning period of the working voltage of the first scanning signal, where N≥2 and N is an integer.

9. The pixel circuit according to any one of claims 5 to 8, wherein: The start and end time of the second working voltage of the second scanning signal is between the end time of the working voltage of the first scanning signal and the start time of the working voltage of the enable signal; Moreover, the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period; the time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scanning period; the row scanning period is the duration of an operating voltage of the second scanning signal.

10. The pixel circuit according to any one of claims 5 to 7, wherein: The data writing sub-circuit is further configured to transmit the data holding signal received at the data signal terminal to the second node in response to a third operating voltage of the second scan signal received at the second scan signal terminal.

11. The pixel circuit according to any one of claims 5 to 8, wherein: The reset sub-circuit is also coupled to the second initialization signal terminal, the third scan signal terminal and the fifth node; the reset sub-circuit is also configured to transmit the second initialization signal received at the second initialization signal terminal to the fifth node under the control of the working voltage of the third scan signal received at the third scan signal terminal.

12. The pixel circuit according to any one of claims 1 to 11, wherein: The starting time of the working voltage of the reset signal is before the starting time of the working voltage of the first scanning signal; and the time interval between the starting time of the working voltage of the reset signal and the starting time of the working voltage of the first scanning signal is greater than or equal to 3 row scanning periods; and / or; The cut-off time of the working voltage of the reset signal is after the start time of the working voltage of the first scanning signal; and the time interval between the cut-off time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 2 row scanning periods.

13. A method for driving a pixel circuit, for driving the pixel circuit according to any one of claims 1 to 12, wherein a display frame comprises a refresh frame, and the refresh frame comprises a first reset phase and a second reset phase; In the first reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the working voltage of the reset signal at the reset signal terminal; and the storage subcircuit stores the voltage of the second node after the previous frame ends; In the second reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the working voltage of the reset signal at the reset signal terminal; The compensation subcircuit transmits the voltage of the first node to the third node in response to the working voltage of the first scan signal received at the first scan signal terminal; And, the driving sub-circuit transmits the voltage of the third node to the second node under the control of the voltage of the first node.

14. The driving method according to claim 13, wherein: The pixel circuit further includes a data writing subcircuit, and the refresh frame further includes a first data writing phase and a second data writing phase; In the first data writing phase, the data writing subcircuit transmits the data signal received at the data signal terminal to the second node in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal, and writes the data signal into the storage subcircuit; The driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node; The compensation subcircuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal terminal; In the second data writing phase, the storage sub-circuit discharges and transmits the stored data signal to the second node; The driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node; the compensation subcircuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal terminal.

15. The driving method according to claim 14, wherein: The transistors included in the compensation subcircuit are P-type transistors; the second reset phase includes at least 3 row scanning periods; In the second reset stage, the voltage in the first row scanning period after the first scanning signal works is greater than the voltage in the second row scanning period after the first scanning signal works; The first data writing phase is located after the second resetting phase and coincides with the 2Nth row scanning period after the start time of the second resetting phase, where N≥2 and N is an integer.

16. The driving method according to any one of claims 13 to 15, wherein: The pixel circuit includes a data writing subcircuit, the refresh frame also includes a third reset phase and a first light emitting phase, and the third reset phase is located between the second data writing phase and the first light emitting phase; In the third reset phase, the data writing sub-circuit transmits the data refresh signal received at the data signal terminal to the second node in response to the second operating voltage of the second scan signal received at the second scan signal terminal.

17. The driving method according to claim 16, wherein: The difference between the start time of the third reset phase and the end time of the second data writing phase is greater than or equal to one row scanning period; and / or the difference between the end time of the third reset phase and the start time of the first light-emitting phase is greater than or equal to one row scanning period.

18. The driving method according to any one of claims 13 to 17, wherein: The pixel circuit includes a data writing subcircuit, a leakage prevention subcircuit and a light emitting control subcircuit; the pixel circuit has a first refresh frequency and a second refresh frequency, the second refresh frequency is less than the first refresh frequency; at the first refresh frequency, a display frame includes a refresh frame; at the second refresh frequency, a display frame includes a refresh frame and at least one holding frame; the holding frame includes a black insertion stage, a fourth reset stage and a second light emitting stage; In the black insertion stage, the light emitting control subcircuit is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal; In the fourth reset phase, the data writing sub-circuit transmits the data holding signal received at the data signal terminal to the second node in response to the third operating voltage of the second scan signal received at the second scan signal terminal; In the second light-emitting stage, the light-emitting control subcircuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the operating voltage of the enable signal received at the enable signal terminal; The driving subcircuit generates the driving current signal according to the voltage of the first node and the voltage of the second node; Moreover, the light-emitting control subcircuit transmits the driving current signal to the light-emitting device in response to the operating voltage of the enable signal received at the enable signal terminal; the leakage prevention subcircuit transmits the constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of the control signal received at the control signal terminal.

19. The driving method according to claim 18, wherein: The difference between the end time of the fourth resetting stage and the start time of the second light emitting stage is greater than or equal to one row scanning period.

20. A display panel, comprising: A plurality of pixel circuits as claimed in any one of claims 1 to 12, wherein the plurality of pixel circuits are arranged in M ​​rows and N columns, each row includes N pixel circuits arranged along a first direction, each column includes M pixel circuits arranged along a second direction, M>1, N>1, and M and N are both integers.

21. The display panel according to claim 20, wherein: Along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The first gate driving circuit comprises M+Q cascaded first shift registers, from the first stage first shift register to the last stage first shift register, the M+Q first shift registers are respectively the 1st to the M+Qth first shift registers; each of the first shift registers comprises a first signal output terminal; Among them, the first scan signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P+Q-th first shift register; the reset signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P-th first shift register; P≤M, Q>0, and P and Q are both integers.

22. The display panel according to claim 20, wherein: Along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The second gate driving circuit comprises M cascaded second shift registers, from the first stage second shift register to the last stage second shift register, the M second shift registers are respectively the first to the Mth second shift registers; each of the second shift registers comprises a second signal output terminal; wherein the first scanning signal terminal of the pixel circuit of the Pth row is connected to the second signal output terminal of the Pth second shift register, P≤M, and P is an integer; The third gate driving circuit includes M cascaded third shift registers, from the first-stage third shift register to the last-stage third shift register, the M third shift registers are respectively the 1st to the Mth third shift registers; each of the third shift registers includes a third signal output terminal; wherein the reset signal terminal of the P-th row pixel circuit is connected to the third signal output terminal of the P-th third shift register, P≤M, and P is an integer.

23. A display device, comprising: The display panel according to any one of claims 20 to 22.

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