Display panel and preparation method therefor, and display apparatus

Abstract

The present application relates to the technical field of display. Disclosed are a display panel and a preparation method therefor, and a display apparatus. A first trace layer of a power source trace in the display panel has a first target region that is exposed from a through groove region of a first organic film layer, and an orthographic projection, which is on a base substrate, of a third material layer, which is located in the first target region, of the first trace layer is located within an orthographic projection of a second material layer on the base substrate; and an orthographic projection, on the base substrate, of the second material layer, which is located in the first target region, of the first trace layer is located within an orthographic projection of a first material layer on the base substrate. In this way, an encapsulation film layer subsequently formed on the display panel can be prevented from cracks generating in the first target region, thereby preventing a display region from being invaded by water and oxygen along intrusion channels formed by the cracks. By means of the solution of the present application, the light emitting effect of pixel units in a display region can be guaranteed, the display region is prevented from dark-spot defects, the yield of display panels is high, and the display panels have a relatively good display effect.

Description

Display panel and manufacturing method thereof, and display device

[0001] This disclosure claims priority to Chinese patent application No. 202310801942.9 filed on June 30, 2023, entitled “Display panel, method for manufacturing the same, and display device.” The entire contents of the above case are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] Organic light-emitting diode (OLED) display panels have become the mainstream development direction in the field of display technology due to their advantages such as self-luminescence, high brightness, good image quality and low energy consumption.

[0004] Summary of the Invention

[0005] This application provides a display panel and a method for manufacturing the same, and a display device. The technical solutions are as follows:

[0006] In one aspect, a display panel is provided, comprising:

[0007] a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0008] a plurality of pixel units, wherein the plurality of pixel units are located in the display area;

[0009] a blocking structure surrounding the display area;

[0010] At least one power line is located on one side of the substrate, each power line is used to receive a power signal and is connected to the plurality of pixel units;

[0011] a first organic film layer, the first organic film layer being located on a side of the power trace away from the base substrate, and the first organic film layer having at least one through-groove region, an orthographic projection of the through-groove region on the base substrate and an orthographic projection of the blocking structure on the base substrate being arranged adjacent to each other, and the through-groove region being used to expose a first target region of the power trace;

[0012] In which, the power routing includes at least a first routing layer, the first routing layer includes a first material layer, a second material layer and a third material layer stacked in sequence in a direction away from the base substrate, the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate, and the orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate.

[0013] Optionally, the first material layer of the first routing layer located in the first target area has a first boundary extending along the first direction, the second material layer of the first routing layer located in the first target area has a second boundary extending along the first direction, and the third material layer of the first routing layer located in the first target area has a third boundary extending along the first direction;

[0014] The distance between the first boundary and the third boundary in the second direction is greater than 3 micrometers, the second boundary is located between the first boundary and the third boundary, and the second direction is perpendicular to the first direction.

[0015] Optionally, the first organic film layer has a groove area, the thickness of the first organic film layer in the groove area is less than the thickness of other areas except the groove area, and the groove area is used to cover the second target area of ​​the first wiring layer;

[0016] The second target area and the first target area are adjacent to each other in the first direction.

[0017] Optionally, the groove area has a first groove boundary close to the first routing layer and extending along the first direction, and the third material layer of the first routing layer located in the first target area has a third boundary extending along the first direction;

[0018] The orthographic projection of the first groove boundary on the substrate is collinear with the orthographic projection of the third boundary on the substrate.

[0019] Optionally, the groove region further has a second groove boundary away from the through-groove region and extending along a second direction, and a third groove boundary adjacent to the through-groove region and extending along the second direction; wherein the second direction is perpendicular to the first direction;

[0020] A distance between the second groove boundary and the third groove boundary in the first direction is greater than 3 micrometers.

[0021] Optionally, the power routing includes a third routing layer, a second routing layer, and the first routing layer stacked sequentially in a direction away from the base substrate; the display panel includes: a third organic film layer located between the third routing layer and the second routing layer, and a second organic film layer located between the second routing layer and the first routing layer, wherein the first organic film layer is located on a side of the first routing layer away from the base substrate;

[0022] The third routing layer and the second routing layer are connected through the opening in the third organic film layer, and the second routing layer and the first routing layer are connected through the opening in the second organic film layer; the through groove area is used to expose the first target area of ​​the first routing layer.

[0023] Optionally, the power supply wiring includes a second wiring layer and the first wiring layer stacked sequentially in a direction away from the base substrate; the display panel includes: a second organic film layer located between the second wiring layer and the first wiring layer, and the first organic film layer is located on a side of the first wiring layer away from the base substrate;

[0024] The second wiring layer and the first wiring layer are connected via an opening in the second organic film layer; and the through-groove area is used to expose a first target area of ​​the first wiring layer.

[0025] Optionally, the at least one power supply line includes a first signal power supply line and a second signal power supply line spaced apart and arranged above the second direction, and the through-slot area includes a first sub-through-slot area for exposing the first signal power supply line and a second sub-through-slot area for exposing the second signal power supply line;

[0026] Wherein, the length of the first sub-through-groove region along the first direction is less than or equal to the length of the second sub-through-groove region along the first direction.

[0027] Optionally, the thickness of the portion of the second material layer located in the first target area is less than or equal to the thickness of the portion of the second material layer located in the other areas.

[0028] Optionally, when the thickness of the second material layer located in the first target area is less than the thickness of the second material layer located in the other areas, the surface of the second material layer located in the first target area away from the base substrate is uneven.

[0029] Optionally, the blocking structure includes: a first blocking dam, a second blocking dam and a third blocking dam sequentially arranged away from the display area;

[0030] The first organic film layer has two through-groove regions, one of which is located on a side of the third barrier dam away from the display region, and the other is located between the second barrier dam and the third barrier dam.

[0031] Optionally, each barrier dam in the barrier structure includes at least one layer of the organic film layers in the display panel, and the organic film layers in the display panel include: a third organic film layer, a second organic film layer, and the first organic film layer;

[0032] Wherein, one of the first organic film layer, the second organic film layer and the third organic film layer is located in an area adjacent to any barrier dam in the barrier structure and where the through groove area is not provided.

[0033] Optionally, in an area of ​​the power supply line covered by the organic film layer in the display panel, side edges of the third material layer, the second material layer, and the first material layer are flat side edges, and the flat side edges are inclined relative to the supporting surface of the base substrate;

[0034] The orthographic projection of the third material layer on the base substrate is located within the orthographic projection of the second material layer on the base substrate, and the orthographic projection of the second material layer on the base substrate is located within the orthographic projection of the first material layer on the base substrate.

[0035] In another aspect, a method for preparing a display panel is provided, the method comprising:

[0036] Providing a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0037] A plurality of pixel units, a blocking structure, and at least one initial power supply line are formed on one side of the base substrate, the plurality of pixel units are located in the display area, the blocking structure surrounds the display area, and each of the initial power supply lines is used to receive a power signal and is connected to the plurality of pixel units; the initial power supply line includes at least a first initial wiring layer, the first initial wiring layer including a first material layer, a second material layer, and a third material layer stacked in sequence in a direction away from the base substrate;

[0038] forming an initial organic film layer on a side of the initial power supply line away from the base substrate, the initial organic film layer having at least one through-groove area, an orthographic projection of the through-groove area on the base substrate and an orthographic projection of the blocking structure on the base substrate being arranged adjacent to each other, and the through-groove area being used to expose a first target area of ​​the initial power supply line;

[0039] An etching process is used to etch the third material layer of the first target area of ​​the first initial routing layer of the at least one initial power routing and to etch the initial organic film layer to obtain the first routing layer and the first organic film layer of the at least one power routing, the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate, and the orthographic projection of the second material layer of the power routing located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate.

[0040] Optionally, forming the plurality of pixel units includes: sequentially forming an anode layer, a pixel defining layer, a light emitting layer, and a cathode layer on a side of the initial organic film layer away from the base substrate;

[0041] The etching of the first initial wiring layer of the at least one initial power wiring and the third material layer located in the first target area and the etching of the initial organic film layer by an etching process include:

[0042] After forming the anode layer and before forming the pixel defining layer, the etching process is used to etch the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and to etch the initial organic film layer.

[0043] Optionally, before forming the anode layer, the first initial routing layer is located in the first target region so that a first boundary of the first material layer, a second boundary of the second material layer, and a third boundary of the third material layer are collinear;

[0044] After forming the anode layer, an orthographic projection of the second material layer of the first initial routing layer located in the first target area on the base substrate is located within an orthographic projection of the third material layer on the base substrate, and a first boundary of the first material layer of the first initial routing layer located in the first target area and a third boundary of the third material layer are collinear;

[0045] The first boundary, the second boundary and the third boundary all extend along a first direction.

[0046] Optionally, forming the plurality of pixel units includes: sequentially forming an anode layer, a pixel defining layer, a light emitting layer, and a cathode layer on a side of the first organic film layer away from the base substrate;

[0047] The etching of the first initial wiring layer of the at least one initial power wiring and the third material layer located in the first target area and the etching of the initial organic film layer by an etching process includes:

[0048] After forming the pixel defining layer and before forming the light emitting layer, the etching process is used to etch the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and to etch the initial organic film layer.

[0049] Optionally, before forming the pixel defining layer, an orthographic projection of the second material layer of the first initial routing layer located in the first target area on the base substrate is located within an orthographic projection of the third material layer on the base substrate, and a first boundary of the first material layer of the first initial routing layer located in the first target area and a third boundary of the third material layer are collinear;

[0050] After forming the pixel definition layer, part of the material of the pixel definition layer is located in a retracted area, where the retracted area is a region of the first initial routing layer having the first material layer and the third material layer but not the second material layer;

[0051] After etching the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and etching the initial organic film layer using the etching process, a portion of the pixel defining layer located in the retracted area is removed.

[0052] Optionally, etching the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and etching the initial organic film layer by using an etching process includes:

[0053] Coating photoresist on a side of the first initial wiring layer away from the substrate;

[0054] exposing the photoresist using a mask;

[0055] Developing the photoresist with a developer to remove the exposed portion of the photoresist;

[0056] Using an etching process to remove the third material layer of the first initial wiring layer located in the first target area and the portion of the initial organic film layer not protected by the photoresist;

[0057] Remove the remaining photoresist.

[0058] Optionally, the mask has a plurality of mask openings, and an orthographic projection of each mask opening on the substrate partially overlaps with the through-slot area and partially overlaps with the first target area of ​​the initial power supply line;

[0059] The mask opening has a first mask boundary extending along a first direction, the first mask boundary is used to form a third boundary of the third material layer after etching, and the orthographic projection of the first mask boundary on the base substrate is located within the orthographic projection of the first material layer on the base substrate, the distance between the first mask boundary and the third boundary in the second direction is greater than 3 microns, and the second direction is perpendicular to the first direction.

[0060] Optionally, the first mask boundary is further used to form a first groove boundary of a groove region of the first organic film layer after etching, and the first groove boundary is close to the power line and extends along the first direction;

[0061] The thickness of the first organic film layer in the groove area is less than the thickness of other areas except the groove area. The groove area is used to cover the second target area of ​​the power line. The second target area and the first target area are adjacent to each other in the first direction.

[0062] Optionally, the mask opening further has a second mask boundary extending along the second direction, the through-groove region is located on one side of the second mask boundary, and the second mask boundary is used to form a groove region of the first organic film layer away from the through-groove region and extending along the second direction; the groove region further has a third groove boundary adjacent to the through-groove region and extending along the second direction;

[0063] Wherein, the distance between the second groove boundary and the third groove boundary in the first direction is greater than 3 micrometers.

[0064] Optionally, forming the power supply wiring includes: forming a first wiring layer on one side of the substrate;

[0065] Alternatively, forming the power wiring includes: sequentially forming a second wiring layer, a second organic film layer, and a first wiring layer on one side of the base substrate, wherein the first wiring layer and the second wiring layer are connected through an opening in the second organic film layer;

[0066] Alternatively, forming the power wiring includes: sequentially forming a third wiring layer, a third organic film layer, a second wiring layer, a second organic film layer, and a first wiring layer on one side of the base substrate, wherein the first wiring layer and the second wiring layer are connected through an opening in the second organic film layer, and the second wiring layer and the third wiring layer are connected through an opening in the third organic film layer;

[0067] The through-groove area is used to expose a first target area of ​​the first wiring layer.

[0068] In yet another aspect, a display device is provided, comprising a power supply component and the display panel according to the above aspect;

[0069] Wherein, the power supply component is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0071] FIG1 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0072] FIG2 is a partial schematic diagram of the display panel shown in FIG1 ;

[0073] FIG3 is a schematic diagram of a substrate provided in an embodiment of the present application;

[0074] FIG4 is a schematic diagram of a stack of power supply lines provided in an embodiment of the present application;

[0075] FIG5 is a schematic diagram of a power supply line with side engraving provided by an embodiment of the present application;

[0076] FIG6 is a schematic diagram of a power supply routing according to an embodiment of the present application;

[0077] FIG7 is a partial schematic diagram of FIG2;

[0078] FIG8 is a cross-sectional view taken along the AA direction in FIG7;

[0079] FIG9 is a cross-sectional view taken along the BB direction in FIG7;

[0080] FIG10 is a cross-sectional view taken along the CC direction of FIG7;

[0081] FIG11 is a cross-sectional view of FIG7 along the DD direction;

[0082] FIG12 is a cross-sectional view taken along the EE direction in FIG7;

[0083] FIG13 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0084] FIG14 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0085] FIG15 is a schematic diagram of a process for etching a third material layer provided in an embodiment of the present application;

[0086] FIG16 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0087] FIG17 is a schematic diagram of forming an active thin film according to an embodiment of the present application;

[0088] FIG18 is a schematic diagram of a patterning process for an active thin film according to an embodiment of the present application;

[0089] FIG19 is a schematic diagram of forming a first insulating layer according to an embodiment of the present application;

[0090] FIG20 is a schematic diagram of forming a first gate film according to an embodiment of the present application;

[0091] FIG21 is a schematic diagram of patterning a first gate film according to an embodiment of the present application;

[0092] FIG22 is a schematic diagram of forming a second insulating layer according to an embodiment of the present application;

[0093] FIG23 is a schematic diagram of forming a second gate film according to an embodiment of the present application;

[0094] FIG24 is a schematic diagram of patterning a second gate film according to an embodiment of the present application;

[0095] FIG25 is a schematic diagram of forming an interlayer dielectric layer according to an embodiment of the present application;

[0096] FIG26 is a schematic diagram of forming a first source / drain thin film according to an embodiment of the present application;

[0097] FIG27 is a schematic diagram of coating photoresist on a side of a first source / drain film away from a substrate, provided by an embodiment of the present application;

[0098] FIG28 is a schematic diagram of exposing and developing a photoresist according to an embodiment of the present application;

[0099] FIG29 is a schematic diagram of etching a first source / drain film according to an embodiment of the present application;

[0100] FIG30 is a schematic diagram of removing photoresist provided in an embodiment of the present application;

[0101] FIG31 is a schematic diagram of forming a first flat film according to an embodiment of the present application;

[0102] FIG32 is a schematic diagram of patterning a first flat film according to an embodiment of the present application;

[0103] FIG33 is a schematic diagram of forming an anode film according to an embodiment of the present application;

[0104] FIG34 is a schematic diagram of a patterning process for an anode film according to an embodiment of the present application;

[0105] FIG35 is a schematic diagram of forming a pixel defining film according to an embodiment of the present application;

[0106] FIG36 is a schematic diagram of a patterning process for a pixel defining film according to an embodiment of the present application;

[0107] FIG37 is a schematic diagram of applying a photoresist after the anode layer is prepared, provided in an embodiment of the present application;

[0108] FIG38 is a schematic diagram of exposure and development of a photoresist provided in an embodiment of the present application;

[0109] FIG39 is a schematic diagram of etching a third material layer according to an embodiment of the present application;

[0110] FIG40 is a schematic diagram of removing photoresist provided in an embodiment of the present application;

[0111] FIG41 is a schematic diagram of applying a photoresist after a pixel definition layer is prepared, according to an embodiment of the present application;

[0112] FIG42 is a schematic diagram of exposure and development of a photoresist provided in an embodiment of the present application;

[0113] FIG43 is a schematic diagram of etching a third material layer provided in an embodiment of the present application;

[0114] FIG44 is a schematic diagram of removing photoresist provided in an embodiment of the present application;

[0115] FIG45 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0116] FIG46 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0117] FIG47 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0118] FIG48 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0119] FIG49 is an electron microscope diagram of an I-shaped structure in which the area of ​​the first wiring layer not covered by the organic film layer is provided in an embodiment of the present application;

[0120] FIG50 is an electron microscope diagram of a region of a first wiring layer covered by an organic film layer provided in an embodiment of the present application;

[0121] FIG51 is a schematic electron micrograph of residual pixel defining material within an I-shaped structure provided by an embodiment of the present application;

[0122] FIG52 is a schematic diagram of an electron microscope for etching a third material layer according to an embodiment of the present application;

[0123] FIG53 is another electron microscope schematic diagram of etching the third material layer provided in an embodiment of the present application;

[0124] FIG54 is a partially enlarged schematic diagram of the electron microscope schematic diagram shown in FIG53;

[0125] Figure 55 is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0126] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0127] In related art, a display panel includes a display area and a peripheral area surrounding the display area. The display panel includes a barrier structure located in the peripheral area and surrounding the display area to prevent organic material from overflowing from the display area. To prevent water and oxygen from infiltrating the organic material from the peripheral area into the display area, the organic film layer located near the barrier structure needs to be removed. Furthermore, the display panel includes power supply wiring that must pass through the barrier structure from the peripheral area and connect to the pixel unit structures in the display area, thereby providing power signals to the pixel unit structures.

[0128] However, because the organic film layer located near the barrier structure must be removed, the power trace is exposed where the organic film layer is removed. During the film preparation process following the power trace, the exposed portion of the power trace may be undercut, which in turn affects the yield of the display panel and results in poor display quality.

[0129] FIG1 is a schematic diagram of the structure of a display panel 10 provided in an embodiment of the present application. FIG2 is a partial schematic diagram of the display panel 10 shown in FIG1 . Referring to FIG1 and FIG2 , the display panel 10 includes: a base substrate 101, a plurality of pixel units 102, a blocking structure 103, at least one power supply line 104, and a first organic film layer 105.

[0130] Figure 3 is a schematic diagram of a substrate provided in an embodiment of the present application. Referring to Figure 3 , the substrate 101 includes a display area 101a and a peripheral area 101b surrounding the display area 101a. Referring to Figures 1 to 3 , a plurality of pixel units 102 are located in the display area 101a. A blocking structure 103 is located in the peripheral area 101b and surrounds the display area 101a to prevent overflow of organic material from the display area 101a.

[0131] At least one power trace 104 is located on one side of the substrate 101. Each power trace 104 is used to receive a power signal and is connected to the pixel unit 102. Thus, each power trace 104 can be used to transmit a power signal to the pixel unit 102, thereby driving the pixel unit 102 to emit light.

[0132] The first organic film layer 105 is located on a side of the power trace 104 away from the base substrate 101, and the first organic film layer 105 has at least one through-groove region 105a. The orthographic projection of the through-groove region 105a on the base substrate 101 is adjacent to the orthographic projection of the blocking structure 103 on the base substrate 101, and the through-groove region 105a is used to expose the first target region m of the power trace 104.

[0133] Because the first organic film layer 105 is made of an organic material, water and oxygen from the outside may intrude along the first organic film layer 105 into the display area 101a, causing the pixel units 102 in the display area 101a to fail. Therefore, to prevent the pixel units 102 from failing, the first organic film layer 105 located adjacent to the blocking structure 103 can be removed, i.e., the through-groove region 105a designed in the first organic film layer 105 is positioned adjacent to the blocking structure 103. Furthermore, since the first organic film layer 105 located adjacent to the blocking structure 103 is removed, the first target region m of the power trace 104, where the first organic film layer 105 is removed, is exposed. In other words, the through-groove region 105a of the first organic film layer 105 exposes the first target region m of the power trace 104.

[0134] Wherein, the power supply line 104 includes at least a first wiring layer. Referring to Figure 4, the first wiring layer includes a first material layer a1, a second material layer a2 and a third material layer a3 stacked in sequence in a direction away from the base substrate 101. Typically, the material of the first material layer a1 is the same as the material of the third material layer a3, for example, the material of the first material layer a1 and the third material layer a3 is titanium (Ti), while the material of the second material layer a2 is different from the material of the first material layer a1 and the third material layer a3, for example, the material of the second material layer a2 is aluminum (Al). In addition, the display panel 10 also includes other film layers located on the side of the power supply line 104 away from the base substrate 101. In the subsequent preparation process of these other film layers, since the portion of the first wiring layer of the power supply line 104 located in the first target area m is exposed to the outside, the portion of the first wiring layer of the power supply line 104 located in the first target area m is easily affected by the process. Since the material of the second material layer a2 is more easily etched than the material of the first material layer a1 (third material layer a3), referring to FIG. 5 , the first wiring layer is easily side-etched and has an undercut structure.

[0135] Furthermore, the display panel 10 also includes an encapsulation film layer (not shown) for encapsulating the display area 101a. The inorganic material layer included in the encapsulation film layer is prone to cracking at the I-shaped location of the power supply line 104. The presence of these cracks provides an intrusion channel for water and oxygen, which can diffuse along this intrusion channel toward the display area 101a, causing the pixel units 102 in the display area 101a to fail, resulting in black spot defects in the display area 101a.

[0136] From the above analysis, it can be seen that the main reason for the failure of the pixel unit 102 in the display area 101a is that the second material layer a2 of the first routing layer of the power routing line 104 located in the first target area m (the first target area m is not protected by the first organic film layer 105) is etched, resulting in the first routing layer having an I-shaped structure.

[0137] In related art, in order to solve the problem of water and oxygen intrusion caused by the I-shaped structure of the first wiring layer, which in turn causes pixel unit failure, an inorganic film layer (for example, a passivation layer (PVX)) is usually formed on the side of the first wiring layer of the power wiring away from the base substrate 101, so that the inorganic film layer covers the area of ​​the first wiring layer exposed by the first organic film layer, thereby preventing the first wiring layer from having an I-shaped structure when subsequent film layers are formed.

[0138] However, forming an inorganic film layer increases the number of manufacturing steps, such as deposition, exposure, and development, which in turn affects the display panel's production capacity. Furthermore, if the display panel includes multiple source and drain layers (e.g., a first source and drain layer SD1, a second source and drain layer SD2, and a third source and drain layer SD3), the inorganic film layer can only be designed between SD1 and SD2. This means that only SD1 can be used for power routing (the power routing is a single-layer routing), which is not conducive to reducing the display panel's power consumption and has limited routing flexibility.

[0139] Therefore, in the embodiment of the present application, referring to FIG6 , to solve the problem of the I-shaped structure of the first routing layer of the power routing line 104, the orthographic projection of the third material layer a3 of the first routing layer of the power routing line 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101. The orthographic projection of the second material layer a2 of the first routing layer of the power routing line 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101.

[0140] It should be noted that after the preparation of the other film layers included in the display panel 10 on the side of the power trace 104 away from the base substrate 101 is completed, since the second material layer a2 of the first trace layer of the power trace 104 located in the first target area m is etched, the orthographic projection of the second material layer a2 of the first trace layer of the power trace 104 located in the first target area m on the base substrate 101 can be made to be located within the orthographic projection of the first material layer a1 on the base substrate 101. Furthermore, referring to FIG6 , after the subsequent film layers are prepared, an etching process can be used to etch the third material layer a3 of the first trace layer of the power trace 104 located in the first target area m, so that the orthographic projection of the third material layer a3 of the power trace 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, thereby avoiding the portion of the first trace layer of the power trace 104 located in the first target area m from forming an I-shaped structure.

[0141] Furthermore, the inorganic material layer in the encapsulation film layer included in the display panel 10 can be gradually ramped in the first target area m, thereby preventing cracks in the inorganic material layer and thus preventing water and oxygen intrusion. This ensures the luminous effect of the pixel unit 102 in the display area 101a and avoids the occurrence of black spots in the display area 101a.

[0142] In summary, an embodiment of the present application provides a display panel, in which the first routing layer of the power routing in the display panel has a first target area exposed by the through-groove area of ​​the first organic film layer, and the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate. The orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate. Thus, it is possible to prevent the encapsulation film layer subsequently formed on the display panel from generating cracks in the first target area, thereby preventing water and oxygen from invading the display area along the intrusion channels generated by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel units in the display area, avoid the occurrence of black spots in the display area, and the yield of the display panel is high, and the display effect of the display panel is good.

[0143] Figure 7 is a partial schematic diagram of Figure 2. Figure 8 is a cross-sectional view of Figure 7 along the AA direction. Figures 9 to 7 are cross-sectional views along the BB direction. Figure 10 is a cross-sectional view of Figure 7 along the CC direction. Figure 11 is a cross-sectional view of Figure 7 along the DD direction, and Figure 12 is a cross-sectional view of Figure 7 along the EE direction. In conjunction with Figures 7 to 11, the first material layer a1 of the first routing layer of the power trace 104 located in the first target area m has a first boundary a11 extending along the first direction X. This first boundary a11 may be the midline of the side surface of the first material layer a1 along its thickness. The second material layer a2 of the first routing layer of the power trace 104 located in the first target area m has a second boundary a21 along the first direction X. This second boundary a21 may be the midline of the side surface of the second material layer a2 along its thickness. The third material layer a3 of the first routing layer of the power trace 104 located in the first target area m has a third boundary a31 extending along the first direction X. This third boundary a31 may be the midline of the side surface of the third material layer a3 along its thickness. The inorganic film layers in Figures 8 to 12 refer to film layers composed entirely of inorganic materials and located on the side of the power trace 104 close to the base substrate. The organic film layers in Figures 8 to 12 refer to film layers composed of organic materials, such as the first organic film layer 105 located on the side of the first trace layer of the power trace 104 away from the base substrate 101.

[0144] Typically, the size of the side engraving of the second material layer a2 during the subsequent film preparation process is usually less than 3 microns (μm). Therefore, in order to ensure that the orthographic projection of the third material layer a3 on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, the distance between the first boundary a11 and the third boundary a31 in the second direction Y can be greater than 3μm. The second boundary a21 is located between the first boundary a11 and the third boundary a31, thereby making the first material layer a1, the second material layer a2, and the third material layer a3 present a step structure that increases layer by layer. The second direction Y is perpendicular to the first direction X. For example, the first direction X is the pixel column direction of the display panel 10, and the second direction Y is the pixel row direction of the display panel 10.

[0145] The second boundary a21 being located between the first boundary a11 and the third boundary a31 may mean that the orthographic projection of the second boundary a21 on the base substrate 101 is located between the orthographic projection of the first boundary a11 on the base substrate 101 and the orthographic projection of the third boundary a31 on the base substrate 101.

[0146] Assuming that the organic film layer shown in FIG12 is the first organic film layer 105, referring to FIG12, the first organic film layer 105 has a recessed region 105b. The thickness h1 of the first organic film layer 105 in the recessed region 105b is less than the thickness h2 of the other regions excluding the recessed region 105b. The recessed region 105b is used to cover the second target region n of the power trace 104. The second target region n and the first target region m are adjacent in the first direction X.

[0147] Optionally, the third material layer a3 of the first routing layer of the power routing trace 104 located in the first target region m and the recessed region 105b of the first organic film layer 105 can be etched using the same etching process. For example, during the etching process, the same mask opening in the reticle can be used to form the etched third material layer a3 and the recessed region 105b. For example, during the etching process, the length w1 of the etched region along the first direction X can be slightly greater than the length of the first target region m along the first direction X. The length w2 along the second direction Y can be determined based on the product. It is sufficient to ensure that the third boundary a31 of the first routing layer is farther from the first boundary a11 relative to the second boundary a21.

[0148] 7 , the recessed region 105 b has a first recessed boundary 105 b 1 located near the first wiring layer of the power supply wiring 104 and extending along the first direction X. Since the recessed region 105 b and the third material layer a3 are formed using the same etching process, assuming the mask opening in the mask is a rectangular opening, the orthographic projection of the first recessed boundary 105 b 1 on the base substrate 101 is collinear with the orthographic projection of the third boundary a31 on the base substrate 101.

[0149] Because the second target region n and the first target region m of the first routing layer of the power trace 104 are adjacent in the first direction X, the groove region 105b covering the second target region n and the through-groove region 105a exposing the first target region m in the first organic film layer 105 are adjacent in the first direction X. Referring to FIG. 7 , the groove region 105b further includes a second groove boundary 105b2 extending away from the through-groove region 105a and along the second direction Y, and a third groove boundary 105b3 adjacent to the through-groove region 105a and extending along the second direction Y. The distance b between the second groove boundary 105b2 and the third groove boundary 105b3 in the first direction X is greater than 3 μm. This ensures that the third material layer a3 of the power trace 104 located in the first target region m is etched, preventing the power trace 104 from forming an I-shaped structure due to a smaller etching range.

[0150] In an embodiment of the present application, when an etching process is used to etch the third material layer a3 of the first routing layer of the power routing 104 located in the first target area m, a portion of the second material layer a2 of the first routing layer located in the first target area m may also be etched away. Of course, the second material layer a2 of the first routing layer located in the first target area m may not be etched away.

[0151] If a portion of the second material layer a2 of the first routing layer located in the first target region m is etched away, the thickness of the portion of the second material layer a2 located in the first target region m will be less than the thickness of the portion of the second material layer a2 located in other regions. In this case, due to the influence of the current process, the surface of the portion of the second material layer a2 located in the first target region (m) away from the base substrate 101 is uneven. Of course, with subsequent process improvements, the surface of the portion of the second material layer a2 located in the first target region (m) away from the base substrate 101 can also be made flat.

[0152] If the second material layer a2 of the first wiring layer located in the first target area m is not etched, the thickness of the second material layer a2 located in the first target area m may be equal to the thickness of the second material layer a2 located in other areas.

[0153] As a first optional implementation, the display panel 10 includes: an active layer (poly), a first insulating layer, a first gate layer (gate1), a second insulating layer, a second gate layer (gate2), a third insulating layer, an oxide layer (IGZO), a fourth insulating layer, a third gate layer (gate3), an inter-level dielectric layer (ILD), a first source-drain layer (SD1), a first planarization layer (PLN), a second source-drain layer (SD2), a second planarization layer (PLN2), a third source-drain layer (SD3), and a third planarization layer (PLN3). That is, the display panel 10 has three source-drain layers. In this implementation, the organic film layers in Figures 8 to 12 include a first planarization layer, a second planarization layer, and a third planarization layer, and the inorganic film layers in Figures 8 to 12 include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and an inter-level dielectric layer.

[0154] In this case, the power trace 104 can be routed using one, two, or three layers of the first source / drain layer (SD1), the second source / drain layer (SD2), and the third source / drain layer (SD3). In other words, the power trace 104 can include one, two, or three layers of traces. If the power trace 104 is routed using multiple layers, it is necessary to ensure that the traces on the upper layer cover the traces on the lower layer to prevent the traces on the lower layer from being exposed and affecting the traces on the lower layer during subsequent film fabrication.

[0155] Optionally, the power supply wiring 104 includes a third wiring layer, a second wiring layer, and a first wiring layer stacked in sequence in a direction away from the base substrate 101. The third wiring layer is located in the first source and drain layer (SD1) of the display panel 10, the second wiring layer is located in the second source and drain layer (SD2), and the first wiring layer is located in the third source and drain layer (SD3). The first flat layer (third organic film layer) between the first source and drain layer and the second source and drain layer has an opening, and the third layer wiring and the second layer wiring are connected through the opening in the first flat layer. The second flat layer (second organic film layer) between the second source and drain layer and the third source and drain layer has an opening, and the second layer wiring and the first layer wiring are connected through the opening in the first flat layer.

[0156] Optionally, the first organic film layer 105 has a through-groove region 105a, and the second and third organic film layers also have through-groove regions 105a. That is, the area next to the blocking structure 103 where the first organic film layer 105 is removed also removes the second and third organic film layers. In other words, the through-groove region 105a refers to the area where all film layers composed of organic materials included in the display panel 10 are removed. Since the first layer of wiring covers the second and third layers of wiring, the design of the through-groove region 105a can expose the first target area m of the first wiring layer without exposing the second and third wiring layers.

[0157] Therefore, during the subsequent film layer preparation process, only the first routing layer located at the top may have an I-shaped structure. Therefore, an etching process can be used to etch the third layer routing located in the first target area m of the first layer routing to prevent the first layer routing from forming an I-shaped structure. In this implementation, the power routing 105 shown in Figures 7 to 12 can be the first layer routing included in the power routing 105, and Figures 7 to 12 do not show the second layer routing and the third layer routing.

[0158] In the embodiment of the present application, when the display panel 10 has three source and drain electrode layers, the display panel 10 may be an oxide (low temperature polycrystalline oxide, LTPO) display panel, which includes oxide thin film transistors.

[0159] As a second optional implementation, the display panel 10 includes: an active layer (poly), a first insulating layer, a first gate layer (gate1), a second insulating layer, a second gate layer (gate2), an interlayer dielectric layer (ILD), a first source and drain layer (SD1), a first planarization layer (PLN1), a second source and drain layer (SD2), and a second planarization layer (PLN2). In other words, the display panel 10 has two source and drain layers.

[0160] In this case, the power supply trace 104 can be routed on one or both of the first source / drain layer and the second source / drain layer. That is, the power supply trace 104 can include one or two layers of traces. If the power supply trace 104 is routed on two layers, it is necessary to ensure that the traces on the upper layer cover the traces on the lower layer to prevent the traces on the lower layer from being exposed and affecting the traces on the lower layer during subsequent film fabrication.

[0161] Optionally, the power supply trace 104 includes a second trace layer and a first trace layer stacked sequentially in a direction away from the base substrate 101. The second trace layer is located in the first source / drain layer (SD1) of the display panel 10, and the first trace layer is located in the second source / drain layer (SD2). The first planar layer (second organic film layer) between the first source / drain layer and the second source / drain layer has an opening, and the second trace layer and the first trace layer are connected through the opening in the first planar layer.

[0162] Optionally, where the first organic film layer 105 has the through-groove region 105a, the second organic film layer also has the through-groove region 105a. That is, where the first organic film layer 105 is removed from the area next to the blocking structure 103, the second organic film layer is also removed. In other words, the through-groove region 105a refers to the region where all film layers composed of organic materials included in the display panel 10 have been removed. Because the first layer of wiring covers the second layer of wiring, the design of the through-groove region 105a can expose the first target area m of the first wiring layer without exposing the second wiring layer.

[0163] Therefore, during the subsequent film layer preparation process, only the first routing layer located on the upper layer may have an I-shaped structure. Therefore, an etching process can be used to etch the third layer routing located in the first target area m of the first layer routing to prevent the first layer routing from forming an I-shape. In this implementation, the power routing 105 shown in Figures 7 to 12 can be the first layer routing included in the power routing 105, and Figures 7 to 12 do not show the second layer routing.

[0164] In the embodiment of the present application, when the display panel 10 has two source and drain electrode layers, the display panel 10 may be a low temperature polysilicon (LTPS) display panel, and the LTPS display panel includes LTPS thin film transistors.

[0165] As a third optional implementation, the display panel 10 includes: an active layer (poly), a first insulating layer, a first gate layer (gate1), a second insulating layer, a second gate layer (gate2), an interlayer dielectric layer (ILD), a first source and drain electrode layer (SD1), and a first planarization layer (PLN1). In other words, the display panel 10 has a single source and drain electrode layer.

[0166] In this case, the power trace 104 can be routed using the first source and drain layer. That is, the power trace 104 can include a single layer of traces. Alternatively, the power trace 104 can include a first trace layer, and the first planar layer on the first trace layer can be the first organic film layer 105 described in the above embodiment. In this implementation, the power trace 105 shown in Figures 7 to 12 can be the first layer of traces included in the power trace 105.

[0167] In the embodiment of the present application, when the display panel 10 has a source and drain electrode layer, the display panel 10 may be a low-temperature polycrystalline silicon (LTPS) display panel, and the LTPS display panel includes LTPS thin film transistors.

[0168] 2 , at least one power supply line 104 includes a first signal power supply line 104 a and a second signal power supply line 104 b spaced apart in a second direction Y. The first signal power supply line 104 a can provide a first signal to the pixel unit 102. The first signal power supply line 104 a can be a negative power supply line (referred to as a VSS line). The second signal power supply line 104 b can provide a second signal to the pixel unit 102. The second signal power supply line 104 b can be a positive power supply line (referred to as a VDD line).

[0169] Typically, other signal lines may be designed in the area where the VSS line is set up, and these other signal lines may also be double-layered, requiring an insulating layer to insulate the double-layered wiring. Therefore, referring to FIG2 , the through-slot area 105a has a first sub-through-slot area 105a1 for exposing the first signal power line 104a and a second sub-through-slot area 105a2 for exposing the second signal power line 104b. The length k1 of the first sub-through-slot area 105a1 along the first direction X is less than or equal to the length k2 of the second sub-through-slot area 105a2 along the first direction X. This allows the first sub-through-slot area 105a1 in the area where the VSS line is set up to be designed to be smaller, allowing the organic film layer in this area to insulate the double-layered wiring of other signal lines.

[0170] In the embodiment of the present application, the orthographic projection of the power trace 104 on the base substrate 101 partially overlaps with the orthographic projection of the blocking structure 103 on the base substrate 101. As a result, a portion of the power trace 104 is located on the side of the blocking structure 103 close to the display area 101a to connect to the pixel unit 102, while another portion of the power trace 104 is located on the side of the blocking structure 103 away from the display area 101a to receive the power signal.

[0171] Optionally, the orthographic projection of the blocking structure 103 on the substrate 101 can be a ring-shaped structure. A portion of the power supply line 104 located on the side of the blocking structure 103 close to the display area 101a is located within the area enclosed by the blocking structure 103. Another portion of the power supply line 104 located on the side of the blocking structure 103 away from the display area 101a is located outside the area enclosed by the blocking structure 103. Thus, the power supply line 104 can pass through the blocking structure 103 and enter the area enclosed by the blocking structure 103. The portion of the blocking structure 103 through which the power supply line 104 passes can also be referred to as a port.

[0172] 1 and 2 , the barrier structure 103 may include a first barrier dam 1031, a second barrier dam 1032, and a third barrier dam 1033. The first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033 are sequentially arranged in a direction away from the display area 101a. Furthermore, gaps are formed between adjacent barrier dams among the first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033.

[0173] Optionally, the through-groove region 105a can be located on the side of the third barrier dam 1033 away from the display area 101a, and can also be located between adjacent barrier dams. Two through-groove regions 105a are designed in FIG2 , one of which is located on the side of the third barrier dam 1033 away from the display area 101a, and the other is located between the second barrier dam 1032 and the third barrier dam 1033. Furthermore, no through-groove region 105a is designed between the first barrier dam 1031 and the second barrier dam 1032, and the through-groove region 105a between the second barrier dam 1032 and the third barrier dam 1033 is located only in the area where the first power signal line is located, and not in the area where the second power signal line is located. This design approach allows the cathode layer and the barrier dam to overlap, facilitating the realization of a narrow bezel for the display panel.

[0174] It should be noted that a through groove region 105 a may be designed between the first barrier dam 1031 and the second barrier dam 1032 , and between the second barrier dam 1032 and the third barrier dam 1033 .

[0175] In the embodiment of the present application, each barrier dam in the barrier structure 103 comprises at least one layer of the organic film layers in the display panel. Specifically, the organic film layers in the display panel 10 include: a third organic film layer, a second organic film layer, and a first organic film layer. Of course, the organic film layers in the display panel 10 also include: a pixel definition layer and a support layer.

[0176] Among them, one of the first organic film layer, the second organic film layer, and the third organic film layer is located in an area adjacent to any barrier dam in the barrier structure 103 and where no through-groove area 105a is provided. In other words, if a through-groove area 105a or an organic film layer is provided between adjacent barrier dams or next to a barrier dam.

[0177] Optionally, the heights of the first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033 may increase sequentially as they move away from the display area 101a. That is, the height of the first barrier dam 1031 is smaller than the height of the second barrier dam 1032, and the height of the second barrier dam 1032 is smaller than the height of the third barrier dam 1033. Alternatively, the heights of the first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033 may be equal. This embodiment of the present application is not limited to this.

[0178] In the embodiment of the present application, the display panel 10 further includes an encapsulation film layer (not shown) for encapsulating the display area 101a. The encapsulation film layer may include: a first film layer, a second film layer, and a third film layer stacked in a direction away from the base substrate 101.

[0179] Optionally, the first film layer and the third film layer may be made of an inorganic material, and the second film layer may be made of an organic material. For example, the first film layer and the third film layer may be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride). The second film layer may be made of a resin material. The resin may be a thermoplastic resin or a thermoplastic resin. The thermoplastic resin may include acrylic (PMMA) resin, and the thermosetting resin may include epoxy resin.

[0180] It should be noted that the second film layer can be located within the area enclosed by the blocking structure 103, and the first film layer and the third film layer can cover the area enclosed by the blocking structure 103 and cover the blocking structure 103. That is, the orthographic projections of the first film layer and the third film layer on the base substrate 101 can be located on the side of the blocking structure 103 away from the display area 101a, that is, can be located in the first target area m of the power trace 104.

[0181] Therefore, by etching the third layer of the power trace 104 located in the first target area m, the power trace 104 is prevented from being in an I-shape, thereby preventing the first and third film layers of the packaging film layer from cracking in the first target area m.

[0182] Optionally, the second film layer may be manufactured by ink jet printing (IJP) and the first film layer and the third film layer may be manufactured by chemical vapor deposition (CVD).

[0183] In the embodiment of the present application, in the area of ​​the power trace 104 covered by the organic film layer in the display panel 10, the side edges of the third material layer a3, the second material layer a2, and the first material layer a1 are flat side edges, and the flat side edges are inclined relative to the supporting surface of the base substrate 101. Specifically, the orthographic projection of the third material layer a3 on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, and the orthographic projection of the second material layer a2 on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101.

[0184] In summary, an embodiment of the present application provides a display panel, in which the first routing layer of the power routing in the display panel has a first target area exposed by the through-groove area of ​​the first organic film layer, and the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate. The orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate. Thus, it is possible to prevent the encapsulation film layer subsequently formed on the display panel from generating cracks in the first target area, thereby preventing water and oxygen from invading the display area along the intrusion channels generated by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel units in the display area, avoid the occurrence of black spots in the display area, and the yield of the display panel is high, and the display effect of the display panel is good.

[0185] FIG13 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present application. Referring to FIG13 , the method includes:

[0186] Step S101: provide a base substrate.

[0187] 3 , the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0188] Step S102 : forming a plurality of pixel units, a blocking structure and at least one initial power supply line on one side of the substrate.

[0189] In particular, multiple pixel units 102 are located in the display area 101a, and the blocking structure 103 surrounds the display area 101a. Each initial power supply line is used to receive a power signal and is connected to the multiple pixel units 102 to provide a power signal to the multiple pixel units 102. The initial power supply line includes at least a first initial wiring layer, which includes a first material layer a1, a second material layer a2, and a third material layer a3 stacked in sequence in a direction away from the base substrate 101.

[0190] Optionally, the material of the first material layer a1 is the same as the material of the third material layer a3, and the material of the second material layer a2 is different from the materials of the first material layer a1 and the third material layer a3.

[0191] Step S103 : forming an initial organic film layer on a side of the initial power supply line away from the base substrate.

[0192] In the embodiment of the present application, the initial organic film layer has at least one through-groove region 105a, the orthographic projection of the through-groove region 105a on the base substrate 101 being adjacent to the orthographic projection of the blocking structure 103 on the base substrate 101. The through-groove region 105a is used to expose the first target region m of the initial power supply line.

[0193] Step S104 , etching the third material layer of the first initial wiring layer of at least one initial power wiring located in the first target area and etching the initial organic film layer to obtain the first wiring layer and the first organic film layer of at least one initial power wiring.

[0194] Referring to Figure 11, the first routing layer of the power routing 104 is located in the first target area m, and the orthographic projection of the third material layer a3 on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, and the first routing layer of the power routing 104 is located in the first target area m, and the orthographic projection of the second material layer a2 on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101.

[0195] In summary, an embodiment of the present application provides a method for preparing a display panel, wherein the first routing layer of the power routing in the display panel prepared by the method has a first target area exposed by the through-groove area of ​​the first organic film layer, and the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate. The orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate. Thus, it is possible to avoid cracks in the encapsulation film layer subsequently formed on the display panel, thereby preventing water and oxygen from invading the display area along the intrusion channels created by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel units in the display area, avoid the occurrence of black spots in the display area, and have a high yield and a good display effect of the display panel.

[0196] In the first implementation, FIG14 is a flow chart of another method for manufacturing a display panel provided by an embodiment of the present application. Taking the power supply line 104 including the first wiring layer as an example, referring to FIG14 , the method includes:

[0197] Step S201: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0198] In an embodiment of the present application, the active layer includes a plurality of active patterns, each of which can be used to constitute a thin film transistor in the pixel circuit included in the pixel unit 102. The first insulating layer is used to insulate the active layer from the first gate layer. The first gate layer includes a plurality of first gate patterns, and the orthographic projection of each first gate pattern on the base substrate 101 partially overlaps with the orthographic projection of an active pattern on the base substrate 101, and the overlapping area can be a channel of the thin film transistor. The second insulating layer is used to insulate the first gate layer from the second gate layer. The second gate layer includes a plurality of second gate patterns, each of which can be used to constitute a plate of a storage capacitor in the pixel circuit. The interlayer dielectric layer is used to insulate the second gate layer from the first source and drain layer formed subsequently.

[0199] Step S202 : forming a first source / drain electrode layer and an initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0200] In the embodiment of the present application, the first source and drain layer includes at least a first wiring layer of the power wiring 104. The first wiring layer includes a first material layer a1, a second material layer a2, and a third material layer a3 stacked in sequence in a direction away from the base substrate 101.

[0201] Optionally, the first material layer a1 and the third material layer a3 may both be made of titanium (Ti), and the second material layer a2 may be made of aluminum (Al). That is, the first wiring layer may be a triple-layer structure of Ti / Al / Ti.

[0202] In the embodiment of the present application, the initial planarizing layer (initial organic film layer) has at least one through-groove region 105a, which is used to expose the first target region m of the first layer of wiring. Furthermore, the initial planarizing layer includes a pattern for forming the blocking structure 103 in the display panel 10. For example, the initial planarizing layer includes at least one annular pattern surrounding the display region 101a, which is used to form a blocking dam in the blocking structure 103.

[0203] The through-groove region 105 a and the annular pattern used to form a barrier dam in the barrier structure 103 are adjacently arranged, that is, the through-groove region 105 a and the barrier structure 103 are adjacently arranged.

[0204] Step S203 : forming an anode layer of a plurality of pixel units on a side of the initial planar layer away from the base substrate.

[0205] In the embodiment of the present application, the process of forming the anode layer includes forming an anode film on a side of the initial flat layer away from the base substrate 101, and processing the anode film using a patterning process to form the anode layer of the plurality of pixel units 102. The patterning process includes photoresist coating, exposure, development, etching, and photoresist removal.

[0206] The developer used in the development process of preparing the anode layer will affect the first target area m of the first wiring layer, and will have a greater impact on the second material layer a2 of the first wiring layer.

[0207] For example, before forming the anode layer, the first boundary a11 of the first material layer a1 of the first target area m, the second boundary a21 of the second material layer a2, and the third boundary a31 of the third material layer a3 of the first routing layer are collinear. After forming the anode layer, the developer used to prepare the anode layer will side-etch the second material layer a2. The orthographic projection of the second material layer a2 of the first routing layer located in the first target area m on the base substrate 101 is located within the orthographic projection of the third material layer a3 on the base substrate 101, and the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m and the third boundary a31 of the third material layer a3 are collinear. That is, after forming the anode layer, the first routing layer has an I-shaped structure. Among them, the first boundary a11, the second boundary a21, and the third boundary a31 all extend along the first direction X.

[0208] Since the first routing layer needs to be etched later, in order to distinguish the first routing layer before and after etching, the layer before etching is referred to as the first initial routing layer, and the layer after etching is referred to as the first routing layer.

[0209] Step S204 : etching the third material layer of the first initial routing layer located in the first target area and etching the initial planar layer using an etching process to obtain a first routing layer and a first planar layer.

[0210] In the embodiment of the present application, since the portion of the first initial routing layer located in the first target region m is exposed and has an I-shaped structure due to the influence of the developer of the anode layer in step S203, an etching process can be used to etch the third material layer a3 of the first initial routing layer located in the first target region m, thereby obtaining the first routing layer. This process can be referred to as a TTE (Top Ti Etch) process.

[0211] Referring to Figure 11 , in the first routing layer obtained through this etching process, the orthographic projection of the third material layer a3 in the first target region m on the base substrate 101 lies within the orthographic projection of the second material layer a2 in the first target region m on the base substrate 101. In other words, the I-shaped structure of the first initial routing layer can be eliminated, resulting in a stepped structure for the final first-layer routing.

[0212] It should be noted that, during the etching process of the third material layer a3 in the first target area m, in order to ensure sufficient etching of the third material layer a3, a portion of the initial flat layer may also be etched to obtain the final first flat layer (the first flat layer is the first organic film layer 105). Furthermore, the formed first flat layer has a recessed region 105b, and the thickness of the portion of the first flat layer located in the recessed region 105b is thinner than the thickness of the portion located in other regions.

[0213] Referring to Figure 15, the etching process includes: coating photoresist on the side of the initial organic film layer and the first target area m of the first initial wiring layer away from the substrate; exposing the photoresist using a mask; developing the photoresist using a developer to remove the exposed portion of the photoresist; using an etching process to remove the third material layer of the first initial wiring layer located in the first target area and the portion of the initial organic film layer not protected by the photoresist; and removing the remaining photoresist.

[0214] In the embodiment of the present application, referring to Figures 2 and 7 , the mask has multiple mask openings, each of which has a first mask boundary extending along a first direction X. The first mask boundary is used to form a third boundary a31 of the third material layer a3 after etching. The orthographic projection of the first mask boundary on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101. Furthermore, the distance between the first mask boundary and the first boundary a11 in the second direction Y is greater than 3 μm. This ensures that the distance between the third boundary a13 and the first boundary a11 in the second direction Y is greater than 3 μm.

[0215] Furthermore, the first mask boundary is used to form a first groove boundary 105b1 in the groove region 105b of the first organic film layer 105 after etching. The first groove boundary 105b1 is located adjacent to the first routing layer of the power trace 104 and extends along the first direction X. Referring to FIG. 11 , the thickness of the first organic film layer 105 in the groove region 105b is less than the thickness of other regions outside the groove region 105b. The groove region is used to cover a second target region n in the first routing layer of the power trace 104. This second target region n is adjacent to the first target region m in the first direction X.

[0216] The mask opening also has a second mask boundary extending along the second direction Y. The through-groove region 105a is located on one side of the second mask boundary. This second mask boundary is used to form a second groove boundary 105b2 of the groove region 105b of the first organic film layer 105, which is away from the through-groove region 105a and extends along the second direction Y. The groove region 105b also has a third groove boundary 105b3 adjacent to the through-groove region 105a and extending along the second direction Y. The distance between the second groove boundary 105b2 and the third groove boundary 105b3 in the first direction X is greater than 3 μm.

[0217] Step S205 : forming a pixel defining layer, a light emitting layer, and a cathode layer in sequence on a side of the anode layer away from the base substrate.

[0218] In an embodiment of the present application, the pixel defining layer may have multiple hollow regions, each of which may be used to expose an anode pattern in the anode layer. The preparation process of the pixel defining layer includes: forming a pixel defining film on a side of the anode layer away from the base substrate 101, and processing the pixel defining film using a patterning process to obtain the pixel defining layer.

[0219] If the third material layer a3 in the first target area m (the first wiring layer has an I-shaped structure) is not etched using an etching process, pixel definition material will remain within the I-shaped structure after the pixel definition layer is prepared. Typically, this pixel definition material is an organic material (such as polyimide (PI)). Therefore, this pixel definition material will absorb water and oxygen, which may affect the display of the display panel 10.

[0220] However, the solution of the embodiment of the present application has eliminated the I-shaped structure of the first wiring layer through the above-mentioned step S204. Therefore, after the pixel definition layer is prepared, no pixel definition material will usually remain at the position of the first wiring layer, and thus will not affect the display of the display panel 10.

[0221] After the pixel definition layer is prepared, the light-emitting layer and cathode layer can be prepared in sequence, thereby completing the preparation of multiple pixel units 102 and realizing the display of the display panel 10. Generally, the cathode layer of multiple pixel units 102 can be a common film layer, and the cathode layer can be located in the peripheral area 101b in addition to the display area 101a. In addition, the boundary of the cathode layer in the peripheral area 101b is located on the side of the through-groove area 105a close to the display area 101a, avoiding the cathode layer from being directly connected to the power supply line 104 of different signals through the through-groove area 105a, thereby preventing short circuits.

[0222] Step S206 : forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0223] In the embodiment of the present application, the packaging film layer may include: a first film layer, a second film layer, and a third film layer stacked in a direction away from the base substrate 101 .

[0224] Optionally, the first film layer and the third film layer may be made of an inorganic material, and the second film layer may be made of an organic material. For example, the first film layer and the third film layer may be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride). The second film layer may be made of a resin material. The resin may be a thermoplastic resin or a thermoplastic resin. The thermoplastic resin may include acrylic (PMMA) resin, and the thermosetting resin may include epoxy resin.

[0225] It should be noted that the second film layer can be located within the area enclosed by the blocking structure 103, and the first film layer and the third film layer can cover the area enclosed by the blocking structure 103 and cover the blocking structure 103. That is, the orthographic projections of the first film layer and the third film layer on the base substrate 101 can be located on the side of the blocking structure 103 away from the display area 101a, that is, can be located in the first target area m of the first wiring layer.

[0226] Therefore, by etching the third layer of wiring in the first target area m in the first initial wiring layer, the first wiring layer formed finally is prevented from being I-shaped, thereby preventing the first film layer and the third film layer of the packaging film layer from cracking in the first target area m.

[0227] Optionally, the second film layer may be manufactured by IJP, and the first film layer and the third film layer may be manufactured by CVD.

[0228] Since the I-shaped structure of the first wiring layer has been removed in the above step S204, even if the first film layer and the third film layer of the packaging film layer cover the first target area m, they will not break due to the existence of the I-shaped structure. Instead, the step structure in the first target area m can climb layer by layer, thereby avoiding the formation of an intrusion channel for water and oxygen, and avoiding the occurrence of black spots in the display area 101a.

[0229] In the second implementation, FIG16 is a flow chart of another method for manufacturing a display panel provided by an embodiment of the present application. Taking the power supply line 104 including the first line layer as an example, referring to FIG16 , the method includes:

[0230] Step S301: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0231] In the embodiment of the present application, the specific process of step S301 can refer to the relevant description in the above-mentioned step S201, and the embodiment of the present application will not be repeated here.

[0232] Step S302 : forming a first source / drain electrode layer and an initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0233] In the embodiment of the present application, the specific process of step S302 can refer to the relevant description in the above-mentioned step S202, and the embodiment of the present application will not be repeated here.

[0234] Step S303 : forming an anode layer of a plurality of pixel units on a side of the initial planar layer away from the base substrate.

[0235] In the embodiment of the present application, the specific process of step S303 can refer to the relevant description in the above-mentioned step S203, and the embodiment of the present application will not be repeated here.

[0236] Step S304 : forming a pixel defining layer on a side of the anode layer away from the base substrate.

[0237] In an embodiment of the present application, the pixel defining layer may have multiple hollow regions, each of which may be used to expose an anode pattern in the anode layer. The preparation process of the pixel defining layer includes: forming a pixel defining film on a side of the anode layer away from the base substrate 101, and processing the pixel defining film using a patterning process to obtain the pixel defining layer.

[0238] Because the third material layer a3 in the first target area m was not etched using an etching process after the anode layer was prepared, the first routing layer has an I-shaped structure. Therefore, after the pixel definition layer is prepared, the first routing layer has a retracted area, and some of the pixel definition layer material will be located in the retracted area (i.e., pixel definition material will remain within the I-shaped structure). This retracted area is the area of ​​the first routing layer that contains the first material layer a1 and the third material layer a3, and does not contain the second material layer a2.

[0239] Step S305 : Etching the third material layer of the first initial routing layer located in the first target area and etching the initial planar layer using an etching process to obtain a first routing layer and a first planar layer.

[0240] In the embodiment of the present application, the portion of the first initial routing layer located in the first target region m is exposed and, in step S303, is affected by the developer of the anode layer to form an I-shaped structure. Furthermore, in step S304, pixel defining material remains within the I-shaped structure. Therefore, in order to eliminate the I-shaped structure and remove the remaining pixel defining material, an etching process can be used to etch the third material layer a3 of the first initial routing layer located in the first target region m, thereby obtaining the first routing layer. This process can be referred to as a TTE process.

[0241] Referring to Figure 11 , in the first routing layer obtained through this etching process, the orthographic projection of the third material layer a3 in the first target region m on the base substrate 101 lies within the orthographic projection of the second material layer a2 in the first target region m on the base substrate 101. This eliminates the I-shaped structure of the first initial routing layer, resulting in a stepped structure for the final first-layer routing. Furthermore, any remaining pixel-defining material in the I-shaped structure can be removed.

[0242] It should be noted that during the etching of the third material layer a3 in the first target area m, in order to ensure sufficient etching of the third material layer a3, a portion of the initial flat layer may also be etched to ultimately form a first flat layer. Furthermore, the formed first flat layer includes a recessed region 105b, and the thickness of the portion of the first flat layer located in the recessed region 105b is thinner than that of the portion located in other regions.

[0243] In addition, the specific process of the etching process can refer to the above-mentioned step S204, and will not be repeated here in the embodiment of the present application.

[0244] Step S306 : forming a light emitting layer and a cathode layer in sequence on a side of the pixel defining layer away from the base substrate.

[0245] After the pixel definition layer is prepared, the light-emitting layer and cathode layer can be prepared in sequence, thereby completing the preparation of multiple pixel units 102 and realizing the display of the display panel 10. Generally, the cathode layer of multiple pixel units 102 can be a common film layer, and the cathode layer can be located in the peripheral area 101b in addition to the display area 101a. In addition, the boundary of the cathode layer in the peripheral area 101b is located on the side of the through-groove area 105a close to the display area 101a, avoiding the cathode layer from being directly connected to the power supply line 104 of different signals through the through-groove area 105a, thereby preventing short circuits.

[0246] Step S307 : forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0247] In the embodiment of the present application, the specific process of step S307 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0248] In the above-mentioned first and second implementations, the cross-sectional view in the DD direction in FIG7 is taken as an example for specific description. Referring to FIG17 to FIG34, the steps include: forming an active thin film; patterning the active thin film (coating photoresist, exposing, developing, etching and removing the photoresist); forming a first insulating layer; forming a first gate thin film; patterning the first gate thin film (coating photoresist, exposing, developing, etching and removing the photoresist); forming a second insulating layer; forming a second gate thin film; patterning the second gate thin film (coating photoresist, exposing, developing, etching and removing the photoresist); forming an interlayer dielectric layer; forming a first source and drain thin film (the first source and drain thin film is used to form the source and drain electrodes of the thin film transistor); The first source-drain film includes a first material layer, a second material layer, and a third material layer; a photoresist is coated on the side of the first source-drain film away from the substrate; the photoresist is exposed using a mask and developed using a developer; the first source-drain film is etched to form a first routing layer; the remaining photoresist is removed; a first flat film is formed; the first flat film is patterned (coating photoresist, exposing, developing, etching, and removing the photoresist), and after patterning, a through-groove area of ​​the first flat layer is formed, exposing the first target area of ​​the first routing layer. As can be seen in Figure 32, after the first flat film is patterned, due to the influence of the process, the second material layer a2 is inset relative to the first material layer a1 and the third material layer a3; referring to Figure 33, an anode film is formed; the anode film is patterned (coating photoresist, exposing, developing, etching, and removing the photoresist). As can be seen from FIG34 , after the anode film is patterned, the second material layer a2 is further inscribed relative to the first material layer a1 and the third material layer a3 due to the influence of the process.

[0249] Referring to Figures 35 and 36 , after patterning the anode film, directly forming the pixel-defining film and patterning the pixel-defining film, residual pixel-defining material will be present in the recessed area of ​​the second material layer a2 relative to the first material layer a1 and the third material layer a3. If the third material layer a3 is not subsequently etched, the first wiring layer will have an I-shaped structure, and residual pixel-defining material will remain within the I-shaped structure. This will cause the subsequent encapsulation film to crack at the location of the I-shaped structure, and the presence of residual pixel-defining material (organic material) will form an intrusion channel for water and oxygen, affecting the yield of the pixel units in the display area.

[0250] In an embodiment of the present application, as an optional implementation, referring to Figures 37 to 40 , after patterning the anode film, the third material layer a3 is etched to eliminate the I-shaped structure of the first wiring layer. The steps include: applying photoresist; exposing the photoresist using a mask and developing the photoresist using a developer; etching the third material layer; and removing the remaining photoresist. This method eliminates the I-shaped structure of the first wiring layer, thereby preventing residual pixel-defining material and cracks in the subsequent encapsulation film, thereby ensuring the yield of pixel units in the display area.

[0251] As another optional implementation, referring to Figures 41 to 44 , after patterning the pixel-defining film, the third material layer a3 is etched to eliminate the I-shaped structure of the first routing layer and remove any remaining pixel-defining material. The steps include: applying photoresist; exposing the photoresist using a mask and developing the photoresist using a developer; etching the third material layer; and removing any remaining photoresist. This method eliminates the I-shaped structure of the first routing layer and removes any remaining pixel-defining material, preventing cracks in the subsequent encapsulation film and ensuring the yield of the pixel units in the display area.

[0252] In a third implementation, FIG45 is a flow chart of another method for manufacturing a display panel provided by an embodiment of the present application. Taking the example of the power supply line 104 including the first layer line and the second layer line, referring to FIG45 , the method includes:

[0253] Step S401: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0254] In the embodiment of the present application, the specific process of step S401 can refer to the relevant description in the above-mentioned step S201, and the embodiment of the present application will not be repeated here.

[0255] Step S402 : forming a first source-drain electrode layer, a first initial planarizing layer, a second source-drain electrode layer, and a second initial planarizing layer on a side of the interlayer dielectric layer away from the substrate.

[0256] In the embodiment of the present application, the first source and drain layer includes at least the second routing layer of the power supply line 104. The second source and drain layer includes at least the first routing layer of the power supply line 104. The orthographic projection of the first routing layer on the base substrate 101 overlaps the orthographic projection of the second routing layer on the base substrate 101. The first and second routing layers each include a first material layer a1, a second material layer a2, and a third material layer a3, which are stacked sequentially in a direction away from the base substrate 101.

[0257] Optionally, the first material layer a1 and the third material layer a3 may both be made of titanium (Ti), and the second material layer a2 may be made of aluminum (Al). That is, the first wiring layer and the second wiring layer may both be a triple-layer structure of Ti / Al / Ti.

[0258] In the embodiment of the present application, the first and second initial flat layers have at least one through-groove region 105a. Furthermore, because the orthographic projection of the first routing layer on the base substrate 101 overlaps the orthographic projection of the second routing layer on the base substrate 101, the through-groove region 105a can only expose the first target region m of the first routing layer and does not expose the second routing layer. Furthermore, the first and second initial flat layers also include patterns for forming the blocking structure 103 in the display panel 10. For example, the first and second initial flat layers each include at least one annular pattern surrounding the display area 101a, which is used to form a blocking dam in the blocking structure 103.

[0259] The through-groove region 105 a and the annular pattern used to form a barrier dam in the barrier structure 103 are adjacently arranged, that is, the through-groove region 105 a and the barrier structure 103 are adjacently arranged.

[0260] Step S403 : forming an anode layer of a plurality of pixel units on a side of the second initial planar layer away from the base substrate.

[0261] In the embodiment of the present application, the process of forming the anode layer includes forming an anode film on a side of the second initial flat layer away from the base substrate 101, and processing the anode film using a patterning process to form the anode layer of the plurality of pixel units 102. The patterning process includes photoresist coating, exposure, development, etching, and photoresist removal.

[0262] The developer used in the development process of preparing the anode layer will affect the first target area m of the first wiring layer, and will have a greater impact on the second material layer a2 of the first wiring layer.

[0263] For example, before forming the anode layer, the first boundary a11 of the first material layer a1 of the first target area m, the second boundary a21 of the second material layer a2, and the third boundary a31 of the third material layer a3 of the first routing layer are collinear. After forming the anode layer, the developer used to prepare the anode layer will side-etch the second material layer a2. The orthographic projection of the second material layer a2 of the first routing layer located in the first target area m on the base substrate 101 is located within the orthographic projection of the third material layer a3 on the base substrate 101, and the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m and the third boundary a31 of the third material layer a3 are collinear. That is, after forming the anode layer, the first routing layer has an I-shaped structure. Among them, the first boundary a11, the second boundary a21, and the third boundary a31 all extend along the first direction X.

[0264] Since the first routing layer will need to be etched later, to distinguish the first routing layer before and after etching, the layer before etching will be referred to as the first initial routing layer, and the layer after etching will be referred to as the first routing layer. Furthermore, the first flat layer and the second flat layer may also be etched to a certain thickness. For ease of description, the first flat layer and the second flat layer before etching will be collectively referred to as the initial flat layer, and the first flat layer and the second flat layer after etching will be collectively referred to as the flat layer.

[0265] Step S404 : etching the third material layer of the first initial routing layer located in the first target area and etching the initial planar layer using an etching process to obtain a first routing layer and a planar layer.

[0266] In the embodiment of the present application, since the portion of the first initial routing layer located in the first target region m is exposed and has an I-shaped structure due to the influence of the developer of the anode layer in step S403, an etching process can be used to etch the third material layer a3 of the first initial routing layer located in the first target region m, thereby obtaining the first routing layer. This process can be referred to as a TTE process.

[0267] Referring to Figure 11 , in the first routing layer obtained through this etching process, the orthographic projection of the third material layer a3 in the first target region m on the base substrate 101 is located within the orthographic projection of the second material layer a2 in the first target region m on the base substrate 101. In other words, the I-shaped structure of the first initial routing layer can be eliminated, resulting in a stepped structure for the final first-layer routing.

[0268] It should be noted that during the etching of the third material layer a3 in the first target region m, in order to ensure sufficient etching of the third material layer a3, a portion of the initial flat layer may also be etched to obtain the final flat layer. Furthermore, the resulting flat layer includes a recessed region 105b, and the thickness of the portion of the flat layer located in the recessed region 105b is thinner than that of the portion located in other regions.

[0269] Step S405 : forming a pixel defining layer, a light emitting layer, and a cathode layer in sequence on a side of the anode layer away from the base substrate.

[0270] In the embodiment of the present application, the specific process of step S405 can refer to the relevant description in the above-mentioned step S205, and the embodiment of the present application will not be repeated here.

[0271] Step S406: forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0272] In the embodiment of the present application, the specific process of step S406 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0273] FIG46 is a flowchart of another method for manufacturing a display panel provided by an embodiment of the present application. Taking the example of the power supply line 104 including the first layer line and the second layer line, referring to FIG46 , the method includes:

[0274] Step S501: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0275] In the embodiment of the present application, the specific process of step S501 can refer to the relevant description in the above-mentioned step S201, and the embodiment of the present application will not be repeated here.

[0276] Step S502 : forming a first source-drain electrode layer, a first initial planarizing layer, a second source-drain electrode layer, and a second initial planarizing layer on a side of the interlayer dielectric layer away from the substrate.

[0277] In the embodiment of the present application, the specific process of step S502 can refer to the relevant description in the above-mentioned step S402, and the embodiment of the present application will not be repeated here.

[0278] Step S503 : forming an anode layer of a plurality of pixel units on a side of the second initial planar layer away from the base substrate.

[0279] In the embodiment of the present application, the specific process of step S503 can refer to the relevant description in the above-mentioned step S403, and the embodiment of the present application will not be repeated here.

[0280] Step S504 : forming a pixel defining layer on a side of the anode layer away from the base substrate.

[0281] In the embodiment of the present application, the specific process of step S504 can refer to the relevant description in the above-mentioned step S304, and the embodiment of the present application will not be repeated here.

[0282] Step S505 : Etching the third material layer of the first initial routing layer located in the first target area and etching the initial planar layer using an etching process to obtain a first routing layer and a planar layer.

[0283] In the embodiment of the present application, the portion of the first initial routing layer located in the first target region m is exposed and, in step S503, is affected by the developer of the anode layer to form an I-shaped structure. Furthermore, in step S504, pixel defining material remains within the I-shaped structure. Therefore, in order to eliminate the I-shaped structure and remove the remaining pixel defining material, an etching process can be used to etch the third material layer a3 of the first initial routing layer located in the first target region m, thereby obtaining the first routing layer. This process can be referred to as a TTE process.

[0284] Referring to Figure 11 , in the first routing layer obtained through this etching process, the orthographic projection of the third material layer a3 in the first target region m on the base substrate 101 lies within the orthographic projection of the second material layer a2 in the first target region m on the base substrate 101. This eliminates the I-shaped structure of the first initial routing layer, resulting in a stepped structure for the final first-layer routing. Furthermore, any remaining pixel-defining material in the I-shaped structure can be removed.

[0285] It should be noted that during the etching of the third material layer a3 in the first target region m, in order to ensure sufficient etching of the third material layer a3, a portion of the initial flat layer may also be etched to obtain the final flat layer. Furthermore, the resulting flat layer includes a recessed region 105b, and the thickness of the portion of the flat layer located in the recessed region 105b is thinner than that of the portion located in other regions.

[0286] Step S506 : forming a light-emitting layer and a cathode layer in sequence on a side of the pixel defining layer away from the base substrate.

[0287] In the embodiment of the present application, the specific process of step S506 can refer to the relevant description in the above-mentioned step S306, and the embodiment of the present application will not be repeated here.

[0288] Step S507 : forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0289] In the embodiment of the present application, the specific process of step S507 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0290] In a fifth implementation, FIG47 is a flow chart of another method for manufacturing a display panel 10 provided in an embodiment of the present application. Taking the example of the power supply trace 104 including a first trace layer, a second trace layer, and a third trace layer, referring to FIG47 , the method includes:

[0291] Step S601: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third insulating layer, an oxide layer, a fourth insulating layer, a third gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0292] In an embodiment of the present application, the active layer includes multiple active patterns, each of which can be used to form a thin film transistor in the pixel circuit included in the pixel unit 102. The first insulating layer is used to insulate the active layer from the first gate layer. The first gate layer includes multiple first gate patterns, and the orthographic projection of each first gate pattern on the base substrate 101 partially overlaps with the orthographic projection of an active pattern on the base substrate 101, and the overlapping area can be the channel of the thin film transistor. The second insulating layer is used to insulate the first gate layer from the second gate layer. The second gate layer includes multiple second gate patterns and multiple third gate patterns. Each second gate pattern can be used to form a plate of a storage capacitor in the pixel circuit, and each third gate pattern can be used to form the bottom gate of an oxide thin film transistor in the pixel circuit. The third insulating layer is used to insulate the second gate layer from the oxide layer. The oxide layer includes multiple oxide patterns, each of which is used to form an oxide thin film transistor. The fourth insulating layer is used to insulate the oxide layer from the third gate layer. The third gate layer includes at least multiple fourth gate patterns, each of which can be used to form the top gate of the oxide thin film transistor. The interlayer dielectric layer is used to insulate the third gate layer from the first source and drain layer formed subsequently.

[0293] Step S602 : forming a first source-drain electrode layer, a first initial planarization layer, a second source-drain electrode layer, a second initial planarization layer, a third source-drain electrode layer, and a third initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0294] In the embodiment of the present application, the first source and drain layer includes at least the third routing layer of the power trace 104. The second source and drain layer includes at least the second routing layer of the power trace 104. The third source and drain layer includes at least the first routing layer of the power trace 104. The orthographic projection of the first routing layer on the base substrate 101 covers the orthographic projection of the second routing layer on the base substrate 101, and also covers the orthographic projection of the third routing layer on the base substrate 101. The first routing layer, the second routing layer, and the third routing layer each include a first material layer a1, a second material layer a2, and a third material layer a3, stacked sequentially in a direction away from the base substrate 101.

[0295] Optionally, the first material layer a1 and the third material layer a3 may both be made of titanium (Ti), and the second material layer a2 may be made of aluminum (Al). That is, the first wiring layer, the second wiring layer, and the third wiring layer may all be a triple-layer structure of Ti / Al / Ti.

[0296] In the embodiment of the present application, the first initial flat layer, the second initial flat layer, and the third initial flat layer have at least one through-groove area 105a. Furthermore, because the orthographic projection of the first routing layer on the base substrate 101 covers the orthographic projections of the second routing layer and the third routing layer on the base substrate 101, the through-groove area 105a can only expose the first target area m of the first routing layer, and does not expose the second routing layer and the third routing layer. Furthermore, the first initial flat layer, the second initial flat layer, and the third initial flat layer also include a pattern for forming the blocking structure 103 in the display panel 10. For example, the first initial flat layer, the second initial flat layer, and the third initial flat layer each include at least one annular pattern surrounding the display area 101a, which is used to form a blocking dam in the blocking structure 103.

[0297] The through-groove region 105 a and the annular pattern used to form a barrier dam in the barrier structure 103 are adjacently arranged, that is, the through-groove region 105 a and the barrier structure 103 are adjacently arranged.

[0298] Step S603 : forming an anode layer of a plurality of pixel units on a side of the third initial planar layer away from the base substrate.

[0299] In the embodiment of the present application, the process of forming the anode layer includes forming an anode film on a side of the third initial flat layer away from the base substrate 101, and processing the anode film using a patterning process to form the anode layer of the plurality of pixel units 102. The patterning process includes photoresist coating, exposure, development, etching, and photoresist removal.

[0300] The developer used in the development process of preparing the anode layer will affect the first target area m of the first wiring layer, and will have a greater impact on the second material layer a2 of the first wiring layer.

[0301] For example, before forming the anode layer, the first boundary a11 of the first material layer a1 of the first target area m, the second boundary a21 of the second material layer a2, and the third boundary a31 of the third material layer a3 of the first routing layer are collinear. After forming the anode layer, the developer used to prepare the anode layer will side-etch the second material layer a2. The orthographic projection of the second material layer a2 of the first routing layer located in the first target area m on the base substrate 101 is located within the orthographic projection of the third material layer a3 on the base substrate 101, and the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m and the third boundary a31 of the third material layer a3 are collinear. That is, after forming the anode layer, the first routing layer has an I-shaped structure. Among them, the first boundary a11, the second boundary a21, and the third boundary a31 all extend along the first direction X.

[0302] Since the first routing layer will need to be etched later, to distinguish the first routing layer before and after etching, the layer before etching will be referred to as the first initial routing layer, and the layer after etching will be referred to as the first routing layer. Furthermore, the first flat layer, second flat layer, and third flat layer may also be etched. For ease of description, the first flat layer, second flat layer, and third flat layer before etching will be collectively referred to as the initial flat layer, and the first flat layer, second flat layer, and third flat layer after etching will be collectively referred to as the flat layer.

[0303] Step S604 : Etching the third material layer of the first initial routing layer located in the first target area and etching the initial planar layer using an etching process to obtain a first routing layer and a planar layer.

[0304] In the embodiment of the present application, the specific process of step S604 can refer to the relevant description in the above-mentioned step S404, and the embodiment of the present application will not be repeated here.

[0305] Step S605 : forming a pixel defining layer, a light emitting layer, and a cathode layer in sequence on a side of the anode layer away from the base substrate.

[0306] In the embodiment of the present application, the specific process of step S605 can refer to the relevant description in the above-mentioned step S205, and the embodiment of the present application will not be repeated here.

[0307] Step S606: forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0308] In the embodiment of the present application, the specific process of step S606 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0309] FIG48 is a flow chart of another method for manufacturing a display panel provided by an embodiment of the present application. Taking the power supply trace 104 as an example, which includes a first layer of traces, a second layer of traces, and a third layer of traces, with reference to FIG48 , the method includes:

[0310] Step S701: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third insulating layer, an oxide layer, a fourth insulating layer, a third gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0311] In the embodiment of the present application, the specific process of step S701 can refer to the relevant description in the above step S601, and the embodiment of the present application will not be repeated here.

[0312] Step S702 : forming a first source-drain layer, a first initial planarization layer, a second source-drain layer, a second initial planarization layer, a third source-drain layer, and a third initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0313] In the embodiment of the present application, the specific process of step S702 can refer to the relevant description in the above step S602, and the embodiment of the present application will not be repeated here.

[0314] Step S703 : forming an anode layer of a plurality of pixel units on a side of the third initial planar layer away from the base substrate.

[0315] In the embodiment of the present application, the specific process of step S703 can refer to the relevant description in the above step S603, and the embodiment of the present application will not be repeated here.

[0316] Step S704 : forming a pixel defining layer on a side of the anode layer away from the base substrate.

[0317] In the embodiment of the present application, the specific process of step S704 can refer to the relevant description in the above-mentioned step S304, and the embodiment of the present application will not be repeated here.

[0318] Step S705 : Etching the third material layer of the first initial routing layer located in the first target area and etching the initial planar layer using an etching process to obtain a first routing layer and a planar layer.

[0319] In the embodiment of the present application, the specific process of step S705 can refer to the relevant description in the above step S505, and the embodiment of the present application will not be repeated here.

[0320] Step S706 : forming a light-emitting layer and a cathode layer in sequence on a side of the pixel defining layer away from the base substrate.

[0321] In the embodiment of the present application, the specific process of step S706 can refer to the relevant description in the above-mentioned step S306, and the embodiment of the present application will not be repeated here.

[0322] Step S507 : forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0323] In the embodiment of the present application, the specific process of step S707 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0324] In the embodiment of the present application, referring to Figures 49 and 50 , it can be seen that the area of ​​the first routing layer not protected by the organic film layer (the first target area) forms an I-shaped structure, while the area protected by the organic film layer does not form an I-shaped structure. Furthermore, referring to Figure 51 , after the pixel definition layer is prepared, residual pixel definition material will remain within the I-shaped structure.

[0325] To prevent the I-shaped structure in the areas of the first routing layer not protected by the organic film layer, an etching process can be used to etch the third material layer a3 of the first routing layer. Referring to Figure 52 , after etching, some indentations of the second material layer a2 may still remain. Therefore, referring to Figures 53 and 54 , to ensure the removal of the I-shaped structure, the distance between the third boundary of the third routing layer a3 and the first boundary of the first routing layer a1 must be greater than 3μm.

[0326] In summary, an embodiment of the present application provides a method for preparing a display panel, wherein the first routing layer of the power routing in the display panel prepared by the method has a first target area exposed by the through-groove area of ​​the first organic film layer, and the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate. The orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate. Thus, it is possible to avoid cracks in the encapsulation film layer subsequently formed on the display panel, thereby preventing water and oxygen from invading the display area along the intrusion channels created by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel units in the display area, avoid the occurrence of black spots in the display area, and have a high yield and a good display effect of the display panel.

[0327] FIG55 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Referring to FIG55 , the display device includes: a power supply component 20 and a display panel 10 provided in the above embodiment. The power supply component 20 is used to supply power to the display panel 10.

[0328] Optionally, the display device may be an LTPO display device, an LTPS display device, or an OLED display device. The display device may be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation devices, and e-books, and any other product or component with a display function.

[0329] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0330] The terms used in the embodiments of this application are only used to explain the embodiments of this application and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the common meaning understood by people with ordinary skills in the field to which this application belongs.

[0331] The terms used in the embodiments of this application are intended solely to illustrate the embodiments of this application and are not intended to limit this application. Unless otherwise defined, technical or scientific terms used in the embodiments of this application should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this application belongs. The terms "first," "second," "third," and similar terms used in this patent specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish between different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather denote the presence of at least one. Terms such as "include" or "comprising" and similar terms mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used solely to indicate relative positions. When the absolute position of the described objects changes, the relative positions may also change accordingly.

[0332] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel (10), characterized in that: The display panel (10) comprises: A base substrate (101), wherein the base substrate (101) has a display area (101a) and a peripheral area (101b) surrounding the display area (101a); A plurality of pixel units (102), wherein the plurality of pixel units (102) are located in the display area (101a); A blocking structure (103), the blocking structure (103) surrounding the display area (101a); At least one power supply line (104) is located on one side of the substrate (101), each of the power supply lines (104) is used to receive a power supply signal and is connected to the plurality of pixel units (102); A first organic film layer (105), the first organic film layer (105) being located on a side of the power supply line (104) away from the base substrate (101), and the first organic film layer (105) having at least one through-groove area (105a), an orthographic projection of the through-groove area (105a) on the base substrate (101) and an orthographic projection of the blocking structure (103) on the base substrate (101) being arranged adjacent to each other, and the through-groove area (105a) being used to expose a first target area (m) of the power supply line (104); The power supply wiring (104) comprises at least a first wiring layer, the first wiring layer comprising a first material layer (a1), a second material layer (a2) and a third material layer (a3) ​​stacked in sequence in a direction away from the base substrate (101), the orthographic projection of the third material layer (a3) ​​of the first wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the second material layer (a2) on the base substrate (101), and the orthographic projection of the second material layer (a2) of the first wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the first material layer (a1) on the base substrate (101).

2. The display panel according to claim 1, characterized in that: The first material layer (a1) of the first routing layer located in the first target area (m) has a first boundary (a11) extending along a first direction (X), the second material layer (a2) of the first routing layer located in the first target area (m) has a second boundary (a21) extending along the first direction (X), and the third material layer (a3) ​​of the first routing layer located in the first target area (m) has a third boundary (a31) extending along the first direction (X); The distance between the first boundary (a11) and the third boundary (a31) in the second direction (Y) is greater than 3 micrometers, the second boundary (a21) is located between the first boundary (a11) and the third boundary (a31), and the second direction (Y) is perpendicular to the first direction (X).

3. The display panel according to claim 1 or 2, characterized in that: The first organic film layer (105) has a groove region (105b), the thickness of the first organic film layer (105) in the groove region (105b) is less than the thickness of other regions except the groove region (105b), and the groove region (105b) is used to cover the second target region (n) of the first wiring layer; The second target area (n) and the first target area (m) are adjacent to each other in the first direction (X).

4. The display panel according to claim 3, characterized in that: The groove area (105b) has a first groove boundary (105b1) close to the first wiring layer and extending along the first direction (X), and the third material layer (a3) ​​of the first wiring layer located in the first target area (m) has a third boundary (a31) extending along the first direction (X); The orthographic projection of the first groove boundary (105b1) on the base substrate (101) is collinear with the orthographic projection of the third boundary (a31) on the base substrate (101).

5. The display panel according to claim 4, characterized in that: The groove region (105b) further comprises a second groove boundary (105b2) which is away from the through groove region (105a) and extends along a second direction (Y), and a third groove boundary (105b3) which is adjacent to the through groove region (105a) and extends along the second direction (Y); wherein the second direction (Y) is perpendicular to the first direction (X); The distance between the second groove boundary (105b2) and the third groove boundary (105b3) in the first direction (X) is greater than 3 micrometers.

6. The display panel according to any one of claims 1 to 5, characterized in that: The power wiring (104) comprises a third wiring layer, a second wiring layer and the first wiring layer which are sequentially stacked in a direction away from the base substrate (101); the display panel (10) comprises: a third organic film layer located between the third wiring layer and the second wiring layer, and a second organic film layer located between the second wiring layer and the first wiring layer, and the first organic film layer (105) is located on a side of the first wiring layer away from the base substrate (101); Wherein, the third wiring layer and the second wiring layer are connected through the openings in the third organic film layer, and the second wiring layer and the first wiring layer are connected through the openings in the second organic film layer; The through-groove area (105a) is used to expose the first target area (m) of the first wiring layer.

7. The display panel according to any one of claims 1 to 5, characterized in that: The power wiring (104) comprises a second wiring layer and the first wiring layer which are sequentially stacked in a direction away from the base substrate (101); the display panel (10) comprises: a second organic film layer located between the second wiring layer and the first wiring layer, and the first organic film layer (105) is located on a side of the first wiring layer away from the base substrate (101); The second wiring layer and the first wiring layer are connected via an opening in the second organic film layer; and the through groove area (105a) is used to expose the first target area (m) of the first wiring layer.

8. The display panel according to any one of claims 1 to 7, characterized in that: The at least one power supply line (104) comprises a first signal power supply line (104a) and a second signal power supply line (104b) spaced apart above the second direction (Y), and the through-slot area (105a) comprises a first sub-through-slot area (105a1) for exposing the first signal power supply line (104a) and a second sub-through-slot area (105a2) for exposing the second signal power supply line (104b); Wherein, the length of the first sub-through groove area (105a1) along the first direction (X) is less than or equal to the length of the second sub-through groove area (105a2) along the first direction (X).

9. The display panel according to any one of claims 1 to 8, characterized in that: The thickness of the second material layer (a2) located in the first target area (m) is less than or equal to the thickness of the second material layer (a2) located in the other areas.

10. The display panel according to claim 9, characterized in that: When the thickness of the second material layer (a2) located in the first target area (m) is less than the thickness of the second material layer (a2) located in the other areas, the surface of the second material layer (a2) located in the first target area (m) is uneven away from the base substrate (101).

11. The display panel according to any one of claims 1 to 10, characterized in that: The blocking structure (103) comprises: a first blocking dam (1031), a second blocking dam (1032) and a third blocking dam (1033) which are sequentially arranged away from the display area (101a); The first organic film layer (105) has two through-groove regions (105a), one of which is located on a side of the third blocking dam (1033) away from the display region (101a), and the other through-groove region (105a) is located between the second blocking dam (1032) and the third blocking dam (1033).

12. The display panel according to claim 11, characterized in that: Each barrier dam in the barrier structure (103) comprises at least one layer of the organic film layers in the display panel (10), and the organic film layers in the display panel (10) comprise: a third organic film layer, a second organic film layer and the first organic film layer; Among them, one of the first organic film layer, the second organic film layer and the third organic film layer is located in an area adjacent to any blocking dam in the blocking structure (103) and where the through groove area (105a) is not provided.

13. The display panel according to any one of claims 1 to 12, characterized in that: In the area of ​​the power supply wiring (104) covered by the organic film layer in the display panel (10), the side edges of the third material layer (a3), the second material layer (a2) and the first material layer (a1) are flat side edges, and the flat side edges are inclined relative to the supporting surface of the base substrate (101); The orthographic projection of the third material layer (a3) ​​on the base substrate (101) is located within the orthographic projection of the second material layer (a2) on the base substrate (101), and the orthographic projection of the second material layer (a2) on the base substrate (101) is located within the orthographic projection of the first material layer (a1) on the base substrate (101).

14. A method for preparing a display panel, characterized in that: The method comprises: Providing a base substrate (101), wherein the base substrate (101) has a display area (101a) and a peripheral area (101b) surrounding the display area (101a); A plurality of pixel units (102), a blocking structure (103) and at least one initial power supply wiring are formed on one side of the base substrate (101); the plurality of pixel units (102) are located in the display area (101a); the blocking structure (103) surrounds the display area (101a); each of the initial power supply wiring is used to receive a power supply signal and is connected to the plurality of pixel units (102); the initial power supply wiring comprises at least a first initial wiring layer, the first initial wiring layer comprising a wiring layer extending away from the base substrate A first material layer (a1), a second material layer (a2) and a third material layer (a3) ​​are sequentially stacked in the direction of (101); An initial organic film layer is formed on a side of the initial power supply line away from the base substrate (101), the initial organic film layer having at least one through-groove area (105a), an orthographic projection of the through-groove area (105a) on the base substrate (101) and an orthographic projection of the blocking structure (103) on the base substrate (101) being arranged adjacent to each other, and the through-groove area (105a) is used to expose a first target area (m) of the initial power supply line; The first initial routing layer of the at least one initial power routing line, the third material layer (a3) ​​located in the first target area (m), and the initial organic film layer are etched by an etching process to obtain a first routing layer and a first organic film layer (105) of the at least one power routing line (104), wherein the orthographic projection of the third material layer (a3) ​​of the first routing layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the second material layer (a2) on the base substrate (101), and the orthographic projection of the second material layer (a2) of the first routing layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the first material layer (a1) on the base substrate (101).

15. The method according to claim 14, characterized in that Forming a plurality of pixel units (102) comprises: sequentially forming an anode layer, a pixel defining layer, a light emitting layer and a cathode layer on a side of the initial organic film layer away from the base substrate (101); The method of etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer by using an etching process comprises: After forming the anode layer and before forming the pixel defining layer, the etching process is used to etch the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and to etch the initial organic film layer.

16. The method according to claim 15, characterized in that Before forming the anode layer, the first initial wiring layer is located in the first target area (m) at a first boundary (a11) of the first material layer (a1), a second boundary (a21) of the second material layer (a2), and a third boundary (a31) of the third material layer (a3) ​​on a collinear basis; After the anode layer is formed, the orthographic projection of the second material layer (a2) of the first initial wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the third material layer (a3) ​​on the base substrate (101), and the first boundary (a11) of the first material layer (a1) of the first initial wiring layer located in the first target area (m) and the third boundary (a31) of the third material layer (a3) ​​are collinear; The first boundary (a11), the second boundary (a21) and the third boundary (a31) all extend along the first direction (X).

17. The method according to claim 16, characterized in that Forming a plurality of pixel units (102) comprises: sequentially forming an anode layer, a pixel defining layer, a light emitting layer and a cathode layer on a side of the first organic film layer (105) away from the base substrate (101); The method of etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer by using an etching process comprises: After forming the pixel defining layer and before forming the light emitting layer, the etching process is used to etch the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and to etch the initial organic film layer.

18. The method according to claim 17, characterized in that Before forming the pixel definition layer, the orthographic projection of the second material layer (a2) of the first initial wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the third material layer (a3) ​​on the base substrate (101), and the first boundary (a11) of the first material layer (a1) of the first initial wiring layer located in the first target area (m) and the third boundary (a31) of the third material layer (a3) ​​are collinear; After forming the pixel definition layer, part of the material of the pixel definition layer is located in a retracted area, and the retracted area is an area where the first initial wiring layer has the first material layer (a1) and the third material layer (a3) ​​but does not have the second material layer (a2); After etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer using the etching process, part of the material of the pixel defining layer located in the retracted area is removed.

19. The method according to any one of claims 14 to 18, characterized in that: The method of etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer by using an etching process comprises: Coating photoresist on a side of the first initial wiring layer away from the substrate (101); Exposing the photoresist using a mask; Developing the photoresist with a developer to remove the exposed portion of the photoresist; Using an etching process to remove the third material layer (a3) ​​of the first initial wiring layer located in the first target area (m) and the portion of the initial organic film layer not protected by the photoresist; Remove the remaining photoresist.

20. The method according to claim 19, characterized in that The mask plate has a plurality of mask openings, and the orthographic projection of each mask opening on the base substrate (101) partially overlaps with the through-slot area (105a) and partially overlaps with the first target area (m) of the initial power supply wiring; The mask opening has a first mask boundary extending along a first direction (X), the first mask boundary is used to form a third boundary (a31) of the third material layer (a3) ​​after etching, and the orthographic projection of the first mask boundary on the substrate (101) is located within the orthographic projection of the first material layer (a1) on the substrate (101), the distance between the first mask boundary and the first boundary (a11) in the second direction (Y) is greater than 3 microns, and the second direction (Y) is perpendicular to the first direction (X).

21. The method according to claim 20, characterized in that The first mask boundary is also used to form a first groove boundary (105b1) of the groove region (105b) of the first organic film layer (105) after etching, and the first groove boundary (105b1) is close to the first wiring layer and extends along the first direction (X); The thickness of the first organic film layer (105) in the groove area (105b) is less than the thickness of other areas except the groove area (105b), and the groove area (105b) is used to cover the second target area (n) of the power line (104), and the second target area (n) and the first target area (m) are adjacent in the first direction (X).

22. The method according to claim 20 or 21, characterized in that The mask opening also has a second mask boundary extending along a second direction (Y); the through-groove region (105a) is located on one side of the second mask boundary; the second mask boundary is used to form a groove region (105b) of the first organic film layer (105); the groove region (105b) is away from the through-groove region (105a) and extends along the second direction (Y); the groove region (105b) also has a third groove boundary (105b3) adjacent to the through-groove region (105a) and extending along the second direction (Y); Wherein, the distance between the second groove boundary (105b2) and the third groove boundary (105b3) in the first direction (X) is greater than 3 micrometers.

23. The method according to any one of claims 14 to 22, characterized in that: Forming the power supply wiring (104) comprises: forming a first wiring layer on one side of the base substrate (101); Alternatively, forming the power wiring (104) comprises: sequentially forming a second wiring layer, a second organic film layer and the first wiring layer on one side of the base substrate (101), wherein the first wiring layer and the second wiring layer are connected via an opening in the second organic film layer; Alternatively, forming the power wiring (104) comprises: sequentially forming a third wiring layer, a third organic film layer, a second wiring layer, a second organic film layer and the first wiring layer on one side of the base substrate (101), the first wiring layer and the second wiring layer being connected via an opening in the second organic film layer, and the second wiring layer and the third wiring layer being connected via an opening in the third organic film layer; Wherein, the through-groove area (105a) is used to expose the first target area (m) of the first wiring layer.

24. A display device, characterized in that: The display device comprises a power supply component and a display panel (10) according to any one of claims 1 to 13; Wherein, the power supply component is used to supply power to the display panel (10).

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