Pixel driving circuit, display apparatus and driving method

Abstract

A pixel driving circuit, a display apparatus and a driving method. The pixel driving circuit comprises: a driving transistor (DT), wherein a gate of the driving transistor (DT) is coupled to a first node (N1), a first electrode of the driving transistor (DT) is coupled to a second node (N2), a second electrode of the driving transistor (DT) is coupled to a third node (N3), and the driving transistor (DT) is configured to generate a driving current on the basis of a data voltage; a first reset control sub-circuit (10), coupled to the second node (N2) and a fourth node (N4) and configured to reset the potentials of the second node (N2) and the fourth node (N4); a data writing sub-circuit (20), coupled to the second node (N2) and configured to input a data voltage of a data signal end (Data) into the first node (N1) in response to a signal of a first scanning signal end (Gate_P(n)); and a light-emitting control sub-circuit (30), coupled to a light-emitting device (OLED) by means of the driving transistor (DT), wherein the light-emitting control sub-circuit (30) is configured to provide the driving current generated by the driving transistor (DT) to the light-emitting device (OLED). The reset of the second node (N2) can be implemented without adding an additional reset port, simplifying the reset process of the driving transistor (DT).

Description

Pixel driving circuit, display device and driving method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on June 29, 2023, with application number 202310789132.6 and application name “A pixel driving circuit, display device and driving method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology and provides a pixel driving circuit, a display device, and a driving method. Background Art

[0004] For a display device to display images properly, each pixel unit must be equipped with a corresponding pixel driver circuit. Specifically, a driver transistor drives the light-emitting device to emit light. To ensure better display quality between image frames, the terminals of the driver transistor must be reset after each frame is displayed, ensuring that the display of the next frame is not affected by the previous frame.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a pixel driving circuit, a display device, and a driving method to simplify the resetting process of the driving transistor and improve the display effect of the picture.

[0007] The specific technical solutions provided by this disclosure are as follows:

[0008] In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit, comprising: a driving transistor, a light-emitting device, a first reset control subcircuit, a data writing subcircuit, and a light-emitting control subcircuit;

[0009] The gate of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node, and is configured to generate a driving current according to the data voltage;

[0010] The first reset control subcircuit is coupled to the second node and the fourth node and is configured to reset the potentials of the second node and the fourth node;

[0011] The data writing sub-circuit is coupled to the second node and is configured to input the data voltage of the data signal terminal into the first node in response to the signal of the first scanning signal terminal;

[0012] The light emitting control subcircuit is coupled to the light emitting device through the driving transistor, and the light emitting control subcircuit is configured to provide the driving current generated by the driving transistor to the light emitting device.

[0013] Optionally, the first reset control subcircuit includes: a first switch transistor and a second switch transistor, wherein the first switch transistor and the second switch transistor have different polarities;

[0014] The control terminal of the first switch transistor is coupled to the second scan signal terminal, the first terminal of the first switch transistor is coupled to the fourth node, and the second terminal of the first switch transistor is coupled to the second node;

[0015] The control terminal of the second switch transistor is coupled to the enable signal terminal, the first terminal of the second switch transistor is coupled to the second initialization signal terminal, and the second terminal of the second switch transistor is coupled to the fourth node.

[0016] Optionally, the first reset control subcircuit includes: a first switch transistor and a second switch transistor, wherein the first switch transistor and the second switch transistor have the same polarity;

[0017] The control terminal of the first switch transistor is coupled to the fourth scan signal terminal, the first terminal of the first switch transistor is coupled to the fourth node, and the second terminal of the first switch transistor is coupled to the second node;

[0018] The control terminal of the second switch transistor is coupled to the third scan signal terminal, the first terminal of the second switch transistor is coupled to the second initialization signal terminal, and the second terminal of the second switch transistor is coupled to the fourth node.

[0019] Optionally, the first reset control subcircuit includes: a first switch transistor, a second switch transistor, and a third switch transistor, wherein the first switch transistor and the second switch transistor have different polarities, and the third switch transistor and the second switch transistor have the same polarity;

[0020] The control terminal of the first switch transistor is coupled to the second scan signal terminal, the first terminal of the first switch transistor is coupled to the third switch transistor, and the second terminal of the first switch transistor is coupled to the second node;

[0021] A control terminal of the second switch transistor is coupled to the enable signal terminal, a first terminal of the second switch transistor is coupled to the second initialization signal terminal, and a second terminal of the second switch transistor is coupled to the fourth node;

[0022] The control terminal of the third switch transistor is coupled to the fourth scan signal terminal, the first terminal of the third switch transistor is coupled to the first terminal of the first switch transistor, and the second terminal of the third switch transistor is coupled to the fourth node.

[0023] Optionally, it further includes: a second reset control subcircuit;

[0024] The second reset control subcircuit is coupled to the first node and the third node, and is configured to reset the first node and the third node.

[0025] Optionally, the second reset control subcircuit includes: a fourth switch transistor and a fifth switch transistor, wherein the fourth switch transistor and the fifth switch transistor have different polarities;

[0026] The control terminal of the fourth switch transistor is coupled to the second scan signal terminal, the first terminal of the fourth switch transistor is coupled to the first initialization signal terminal, and the second terminal of the fourth switch transistor is coupled to the first terminal of the fifth switch transistor;

[0027] The control terminal of the fifth switch transistor is coupled to the third scan signal terminal, and the second terminal of the fifth switch transistor is coupled to the first node.

[0028] Optionally, the second reset control subcircuit includes: a fifth switch transistor;

[0029] The control terminal of the fifth switch transistor is coupled to the third scan signal terminal, the first terminal of the fifth switch transistor is coupled to the third node, and the second terminal of the fifth switch transistor is coupled to the first node.

[0030] Optionally, the data writing sub-circuit includes: a sixth switching transistor;

[0031] The control terminal of the sixth switch transistor is coupled to the first scan signal terminal, the first terminal of the sixth switch transistor is coupled to the data signal terminal, and the second terminal of the sixth switch transistor is coupled to the second node.

[0032] Optionally, the light emitting control subcircuit includes: a seventh switching transistor;

[0033] The control terminal of the seventh switch transistor is coupled to the enable signal terminal, the first terminal of the seventh switch transistor is coupled to the fourth node, and the second terminal of the seventh switch transistor is coupled to the third node.

[0034] Optionally, it further includes: an eighth switching transistor;

[0035] The control terminal of the eighth switch transistor is coupled to the enable signal terminal, the first terminal of the eighth switch transistor is coupled to the second node, and the second terminal of the eighth switch transistor is coupled to the first power supply terminal.

[0036] Optionally, it further includes: a first capacitor;

[0037] A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to the first power supply terminal.

[0038] Optionally, the light emitting control subcircuit includes: a seventh switching transistor;

[0039] The seventh switch transistor is a dual-gate transistor. A first gate of the seventh switch transistor is coupled to the second scan signal terminal. A second gate of the seventh switch transistor is coupled to the enable signal terminal.

[0040] In a second aspect, an embodiment of the present disclosure further provides a display device comprising any one of the above-mentioned pixel driving circuits.

[0041] In a third aspect, an embodiment of the present disclosure further provides a shift register driving method, comprising:

[0042] The first reset control subcircuit resets the potential of the second node coupled to the driving transistor;

[0043] The data writing sub-circuit inputs the data voltage of the data signal terminal into the first node coupled to the driving transistor in response to the signal of the first scanning signal terminal;

[0044] The driving transistor generates a driving current according to the data voltage;

[0045] The light emitting control subcircuit provides the driving current generated by the driving transistor to the light emitting device.

[0046] The beneficial effects of the present disclosure are as follows:

[0047] In summary, the embodiments of the present disclosure provide a pixel driving circuit, a display device, and a driving method. The pixel driving circuit includes: a driving transistor, a light-emitting device, a first reset control subcircuit, a data writing subcircuit, and a light-emitting control subcircuit. The gate of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node. The driving circuit is configured to generate a driving current according to a data voltage. The first reset control subcircuit is coupled to the second node and the fourth node, and is configured to reset the potentials of the second node and the fourth node. The data writing subcircuit is coupled to the second node, and is configured to input the data voltage of the data signal end into the first node in response to the signal of the first scanning signal end. The light-emitting control subcircuit is coupled to the light-emitting device through the driving transistor, and the light-emitting control subcircuit is configured to provide the driving current generated by the driving transistor to the light-emitting device. In the above scheme, the second node can be reset without additionally setting a reset port, thereby simplifying the reset process of the driving transistor.

[0048] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0050] FIG1 is a schematic diagram of a pixel driving circuit in the related art;

[0051] FIG2 is a schematic diagram of another pixel driving circuit in the related art;

[0052] FIG3 is a connection diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0053] FIG4 is a circuit diagram of a first pixel driving circuit according to an embodiment of the present disclosure;

[0054] FIG5 is a circuit diagram of a second pixel driving circuit in an embodiment of the present disclosure;

[0055] FIG6 is a circuit diagram of a third pixel driving circuit in an embodiment of the present disclosure;

[0056] FIG7 is a circuit diagram of a fourth pixel driving circuit in an embodiment of the present disclosure;

[0057] FIG8 is a first operation schematic diagram of the first pixel driving circuit according to an embodiment of the present disclosure;

[0058] FIG9 is a first timing diagram of a first pixel driving circuit according to an embodiment of the present disclosure;

[0059] FIG10 is a second operating schematic diagram of the first pixel driving circuit according to an embodiment of the present disclosure;

[0060] FIG11 is a second timing diagram of the first pixel driving circuit according to an embodiment of the present disclosure;

[0061] FIG12 is a third working schematic diagram of the first pixel driving circuit according to an embodiment of the present disclosure;

[0062] FIG13 is a third timing diagram of the first pixel driving circuit according to an embodiment of the present disclosure;

[0063] FIG14 is a timing diagram of a second pixel driving circuit according to an embodiment of the present disclosure;

[0064] FIG15 is a timing diagram of a third pixel driving circuit according to an embodiment of the present disclosure;

[0065] FIG16 is a timing diagram of a fourth pixel driving circuit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the technical solutions of the present disclosure, but not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments described in this disclosure without making any creative efforts shall fall within the scope of protection of the technical solutions of the present disclosure.

[0067] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0068] In related art, resetting the N2 node of the driver transistor in a pixel circuit is often achieved by connecting a new external reset port. Referring to FIG1 , resetting the N2 node of the driver transistor requires adding an M8 transistor, which is connected to a new external reset port, Vinit3. Alternatively, referring to FIG2 , resetting the N2 node of the driver transistor requires adding an M9 transistor, which is connected to a new external reset port, Vref. In summary, the current reset routing and external interface for the N2 node of the driver transistor are relatively complex.

[0069] The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0070] 3 , a pixel driving circuit proposed in an embodiment of the present application includes: a driving transistor DT, a light-emitting device OLED, a first reset control subcircuit 10 , a data writing subcircuit 20 , and a light-emitting control subcircuit 30 .

[0071] It should be noted that the pixel driving circuit proposed in the embodiments of the present application generally drives an organic light emitting diode (OLED), that is, the light emitting device is usually an OLED. In some application scenarios, the light emitting device may also be a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), or other light emitting devices with advantages such as self-luminescence and low energy consumption.

[0072] 4 , the gate of the driving transistor DT is coupled to the first node N1 , the first electrode of the driving transistor DT is coupled to the second node N2 , and the second electrode of the driving transistor DT is coupled to the third node N3 , and is configured to generate a driving current according to the data voltage.

[0073] The first reset control sub-circuit is coupled to the second node N2 and the fourth node N4 and is configured to reset the potentials of the second node N2 and the fourth node N4.

[0074] The data writing sub-circuit is coupled to the second node N2 and is configured to input the data voltage of the data signal terminal into the first node N1 in response to the signal of the first scan signal terminal Gate_P(n).

[0075] The light emitting control sub-circuit is coupled to the light emitting device OLED via the driving transistor DT. The light emitting control sub-circuit is configured to provide the driving current generated by the driving transistor DT to the light emitting device OLED.

[0076] During the implementation process, before the driving transistor DT displays the current frame, that is, before the driving transistor DT generates a driving current to make the light-emitting device OLED emit light, it is necessary to first reset the relevant nodes of the driving transistor DT (especially the above-mentioned second node N2). In the embodiment of the present application, the potentials of the second node N2 and the fourth node N4 are reset at the same time through the first reset control sub-circuit. Thereafter, after the data writing sub-circuit responds to the signal of the first scanning signal terminal Gate_P(n), the data voltage of the data signal terminal is input to the first node N1. In this way, the driving transistor DT can generate a driving current according to the data voltage, and then provide the above-mentioned driving current to the light-emitting device OLED under the control of the light-emitting control sub-circuit, thereby realizing the light-emitting device OLED.

[0077] Referring to FIG. 4 , in one embodiment, the first reset control subcircuit includes a first switch transistor T1 and a second switch transistor T2 , wherein the first switch transistor T1 and the second switch transistor T2 have different polarities.

[0078] It should be noted that, in the embodiment of the present application, the first switch transistor T1 and the second switch transistor T2 have different polarities. Referring to FIG. 4 , the first switch transistor T1 is a P-type transistor, and the second switch transistor T2 is an N-type transistor.

[0079] The connection relationship between the first switch transistor T1 and other devices in Figure 4 is: the control end of the first switch transistor T1 is coupled to the second scan signal end Gate_P(n-1), the first end of the first switch transistor T1 is coupled to the fourth node N4, and the second end of the first switch transistor T1 is coupled to the second node N2.

[0080] During implementation, when the signal of the second scanning signal terminal Gate_P(n-1) is at a low level, the first switch transistor T1 is turned on, and the fourth node N4 connected to the first switch transistor T1 and the second node N2 have the same potential.

[0081] The connection relationship between the second switch transistor T2 and other devices in Figure 4 is: the control end of the second switch transistor T2 is coupled to the enable signal end EM(n), the first end of the second switch transistor T2 is coupled to the second initialization signal end Vinit2, and the second end of the second switch transistor T2 is coupled to the fourth node N4.

[0082] During implementation, when the signal at the enable signal terminal EM(n) is at a high level, the second switch transistor T2 is turned on, and the signal at the second initialization signal terminal Vinit2 is provided to the fourth node N4. Simultaneously, the signal at the second initialization signal terminal Vinit2 is provided to the second node N2 via the fourth node N4 and the turned-on first switch transistor T1.

[0083] Referring to FIG. 5 , in another embodiment, the first reset control sub-circuit includes: a first switch transistor T1 and a second switch transistor T2 , wherein the first switch transistor T1 and the second switch transistor T2 have the same polarity.

[0084] It should be noted that, in the embodiment of the present application, the first switch transistor T1 and the second switch transistor T2 have the same polarity. Referring to FIG. 5 , the first switch transistor T1 is an N-type transistor, and the second switch transistor T2 is also an N-type transistor.

[0085] The connection relationship between the first switch transistor T1 and other devices in Figure 5 is: the control end of the first switch transistor T1 is coupled to the fourth scan signal end Gate (n2), the first end of the first switch transistor T1 is coupled to the fourth node N4, and the second end of the first switch transistor T1 is coupled to the second node N2.

[0086] During implementation, when the signal of the fourth scan signal terminal Gate(n2) is at a high level, the first switch transistor T1 is turned on, and the fourth node N4 is at the same level as the second node N2.

[0087] The connection relationship between the second switch transistor T2 and other devices in Figure 5 is: the control end of the second switch transistor T2 is coupled to the third scan signal end Gate(n), the first end of the second switch transistor T2 is coupled to the second initialization signal end Vinit2, and the second end of the second switch transistor T2 is coupled to the fourth node N4.

[0088] During the implementation process, when the signal of the third scan signal terminal Gate(n) is at a high level, the second switch transistor T2 is turned on, and the signal of the second initialization signal terminal Vinit2 passes through the turned-on second switch transistor T2 and the first switch transistor T1, so that the fourth node N4 and the second node N2 are reset at the same time.

[0089] Referring to FIG. 6 , in another embodiment, the first reset control subcircuit includes: a first switch transistor T1, a second switch transistor T2, and a third switch transistor T3, wherein the first switch transistor T1 and the second switch transistor T2 have different polarities, and the third switch transistor T3 and the second switch transistor T2 have the same polarity.

[0090] It should be noted that, referring to Figure 6, in the embodiment of the present application, the polarities of the first switch transistor T1 and the second switch transistor T2 are different, and the polarities of the third switch transistor T3 and the second switch transistor T2 are the same, that is, the first switch transistor T1 is P-type, and the polarities of the third switch transistor T3 and the second switch transistor T2 are both N-type.

[0091] The connection relationship between the second switch transistor T2 and other devices in Figure 6 is: the control end of the first switch transistor T1 is coupled to the second scan signal end Gate_P(n-1), the first end of the first switch transistor T1 is coupled to the third switch transistor T3, and the second end of the first switch transistor T1 is coupled to the second node N2.

[0092] During implementation, when the signal of the second scanning signal terminal Gate_P(n-1) is at a low level, the first switch transistor T1 is turned on, and the second node N2 is connected to the third switch transistor T3.

[0093] The connection relationship between the second switch transistor T2 and other devices in Figure 6 is: the control end of the second switch transistor T2 is coupled to the enable signal end EM(n), the first end of the second switch transistor T2 is coupled to the second initialization signal end Vinit, and the second end of the second switch transistor T2 is coupled to the fourth node N4.

[0094] During implementation, when the signal at the enable signal terminal EM(n) is at a high level, the second switch transistor T2 is turned on, and the signal at the second initialization signal terminal Vinit is provided to the fourth node N4.

[0095] The connection relationship between the second switch transistor T2 and other devices in Figure 6 is: the control end of the third switch transistor T3 is coupled to the fourth scan signal end Gate (n2), the first end of the third switch transistor T3 is coupled to the first end of the first switch transistor T1, and the second end of the third switch transistor T3 is coupled to the fourth node N4.

[0096] During implementation, when the signal of the fourth scan signal terminal Gate(n2) is at a high level, the third switch transistor T3 is turned on, and the fourth node N4 has the same potential as the second node N2 via the turned-on third switch transistor T3 and the first switch transistor T1.

[0097] In order to ensure the display effect, in addition to resetting the second node N2 of the driving transistor DT, referring to FIG. 3 and FIG. 4 , the pixel driving circuit in the embodiment of the present application further includes: a second reset control subcircuit 40 .

[0098] The second reset control sub-circuit is coupled to the first node N1 and the third node N3 and is configured to reset the first node N1 and the third node N3.

[0099] During implementation, the second reset control subcircuit is configured to reset the first node N1 and the third node N3 simultaneously.

[0100] Referring to FIG. 4 , in one embodiment, the second reset control subcircuit includes: a fourth switch transistor T4 and a fifth switch transistor T5 , wherein the fourth switch transistor T4 and the fifth switch transistor T5 have different polarities.

[0101] It should be noted that, referring to FIG4 , in the embodiment of the present application, the fourth switch transistor T4 and the fifth switch transistor T5 have different polarities. As shown in FIG4 , the fourth switch transistor T4 is P-type and the fifth switch transistor T5 is N-type.

[0102] The connection relationship between the fourth switch transistor T4 and other devices in Figure 4 is: the control end of the fourth switch transistor T4 is coupled to the second scan signal end Gate_P(n-1), the first end of the fourth switch transistor T4 is coupled to the first initialization signal end Vinit1, and the second end of the fourth switch transistor T4 is coupled to the first end of the fifth switch transistor T5.

[0103] During implementation, when the signal of the second scan signal terminal Gate_P(n-1) is at a low level, the fourth switch transistor T4 is turned on, and the signal of the first initialization signal terminal Vinit1 reaches the third node N3 via the turned-on fourth switch transistor T4.

[0104] The connection relationship between the fifth switch transistor T5 and other devices in FIG. 4 is as follows: the control terminal of the fifth switch transistor T5 is coupled to the third scan signal terminal Gate(n), and the second terminal of the fifth switch transistor T5 is coupled to the first node N1.

[0105] During implementation, when the signal at the third scan signal terminal Gate(n) is at a high level, the fifth switch transistor T5 is turned on, and the signal at the first initialization signal terminal is provided to the first node N1 via the turned-on fourth switch transistor T4 and fifth switch transistor T5.

[0106] In another embodiment, referring to FIG. 6 or FIG. 7 , the second reset control sub-circuit includes: a fifth switch transistor T5 .

[0107] A control terminal of the fifth switch transistor T5 is coupled to the third scan signal terminal Gate(n), a first terminal of the fifth switch transistor T5 is coupled to the third node N3, and a second terminal of the fifth switch transistor T5 is coupled to the first node N1.

[0108] During implementation, after the fourth switch transistor T4 is removed, when the signal at the third scan signal terminal Gate(n) is at a high potential, the fifth switch transistor T5 is turned on, and the signal at the initialization signal terminal is provided to the first node N1 and the third node N3 via the turned-on fifth switch transistor T5.

[0109] After resetting each node associated with the driving transistor DT, a data voltage is written into the driving transistor DT via a data writing sub-circuit. Referring to FIG. 4 , the data writing sub-circuit includes a sixth switch transistor T6 .

[0110] The connection relationship between the sixth switch transistor T6 and other devices in Figure 4 is: the control end of the sixth switch transistor T6 is coupled to the first scan signal end Gate_P(n), the first end of the sixth switch transistor T6 is coupled to the data signal end, and the second end of the sixth switch transistor T6 is coupled to the second node N2.

[0111] During implementation, when the signal of the first scanning signal terminal Gate_P(n) is at a low level, the sixth switch transistor T6 is turned on, and the data voltage of the data signal terminal is provided to the gate of the driving transistor DT via the turned-on sixth switch transistor T6 and the driving transistor DT.

[0112] 4 , the light emitting control sub-circuit in the embodiment of the present application includes: a seventh switch transistor T7 .

[0113] The connection relationship between the seventh switch transistor T7 and other devices in Figure 4 is as follows: the control terminal of the seventh switch transistor T7 is coupled to the enable signal terminal EM(n), the first terminal of the seventh switch transistor T7 is coupled to the fourth node N4, and the second terminal of the seventh switch transistor T7 is coupled to the third node N3.

[0114] During implementation, when the enable signal terminal EM(n) is at a low potential, the seventh switch transistor T7 is turned on, and the turned-on seventh switch transistor T7 provides a driving current to the light emitting device OLED.

[0115] In addition, referring to FIG. 4 , in order to enable the light-emitting device OLED to emit light normally, the pixel driving circuit in the embodiment of the present application further includes: an eighth switch transistor T8 .

[0116] The connection relationship between the eighth switch transistor T8 and other devices in Figure 4 is: the control end of the eighth switch transistor T8 is coupled to the enable signal end EM(n), the first end of the eighth switch transistor T8 is coupled to the second node N2, and the second end of the eighth switch transistor T8 is coupled to the first power supply end.

[0117] During implementation, when the signal at the enable signal terminal EM(n) is at a low level, the eighth switch transistor T8 is turned on, and the electrical signal at the first power supply terminal reaches the driving transistor DT via the turned-on eighth switch transistor T8 to ensure normal operation of the driving transistor DT.

[0118] In addition, in order to enable the gate of the driving transistor DT to effectively store the above data voltage, the embodiment of the present application further includes: a first capacitor Cst.

[0119] A first terminal of the first capacitor Cst is coupled to the first node N1 , and a second terminal of the first capacitor Cst is coupled to the first power supply terminal.

[0120] During implementation, after the data writing subcircuit writes the data voltage into the gate of the driving transistor DT, the data voltage is stored by the first capacitor Cst to ensure that the data voltage is provided to the light emitting device OLED during the light emitting phase of the light emitting device OLED.

[0121] Referring to FIG. 7 , in another embodiment, the light emitting control sub-circuit includes: a seventh switch transistor T7 .

[0122] The connection relationship between the seventh switch transistor T7 and other devices in Figure 7 is as follows: the seventh switch transistor T7 is a dual-gate transistor, the first gate of the seventh switch transistor T7 is coupled to the second scan signal terminal Gate_P(n-1), and the second gate of the seventh switch transistor T7 is coupled to the enable signal terminal EM(n).

[0123] During implementation, the seventh switch transistor T7 is turned on in a time-sharing manner under the control of the second scan signal terminal Gate_P(n-1) and the enable signal terminal EM(n).

[0124] The main working process of the pixel driving circuit is described below with reference to the timing diagram.

[0125] Timing T1 stage: enable signal terminal EM(n) = 1, second scan signal terminal Gate_P(n-1) = 0, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n) = 1

[0126] 8 and 9 , when the enable signal terminal EM(n) is at a high level, the second switch transistor is turned on, and the second initialization signal terminal Vinit2 resets the fourth node via the turned-on second switch transistor. When the signal of the second scan signal terminal Gate_P(n-1) is at a low level, the first switch transistor is turned on, and the second initialization signal terminal Vinit2 resets the second node via the turned-on first switch transistor.

[0127] When the second scan signal terminal Gate_P(n-1) is at a low level, the fourth switch transistor is turned on, and the first initialization signal terminal Vinit1 resets the third node via the turned-on fourth switch transistor. When the third scan signal terminal Gate(n) is at a high level, the fifth switch transistor is turned on, and the first initialization signal terminal Vinit1 resets the first node via the turned-on fifth switch transistor.

[0128] In summary, the timing T1 stage can achieve simultaneous reset of the first node, the second node, the third node and the fourth node, thereby simplifying the circuit structure and improving the reset efficiency.

[0129] Timing T2 stage: enable signal terminal EM(n) = 1, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 0, third scan signal terminal Gate(n) = 1

[0130] Referring to Figures 10 and 11, when the first scan signal terminal Gate_P(n) is at a low potential, the sixth switch transistor is turned on, and the data voltage at the data signal terminal reaches the second node through the turned-on sixth switch transistor. Since the first node is reset in the above-mentioned timing T1 stage, the driving transistor is turned on. When the third scan signal terminal Gate(n) is at a high potential, the fifth switch transistor is turned on, and the data voltage then passes through the turned-on driving transistor and the fifth switch transistor to reach the first node, i.e., the gate of the driving transistor.

[0131] Timing T3 stage: enable signal terminal EM(n) = 0, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n) = 0

[0132] 12 and 13 , when the enable signal terminal EM(n) is at a low potential, the seventh and eighth switch transistors are turned on, and the signal from the first power supply terminal is provided to the driving transistor via the turned-on eighth transistor, so that the driving current of the gate of the driving transistor is provided to the light-emitting device OLED via the turned-on seventh transistor, thereby causing the light-emitting device to emit light.

[0133] In addition, the embodiment of the present application further provides a timing diagram corresponding to the circuit of Figure 5 , namely Figure 14 . The working process of the circuit shown in Figure 5 will be described below in conjunction with Figure 14 .

[0134] Timing T1 stage: enable signal terminal EM(n) = 1, second scan signal terminal Gate_P(n-1) = 0, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n1) = 1, fourth scan signal terminal Gate(n2) = 1

[0135] 5 and 14 , when the signal of the second scan signal terminal Gate_P(n-1) is at a low level, the fourth switch transistor is turned on, and the first initialization signal terminal Vinit1 resets the third node via the turned-on fourth switch transistor.

[0136] When the third scan signal terminal Gate(n1) is at a high potential, the second and fifth switching transistors are turned on, and the second initialization signal terminal Vinit2 resets the fourth node via the turned-on fourth switching transistor. When the fourth scan signal terminal Gate(n2) is at a high potential, the first switching transistor is turned on, and the first initialization signal terminal Vinit1 resets the second node via the fourth node and the turned-on first switching transistor.

[0137] The first initialization signal terminal Vinit1 resets the first node after passing through the third node and the turned-on fifth switch transistor.

[0138] In summary, the timing T1 stage can achieve simultaneous reset of the first node, the second node, the third node and the fourth node, thereby simplifying the circuit structure and improving the reset efficiency.

[0139] Timing T2 stage: enable signal terminal EM(n) = 1, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 0, third scan signal terminal Gate(n1) = 1, fourth scan signal terminal Gate(n2) = 0

[0140] Referring to Figures 5 and 14, when the first scan signal terminal Gate_P(n) is at a low potential, the sixth switch transistor is turned on, and the data voltage at the data signal terminal reaches the second node through the turned-on sixth switch transistor. Since the first node is reset in the above-mentioned timing T1 stage, the driving transistor is turned on. When the third scan signal terminal Gate(n) is at a high potential, the fifth switch transistor is turned on, and the data voltage then reaches the first node, i.e., the gate of the driving transistor, through the turned-on driving transistor and the fifth switch transistor.

[0141] Timing T3 stage: enable signal terminal EM(n) = 0, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n1) = 0, fourth scan signal terminal Gate(n2) = 0

[0142] 5 and 14 , when the enable signal terminal EM(n) is at a low potential, the seventh and eighth switch transistors are turned on, and the signal from the first power supply terminal is provided to the driving transistor via the turned-on eighth transistor, so that the driving current of the gate of the driving transistor is provided to the light-emitting device OLED via the turned-on seventh transistor, thereby causing the light-emitting device to emit light.

[0143] In addition, the embodiment of the present application further provides a timing diagram corresponding to the circuit of Figure 6, namely Figure 15. The working process of the circuit shown in Figure 6 will be described below in conjunction with Figure 15.

[0144] Timing T1 stage: enable signal terminal EM(n) = 1, second scan signal terminal Gate_P(n-1) = 0, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n) = 1, third scan signal terminal Gate(n1) = 1, fourth scan signal terminal Gate(n2) = 1

[0145] 6 and 15 , when the enable signal terminal EM(n) is at a high potential, the second switch transistor is turned on, and the second initialization signal terminal Vinit resets the fourth node via the turned-on second switch transistor. When the second scan signal terminal Gate_P(n-1) is at a low potential, the first switch transistor is turned on. When the fourth scan signal terminal Gate(n2) is at a high potential, the third switch transistor is turned on, and the second initialization signal terminal Vinit resets the second node via the turned-on third switch transistor and the first switch transistor.

[0146] When the third scan signal terminal Gate(n) is at a high potential, the fifth switch transistor is turned on, and the first initialization signal terminal Vinit resets the third node via the turned-on third switch transistor. The first initialization signal terminal Vinit resets the first node via the turned-on third switch transistor and the turned-on fifth switch transistor.

[0147] In summary, the first initialization signal terminal and the second initialization signal terminal may be the same signal terminal, and the embodiment of the present application uses the same initialization signal to reset different nodes.

[0148] In the above-mentioned timing T1 phase, one initialization signal terminal can be used to simultaneously reset the first node, the second node, the third node and the fourth node, thereby simplifying the circuit structure and improving the reset efficiency.

[0149] Timing T2 stage: enable signal terminal EM(n) = 1, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 0, third scan signal terminal Gate(n1) = 1, fourth scan signal terminal Gate(n2) = 0

[0150] Referring to Figures 6 and 15, when the first scan signal terminal Gate_P(n) is at a low potential, the sixth switch transistor is turned on, and the data voltage at the data signal terminal reaches the second node through the turned-on sixth switch transistor. Since the first node is reset in the above-mentioned timing T1 stage, the driving transistor is turned on. When the third scan signal terminal Gate(n) is at a high potential, the fifth switch transistor is turned on, and the data voltage then passes through the turned-on driving transistor and the fifth switch transistor to reach the first node, i.e., the gate of the driving transistor.

[0151] Timing T3 stage: enable signal terminal EM(n) = 0, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n1) = 0, fourth scan signal terminal Gate(n2) = 0

[0152] 6 and 15 , when the enable signal terminal EM(n) is at a low potential, the seventh and eighth switch transistors are turned on, and the signal from the first power supply terminal is provided to the driving transistor via the turned-on eighth transistor, so that the driving current of the gate of the driving transistor is provided to the light-emitting device OLED via the turned-on seventh transistor, thereby causing the light-emitting device to emit light.

[0153] In addition, the embodiment of the present application further provides a timing diagram corresponding to the circuit of Figure 7, namely Figure 16. The working process of the circuit shown in Figure 7 will be described below in conjunction with Figure 16.

[0154] Timing T1 stage: enable signal terminal EM1(n) = EM2(n) = 1, second scan signal terminal Gate_P(n-1) = 0, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n) = 1

[0155] 7 and 16 , when the enable signal terminal EM1(n) is at a high level, the second switch transistor is turned on, and the second initialization signal terminal Vinit is reset via the turned-on second switch transistor to reset the fourth node. When the second scan signal terminal Gate_P(n-1) is at a low level, the first switch transistor is turned on, and the second initialization signal terminal Vinit is reset via the turned-on first switch transistor to reset the second node.

[0156] When the second scan signal terminal Gate_P(n-1) is at a low level, the seventh switching transistor is turned on, and the first initialization signal terminal Vinit resets the third node via the turned-on second and seventh switching transistors. When the third scan signal terminal Gate(n) is at a high level, the fifth switching transistor is turned on, and the first initialization signal terminal Vinit resets the first node via the third node and the turned-on fifth switching transistor.

[0157] In summary, the first initialization signal terminal and the second initialization signal terminal may be the same signal terminal, and the embodiment of the present application may use the same initialization signal to reset different nodes.

[0158] In the above-mentioned timing T1 phase, one initialization signal terminal can be used to simultaneously reset the first node, the second node, the third node and the fourth node, thereby simplifying the circuit structure and improving the reset efficiency.

[0159] Timing T2 stage: enable signal terminal EM1(n) = EM2(n) = 1, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 0, third scan signal terminal Gate(n) = 1

[0160] Referring to Figures 7 and 16, when the first scan signal terminal Gate_P(n) is at a low potential, the sixth switch transistor is turned on, and the data voltage at the data signal terminal reaches the second node through the turned-on sixth switch transistor. Since the first node is reset in the above-mentioned timing T1 stage, the driving transistor is turned on. When the third scan signal terminal Gate(n) is at a high potential, the fifth switch transistor is turned on, and the data voltage then passes through the turned-on driving transistor and the fifth switch transistor to reach the first node, i.e., the gate of the driving transistor.

[0161] Timing T3 stage: enable signal terminal EM1(n) = EM2(n) = 0, second scan signal terminal Gate_P(n-1) = 1, first scan signal terminal Gate_P(n) = 1, third scan signal terminal Gate(n) = 0

[0162] 7 and 16 , when the enable signal terminal EM1(n) is at a low potential, the eighth switch transistor is turned on. When the enable signal terminal EM2(n) is at a low potential, the seventh switch transistor is turned on. The signal from the first power supply terminal is provided to the driving transistor via the turned-on eighth transistor, so that the driving current of the gate of the driving transistor is provided to the light-emitting device OLED via the turned-on seventh transistor, thereby causing the light-emitting device to emit light.

[0163] Based on the same inventive concept, an embodiment of the present disclosure provides a display device comprising any of the above-mentioned pixel driving circuits.

[0164] In the embodiments of the present invention, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described in detail herein, nor should they be construed as limiting the present invention.

[0165] Based on the same inventive concept, an embodiment of the present disclosure provides a driving method for a pixel driving circuit, including:

[0166] The first reset control subcircuit resets the potential of the second node coupled to the driving transistor.

[0167] During the implementation process, the potential of the second node coupled to the driving transistor is first reset by the first switching transistor and the second switching transistor in the first reset control sub-circuit.

[0168] The data writing sub-circuit inputs a data voltage of the data signal terminal into a first node coupled to the driving transistor in response to a signal of the first scanning signal terminal.

[0169] After resetting the second node, the data writing sub-circuit inputs the data voltage of the data signal terminal into the first node coupled to the driving transistor in response to the valid signal of the first scanning signal terminal.

[0170] The driving transistor generates a driving current according to the data voltage.

[0171] During implementation, after the data voltage is written into the gate of the driving transistor, the driving transistor generates a driving current for providing to the light emitting device according to the data voltage.

[0172] The light emitting control subcircuit provides the driving current generated by the driving transistor to the light emitting device.

[0173] During implementation, after the driving current is generated, the driving current generated by the driving transistor is provided to the light-emitting device via the light-emitting control subcircuit, so that the light-emitting device emits light.

[0174] In summary, in an embodiment of the present disclosure, a pixel driving circuit, a display device, and a driving method are provided. The pixel driving circuit includes: a driving transistor, a light-emitting device, a first reset control subcircuit, a data writing subcircuit, and a light-emitting control subcircuit. The gate of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node. The driving circuit is configured to generate a driving current according to a data voltage. The first reset control subcircuit is coupled to the second node and the fourth node, and is configured to reset the potentials of the second node and the fourth node. The data writing subcircuit is coupled to the second node, and is configured to input the data voltage of the data signal end into the first node in response to a signal of the first scanning signal end. The light-emitting control subcircuit is coupled to the light-emitting device through the driving transistor, and the light-emitting control subcircuit is configured to provide the driving current generated by the driving transistor to the light-emitting device. In the above scheme, the second node can be reset without additionally setting a reset port, thereby simplifying the reset process of the driving transistor.

[0175] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0176] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0177] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0178] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0179] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A pixel driving circuit, wherein: include: A driving transistor, a light emitting device, a first reset control subcircuit, a data writing subcircuit, and a light emitting control subcircuit; The gate of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, the second electrode of the driving transistor is coupled to the third node, and is configured to generate a driving current according to a data voltage; The first reset control subcircuit is coupled to the second node and the fourth node, and is configured to reset the potentials of the second node and the fourth node; The data writing subcircuit is coupled to the second node and is configured to input the data voltage of the data signal terminal into the first node in response to the signal of the first scanning signal terminal; The light emission control subcircuit is coupled to the light emitting device through the driving transistor, and the light emission control subcircuit is configured to provide the driving current generated by the driving transistor to the light emitting device.

2. The circuit of claim 1, wherein: The first reset control subcircuit comprises: a first switch transistor and a second switch transistor, wherein the first switch transistor and the second switch transistor have different polarities; The control terminal of the first switch transistor is coupled to the second scan signal terminal, the first terminal of the first switch transistor is coupled to the fourth node, and the second terminal of the first switch transistor is coupled to the second node; The control terminal of the second switch transistor is coupled to the enable signal terminal, the first terminal of the second switch transistor is coupled to the second initialization signal terminal, and the second terminal of the second switch transistor is coupled to the fourth node.

3. The circuit of claim 1, wherein: The first reset control subcircuit comprises: a first switch transistor and a second switch transistor, wherein the first switch transistor and the second switch transistor have the same polarity; The control terminal of the first switch transistor is coupled to the fourth scan signal terminal. The first end of the body transistor is coupled to the fourth node, and the second end of the first switch transistor is coupled to the second node; The control terminal of the second switch transistor is coupled to the third scan signal terminal, the first terminal of the second switch transistor is coupled to the second initialization signal terminal, and the second terminal of the second switch transistor is coupled to the fourth node.

4. The circuit of claim 1, wherein: The first reset control subcircuit comprises: a first switch transistor, a second switch transistor and a third switch transistor, wherein the first switch transistor and the second switch transistor have different polarities, and the third switch transistor and the second switch transistor have the same polarity; The control terminal of the first switch transistor is coupled to the second scan signal terminal, the first terminal of the first switch transistor is coupled to the third switch transistor, and the second terminal of the first switch transistor is coupled to the second node; The control terminal of the second switch transistor is coupled to the enable signal terminal, the first terminal of the second switch transistor is coupled to the second initialization signal terminal, and the second terminal of the second switch transistor is coupled to the fourth node; The control end of the third switch transistor is coupled to the fourth scan signal end, the first end of the third switch transistor is coupled to the first end of the first switch transistor, and the second end of the third switch transistor is coupled to the fourth node.

5. The circuit of claim 1, wherein: Also includes: a second reset control subcircuit; The second reset control subcircuit is coupled to the first node and the third node, and is configured to reset the first node and the third node.

6. The circuit of claim 5, wherein: The second reset control subcircuit comprises: a fourth switch transistor and a fifth switch transistor, wherein the fourth switch transistor and the fifth switch transistor have different polarities; The control terminal of the fourth switch transistor is coupled to the second scan signal terminal, the first terminal of the fourth switch transistor is coupled to the first initialization signal terminal, and the second terminal of the fourth switch transistor is coupled to the first terminal of the fifth switch transistor; The control terminal of the fifth switch transistor is coupled to the third scan signal terminal, and the second terminal of the fifth switch transistor is coupled to the first node.

7. The circuit of claim 5, wherein: The second reset control subcircuit includes: a fifth switch transistor; The control terminal of the fifth switch transistor is coupled to the third scan signal terminal, the first terminal of the fifth switch transistor is coupled to the third node, and the second terminal of the fifth switch transistor is coupled to the first node.

8. The circuit of claim 1, wherein: The data writing sub-circuit comprises: a sixth switch transistor; The control terminal of the sixth switch transistor is coupled to the first scan signal terminal, the first terminal of the sixth switch transistor is coupled to the data signal terminal, and the second terminal of the sixth switch transistor is coupled to the second node.

9. The circuit of claim 1, wherein: The light emitting control subcircuit comprises: a seventh switch transistor; The control terminal of the seventh switch transistor is coupled to the enable signal terminal, the first terminal of the seventh switch transistor is coupled to the fourth node, and the second terminal of the seventh switch transistor is coupled to the third node.

10. The circuit according to any one of claims 1 to 6, wherein: Also included: an eighth switching transistor; The control terminal of the eighth switch transistor is coupled to the enable signal terminal, the first terminal of the eighth switch transistor is coupled to the second node, and the second terminal of the eighth switch transistor is coupled to the first power supply terminal.

11. The circuit according to any one of claims 1 to 10, wherein: Also included: a first capacitor; A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to the first power supply terminal.

12. The circuit of claim 1, wherein: The light emitting control subcircuit comprises: a seventh switch transistor; The seventh switch transistor is a dual-gate transistor, a first gate of the seventh switch transistor is coupled to the second scan signal terminal, and a second gate of the seventh switch transistor is coupled to the enable signal terminal.

13. A display device, wherein: The method comprises a pixel driving circuit as described in any one of claims 1 to 12.

14. A driving method for a pixel driving circuit according to any one of claims 1 to 12, wherein: include: The first reset control subcircuit resets the potential of the second node coupled to the driving transistor; The data writing sub-circuit inputs the data voltage of the data signal terminal into the first node coupled to the driving transistor in response to the signal of the first scanning signal terminal; The driving transistor generates a driving current according to the data voltage; The light emitting control subcircuit provides the driving current generated by the driving transistor to the light emitting device.

Images