Communication system and method of performing communication between devices

Abstract

A communication system for performing communication between devices includes: a master device configured to transmit a clock and data through one serial line; and a slave device configured to receive the clock and the data from the master device through the one serial line. The slave device may be configured to receive the clock, search for a reception start point based on a frame block representing a start of the data, and set or change an operation mode based on a sequence of a second frame block subsequent to the frame block.

Description

COMMUNICATION SYSTEM AND METHOD OF PERFORMING COMMUNICATION BETWEEN DEVICES

[0001] The present disclosure relates to a communication system and method for performing communication between devices. A particular implementation relates to communication methods performed by a method of performing communication between chips within an electronic device.

[0002] As functions of electronic devices diversify, an image display apparatus such as a multimedia player having composite functions such as playback of music or video files, games, broadcasting reception, etc. may be implemented.

[0003] The image display apparatus is an apparatus configured to playback image content, and receives an image from various sources and plays the image back. The image display apparatus is implemented as various devices such as a smartphone, a tablet PC, a laptop computer, a TV, etc. The image display apparatus such as a smart TV, etc. may provide an application for providing web content such as a web browser, etc.

[0004] The electronic device such as the image display apparatus may be configured to receive wireless audiovisual (AV) data from other neighboring electronic devices or servers. A WiFi wireless interface may be taken into account, as an interface for a communication service between electronic devices. When using such a WiFi wireless interface, a millimeter wave (mmWave) band may be used for high-speed data transmission between electronic devices. In particular, high-speed data transmission between electronic devices may be performed using a wireless interface such as an 802.11ay wireless interface.

[0005] When an electronic device is configured to receive wireless AV data from another neighboring electronic device or server, synchronization and data transmission need to be performed for communication between modules / blocks / chips inside the electronic device.

[0006] In this regard, synchronization and data transmission and reception between a plurality of devices inside the electronic device or between the electronic device and another electronic device are required. Accordingly, there is a need to provide a method and apparatus for quickly transmitting and receiving data without errors in asynchronous transmission between devices or chips within the electronic device.

[0007] Therefore, the detailed description is directed to solving the aforementioned problems and other drawbacks. Accordingly, one aspect of the present disclosure is to provide a method and apparatus for quickly transmitting and receiving data without errors in asynchronous transmission between internal devices or chips of an electronic device.

[0008] Another aspect of the present disclosure is to synchronize data communication between devices in an asynchronous system.

[0009] Another aspect of the present disclosure is to enable synchronization of data communication between devices in an asynchronous system.

[0010] Another aspect of the present disclosure is to control synchronization and an operation mode of a slave device by setting or changing the operation mode of the slave device.

[0011] Another aspect of the present disclosure is to prevent shifting of data transmitted between a master device and a slave device and to improve transmission speed.

[0012] Another aspect of the present disclosure is to optimize a state configuration and operation of a slave chip by allowing various state configurations to be transmitted in advance before data transmission.

[0013] Another aspect of the present disclosure is to solve a problem of taking a long time to change a state of a slave device based on existing excess-type data, by constructing a short command.

[0014] Another aspect of the present disclosure is to increase link robustness by receiving a short command from a master chip.

[0015] Another aspect of the present disclosure is to avoid an RF receiver DC problem when Tx power is changed.

[0016] Another aspect of the present disclosure is to eliminate a DC effect by suppressing a DC problem during data transmission.

[0017] To achieve the above or other aspect and advantages, there is provided a communication system for performing communication between devices includes a master device configured to transmit a clock and data through one serial line; and a slave device configured to receive the clock and the data from the master device through the one serial line. The slave device may be configured to receive the clock, search for a reception start point based on a frame block representing a start of the data, and set or change an operation mode based on a sequence of a second frame block subsequent to the frame block.

[0018] In an embodiment disclosed herein, when a first bit of the second frame block is 1, the operation mode of the slave device may be set or changed by a first command corresponding to subsequent bits. Operations relating to switching between a transmission mode and a reception mode of the slave device, a power level, and a beam direction may be controlled based on the first command.

[0019] In an embodiment disclosed herein, when a first bit of the second frame block is 0, the operation mode of the slave device may be set or changed by a second command corresponding to subsequent bits. The slave device may be controlled to operate any one of a read mode, a write mode, or a read and response mode based on the second command.

[0020] In an embodiment disclosed herein, the frame block representing the start and the second frame block may constitute a plurality of command frames. Learning frames may be disposed between the command frames, and the command frames and the learning frames may constitute a trigger sequence.

[0021] In an embodiment disclosed herein, the frame block representing the start, the second frame block, a parameter block, a payload block, and a stop block representing a stop of the data may constitute at least one normal frame. Learning frames may be disposed at a position before the frame block and at a position after the stop block. The normal frame and the learning frames may constitute a normal sequence.

[0022] In an embodiment disclosed herein, the master device may transmit the RF signal of a first frequency band, including On-Off Keying (OOK) coded data, and a clock signal of a second frequency band including the reference clock to the slave device. The first frequency band may be set to a higher frequency than the second frequency band.

[0023] In an embodiment disclosed herein, the master device may include a first radio frequency (RF) transceiver configured to transmit an RF signal including the reference clock and the data, and a first modem operably coupled to the first RF transceiver and configured to transmit the data to the first RF transceiver. The first modem may include a transmission unit configured to output a transmission signal and a reception unit configured to receive a reception signal.

[0024] In an embodiment disclosed herein, the master device may further include a first diplexer configured to receive the clock and the data from the first RF transceiver and to separate the clock and the data. The first diplexer may transfer the clock and the data to the reception unit through the first RF transceiver.

[0025] In an embodiment disclosed herein, the master device may further include a phase-locked loop (PLL) configured to output the clock by controlling an output signal using a phase difference between an input signal and a signal fed back from the output signal, and a divider configured to generate the clock by dividing the reference clock output from the PLL. The clock output from the divider may be transferred to the first modem and the first diplexer.

[0026] In an embodiment disclosed herein, the transmission unit may include a transmitter configured to receive data output from a processor and transmit the data, a first encoder configured to convert the output data of a first bit set into data of a second bit set, a second encoder configured to convert the data of the second bit set into forward error correction (FEC)-performed data, and a serializer configured to sequentially transmit the converted data.

[0027] In an embodiment disclosed herein, the reception unit may include a de-serializer configured to parallelize the converted FEC-performed data sequentially received from the first RF transceiver, a first decoder configured to restore the converted data into the data of the second bit set before the FEC is performed, a second decoder configured to restore the data of the second bit set into the data of the first bit set, and a receiver configured to receive the data of the first bit set to transfer to the processor.

[0028] In an embodiment disclosed herein, the first encoder may be configured to perform encoding such that 8-bit data is mapped to a 10-bit symbol in order to suppress a direct-current (DC) offset during data transmission, and the second encoder may be configured to perform encoding by a 2 / 3 FEC method of converting 2-bit input data into 3-bit output data. The first decoder may be configured to perform decoding by a 2 / 3 FEC method of converting 3-bit input data into 2-bit output data, and the second decoder may be configured to perform decoding such that the 10-bit symbol is de-mapped into the 8-bit data.

[0029] In an embodiment disclosed herein, the slave device may include a second RF transceiver configured to receive an RF signal including the reference clock restored from the clock and the data, and a second modem operably coupled to the second RF transceiver and configured to obtain the data from the RF signal received from the second RF transceiver. An envelope of the RF signal may be converted into input data that is input to the second modem. The second modem may include a transmission unit configured to output a transmission signal and a reception unit configured to receive a reception signal.

[0030] In an embodiment disclosed herein, the slave device may further include a second diplexer configured to receive the clock and the data from the second RF transceiver and to separate the clock and the data. The second diplexer may transfer the clock and the data to the reception unit through the second RF transceiver.

[0031] In an embodiment disclosed herein, the slave device may include a phase-locked loop (PLL) configured to output the reference clock by controlling an output signal using a phase difference between the clock as an input signal and a signal fed back from the output signal, and a divider configured to generate the clock by dividing the reference clock output from the PLL. The reference clock output from the PLL may be transferred to the second RF transceiver, and the clock output from the divider may be transferred to the second modem.

[0032] In an embodiment disclosed herein, the transmission unit may include a transmitter configured to receive data output from a processor and transmit the data, a first encoder configured to convert the output data of a first bit set into data of a second bit set, a second encoder configured to convert the data of the second bit set into forward error correction (FEC)-performed data, and a serializer configured to sequentially transmit the converted data.

[0033] In an embodiment disclosed herein, the reception unit may include a de-serializer configured to parallelize the converted FEC-performed data sequentially received from the second RF transceiver, a first decoder configured to restore the converted data into the data of the second bit set before the FEC is performed, a second decoder configured to restore the data of the second bit set into the data of the first bit set, and a receiver configured to receive the data of the first bit set to transfer to the processor.

[0034] In an embodiment disclosed herein, the first encoder may be configured to perform encoding such that 8-bit data is mapped to a 10-bit symbol in order to suppress a direct-current (DC) offset during data transmission, and the second encoder may be configured to perform encoding by a 2 / 3 FEC method of converting 2-bit input data into 3-bit output data. The first decoder may be configured to perform decoding by a 2 / 3 FEC method of converting 3-bit input data into 2-bit output data, and the second decoder may be configured to perform decoding such that the 10-bit symbol is de-mapped into the 8-bit data.

[0035] In an embodiment disclosed herein, the first transceiver and the transceiver may generate digital data in which a clock signal having second pulses formed in a second period shorter than a first period is applied to an inside of a data signal having first pulses formed in the first period, and transfer the RF signal to the slave device by including the digital data in the RF signal.

[0036] In an embodiment disclosed herein, the first transceiver and the transceiver may include a first element to which the data signal and the clock signal are input, a second element connected in parallel to the first element and configured to receive the data signal and the clock signal, and a first resistor and a second resistor connected to a first output end and a second output end of the second element

[0037] Technical effects of a communication system performing communication between devices, and communication methods performed by a master device and a slave device that perform communication between the devices in the communication system will be described, but are not limited thereto.

[0038] According to at least one embodiment of the present disclosure, a master device and a slave device may simultaneously transmit and receive data and clock through a single wire, which may enable synchronization of data communication between devices in an asynchronous system.

[0039] According to at least one embodiment of the present disclosure, a reception start point may be searched for based on a frame block indicating the start of data after reception of a clock, thereby enabling synchronization of data communication between devices in an asynchronous system.

[0040] According to at least one embodiment of the present disclosure, an operation mode of a slave device may be set or changed based on a sequence of a second frame block subsequent to a frame block, thereby enabling synchronization and operation mode control of the slave device.

[0041] According to at least one embodiment of the present disclosure, the same clock may be used between the master device and the slave device to prevent shifting of data transmitted based on the clock signal, and improve transmission speed.

[0042] According to at least one embodiment of the present disclosure, various state configurations may be transmitted in advance before data transmission from a master chip to a slave chip, thereby optimizing the state configuration and operation of the slave chip.

[0043] According to at least one embodiment of the present disclosure, a problem of taking too long to change a state of a slave device based on data in an existing access manner may be solved by constructing a short command.

[0044] According to at least one embodiment of the present disclosure, link robustness may be further increased by receiving a short command having a short data length from a master chip.

[0045] According to at least one embodiment of the present disclosure, a direct-current (DC) problem of a radio frequency (RF) receiver may be avoided by designing a DC of an RF transmitter not to change when transmission (Tx) power is changed.

[0046] According to at least one embodiment of the present disclosure, a DC effect may be removed by using a programmable amount of preamble data and 8b / 10b coding to suppress a DC problem during data transmission.

[0047] Further scope of applicability of the present disclosure will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, such as the preferred embodiment of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will be apparent to those skilled in the art.

[0048] FIG. 1 is a diagram schematically illustrating an example of a whole of a wireless audiovisual (AV) system including an image display device according to an embodiment of the present disclosure.

[0049] FIG. 2 illustrates a detailed configuration of electronic devices configured to support a wireless interface according to the present disclosure.

[0050] FIG. 3 is a diagram illustrating a system including a master device and a slave device in accordance with the present disclosure.

[0051] FIG. 4 is a diagram illustrating a detailed configuration of the master device of FIG. 3.

[0052] FIG. 5 is a diagram illustrating a detailed configuration of the slave device of FIG. 3.

[0053] FIG. 6 is a diagram illustrating sequences transmitted from a master device to a slave device according to the present disclosure.

[0054] FIG. 7 is a circuit and timing diagram illustrating that a data signal and a clock signal are transmitted by being implemented as pulse signals of different periods in a communication system in accordance with the present disclosure.

[0055] FIG. 8 is a flowchart of a communication method performed by a master device performing communication between devices of a communication system in accordance with the present disclosure.

[0056] FIG. 9 is a flowchart of a method performed by a slave device performing communication between devices of a communication system in accordance with the present disclosure.

[0057] Hereinafter, embodiments disclosed herein will be described in detail with reference to the accompanying drawings, and the same or similar elements are designated with the same numeral references, regardless of the numerals in the drawings, and their redundant description will be omitted. In general, a suffix such as "module" and "unit" may be used to refer to elements or components. Use of such a suffix herein is merely intended to facilitate description of the specification, and the suffix itself is not intended to give any special meaning or function. In describing the present disclosure, if a detailed explanation for a related known function or construction is considered to unnecessarily divert the gist of the present disclosure, such explanation has been omitted but would be understood by those skilled in the art. The accompanying drawings are used to help easily understand the technical idea of the present disclosure and it should be understood that the idea of the present disclosure is not limited by the accompanying drawings. The idea of the present disclosure should be construed to extend to any alterations, equivalents and substitutes besides the accompanying drawings.

[0058] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are generally only used to distinguish one element from another.

[0059] It will be understood that when an element is referred to as being "connected with" another element, the element can be connected with the another element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected with" another element, there are no intervening elements present.

[0060] A singular representation may include a plural representation unless it represents a definitely different meaning from the context.

[0061] Terms such as "include" or "has" are used herein and should be understood that they are intended to indicate an existence of several components, functions or steps, disclosed in the specification, and it is also understood that greater or fewer components, functions, or steps may likewise be utilized.

[0062] Description will now be given in detail according to exemplary embodiments disclosed herein, with reference to the accompanying drawings. For the sake of brief description with reference to the drawings, the same or equivalent components may be provided with the same or similar reference numbers, and description thereof will not be repeated. In general, a suffix such as "module" and "unit" may be used to refer to elements or components. Use of such a suffix herein is merely intended to facilitate description of the specification, and the suffix itself is not intended to give any special meaning or function. In describing the present disclosure, if a detailed explanation for a related known function or construction is considered to unnecessarily divert the gist of the present disclosure, such explanation has been omitted but would be understood by those skilled in the art. The accompanying drawings are used to help easily understand the technical idea of the present disclosure and it should be understood that the idea of the present disclosure is not limited by the accompanying drawings. The idea of the present disclosure should be construed to extend to any alterations, equivalents and substitutes besides the accompanying drawings.

[0063] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are generally only used to distinguish one element from another.

[0064] It will be understood that when an element is referred to as being "connected with" another element, the element can be connected with the another element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected with" another element, there are no intervening elements present.

[0065] A singular representation may include a plural representation unless it represents a definitely different meaning from the context.

[0066] Terms such as "include" or "has" are used herein and should be understood that they are intended to indicate an existence of several components, functions or steps, disclosed in the specification, and it is also understood that greater or fewer components, functions, or steps may likewise be utilized.

[0067] Electronic devices presented herein may be implemented using a variety of different types of terminals. Examples of such devices include cellular phones, smart phones, laptop computers, digital broadcasting terminals, personal digital assistants (PDAs), portable multimedia players (PMPs), navigators, slate PCs, tablet PCs, ultra books, wearable devices (for example, smart watches, smart glasses, head mounted displays (HMDs)), and the like.

[0068] By way of non-limiting example only, further description will be made with reference to particular types of mobile terminals. However, such teachings apply equally to other types of terminals, such as those types noted above. In addition, these teachings may also be applied to stationary terminals such as digital TVs, desktop computers, digital signages, and the like.

[0069] FIG. 1 is a diagram schematically illustrating an example of a whole of a wireless audiovisual (AV) system including an image display device according to an embodiment of the present disclosure.

[0070] As illustrated in FIG. 1, an image display device 100 according to another embodiment of the present disclosure is connected to the wireless AV system (or a broadcasting network) and an Internet network. The image display device 100 may be, for example, a network TV, a smart TV, a hybrid broadcast broadband TV (HBBTV), or the like.

[0071] The image display device 100 may be wirelessly connected to the wireless AV system (or the broadcasting network) via a wireless interface or wirelessly or wiredly connected to the Internet network via an Internet interface. In relation to this, the image display device 100 may be configured to be connected to a server or another electronic device via a wireless communication system. As an example, the image display device 100 needs to provide an 802.11ay communication service operating in a millimeter wave (mmWave) band to transmit or receive large-capacity data at a high speed.

[0072] The mmWave band may be any frequency band in a range of 10 GHz to 300 GHz. In this disclosure, the mmWave band may include an 802.11ay band of a 60 GHz band. In addition, the mmWave band may include a 5G frequency band of a 28 GHz band or the 802.11ay band of the 60 GHz band. The 5G frequency band may be set to about 24 to 43 GHz band and the 802.11ay band may be set to 57 to 70 GHz or 57 to 63 GHz band, but are not limited thereto.

[0073] The image display device 100 may wirelessly transmit or receive data to / from an electronic device in a periphery of the image display device 100, e.g., a set-top box or another electronic device via the wireless interface. As an example, the image display device 100 may transmit or receive wireless AV data to / from a set-top box or another electronic device, e.g., a mobile terminal arranged in front of or below the image display device 100.

[0074] The image display device 100 includes, for example, a wireless interface 101b, a section filter 102b, an application information table (AIT) filter 103b, an application data processing unit 104b, a data processing unit 111b, a media player 106b, an Internet protocol processing unit 107b, an Internet interface 108b, and a runtime module 109b.

[0075] Through a broadcast interface that is the wireless interface 101b, AIT data, real-time broadcast content, application data, and a stream event are received. The real-time broadcast content may be referred to as linear audio / video (A / V) content.

[0076] The section filter 102b performs section filtering on four types of data received through the wireless interface 101b to transmit the AIT data to the AIT filter 103b, the linear A / V content to the data processing unit 111b, and the stream events and the application data to the application data processing unit 104b.

[0077] Non-linear A / V content and the application data are received through the Internet interface 108b. The non-linear A / V content may be, for example, a content on demand (COD) application. The non-linear A / V content is transmitted to the media player 106b, and the application data is transmitted to the runtime module 109b.

[0078] Further, the runtime module 109b includes, for example, an application manager and a browser as illustrated in FIG. 1. The application manager controls a life cycle of an interactive application using, for example, the AIT data. In addition, the browser performs, for example, a function of displaying and processing the interactive application.

[0079] Hereinafter, a communication module having an antenna for providing a wireless interface in an electronic device such as the above-described image display device will be described in detail. In relation to this, the wireless interface for communication between electronic devices may be a WiFi wireless interface, but is not limited thereto. As an example, a wireless interface supporting the 802.11ay standard may be provided for high-speed data transmission between electronic devices.

[0080] The 802.11ay standard is a successor standard for raising a throughput for the 802.11ad standard to 20 Gbps or greater. An electronic device supporting an 802.11ay wireless interface may be configured to use a frequency band of about 57 to 64 GHz. The 802.11ay wireless interface may be configured to provide backward compatibility for an 802.11ad wireless interface. The electronic device providing the 802.11ay wireless interface may be configured to provide coexistence with a legacy device using the same band.

[0081] In relation to a wireless environment for the 802.11ay standard, it may be configured to provide a coverage of 10 meters or longer in an indoor environment, and 100 meters or longer in an outdoor environment with a line of sight (LOS) channel condition.

[0082] The electronic device supporting the 802.11ay wireless interface may be configured to provide visual reality (VR) headset connectivity, support server backups, and support cloud applications that require low latency.

[0083] An ultra-short range (USR) communication scenario, i.e., a near field communication scenario which is a use case of the 802.11ay wireless interface, is a model for fast large-capacity data exchange between two terminals. The USR communication scenario may be configured to require low power consumption of less than 400 mW, while providing a fast link setup within 100 msec, transaction time within 1 second, and a 10 Gbps data rate at a very close distance of less than 10 cm.

[0084] As the use case of the 802.11ay wireless interface, the 8K UHD Wireless Transfer at Smart Home Usage Model may be taken into account. In the Smart Home Usage Model, a wireless interface between a source device and a sync device may be taken into consideration to stream 8K UHD content at home. In relation to this, the source device may be one of a set-top box, a Blue-ray player, a tablet PC, and a smart phone and the sink device may be one of a smart TV and a display device, but are not limited thereto. In relation to this, the wireless interface may be configured to transmit uncompressed 8K UHD streaming data (60 fps, 24 bits per pixel, at least 4:2:2) with a coverage of less than 5 m between the source device and the sink device. To do so, the wireless interface may be configured such that data is transmitted between electronic devices at a speed of at least 28 Gbps.

[0085] In order to provide such a wireless interface, embodiments related to an array antenna operating in a mmWave band and an electronic device including the array antenna will be described with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

[0086] FIG. 2 illustrates a detailed configuration of electronic devices configured to support a wireless interface according to the present disclosure. FIG. 2 illustrates a block diagram of an access point 110 (generally, a first wireless node) and an access terminal 120 (generally, a second wireless node) in a wireless communication system. The access point 110 is a transmitting entity for downlink transmission and a receiving entity for uplink transmission. The access terminal 120 is a transmitting entity for uplink transmission and a receiving entity for downlink transmission. As used herein, the "transmitting entity" is an independently operating apparatus or device capable of transmitting data through a wireless channel, and the "receiving entity" is an independently operating apparatus or device capable of receiving data through a wireless channel.

[0087] Referring to FIGS. 1 and 2, the set-top box (STB) of FIG. 1 may be the access point 110, and an electronic device, that is, the image display device 100 of FIG. 1 may be the access terminal 120, but are not limited thereto. Accordingly, it should be understood that the access point 110 may alternatively be an access terminal, and the access terminal 120 may alternatively be an access point.

[0088] To transmit data, the access point 110 includes a transmission (TX) data processor 220, a frame builder 222, a TX processor 224, a plurality of transceivers 226-1 to 226-N, and a plurality of antennas 230-1 to 230-N. The access point 110 also includes a controller 234 configured to control operations of the access point 110.

[0089] To transmit data, the access point 110 includes a transmission (TX) data processor 220, a frame builder 222, a TX processor 224, a plurality of transceivers 226-1 to 226-N, and a plurality of antennas 230-1 to 230-N. The access point 110 also includes a controller 234 configured to control operations of the access point 110.

[0090] During operation, the TX data processor 220 receives data (e.g., data bits) from a data source 215, and processes the data for transmission. For example, the TX data processor 220 may encode data (e.g., data bits) into encoded data, and modulate the encoded data into data symbols. The TX data processor 220 may support different modulation and coding schemes (MCSs). For example, the TX data processor 220 may encode data at any one of a plurality of different coding rates (e.g., using low-density parity check (LDPC) encoding). In addition, the TX data processor 220 may modulate the encoded data using any one of a plurality of different modulation schemes including, but not limited to, BPSK, QPSK, 16QAM, 64QAM, 64APSK, 128APSK, 256QAM, and 256APSK.

[0091] The controller 234 may transmit, to the TX data processor 220, a command for specifying an MCS to be used (e.g., based on channel conditions for downlink transmission). The TX data processor 220 may encode and modulate the data received from the data source 215 according to the specified MCS. It needs to be recognized that the TX data processor 220 may perform additional processing on the data, such as data scrambling and / or other processing. The TX data processor 220 outputs the data symbols to the frame builder 222.

[0092] The frame builder 222 constructs a frame (also referred to as a packet) and inserts the data symbols into a data payload of the frame. The frame may include a preamble, a header, and a data payload. The preamble may include a short training field (STF) sequence and a channel estimation (CE) sequence to assist the access terminal 120 in receiving the frame. The header may include information regarding data in a payload, such as a length of the data and an MCS used to encode and modulate the data. Based on this information, the access terminal 120 may demodulate and decode the data. The data in the payload may be partitioned among a plurality of blocks, and each block may contain a part of the data and a guard interval (GI) to assist the receiver in phase tracking. The frame builder 222 outputs the frame to the TX processor 224.

[0093] The TX processor 224 processes the frame for transmission on downlink. For example, the TX processor 224 may support different transmission modes, e.g., an orthogonal frequency-division multiplexing (OFDM) transmission mode and a single-carrier (SC) transmission mode. In this example, the controller 234 may transmit, to the TX processor 224, a command for specifying a transmission mode to be used, and the TX processor 224 may process the frame for transmission according to the specified transmission mode. The TX processor 224 may apply a spectrum mask to the frame so that a frequency configuration of a downlink signal complies with particular spectrum requirements.

[0094] The TX processor 224 may support multiple-input-multiple-output (MIMO) transmission. In these aspects, the access point 110 may include a plurality of antennas 230-1 to 230-N and a plurality of transceivers 226-1 to 226-N (e.g., one for each antenna). The TX processor 224 may perform spatial processing on incoming frames and provide a plurality of transmission frame streams to a plurality of antennas. The transceivers 226-1 to 226-N receive and process (e.g., convert to analog, amplify, filter, and frequency up-convert) each of the transmission frame streams to generate transmission signals for transmission through the antennas 230-1 to 230-N.

[0095] To transmit data, the access terminal 120 includes a TX data processor 260, a frame builder 262, a TX processor 264, a plurality of transceivers 266-1 to 266-M, and a plurality of antennas 270-1 to 270-M (e.g., one antenna per transceiver). The access terminal 120 may transmit data to the access point 110 on uplink and / or transmit the data to another access terminal (e.g., for peer-to-peer communication). The access terminal 120 also includes a controller 274 configured to control operations of the access terminal 120.

[0096] The transceivers 266-1 to 266-M receive and process (e.g., convert to analog, amplify, filter, and frequency up-convert) an output from the TX processor 264 for transmission via one or more of the antennas 270-1 to 270-M. For example, the transceiver 266-1 may up-convert the output from the TX processor 264 into a transmission signal having a frequency in a 60 GHz band. Accordingly, the antenna module described herein may be configured to perform a beamforming operation in the 60 GHz band, for example, in a band of about 57 to 63 GHz. In addition, the antenna module may be configured to support MIMO transmission while performing beamforming in the 60 GHz band.

[0097] In relation to this, the antennas 270-1 to 270-M and the transceivers 266-1 to 266-M may be implemented in an integrated form on a multi-layer circuit substrate. To do so, among the antennas 270-1 to 270-M, an antenna configured to operate with vertical polarization may be vertically arranged inside the multi-layer circuit substrate.

[0098] To receive data, the access point 110 includes a reception (RX) processor 242 and an RX data processor 244. During operation, the transceivers 226-1 to 226-N receive a signal (e.g., from the access terminal 120) and spatially process (e.g., frequency down-convert, amplify, filter, and digitally convert) the received signal.

[0099] The RX processor 242 receives outputs from the transceivers 226-1 through 226-N and processes the outputs to recover data symbols. For example, the access point 110 may receive data from a frame (e.g., from the access terminal 120). In this example, the RX processor 242 may detect a start of the frame using a short training field (STF) sequence in a preamble of the frame. The RX processor 242 may also use the STF for automatic gain control (AGC) adjustment. The RX processor 242 may also perform channel estimation (e.g., using a channel estimation (CE) sequence in the preamble of the frame), and perform channel equalization on the received signal based on the channel estimation.

[0100] The RX data processor 244 receives data symbols from the RX processor 242 and an indication of a corresponding MSC scheme from the controller 234. The RX data processor 244 demodulates and decodes the data symbols, recovers the data according to the indicated MSC scheme, and stores and / or outputs the recovered data (e.g., data bits) to a data sink 246 for additional processing.

[0101] The access terminal 120 may transmit the data using an orthogonal frequency-division multiplexing (OFDM) transmission mode or a single-carrier (SC) transmission mode. In this case, the RX processor 242 may process the received signal according to a selected transmission mode. In addition, as described above, the TX processor 264 may support MIMO transmission. In this case, the access point 110 includes the antennas 230-1 to 230-N and the transceivers 226-1 to 226-N (e.g., one for each antenna). Accordingly, the antenna module described herein may be configured to perform a beamforming operation in the 60 GHz band, for example, in a band of about 57 to 63 GHz. In addition, the antenna module may be configured to support MIMO transmission while performing beamforming in the 60 GHz band.

[0102] In relation to this, the antennas 230-1 to 230-M and the transceivers 226-1 to 226-M may be implemented in an integrated form on a multi-layer circuit substrate. To do so, among the antennas 230-1 to 230-M, an antenna configured to operate with vertical polarization may be vertically arranged inside the multi-layer circuit substrate.

[0103] Meanwhile, each transceiver receives and processes (e.g., frequency down-converts, amplifies, filters, and digitally converts) a signal from each antenna. The RX processor 242 may perform spatial processing on the outputs from the transceivers 226-1 to 226-N to recover the data symbols.

[0104] The access point 110 also includes a memory 236 coupled to the controller 234. The memory 236 may store commands that, when executed by the controller 234, cause the controller 234 to perform one or more of the operations described herein. Similarly, the access terminal 120 also includes a memory 276 coupled to the controller 274. The memory 276 may store commands that, when executed by the controller 274, cause the controller 274 to perform one or more of the operations described herein.

[0105] Meanwhile, the electronic device according to the present disclosure may perform data transmission / reception between components or with another electronic device.

[0106] One aspect of the present disclosure is to provide a method and apparatus for quickly transmitting and receiving data without errors in asynchronous transmission between internal devices or chips of an electronic device. Another aspect of the present disclosure is to synchronize data communication between devices in an asynchronous system. Another aspect of the present disclosure is to enable synchronization of data communication between devices in an asynchronous system. Another aspect of the present disclosure is to control synchronization and an operation mode of a slave device by setting or changing the operation mode of the slave device. Another aspect of the present disclosure is to prevent shifting of data transmitted between a master device and a slave device and to improve transmission speed. Another aspect of the present disclosure is to optimize a state configuration and operation of a slave chip by allowing various state configurations to be transmitted in advance before data transmission. Another aspect of the present disclosure is to solve a problem of taking too long to change a state of a slave device based on existing excess-type data, by constructing a short command. Another aspect of the present disclosure is to increase link robustness by receiving a short command from a master chip. Another aspect of the present disclosure is to avoid an RF receiver DC problem when Tx power is changed. Another aspect of the present disclosure is to eliminate a DC effect by suppressing a DC problem during data transmission.

[0107] In relation to this, FIG. 3 is a diagram illustrating a system including a master device and a slave device in accordance with the present disclosure. In this regard, the master device and the slave device may be implemented as a master block (or master chip) and a slave block (or slave chip) disposed inside the electronic device.

[0108] Data transmission between blocks or integrated chips (ICs) may be parallel or serial. In the parallel transmission, a plurality of bits may be transmitted simultaneously. On the other hand, in the serial transmission, one bit may be transmitted at a time. The parallel transmission is faster but may require more pins. The data transmission may be a synchronous transmission or an asynchronous transmission. In the synchronous transmission, timing information (typically, a clock) may be transmitted, along with receive data, to be used to sample the data. In the asynchronous transmission, over-sampling may be generally used to find an optimal sampling point. The synchronous transmission is faster but may require additional pins to transmit the timing information. A device (or chip) may be designed for the synchronous transmission, but typically more pins may be needed and more power may be consumed.

[0109] In the present disclosure, On-Off Keying (OOT) coded RF data may be used for transmission, all other configurations may be preloaded on a slave IC, and an operation mode may be changed in the slave IC using a special short command (trigger sequence). In this regard, referring to FIG. 3, the master device 1000 may include a diplexer 1110, an RF transceiver 1120, a phased lock loop (PLL) 1130, a divider 1140, and a modem 1200. The slave device 2000 may include a diplexer 2110, an RF transceiver 2120, a phase-locked loop (PLL) 2130, a divider 2140, and a modem 2200.

[0110] The master device 1000 may be referred to as a first device and the slave device 2000 may be referred to as a second device. Accordingly, the master device 1000 may include a first diplexer 1110, a first RF transceiver 1120, and a first modem 1200. The slave device 2000 may include a second diplexer 2110, a second RF transceiver 2120, and a second modem 2200. The first modem 1200 of the master device 1000 may be referred to as a first baseband processor. The second modem 2200 of the slave device 2000 may be referred to as a second baseband processor.

[0111] The first modem 1200 may include a processor 1210, a transmission unit 1220, and a reception unit 1230. The second modem 2200 may also include a processor 2210, a transmission unit 2220, and a reception unit 2230.

[0112] The electronic device according to the present disclosure may include an RF circuit and a baseband circuit for performing data transmission / reception between components or with another electronic device. The baseband circuit may be referred to as a modem and the modem may include a transmission unit, a reception unit, and a processor. The modem of the master device and the modem of the slave device each may include a transmission unit to transmit data and a reception unit to receive data.

[0113] In this regard, FIG. 4 is a diagram illustrating a detailed configuration of the master device of FIG. 3. FIG. 5 is a diagram illustrating a detailed configuration of the slave device of FIG. 3.

[0114] Referring to FIGS. 3 and 4, the transmission unit 1220 of the master device 1000 may include a transmitter (transmission interface) 1221, a first encoder 1222, a second encoder 1223, and a serializer 1224. The reception unit 1230 of the master device 1000 may include a de-serializer 1231, a first decoder 1232, a second decoder 1233, and a receiver (reception interface) 1234.

[0115] Referring to FIGS. 3 and 5, the transmission unit 2220 of the slave device 2000 may include a transmitter (transmission interface) 2221, a first encoder 2222, a second encoder 2223, and a serializer 2224. The reception unit 2230 of the slave device 2000 may include a de-serializer 2231, a first decoder 2232, a second decoder 2233, and a receiver (reception interface) 2234.

[0116] Hereinafter, a communication system for performing communication between devices according to the present disclosure will be described in detail, with reference to FIGS. 3 to 5. The communication system that performs communication between devices may be configured to include a master device 1000 and a slave device 2000.

[0117] The master device 1000 may be configured to transmit a clock Clk and a control signal through one serial line. The clock (Clk) of about 330 MHz and the control signal of a frequency band of 2.6 GHz may be transferred from the master device 1000 to the slave device 2000. The master device 1000 may transmit the clock and the control signal to the slave device 2000 on a control channel through the one serial line. The master device 1000 may be configured to transmit AV signal data in the 10 GHz band through the one serial line. The slave device 2000 may be configured to receive the clock Clk and the control signal from the master device 1000 through the one serial line, and then receive data. The master device 1000 may transfer the clock Clk divided from the reference clock RefClk and data to the slave device 2000.

[0118] The slave device 2000 may be configured to receive the clock Clk and data from the master device 1000 through the one serial line. The master device 1000 may transmit the clock Clk divided from a reference clock RefClk and the data to the slave device 2000.

[0119] The slave device 2000 may receive the clock Clk and search for a reception start point based on a frame block representing the start of the data. The slave device 2000 may be configured to change an operation mode based on a sequence of a second frame block following the frame block.

[0120] The operation mode of the slave device according to the present disclosure may be determined according to a type of sequence transmitted from the master device. In this regard, FIG. 6 is a diagram illustrating sequences transmitted from a master device to a slave device according to the present disclosure.

[0121] (a) of FIG. 6 illustrates a trigger sequence 3100, and (b) of FIG. 6 illustrates a normal sequence 3200.

[0122] The trigger sequence 3100 may be configured to include a frame block 3010 and a second frame block 3110 following the frame block 3010. The second frame block 3110 may be configured to include a trigger command 3111 and a first command 3112 that are coded triggers. The trigger command 3111 constitutes a first bit 3111 of the second frame block 3110 and the first command 3112 which are the coded triggers constitutes subsequent bits 3112 of the second frame block 3110.

[0123] The trigger sequence 3100 may be disposed between learning frames 3001 and 3002. The trigger sequence 3100 may be configured as a short command that includes the trigger command 3111 and the first command 3112 which are the coded triggers. On the other hand, the normal sequence 3200 may be configured as a long command that includes a frame block 3010, a second frame block 3210, a parameter block 3220, a payload block 3230, and a stop block 3240.

[0124] The normal sequence 3200 may be configured to include the frame block 3010 and the second frame block 3210 following the frame block 3010. The second frame block 3210 may be configured to include a non-trigger command 3211 and a second command 3212. The non-trigger command 3211 constitutes a first bit 3211 of the second frame block 3210 and the second command 3212 constitutes subsequent bits 3212 of the second frame block 3210.

[0125] Hereinafter, an operation mode of a communication system for performing communication between devices according to the present disclosure will be described in detail, with reference to FIGS. 3 to 6.

[0126] The slave device 2000 may be configured to change an operation mode based on the sequences of the second frame blocks 3110 and 3210 following the frame block 3010.

[0127] When the first bit 3111 of the second frame block 3110 is 1, the slave device 2000 may set or change the operation mode thereof based on the first command 3112 corresponding to the subsequent bits. Operations relating to switching between a transmission mode and a reception mode of the slave device 2000, a power level, and a beam direction may be controlled based on the first command 3112.

[0128] When the first bit 3211 of the second frame block 3210 is 0, the slave device 2000 may set or change the operation mode thereof based on the second command 3212 corresponding to the subsequent bits. The slave device 2000 may be controlled to operate in any one of a read mode, a write mode, a read and write mode, or a read and response mode based on the second command 3212. In this regard, the master device 1000 may transmit a read command or a write command. The write command may be a command for a normal write operation to a register address. In the read and response mode, the slave device 2000 may respond with a read result command or a read result error command. When an actual read operation is successful inside the slave device 2000, the slave device 2000 may respond with the read result command. When an actual read operation fails inside the slave device 2000, the slave device 2000 may respond with the read result error command.

[0129] The frame block 3010 representing a start of data and the second frame block 3110 may configure a plurality of command frames 3100a and 3100b. Learning frames 3001 and 3002 may be disposed between the command frames 3100 and 3100b. The command frames 3100a and 3100b and the learning frames 3001 and 3002 may constitute the trigger sequence 3100.

[0130] The frame block 3010 representing the start of the data, the second frame block 3210, the parameter block 3220, the payload block 3230, and the stop block 3240 representing the end of the data may constitute the normal frame 3200a. The learning frames 3001 and 3002 may be disposed at a position before the frame block 3010 and a position after the stop block 3240. The normal frame 3200a and the learning frames 3001 and 3002 may constitute the normal sequence 3200.

[0131] The trigger sequence 3100 may be a special short command, and the normal sequence 3200, which is another sequence, may be used along with read, write, and read and response. The learning frames 3001 and 3002 may optionally be implemented. The frame blocks 3010, which are start bytes of the trigger sequence 3100 and the normal sequence 3200, may be used by a receiver to find a reception start point. The first bits 3111 and 3211 of the second frame blocks 3110 and 3210, which are command bytes, may make a difference. If the first bit 3111 is '1', the first bit indicates a trigger command that is a short command, and subsequent bits 3112, which are the remaining seven bits, may be used to code a command. Accordingly, 127 different trigger commands may be provided by the seven bits as the subsequent bits 3112.

[0132] As it takes too long to change a slave state based on data uploaded in an existing access manner, including start, read / write information, address and data, a special short command including only start and command may be used. This short command may select a preloaded value displayed by the slave. To avoid a DC problem of an RF receiver, an RF transmitter may be designed so that DC does not change when Tx power changes. A DC effect may be removed using a programmable amount of preamble data. Data may go through 8b / 10b coding to avoid DC problems during data transmission. FEC coding may be used for error correction. Meanwhile, link robustness may be further increased by checking a master chip using the short command described above.

[0133] After booting, the master device 1000 may preload a task that is performed by a certain command (e.g., Tx, Rx, power level, beam direction) on the slave device 2000, and change the state of the slave device 2000 by transmitting the short command during operation.

[0134] A clock may be generated in the master device 1000, and the clock and data may be transferred from the master device 1000 to the slave device 2000. The master device 1000 may generate these clock and data, and a digital component of the master device 1000 may be implemented as the first modem 1200.

[0135] The first modem 1200, which is the digital component of the master device 1000, may transmit data bits based on the clock Clk at a speed obtained by dividing a reference clock RefClk by n (e.g., 3). A down-divided clock may also be applied to the slave device 2000. The PLL 2130 of the slave device 2000 restores the reference clock RefClk from the clock Clk by multiplying n (e.g., 3), and transmits the restored reference clock RefClk to the second RF transceiver 2120. The second modem 2200, which is the digital component of the slave device 2000, may receive data bits based on the clock Clk generated at the same rate as that used in the master device 1000. Since the clocks Clk of the master device 1000 and the slave device 2000 are based on the same source, they may have the same speed but different phases. Accordingly, the clocks Clk of the master device 1000 and the slave device 2000 may be implemented to be isochronous. The clock Clk of a first frequency (first period) corresponding to about 330 MHz may be converted into a clock of a second frequency (second period) corresponding to 2.6 GHz through the PLLs 1130 and 2130. The clock of the second frequency may be transferred to the RF transceiver 1120 through the PLL 1130, and the clock of the first frequency may be transferred to the slave device 2000 by dividing it by 4 or 8. In the slave device 2000, the clock of the first frequency is converted into the clock of the second frequency through the PLL 2130. The digital clock of the second frequency may be divided into the clock of the first frequency to match the speed of the master clock.

[0136] The master device and the slave device of the communication system that performs communication between devices according to the present disclosure may simultaneously transmit coded data and a clock signal through a single transmission line. In this regard, the coded data and the clock signal may be transferred at the same time using different frequencies over the single transmission line.

[0137] In the PLLs 1130 and 2130 of the master device 1000 and the slave device 2000, the clocks Clk which are implemented as high-frequency clocks having a short period may be obtained. In addition, the first and second modems 1200 and 2200, which are the digital components of the master device 1000 and the slave device 2000, may acquire data. Meanwhile, the clock of about 330 MHz may be continuously transmitted from the master device 1000 to the slave device 2000. When the data is "1", the data signal is transmitted from the master device 1000 to the slave device 2000, and when the data is "0", the data signal is not transmitted. To this end, the control signal of the 2.6 GHz band may be used. In this regard, the master device 1000 may be implemented such that the data is coded through on-off keying (OOK). The slave device 2000 on a receiver side may convert an envelope of a received RF signal into input data for a digital design part. The slave device 2000 may synchronize the input data.

[0138] High-frequency OOK-coded RF data may be used and the reference clock may be transferred on the same line at a lower frequency. When generating a clock with PLLs on both sides by using the same reference clock, the clock may be isochronous, which may suppress transmission data shift in relation to the reference clock. An OOK envelope may be converted into digital bits at a receiving end. This methodology may improve transmission speed of data sequences. Various state configurations may be uploaded in advance from the master chip to the slave chip before use. These various state configurations may be transferred in advance because a required amount of writes needs a too long time although speed increases.

[0139] In this regard, the master device 1000 may transmit an RF signal of a first frequency band including On-Off Keying (OOK) coded data and a clock signal of a second frequency band including a reference clock RefClk to the slave device 2000. The first frequency band is set to a higher frequency than the second frequency band to expand a bandwidth of the RF signal, enabling high-speed data communication.

[0140] The master device 1000 may be configured to include a first RF transceiver 1120 and a first modem 1200. The master device 1000 may be configured to further include a first diplexer 1110. The master device 1000 may be configured to further include a phase-locked loop (PLL) 1130 and a divider 1140.

[0141] The first RF transceiver 1120 may be configured to transmit an RF signal including a reference clock RefClk and data. In this regard, the first RF transceiver 1120 may receive the reference clock RefClk from the PLL 1130 and receive the data from the first modem 1200. The first RF transceiver 1120 may transmit a reception signal received from the slave device 2000 to the first modem 1200.

[0142] The first modem 1200 may be operably coupled to the first RF transceiver 1120. The first modem 1200 may include a transmission unit 1220 that outputs a transmission signal and a reception unit 1230 that receives a reception signal. The first modem 1200 may be configured to transmit data to the first RF transceiver 1120 through the transmission unit 1220. The first modem 1200 may also receive the reception signal received from the slave device 2000 through the first RF transceiver 1120 and the reception unit 1230.

[0143] The first diplexer 1110 may be configured to receive data from the first RF transceiver 1120 and to divide the transmission signal and the reception signal. The first diplexer 1110 may transmit the reception signal received from the slave device 2000 to the reception unit 1230 through the first RF transceiver 1120. Also, the first diplexer 1110 may transmit the transmission signal transmitted from the transmission unit 1220 to the slave device 2000 through the first RF transceiver 1120. RF bands of the transmission signal and the reception signal may be set to be different in order to transmit the transmission signal and receive the reception signal at the same time.

[0144] Meanwhile, the first diplexer 1110 may be configured to separate the clock Clk at a lower frequency and separate OOK coded data at a higher frequency. In this regard, the transmission operation and the reception operation are not performed simultaneously, and the communication system may be implemented in a half-duplex scheme. Accordingly, the first diplexer 1110 may separate the clock Clk and the OK coded data without separating the transmission signal and the reception signal. The slave device 2000 responds only to the read command, and the master device 1000 does not transmit data while master device 1000 receives a response to the read command. In response, the slave device 2000 may transmit only OOK coded data without transmitting the reference clock of about 330 MHz to the master device 1000 again. The master device 1000 and the slave device 2000 may transmit data through the same frequency band. In this regard, the slave device 2000 may transmit data only when the master device 1000 commands to transmit data. As another example, the master device 1000 and the slave device 2000 may simultaneously transmit and receive data through different frequency bands.

[0145] The phase-locked circuit (PLL) 1130 may be configured to output a clock Clk by controlling an output signal using a phase difference between an input signal and a signal fed back from an output signal. The divider 1140 may be configured to generate the clock Clk by dividing a reference clock RefClk output from the PLL 1130. The clock Clk output from the divider 1140 may be transmitted to the first modem 1200 and the first diplexer 1110.

[0146] The transmission unit 1220 of the first modem 1200 may include a transmitter 1221, a first encoder 1222, a second encoder 1223, and a serializer 1224.

[0147] The transmitter 1221 may be configured to receive data output from the processor 1210 and transmit the data. The first encoder 1222 may be operably coupled to the transmitter 1221. An output of the transmitter 1221 may be coupled to an input of the first encoder 1222. The first encoder 1222 may be configured to convert output data of a first bit set into data of a second bit set.

[0148] The second encoder 1223 may be operably coupled to the first encoder 1222. An output of the first encoder 1222 may be coupled to an input of the second encoder 1223. The second encoder 1223 may be configured to convert data of a second bit set into forward error correction (FEC)-performed data. The serializer 1224 may be operably coupled to the second encoder 1223. An output of the second encoder 1223 may be connected to an input of the serializer 1224. The serializer 1224 may be configured to sequentially transmit the converted data.

[0149] The reception unit 1230 of the first modem 1200 may include a de-serializer 1231, a first decoder 1232, a second decoder 1233, and a receiver 1234.

[0150] The de-serializer 1231 may be configured to parallelize the converted data, on which the FEC has been performed, sequentially received from the first RF transceiver 1120. The first decoder 1232 may be operably coupled to the de-serializer 1231. An output of the de-serializer 1231 may be coupled to an input of the first decoder 1232. The first decoder 1232 may be configured to restore the converted data into the data of the second bit set before the FEC is performed.

[0151] The second decoder 1233 may be operably coupled to the first decoder 1232. An output of the first decoder 1232 may be coupled to an input of the second decoder 1233. The second decoder 1233 may be configured to restore the data of the second bit set to the data of the first bit set. The receiver 1234 may be operably coupled to the second decoder 1233. An output of the second decoder 1233 may be coupled to an input of the receiver 1234. The receiver 1234 may be configured to receive the data of the first bit set to transmit to the processor 1210.

[0152] The first encoder 1222 may be configured to perform encoding such that 8-bit data is mapped to a 10-bit symbol in order to suppress a DC offset during data transmission. The second encoder 1223 may be configured to perform encoding by a 2 / 3 FEC method of converting 2-bit input data into 3-bit output data.

[0153] The first decoder 1232 may be configured to perform decoding by a 2 / 3 FEC method of converting 3-bit input data into 2-bit output data. The second decoder 1233 may be configured to perform decoding such that the 10-bit symbol is de-mapped into the 8-bit data.

[0154] The slave device 2000 may be configured to include a second RF transceiver 2120 and a second modem 2200. The slave device 2000 may be configured to further include a second diplexer 2110. The slave device 2000 may be configured to further include a phase-locked loop (PLL) 2130 and a divider 2140.

[0155] The first RF transceiver 1120 may be configured to transmit an RF signal including a reference clock RefClk and data. In this regard, the first RF transceiver 1120 may receive the reference clock RefClk from the PLL 1130 and receive the data from the first modem 1200. The first RF transceiver 1120 may transmit a reception signal received from the slave device 2000 to the first modem 1200.

[0156] The second RF transceiver 2120 may be configured to receive an RF signal which includes the reference clock RefClk restored from the clock Clk and the data. In this regard, the second RF transceiver 2120 may receive the reference clock RefClk from the PLL 2130 and receive the data from the second modem 2200. The second RF transceiver 2120 may transmit a reception signal received from the master device 1000 to the second modem 2200. The second RF transceiver 2120 may transmit a transmission signal transmitted from the second modem 2200 to the master device 1000.

[0157] The second modem 2200 may be operably coupled to the second RF transceiver 2220. The second modem 2200 may include a transmission unit 2220 that outputs a transmission signal and a reception unit 2230 that receives a reception signal. The second modem 2200 may be configured to obtain data from an RF signal received from the second RF transceiver 2220.

[0158] The second modem 2200 may be configured to transmit data to the second RF transceiver 2120 through the transmission unit 2220. The second modem 2200 may also receive the reception signal, which is received from the master device 1000, through the second RF transceiver 2120 and the reception unit 2230. An envelope of the RF signal received from the second RF transceiver 2220 may be converted into input data which is to be input to the second modem 2200.

[0159] The second diplexer 2110 may be configured to receive data from the second RF transceiver 2120 and to divide the transmission signal and the reception signal. The second diplexer 2110 may transmit the reception signal received from the master device 1000 to the reception unit 2230 through the second RF transceiver 2120. Also, the second diplexer 2110 may transmit the transmission signal transmitted from the transmission unit 2220 to the master device 1000 through the second RF transceiver 2120. RF bands of the transmission signal and the reception signal may be set to be different in order to transmit the transmission signal and receive the reception signal at the same time. Meanwhile, the first and second diplexers 1110 and 21110 are implemented as a triplexer that separates the clock (Clk) of about 330 MHz, the control signal of 2.6 GHz frequency band, and data, which is an AV signal in the 10 GHz band. For example, the second diplexer 21110 may be configured to separate the clock (Clk), the control signal, and the data from among the received signals received from the master device 1000.

[0160] The phase-locked circuit (PLL) 2130 may be configured to output a reference clock RefClk by controlling an output signal using a phase difference between the clock Clk as an input signal and a signal fed back from the output signal. The divider 2140 may be configured to generate the clock Clk by dividing the reference clock RefClk output from the PLL 2130. The reference clock RefClk output from the PLL 2130 may be transmitted to the second RF transceiver 2120. The clock Clk output from the divider 1140 may be transmitted to the second modem 1200.

[0161] The transmission unit 2220 of the second modem 2200 may include a transmitter 2221, a first encoder 2222, a second encoder 2223, and a serializer 2224.

[0162] The transmitter 2221 may be configured to receive data output from the processor 2210 and transmit the data. The second encoder 2222 may be operably coupled to the transmitter 2221. An output of the transmitter 2221 may be coupled to an input of the first encoder 2222. The first encoder 2222 may be configured to convert output data of a first bit set into data of a second bit set.

[0163] The second encoder 2223 may be operably coupled to the first encoder 2222. An output of the first encoder 2222 may be coupled to an input of the second encoder 2223. The second encoder 2223 may be configured to convert the data of the second bit set into forward error correction (FEC)-performed data. The serializer 2224 may be operably coupled to the second encoder 2223. An output of the second encoder 2223 may be connected to an input of the serializer 2224. The serializer 2224 may be configured to sequentially transmit the converted data.

[0164] The reception unit 2230 of the second modem 2200 may include a de-serializer 2231, a first decoder 2232, a second decoder 2233, and a receiver 2234.

[0165] The de-serializer 2231 may be configured to parallelize the converted data, on which the FEC has been performed, sequentially received from the first RF transceiver 2120. The second decoder 2232 may be operably coupled to the de-serializer 2231. An output of the de-serializer 2231 may be coupled to an input of the first decoder 2232. The first decoder 2232 may be configured to restore the converted data into the data of the second bit set before the FEC is performed.

[0166] The second decoder 2233 may be operably coupled to the first decoder 2232. An output of the first decoder 2232 may be coupled to an input of the second decoder 2233. The second decoder 2233 may be configured to restore the data of the second bit set to the data of the first bit set. The receiver 2234 may be operably coupled to the second decoder 2233. An output of the second decoder 2233 may be coupled to an input of the receiver 2234. The receiver 2234 may be configured to receive the data of the first bit set to transmit to the processor 2210.

[0167] The first encoder 2222 may be configured to perform encoding such that 8-bit data is mapped to a 10-bit symbol in order to suppress a DC offset during data transmission. The second encoder 2223 may be configured to perform encoding by a 2 / 3 FEC method of converting 2-bit input data into 3-bit output data.

[0168] The second decoder 1232 may be configured to perform decoding by a 2 / 3 FEC method of converting 3-bit input data into 2-bit output data. The second decoder 2233 may be configured to perform decoding such that the 10-bit symbol is de-mapped into the 8-bit data.

[0169] Meanwhile, in a communication system for performing communication between devices according to the present disclosure, a data signal and a clock signal may be implemented as pulse signals having different periods, and the data signal and the clock signal may be multiplexed and transmitted together. In this regard, FIG. 7 a circuit and timing diagram illustrating that a data signal and a clock signal are transmitted by being implemented as pulse signals of different periods in a communication system in accordance with the present disclosure.

[0170] Referring to FIG. 7, a data signal 710 may be implemented with first pulses having a first period. A clock signal 720 may be implemented with second pulses having a second period shorter than the first period. Data signal 710 may be generated by a modem and clock signal 720 may be generated by a PLL. Clock signal 720 may be OOK coded data transferred by the serializer. The clock signal 720 may be a clock signal converted through a PLL of 2,6 GHz band. The clock having a lower frequency than the clock signal 720 may be transmitted from the master device to the slave device.

[0171] Referring to FIGS. 3, 4, and 7, the data signal 710 and the clock signal 720 may be generated and synthesized by the RF transceiver 1120 of the master device 1000 and / or the RF transceiver 2120 of the slave device 2000. To this end, the processor 1210 of the master device 1000 may control the RF transceiver 1120 and the processor 2210 of the slave device 2000 may control the RF transceiver 2120.

[0172] The RF transceiver 1120, 2120 may be gated to the clock signal 720 to generate the data signal 710. The RF transceiver 1120, 2120 may generate digital data by applying the clock signal 720 having the second pulses formed in the second period to the inside of the data signal 710 having the first pulses formed in the first period. The RF transceiver 1120, 2120 may generate digital data obtained by multiplying the data signal 710 having the first pulses formed in the first period by the clock signal 720 having the second pulses formed in the second period.

[0173] The second period of the clock signal 720 may be shorter than the first period of the data signal 710. For example, the first period of the data signal 710 may be implemented as an integer multiple (n times) of the second period of the clock signal 720. The processor 1210, 2210 may transmit an RF signal to the slave device 2000 or the master device 1000 by including digital data in the RF signal.

[0174] The RF transceiver 1120, 2120 may include a first element EL1 and a second element EL2. The first element EL1 may be configured to receive the data signal 710 and the clock signal 720 as inputs. The first element EL1 may output digital data in which the clock signal 720 having the second pulses formed in the second period is applied to the inside of the data signal 710 having the first pulses formed in the first period.

[0175] The second element EL2 may be connected in parallel to the first element EL1. The second element EL2 may be configured to receive the data signal 710 and the clock signal 720 as inputs. The second element EL2 may output digital data in which the clock signal 720 having the second pulses formed in the second period is applied to the inside of the data signal 710 having the first pulses formed in the first period.

[0176] The processor 1210, 2210 may further include a first resistor R1 connected to a first output 730a of the first element EL1 and a second resistor R2 connected to a second output 730b of the second element EL2. Resistance values of the first resistor R1 and the second resistor R2 may be set to 100 ohm, but are not limited thereto and may vary depending on a magnitude of a pulse voltage value. The processor 1210, 2210 may be configured to output an output signal 730 in which the first output 730a of the first element EL1 and the second output 730b of the second element EL2 are synthesized.

[0177] On the other hand, in a communication system for performing communication between devices according to the present disclosure, a DC voltage may rest constantly without a change even if power of the transmission unit changes. In this regard, the clock signal 720, which is a local signal, may be gated with the data signal 710 in various ways. When the data signal 710 is "0" in a first path, the signal may rest at VDD. In a second path, the signal may rest at VSS. If the signal is resistively coupled, a DC-component with a value of VDD / 2 may be generated in a resultant signal. The DC-component may be implemented independently of the data signal 710.

[0178] The digital circuit of FIG. 7 may represent one transmitter cell. Several of these cells may be connected in parallel, so output power may be adjusted by turning the cells on or off. An R2R network may be constructed through these transmitter cells. Then, the output power may be selected through a binary control signal and an output DC level may be constant maintained at VDD / 2.

[0179] In the above, the communication system for performing communication between devices according to one aspect of the present disclosure has been described. Hereinafter, a method of performing communication between devices of a communication system according to another aspect of the present disclosure will be described.

[0180] In this regard, FIG. 8 is a flowchart of a communication method performed by a master device performing communication between devices of a communication system in accordance with the present disclosure.

[0181] Referring to FIG. 8, a communication method performed by the master device may include configuring a data sequence (S110), including a clock signal in the data sequence (S120), and including the data sequence including the clock signal in an RF signal (S130). The communication method may further include transmitting a clock and data through one serial line (S140).

[0182] The communication method performed by the master device may further include a first encoding step (S101) and a second encoding step (S102). In the first encoding step (S101), data of a first bit set may be converted into data of a second bit set. In the second encoding step (S102), the data of the second bit set may be converted into FEC-performed data, and the converted data may be sequentially transmitted.

[0183] In step S110, the data sequence may be configured using the sequentially converted data. In step S110, the data sequence may be configured as a trigger sequence or a normal sequence. The trigger sequence may be configured to include a plurality of command frames which include a frame block representing the start of the data and a second frame block. The normal sequence may be configured to include at least one normal frame which includes a frame block representing the start of data, a second frame block, a parameter block, a payload block, and a stop block indicating the stop (end) of data.

[0184] In step S120, the clock signal may be included in the data sequence. In this regard, the data sequence (or data signal) may be configured to include first pulses formed in a first period. The clock signal may be configured to include second pulses formed in a second period shorter than the first period.

[0185] In step S130, the data sequence including the clock signal may be included in the RF signal. The step S130 may be performed before step S120. The clock may be included in the RF signal of about 330 MHz, and the control signal may be included in the RF signal of the 2.6 GHz band. Meanwhile, the AV data may be included in the RF signal of the 10 GHz band in step S130 separately from the clock and control signals. In step S140, the clock and data may be transmitted to the slave device through the one serial line.

[0186] FIG. 9 is a flowchart of a method performed by a slave device performing communication between devices of a communication system in accordance with the present disclosure. Referring to FIG. 9, a communication method performed by the slave device may include receiving a clock and data (S210), acquiring a clock and data sequence included in an RF signal (S220), and performing decoding (S230).

[0187] The method performed by the slave device may further include searching for a reception start point based on a frame block (S240), determining a first bit of a second frame block (S245), and setting or changing an operation mode based on a sequence of the second frame block (S250).

[0188] In step S210, the RF signal including the clock and data may be received from the master device through the one serial line. In step S220, the clock and the data sequence included in the received RF signal may be acquired. In step S230, decoding may be performed to restore a data set from the acquired data sequence.

[0189] The step S230 may include restoring the data sequence to data of a second bit set prior to performing FEC (S231) and restoring the data of the second bit set to data of a first bit set (S232).

[0190] In step S240, a reception start point may be searched for based on the frame block of the data sequence. In step S245, it may be determined whether the first bit of the second frame block following the frame block is 1.

[0191] In step S250, the operation mode of the slave device may be set or changed based on a sequence of the second frame block. The step S250 may include controlling a first operation of the slave device based on a first command (S251) and controlling a second operation of the slave device based on a second command (S252). When the first bit of the second frame block is 1, the step S251 may be performed. On the other hand, when the first bit of the second frame block is 0, the step S252 may be performed.

[0192] When the first bit of the second frame block is 1, the operation mode of the slave device may be set or changed by the first command corresponding to the subsequent bits in step S251. Operations relating to switching between a transmission mode and a reception mode of the slave device, a power level, and a beam direction may be controlled based on the first command.

[0193] When the first bit of the second frame block is 0, the operation mode of the slave device may be set or changed by the second command corresponding to the subsequent bits in step S252. The slave device may be controlled to operate in any one of a read mode, a write mode, a read and write mode, or a read and response mode based on the second command.

[0194] So far, a communication system performing communication between devices, and communication methods performed by a master device and a slave device that perform communication between the devices in the communication system have been described. Hereinafter, technical effects of the communication system performing communication between devices, and the communication methods performed by the master device and the slave device that perform communication between the devices in the communication system will be described, but are not limited thereto.

[0195] According to at least one embodiment of the present disclosure, a master device and a slave device may simultaneously transmit and receive data and clock through a single wire, which may enable synchronization of data communication between devices in an asynchronous system.

[0196] According to at least one embodiment of the present disclosure, a reception start point may be searched for based on a frame block representing the start of data after reception of a clock, thereby enabling synchronization of data communication between devices in an asynchronous system.

[0197] According to at least one embodiment of the present disclosure, an operation mode of a slave device may be set or changed based on a sequence of a second frame block subsequent to a frame block, thereby enabling synchronization and operation mode control of the slave device.

[0198] According to at least one embodiment of the present disclosure, the same clock may be used between a master device and a slave device and a data signal may be included in a clock signal, thereby suppressing shifting of transmitted data and improving transmission speed.

[0199] According to at least one embodiment of the present disclosure, the same clock may be used between the master device and the slave device to prevent shifting of data transmitted based on the clock signal, and improve transmission speed.

[0200] various state configurations may be transmitted in advance before data transmission from a master chip to a slave chip, thereby optimizing the state configuration and operation of the slave chip.

[0201] According to at least one embodiment of the present disclosure, a problem of taking too long to change a state of a slave device based on data in an existing access manner may be solved by constructing a short command.

[0202] According to at least one embodiment of the present disclosure, link robustness may be further increased by receiving a short command having a short data length from a master chip.

[0203] According to at least one embodiment of the present disclosure, a DC problem of an RF receiver may be avoided by designing a DC of an RF transmitter not to change when Tx power is changed.

[0204] According to at least one embodiment of the present disclosure, a DC effect may be removed by using a programmable amount of preamble data and 8b / 10b coding to suppress a DC problem during data transmission.

[0205] Further scope of applicability of the present disclosure will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, such as the preferred embodiment of the disclosure, are given by way of illustration only, since various changes and modifications within the spirit and scope of the disclosure will be apparent to those skilled in the art.

[0206] In relation to the present disclosure, a control operation for a communication method and communication system between a master device and a slave device may be performed by software, firmware, or a combination thereof. The configuration of performing the control operation for the communication method and communication system between the master device and the slave device may be implemented as computer readable codes in a program recording medium. The computer-readable medium may include all types of recording devices each storing data readable by a computer system. Examples of the computer-readable medium include a hard disk drive (HDD), a solid state disk (SSD), a silicon disk drive (SDD), a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device and the like, and may also be implemented in the form of a carrier wave (e.g., transmission over the Internet). The computer may also include a controller of a terminal or vehicle, namely, a processor. Therefore, the detailed description should not be limitedly construed in all of the aspects, and should be understood to be illustrative. The scope of the present disclosure should be determined by rational interpretation of the appended claims, and all changes within the scope of equivalents of the present disclosure are included in the scope of the present disclosure.

Claims

1.A communication system that performs communication between devices, the system comprising:a master device configured to transmit a clock and data through one serial line; anda slave device configured to receive the clock and the data from the master device through the one serial line,wherein the master device transmits the clock divided from a reference clock and the data to the slave device, andthe slave device receives the clock, searches for a reception start point based on a frame block representing a start of the data, and sets or changes an operation mode based on a sequence of a second frame block subsequent to the frame block.2.The communication system of claim 1, wherein the operation mode of the slave device is set or changed, when a first bit of the second frame block is 1, by a first command corresponding to subsequent bits, andoperations relating to switching between a transmission mode and a reception mode of the slave device, a power level, and a beam direction are controlled based on the first command.3.The communication system of claim 2, wherein the operation mode of the slave device is set or changed, when a first bit of the second frame block is 0, by a second command corresponding to subsequent bits, andthe slave device is controlled to operate any one of a read mode, a write mode, or a read and response mode based on the second command.4.The communication system of claim 1, wherein the frame block representing the start and the second frame block constitute a plurality of command frames,learning frames are disposed between the command frames, andthe command frames and the learning frames constitute a trigger sequence.5.The communication system of claim 4, wherein the frame block representing the start, the second frame block, a parameter block, a payload block, and a stop block representing a stop of the data constitute at least one normal frame,learning frames are disposed at a position before the frame block and at a position after the stop block, andthe normal frame and the learning frames constitute a normal sequence.6.The communication system of claim 1, wherein the master device transmits the RF signal of a first frequency band, including On-Off Keying (OOK) coded data, and a clock signal of a second frequency band including the reference clock to the slave device, andthe first frequency band is set to a higher frequency than the second frequency band.7.The communication system of claim 1, wherein the master device comprises:a first radio frequency (RF) transceiver configured to transmit an RF signal including the reference clock and the data; anda first modem operably coupled to the first RF transceiver and configured to transmit the data to the first RF transceiver, andthe first modem comprises a transmission unit configured to output a transmission signal and a reception unit configured to receive a reception signal.8.The communication system of claim 7, wherein the master device further comprises a first diplexer configured to receive the clock and the data from the first RF transceiver and to separate the clock and the data, andthe first diplexer transfers the clock and the data to the reception unit through the first RF transceiver.9.The communication system of claim 8, wherein the master device further comprises:a phase-locked loop (PLL) configured to output the clock by controlling an output signal using a phase difference between an input signal and a signal fed back from the output signal; anda divider configured to generate the clock by dividing the reference clock output from the PLL, andthe clock output from the divider is transferred to the first modem and the first diplexer.10.The communication system of claim 7, wherein the transmission unit comprises:a transmitter configured to receive data output from a processor and transmit the data;a first encoder configured to convert the output data of a first bit set into data of a second bit set;a second encoder configured to convert the data of the second bit set into forward error correction (FEC)-performed data; anda serializer configured to sequentially transmit the converted data.11.The communication system of claim 10, wherein the reception unit comprises:a de-serializer configured to parallelize the converted FEC-performed data sequentially received from the first RF transceiver;a first decoder configured to restore the converted data into the data of the second bit set before the FEC is performed;a second decoder configured to restore the data of the second bit set into the data of the first bit set; anda receiver configured to receive the data of the first bit set to transfer to the processor.12.The communication system of claim 11, wherein the first encoder is configured to perform encoding such that 8-bit data is mapped to a 10-bit symbol in order to suppress a direct-current (DC) offset during data transmission,the second encoder is configured to perform encoding by a 2 / 3 FEC method of converting 2-bit input data into 3-bit output data,the first decoder is configured to perform decoding by a 2 / 3 FEC method of converting 3-bit input data into 2-bit output data, andthe second decoder is configured to perform decoding such that the 10-bit symbol is de-mapped into the 8-bit data.13.The communication system of claim 7, wherein the slave device comprises:a second RF transceiver configured to receive an RF signal including the reference clock restored from the clock and the data; anda second modem operably coupled to the second RF transceiver and configured to obtain the data from the RF signal received from the second RF transceiver,an envelope of the RF signal is converted into input data that is input to the second modem, andthe second modem comprises a transmission unit configured to output a transmission signal and a reception unit configured to receive a reception signal.14.The communication system of claim 13, wherein the slave device further comprises a second diplexer configured to receive the clock and the data from the second RF transceiver and to separate the clock and the data, andthe second diplexer transfers the clock and the data to the reception unit through the second RF transceiver.15.The communication system of claim 14, wherein the slave device comprises:a phase-locked loop (PLL) configured to output the reference clock by controlling an output signal using a phase difference between the clock as an input signal and a signal fed back from the output signal; anda divider configured to generate the clock by dividing the reference clock output from the PLL,the reference clock output from the PLL is transferred to the second RF transceiver, andthe clock output from the divider is transferred to the second modem.16.The communication system of claim 13, wherein the transmission unit comprises:a transmitter configured to receive data output from a processor and transmit the data;a first encoder configured to convert the output data of a first bit set into data of a second bit set;a second encoder configured to convert the data of the second bit set into forward error correction (FEC)-performed data; anda serializer configured to sequentially transmit the converted data.17.The communication system of claim 16, wherein the reception unit comprises:a de-serializer configured to parallelize the converted FEC-performed data sequentially received from the second RF transceiver;a first decoder configured to restore the converted data into the data of the second bit set before the FEC is performed;a second decoder configured to restore the data of the second bit set into the data of the first bit set; anda receiver configured to receive the data of the first bit set to transfer to the processor.18.The communication system of claim 17, wherein the first encoder is configured to perform encoding such that 8-bit data is mapped to a 10-bit symbol in order to suppress a direct-current (DC) offset during data transmission,the second encoder is configured to perform encoding by a 2 / 3 FEC method of converting 2-bit input data into 3-bit output data,the first decoder is configured to perform decoding by a 2 / 3 FEC method of converting 3-bit input data into 2-bit output data, andthe second decoder is configured to perform decoding such that the 10-bit symbol is de-mapped into the 8-bit data.19.The communication system of claim 13, wherein the first transceiver and the transceiver generates digital data in which a clock signal having second pulses formed in a second period shorter than a first period is applied to an inside of a data signal having first pulses formed in the first period, andtransfers the RF signal to the slave device by including the digital data in the RF signal.20.The communication system of claim 19, wherein the first transceiver and the transceiver comprises:a first element to which the data signal and the clock signal are input;a second element connected in parallel to the first element and configured to receive the data signal and the clock signal; anda first resistor and a second resistor connected to a first output end and a second output end of the second element.

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