Display panel and display device

Abstract

The present application discloses a display panel and a display device. A non-display area of the display panel comprises at least one arc angle area; the non-display area is provided with a first power bus, the first power bus passes through the at least one arc angle area, the first power bus comprises a first bus portion and a second bus portion, the first bus portion is provided on one side of a display area and electrically connected to the second bus portion, and the first bus portion is configured to connect to a power supply; a plurality of power signal lines are further provided in a display area, and the power signal lines are electrically connected between the second bus portion and the first bus portion of the at least one arc angle area. The current in the second bus portion of the arc angle area is shunted into the display area by means of the power signal lines provided in the display area, thereby effectively reducing the current density on the second bus portion at the arc angle area, and reducing heating of a screen body caused by excessive current at the arc angle area. The first power bus is connected to the power signal lines, thereby reducing the voltage loss on the first power bus, and facilitating reduction of the power consumption of the display panel.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 14, 2023, with application number 202310871319.0, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a display panel and a display device. Background Art

[0003] With the rapid development of organic light-emitting diode display panels, consumers have increasingly higher requirements for the appearance of display devices. Many display panels have changed from the traditional square shape to the popular irregular structure, which makes the display panels prone to heat generation.

[0004] Summary of the Invention

[0005] The present application provides a display panel and a display device to at least reduce the current density on the first power bus at the arc corner of the display panel, reduce the heating of the screen, reduce the voltage drop of the power signal on the transmission path, and reduce the power consumption and temperature of the display panel.

[0006] According to one aspect of the present application, a display panel is provided, comprising a display area and a non-display area surrounding the display area; the non-display area comprises at least one arc corner area;

[0007] A first power bus is provided in the non-display area. The first power bus surrounds at least a portion of the display area and passes through at least one of the arc corner areas. The first power bus includes a first bus portion and a second bus portion. The first bus portion is provided on one side of the display area and is electrically connected to the second bus portion. The first bus portion is used to connect to a power source.

[0008] A plurality of power signal lines are further provided in the display area, and the power signal lines are electrically connected between the second bus portion and the first bus portion in at least one arc angle area.

[0009] According to another aspect of the present application, a display device is provided, comprising the display panel described above.

[0010] The display panel and display device provided in the embodiments of the present application have a non-display area including at least one arc-angle area; a first power bus is provided in the non-display area, the first power bus is provided around at least a portion of the display area, and the first power bus passes through at least one arc-angle area, the first power bus includes a first bus portion and a second bus portion, the first bus portion is provided on one side of the display area and electrically connected to the second bus portion, and the first bus portion is used to connect to a power source; a plurality of power signal lines are also provided in the display area, the power signal lines are electrically connected between the second bus portion and the first bus portion in at least one arc-angle area. The power signal lines provided in the display area shunt current in the second bus portion to the display area, and then the shunt current is converged to the first bus portion by the power signal lines, effectively reducing the current density on the second bus portion in the arc-angle area, reducing screen heating caused by excessive current in the arc-angle area, and lowering the temperature of the display panel. At the same time, the first power bus is connected to the power signal line, and the resistance of the overall structure of the first power bus and the power signal line is reduced compared to the resistance of the first power bus, thereby reducing voltage loss during power signal transmission, reducing power consumption of the display panel, and further reducing the temperature of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0012] FIG2 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0013] FIG3 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0014] FIG4 is a schematic diagram of the layout of the display area of ​​a display panel provided in an embodiment of the present application;

[0015] FIG5 is a current simulation diagram of a display area of ​​a display panel provided by an embodiment of the present application;

[0016] FIG6 is a cross-sectional view of a display panel provided in an embodiment of the present application;

[0017] FIG7 is another cross-sectional view of a display panel provided in an embodiment of the present application;

[0018] FIG8 is a schematic diagram of the layout of the arc corner region in the non-display area of ​​the display panel provided by an embodiment of the present application;

[0019] FIG9 is a current simulation diagram of an arc angle region in a non-display area of ​​a display panel provided by an embodiment of the present application;

[0020] FIG10 is a schematic diagram of the layout of the side area in the non-display area of ​​the display panel provided in an embodiment of the present application;

[0021] FIG11 is a current simulation diagram of a side area of ​​a non-display area of ​​a display panel provided by an embodiment of the present application;

[0022] FIG12 is a schematic diagram of the layout of the lower frame area in the non-display area of ​​the display panel provided in an embodiment of the present application;

[0023] FIG13 is a current simulation diagram of the lower frame area in the non-display area of ​​the display panel provided by an embodiment of the present application;

[0024] FIG14 is a schematic structural diagram of a pixel circuit in a display panel provided in an embodiment of the present application;

[0025] FIG15 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0026] FIG16 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] As described in the background art, in the high-brightness mode of the display panel, the current in the display panel is large, which easily generates heat. The applicant has found that the reason for this is that the current concentration in the arc angle area of ​​the display panel is high, and the current density is large, resulting in a large amount of heat generation. For example, the display panel includes a display area and a non-display area surrounding the display area. The display area is provided with a light-emitting device, and the non-display area is provided with a cathode wiring. The current flowing through all the light-emitting devices in the display area is converged from the cathode to the cathode wiring in the non-display area, and finally flows back to the power chip. The current density in the arc angle area of ​​the non-display area, especially the arc angle area closer to the power chip, is the largest, resulting in a large amount of heat generation, making the temperature of the display panel higher.

[0028] An embodiment of the present application provides a display panel. FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present application. Referring to FIG1 , the display panel includes: a display area AA and a non-display area NAA surrounding the display area AA; the non-display area NAA includes at least one arc angle area O1;

[0029] A first power bus 10 is provided in the non-display area NAA. The first power bus 10 surrounds at least a portion of the display area AA and passes through at least one arc angle area 01. The first power bus 10 includes a first bus portion 11 and a second bus portion 12. The first bus portion 11 is provided on one side of the display area AA and is electrically connected to the second bus portion 12. The first bus portion 11 is used to connect to the power source 1.

[0030] A plurality of power signal lines V are further provided in the display area AA. The power signal lines V are electrically connected between the second bus portion 12 and the first bus portion 11 of at least one arc angle region 01 .

[0031] For example, the display panel also includes a light-emitting device, which is arranged in the display area AA to realize the display of the display panel. The non-display area NAA can be arranged around the display area AA. Exemplarily, the display area AA and the non-display area NAA are both rounded rectangles, and the non-display area NAA includes four arc angle areas 01, wherein two arc angle areas 01 are close to the upper frame area of ​​the non-display area NAA, and the other two arc angle areas 01 are close to the lower frame area of ​​the non-display area NAA. In other embodiments, the display panel can be other special-shaped display panels, which can include only one, two or more arc angle areas 01, and this embodiment is not specifically limited here. In this embodiment, the case where the first power bus 10 is only arranged around part of the display area AA is exemplified. In other embodiments of the present application, the first power bus 10 can surround the entire display area AA.

[0032] The first bus portion 11 is arranged in the non-display area NAA and is arranged close to the power supply 1. For example, the power supply 1 is arranged in the lower frame area in the non-display area NAA, and the first bus portion 11 is arranged in the lower frame area. The power supply 1 can be used to provide the power signal required by the cathode of the light-emitting device. The first power bus 10 can be a cathode trace for transmitting the cathode signal of the light-emitting device. The cathode of at least part of the light-emitting device is connected to the second bus portion 12 in the first power bus 10. The second bus portion 12 is connected to the first bus portion 11 through the power signal line V in the display area AA. The current of the light-emitting device is converged to the first bus portion 11 after passing through the second bus portion 12 connected to the light-emitting device and the power signal line V in the display area AA, and then transmitted to the power supply 1, so as to realize the current on the second bus portion 12 being diverted to the display area AA. It is worth noting that the power signal line V can be set for the entire screen, or it can be set only in the display area AA corresponding to the arc angle area 01. No specific limitation is made here.

[0033] In this embodiment, the display panel uses power signal lines provided in the display area to shunt current from the second bus portion into the display area. The power signal lines then converge the shunt current back into the first bus portion, effectively reducing the current density on the second bus portion in the corner region, alleviating screen heating caused by excessive current in the corner region and lowering the temperature of the display panel. Furthermore, the first power bus is connected to the power signal lines, and the overall resistance of the first power bus and power signal lines is lower than the resistance of the first power bus. This reduces voltage loss during power signal transmission, lowers power consumption of the display panel, and further reduces the temperature of the display panel.

[0034] 1 , for example, the non-display area NAA includes a first arc angle region 011 and a second arc angle region 012 , and a distance between the first arc angle region 011 and the first bus portion 11 is greater than a distance between the second arc angle region 012 and the first bus portion 11 ;

[0035] At least the second bus portion 12 in the second arc angle region 012 is electrically connected to the first bus portion 11 through a power signal line.

[0036] The distance between the first arc angle region 011 and the first bus portion 11 may refer to the distance between the edge of the first arc angle region 011 closest to the first bus portion 11 and the first bus portion 11. The distance between the second arc angle region 012 and the first bus portion 11 may refer to the distance between the edge of the second arc angle region 012 closest to the first bus portion 11 and the first bus portion 11.

[0037] As described above, the current in the display area AA ultimately flows through the first bus portion 11 to the power source 1. Therefore, the current density in the corner region 01 closer to the first bus portion 11 is greater, which can easily lead to excessive temperature in the display panel. Therefore, a second corner region 012 with a higher current density is electrically connected to the first bus portion 11 via a power signal line V. This allows the current in the second corner region 012 to be shunted through multiple power signal lines V, reducing the current density in the second corner region 012. To further reduce the current density in the second corner region 012, the first corner region 011 can also be shunted through multiple power signal lines V. This prevents excessive current density in the first corner region 011 and reduces the current flowing from the first corner region 011 to the second corner region 012, thereby lowering the current density in the corner region 012.

[0038] Figure 2 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application. Compared with the display panel shown in Figure 1, the display panel shown in Figure 2 has a larger area surrounding the display area AA. Referring to Figures 1 and 2, for example, the first bus portion 11 and the second bus portion 12 are an integrated structure.

[0039] The first bus portion 11 and the second bus portion 12 are an integrated structure, which can simplify the manufacturing process and does not require an additional conductive structure to connect the first bus portion 11 and the second bus portion 12 .

[0040] In other embodiments of the present application, the first bus portion 11 and the second bus portion 12 may also be a non-integrated structure, and the two may be electrically connected in the non-display area NAA by direct electrical connection or overlapping.

[0041] Figure 3 is a structural schematic diagram of another display panel provided in an embodiment of the present application. Referring to Figure 3, for example, the non-display area NAA also includes a side area adjacent to the arc angle area 01, and the second bus portion 12 of at least one side area is electrically connected to the first bus portion 11 through a power signal line.

[0042] Exemplarily, the non-display area NAA may include four side areas, namely the left frame area, the right frame area, the upper frame area and the lower frame area. The second bus portion in at least one of the left frame area, the right frame area, the upper frame area and the lower frame area may be electrically connected to the first bus portion 11 through a plurality of power signal lines. The second bus portions 12 of the multiple side areas may also have a certain degree of current concentration. The side areas shunt the current on the second bus portions 12 of the side areas through a plurality of power signal lines to reduce the current density of the second bus portions 12 at the side areas and reduce the overall temperature of the display panel. At the same time, after the side areas are shunted, the current density of the second bus portion 12 flowing into the arc angle area 01 through the side areas is reduced, which is beneficial to reducing the temperature at the arc angle area. The second bus portion 12 of the side areas is electrically connected to the first bus portion 11 through a plurality of power signal lines, which can reduce the voltage drop generated when the second bus portion 12 transmits the power signal, thereby reducing power consumption and improving display uniformity.

[0043] Continuing with reference to Figure 3, for example, the power signal line includes a first power signal line V1 and a second power signal line V2, the first power signal line V1 extends along a first direction X, the second power signal line V2 extends along a second direction Y, and the first direction X and the second direction Y intersect; the first power signal line V1 is electrically connected to the second power signal line V2; in the second direction Y, the first bus portion 11 is located on one side of the display area AA; the first bus portion 11 is electrically connected to the second power signal line V2; the second bus portion 12 in the arc angle area 01 is electrically connected to the first power signal line V1.

[0044] Exemplarily, the first direction X is the row direction of the light-emitting devices arranged in the display panel, and the second direction Y is the column direction of the light-emitting devices. The multiple power signal lines include multiple first power signal lines V1 arranged along the second direction Y and multiple second power signal lines V2 arranged along the first direction X. Any first power signal line V1 is electrically connected to any second power signal line V2. Because the second power signal lines V2 extend along the second direction Y, the first bus portion 11 is located on one side of the display area AA in the second direction Y, that is, the first bus portion 11 is located on one side of the second power signal line V2. Therefore, by electrically connecting the second bus portion 12 of the arc angle region 01 to the first power signal line V1, the first power signal line V1 to the second power signal line V2, and the second power signal line V2 to the first bus portion 11, the current in the arc angle region 01 can be diverted via the multiple first power signal lines V1 to the multiple second power signal lines V2, and the multiple second power signal lines V2 then converge the current to the first bus portion 11.

[0045] The multiple first power signal lines V1 and the multiple second power signal lines V2 shunt the current in the corner region 01, reducing the current density there and alleviating screen heating caused by excessive current flow. Furthermore, the multiple first power signal lines V1 and the multiple second power signal lines V2 form a mesh structure. This mesh structure has lower resistance than a structure with power signal lines extending only in the first direction X or the second direction Y. This effectively reduces voltage loss during power signal transmission, thereby lowering the power consumption of the display panel.

[0046] 3 , for example, the second bus portion 12 of at least one side region is electrically connected to the first power signal line V1 .

[0047] The second bus portion 12 in the side area shunts the current from the second bus portion 12 in the side area to the display area AA via multiple first power signal lines V1, and then converges the current to the first bus portion 11 via multiple second power signal lines V2. Compared to shunting the current from the second bus portion 12 in the corner area 01 only via the first power signal lines V1 and the second power signal lines V2, the second bus portion 12 in the side area also shuns the current via the first power signal lines V1 and the second power signal lines V2. This further reduces the current density in the corner area 01 and alleviates screen heating caused by excessive current in the corner area 01. Furthermore, the current shunting in the side area effectively reduces the current density in the side area, thereby alleviating heating in the side area and extending the life of the display panel.

[0048] Continuing to refer to Figure 3, for example, the display area AA includes a first sub-display area AA1 and a second sub-display area AA2, and the second sub-display area AA2 is located on the side of the first sub-display area AA1 away from the first bus portion 11; the density of the first power signal line V1 in the second sub-display area AA2 is less than the density of the first power signal line V1 in the first sub-display area AA1.

[0049] In the non-display area NAA, the closer the second bus portion 12 is to the first bus portion 11 in the second direction Y, the greater the current density. Therefore, the density of first power signal lines V1 in the display area AA corresponding to the second bus portion 12 with higher current density needs to be higher. This ensures that the current in the second bus portion 12 with higher current density is shunted via a larger number of first power signal lines V1, thereby improving the shunting effect. At the same time, the density of first power signal lines V1 in the display area AA corresponding to the second bus portion 12 with lower current density is lower. This not only achieves the shunting effect, but also reduces the number of first power signal lines V1 in the display panel, thereby reducing wiring difficulty.

[0050] 3 , for example, along the direction from the second sub display area AA2 to the first sub display area AA1 , the density of the first power signal lines V1 gradually increases.

[0051] As the current density of the second power supply headquarters 12 in the non-display area NAA gradually increases from the second sub-display area AA2 toward the first sub-display area AA1, the density of the first power signal lines V1 decreases as the second sub-display area AA2 moves further away from the first sub-display area AA1. A smaller density of first power signal lines V1 can achieve the desired current shunting effect, eliminating the need for excessive first power signal lines V1. As the density of the first power signal lines V1 gradually increases from the second sub-display area AA2 toward the first sub-display area AA1, this ensures the desired current shunting effect at the second power supply headquarters 12 at multiple locations in the non-display area NAA while also reducing the number of first power signal lines V1 in the display panel and simplifying wiring.

[0052] FIG4 is a schematic diagram of the layout of the display area of ​​the display panel shown in FIG3 , and FIG5 is a current simulation diagram of the display area of ​​the display panel shown in FIG3 . Referring to FIG3 , FIG4 and FIG5 , for example, the display panel includes a substrate and an array film layer on the substrate, and the array film layer includes a plurality of stacked metal layers;

[0053] The first power signal line V1 and the second power signal line V2 are disposed in at least one metal layer.

[0054] The substrate can be a flexible substrate, such as a plastic substrate with excellent heat resistance and durability made of polyvinyl ether phthalate, polyarylate, polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), cycloolefin polymer (COP), cellulose acetate propionate (CAP), polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyallyl ester, cellulose triacetate (TAC), etc.; it can also be a rigid substrate, such as a glass substrate. The display panel includes a light-emitting device, and the array film layer may include a driving circuit layer arranged between the substrate and the light-emitting device, in which a pixel circuit is arranged to drive the light-emitting device to emit light. The array film layer includes multiple metal layers stacked to form the source and drain of the transistor included in the pixel circuit. The first power signal line V1 and the second power signal line V2 can be located in the same metal layer of the array film layer, or they can be located in two metal layers respectively. The first power signal line V1 and the second power signal line V2 are disposed in at least one metal layer of the array film layer. Existing metal layers in the display panel can be used to form the first power signal line V1 and the second power signal line V2, eliminating the need for additional metal layers for the first and second power signal lines. This reduces the thickness of the display panel and simplifies the structure of the display panel. Alternatively, at least one additional metal layer can be added to the existing array film layer, with the first power signal line V1 and the second power signal line V2 disposed in the additional at least one metal layer.

[0055] In this embodiment, it is exemplified that the first power signal line V1 and the second power signal line V2 are located in different layers and are connected through a via 2 .

[0056] Figure 6 is a cross-sectional view of a display panel provided in an embodiment of the present application. Figure 6 is a cross-sectional view obtained by cutting along BB' in Figure 3. Referring to Figure 3 and Figure 6, for example, the metal layer includes a light-shielding layer 21, and the light-shielding layer 21 is located between the active layer 22 and the substrate 23 in the array film layer. The first power signal line V1 and the second power signal line V2 are located in the light-shielding layer 21.

[0057] The array film layer also includes an active layer 22, which can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. For example, the orthographic projection of the light-shielding layer 21 on the substrate at least partially covers the orthographic projection of the active layer 22 on the substrate. The active layer 22 includes the channels of the transistors in the display panel. When the channels of the transistors are exposed to light, the leakage current of the transistors increases, affecting the electrical properties of the transistors. By providing the light-shielding layer 21, the leakage current of the transistors in the display panel can be reduced, ensuring good electrical properties of the transistors.

[0058] The first power signal line V1 and the second power signal line V2 provided in the light shielding layer 21 can serve as a light shielding structure. Alternatively, the first power signal line V1, the second power signal line V2, and the light shielding structure can be provided in the light shielding layer 21. The first power signal line V1 and the second power signal line V2 can be provided within a single light shielding layer 21, which helps reduce the thickness of the display panel and ensures a relatively thin and lightweight display panel. In this embodiment, the first power signal line V1 and the second power signal line V2 provided in the light shielding layer 21 serve as a light shielding structure, and both are provided within a single light shielding layer 21.

[0059] Figure 7 is another cross-sectional view of the display panel provided in an embodiment of another application. Figure 7 is a cross-sectional view obtained by cutting along BB' in Figure 3. Referring to Figures 3 and 7, for example, the first power signal line V1 is located in the first metal layer 24, the second power signal line V2 is located in the second metal layer 25, and the second metal layer 25 is located on the side of the first metal layer 24 close to the substrate 23.

[0060] The metal layer includes a first metal layer 24 and a second metal layer 25 that are stacked, and the first metal layer 24 and the second metal layer 25 are insulated. The material of the first metal layer and the second metal layer can be Mo. The display panel includes a pixel circuit, the pixel circuit includes a storage capacitor and at least two transistors, the second metal layer 25 can include a plate of the storage capacitor, and the first metal layer 24 can include the source and. In order to simplify the wiring design of a single metal layer, the first power signal line V1 and the second power signal line V2 can be set in different film layers, such as the first power signal line V1 is located in the first metal layer 24, and the second power signal line V2 is located in the second metal layer 25. When the first power signal line V1 and the second power signal line V2 are located in different layers, they are electrically connected by punching, or transferred through other conductive structures, which is not limited here.

[0061] 7 , for example, the display panel further includes a first electrode Anode and a second electrode. The second electrode is disposed on a side of the first electrode away from the array film layer, and the second bus portion is electrically connected to the second electrode.

[0062] The first electrode Anode is the anode of the light-emitting device, and the second electrode is the cathode of the light-emitting device. Both the anode and the cathode may include a multilayer structure of ITO, Ag, and ITO. The first electrode Anode may be a standalone structure, with multiple first electrodes insulated from each other, and one first electrode Anode corresponds to one light-emitting device. The second electrode may be a full-surface structure, connected to the second bus portion, and used to receive the cathode signal transmitted on the second bus portion.

[0063] For example, the first power bus V and the first electrode Anode are arranged in the same layer, and the first power bus V is insulated from the first electrode Anode; thus, the first power bus V and the first electrode Anode can be prepared in the same preparation process, saving the process steps of display panel preparation and simplifying the display panel preparation process.

[0064] FIG8 is a schematic layout diagram of an arc angle region in a non-display area of ​​the display panel shown in FIG3 , FIG9 is a current simulation diagram of an arc angle region in a non-display area of ​​the display panel shown in FIG3 , FIG10 is a schematic layout diagram of a side region in a non-display area of ​​the display panel shown in FIG3 , and FIG11 is a current simulation diagram of a side region in a non-display area of ​​the display panel shown in FIG3 . The arrows in FIG9 and FIG11 indicate the direction of the current. With reference to FIG3 , FIG8 , FIG9 , FIG10 and FIG11 , the display panel further comprises a first adapter line L1, which is located in a third metal layer, and the third metal layer is located on a side of the first metal layer away from the substrate (for example, with respect to the cross-sectional view of the display panel shown in FIG7 , the third metal layer is between the layer where the first electrode is located and the first metal layer, and the third metal layer is not shown in FIG7 );

[0065] A first end of the first adapter line L1 is electrically connected to the second bus portion 12 , and a second end of the first adapter line L1 is electrically connected to the first power signal line V1 .

[0066] The materials of the third metal layer and the first adapter line L1 can both be Ti / Al / Ti. The first adapter line L1 is used to connect the second bus portion 12 located in the non-display area NAA and the first power signal line V1 located in the display area AA to transmit the current on the second bus portion 12 to the first power signal line V1. The second bus portion 12 in the arc angle area O1 is electrically connected to the first power signal line V1 through the first adapter line L1, as shown in Figure 6. The second bus portion 12 in the side area can also be electrically connected to the first power signal line V1 through the first adapter line L1, as shown in Figure 8. The first adapter line L1 is located in the third metal layer, which eliminates the need for an additional film layer for the first adapter line L1, thereby reducing the thickness of the display panel. When the first power bus is provided in the same layer as the first electrode, the first end of the first adapter line L1 is electrically connected to the second bus portion 12 by punching, and the second end of the first adapter line L1 is electrically connected to the first power signal line V1 located in the first metal layer by punching.

[0067] Continuing to refer to FIG. 3 , for example, the third metal layer is the metal layer closest to the first electrode among the multiple metal layers.

[0068] Because the first adapter line L1 is located in the third metal layer, the first power bus and the first electrode are arranged on the same layer, and the first adapter line L1 needs to be connected to the second power headquarters 12 in the first power bus. Therefore, the third metal layer is the metal layer closest to the layer where the first electrode is located among the multiple metal layers, that is, the distance between the film layer where the first adapter line L1 is located and the film layer where the second power headquarters 12 is located is shorter, which can facilitate the connection between the first adapter line L1 and the second power headquarters 12. For example, the two are connected by punching, which can reduce the difficulty of punching and improve the accuracy of punching.

[0069] Continuing to refer to FIG. 3 , for example, the first metal layer is adjacent to the third metal layer.

[0070] The first and third metal layers are adjacent metal layers, insulated by an insulating layer to prevent signal crosstalk. The proximity of the first and third metal layers shortens the distance between the film layer containing the first adapter cable L1 and the film layer containing the second power supply headquarters 12, facilitating connection between the first adapter cable L1 and the second power supply headquarters 12. For example, connecting the two via a punched hole can reduce drilling difficulty and improve drilling accuracy.

[0071] Figure 12 is a schematic diagram of the layout of the lower border area in the non-display area of ​​the display panel shown in Figure 3, and Figure 13 is a current simulation diagram of the lower border area in the non-display area of ​​the display panel shown in Figure 3. Referring to Figures 3, 12 and 13, for example, the display panel also includes a second adapter line L2, and the second adapter line L2 is arranged on the same layer as the first power bus. The first end of the second adapter line L2 is connected to the second power signal line V2, and the second end of the second adapter line L2 is connected to the first bus portion 11.

[0072] The second adapter line L2 is used to connect the second power signal line V2 to the first bus portion 11. The second adapter line L2 is arranged on the same layer as the first power bus, which can avoid additional drilling or setting of conductive structures when connecting the second adapter line L2 to the first bus portion 11. The second adapter line L2 can be located in the film layer where the first electrode, that is, the anode, is located, and drains the current in the display area to the first bus portion 11, so as to ultimately return the current to the power chip. In this embodiment, the second adapter line L2 and the second power signal line V2 are exemplarily shown to be located on different metal layers and the two are connected by via 2.

[0073] Figure 14 is a structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application. Referring to Figures 3, 12, 13 and 14, for example, the non-display area NAA also includes a second power bus 3 located between the first bus portion 11 and the display area AA. The second power bus 3 is located in at least one metal layer, and the second adapter line L2 is insulated from the second power bus 3.

[0074] The second power bus 3 transmits a first power signal VDD to the anode of the light-emitting device, and the first power bus transmits a second power signal VEE to the cathode of the light-emitting device. The second power bus 3 can be provided on the same layer as the second adapter line L2, and the second adapter line L2 connects to the first bus portion 11 across the second power bus 3.

[0075] Figure 15 is a structural schematic diagram of another display panel provided in an embodiment of the present application. Referring to Figure 15, for example, the non-display area NAA includes a first side area 31, a second side area 32, a third side area 33 and a fourth side area 34. The first side area 31 and the second side area 32 are relatively arranged in the second direction Y, the third side area 33 and the fourth side area 34 are relatively arranged in the first direction X, and the first bus portion 11 is arranged in the first side area 31.

[0076] The first side region 31 may be the lower frame region of the non-display area NAA, the second side region 32 may be the upper frame region of the non-display area NAA, the third side region 33 may be the left frame region of the non-display area NAA, and the fourth side region 34 may be the right frame region of the non-display area NAA. A power chip that provides the first power signal and the second power signal is generally disposed in the lower frame region of the non-display area NAA. Therefore, the first bus portion 11 is also disposed in the first side region 31 to facilitate connection with the power chip.

[0077] Continuing with FIG15 , for example, the non-display area NAA includes a first arc angle region and a second arc angle region. The first arc angle region includes a first lower arc angle region and a second lower arc angle region. The first lower arc angle region is adjacent to the first side region 31 and the third side region 33 , respectively. The second lower arc angle region is adjacent to the first side region 31 and the fourth side region 34 , respectively.

[0078] The second arc angle area includes a first upper arc angle area and a second upper arc angle area. The first upper arc angle area is adjacent to the second side area 32 and the third side area 33 respectively. The second upper arc angle area is adjacent to the second side area 32 and the fourth side area 34 respectively.

[0079] As described above, the distance between the first arc angle region and the first bus portion 11 is greater than the distance between the second arc angle region and the first bus portion 11 .

[0080] Continuing to refer to FIG. 15 , for example, the second bus portion 12 in the first lower arc angle region and the second bus portion 12 in the second lower arc angle region are connected to the same first power signal line V1 .

[0081] The second bus portion 12 connecting the first lower arc angle region and the second bus portion 12 connecting the second lower arc angle region can connect to multiple first power signal lines V1. Each first power signal line corresponding to the first lower arc angle region or the second lower arc angle region has one end connected to the second bus portion 12 in the first lower arc angle region via a first adapter line L1, and the other end connected to the second bus portion 12 in the second lower arc angle region via another first adapter line L1. The second bus portion 12 in the first lower arc angle region and the second bus portion 12 in the second lower arc angle region are connected to the same first power signal line V1. This can reduce the number of first power signal lines V1 while ensuring the shunting effect of the second bus portion 12 in the first lower arc angle region and the second bus portion 12 in the second lower arc angle region, simplifying the wiring design in the display area AA. Furthermore, the second bus portion 12 in the first lower arc angle region and the second bus portion 12 in the second lower arc angle region are connected to the same first power signal line V1, which can ensure more uniform display brightness at the same grayscale for light-emitting devices located at the same distance from the first bus portion 11 in the second direction Y.

[0082] 3 , for example, the second bus portion 12 in the first upper arc corner region and the second bus portion 12 in the second upper arc corner region are connected to the same first power signal line V1 .

[0083] The second bus portion 12 connecting the first upper arc angle region and the second bus portion 12 connecting the second upper arc angle region can connect to multiple first power signal lines V1. Each first power signal line V1 corresponding to the first upper arc angle region or the second upper arc angle region has one end connected to the second bus portion 12 in the first upper arc angle region via a first adapter line L1, and the other end connected to the second bus portion 12 in the second upper arc angle region via another first adapter line L1. The second bus portion 12 in the first upper arc angle region and the second bus portion 12 in the second upper arc angle region are connected to the same first power signal line V1. This can reduce the number of first power signal lines V1 while maintaining the shunting effect between the second bus portion 12 in the first upper arc angle region and the second bus portion 12 in the second upper arc angle region, simplifying the wiring design in the display area AA.

[0084] 3 , for example, the second bus portions 12 of the third side region 33 and the fourth side region 34 are electrically connected to the first power signal line V1 .

[0085] Current can also accumulate in the second bus sections 12 of the third and fourth side regions 33 and 34. By diverting the current from the second bus sections 12 of the third and fourth side regions 33 and 34 to the display area via the first power signal line V1, the current density in the third and fourth side regions 33 and 34 can be reduced, further reducing heating of the display panel caused by the high current density. Furthermore, by diverting the current via multiple first signal lines V1, the IR drop of the cathode signal is reduced, thereby lowering the power consumption of the screen.

[0086] 3 , for example, the second bus portion 12 of the second side region 32 is electrically connected to the second power signal line V2 .

[0087] After the second bus portion 12 of the second side region 32 is electrically connected to the second power signal line V2, the current flowing through the second bus portion 12 of the second side region can be diverted to the display area, reducing the current density flowing through the second bus portion 12 of the second side region. This prevents heating in the second side region due to excessive current density, thereby further lowering the temperature of the entire display panel. Furthermore, the IR drop of the cathode signal is further reduced through the first power signal line V2, thereby reducing screen power consumption.

[0088] The present application also provides a display device. FIG16 is a schematic diagram of the structure of a display device provided in the present application. The display device 4 includes the aforementioned display panel 5. The display device 4 can be a mobile phone as shown in FIG16 , or a computer, a television, a smart wearable display device, etc., which is not particularly limited in the present application.

[0089] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the multiple steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this application can be achieved. This is not limited herein.

Claims

1. A display panel, comprising a display area and a non-display area surrounding the display area; the non-display area comprises at least one arc angle area; A first power bus is disposed in the non-display area, the first power bus surrounds at least a portion of the display area, and the first power bus passes through at least one of the arc angle areas, the first power bus includes a first bus portion and a second bus portion, the first bus portion is disposed at one side of the display area and is electrically connected to the second bus portion, and the first bus portion is used to connect a power source; A plurality of power signal lines are also arranged in the display area, and each power signal line is electrically connected between the second bus portion and the first bus portion in at least one of the arc angle regions.

2. The display panel according to claim 1, wherein: The non-display area includes a first arc angle region and a second arc angle region, and the distance between the first arc angle region and the first bus portion is greater than the distance between the second arc angle region and the first bus portion; At least the second bus portion of the second arc angle region is electrically connected to the first bus portion through the power signal line; The first bus portion and the second bus portion are an integrated structure.

3. The display panel according to claim 1, wherein: The non-display area further includes a side area adjacent to the arc angle area, and the second bus portion of at least one of the side areas is electrically connected to the first bus portion through the power signal line.

4. The display panel according to any one of claims 1 to 3, wherein: The power signal line includes a first power signal line and a second power signal line, the first power signal line extends along a first direction, the second power signal line extends along a second direction, and the first direction and the second direction intersect; The first power signal line is electrically connected to the second power signal line; In the second direction, the first bus portion is located at one side of the display area; the first bus portion is electrically connected to the second power signal line; The second bus portion in the arc angle region is electrically connected to the first power signal line.

5. The display panel according to claim 4, wherein: The second bus portion of at least one side area is electrically connected to the first power signal line.

6. The display panel according to claim 4, wherein: The display area includes a first sub-display area and a second sub-display area, the second sub-display area is located on a side of the first sub-display area away from the first bus portion; the density of the first power signal line in the second sub-display area is less than the density of the first power signal line in the first sub-display area.

7. The display panel according to claim 6, wherein: Along the direction from the second sub-display area to the first sub-display area, the density of the first power signal lines gradually increases.

8. The display panel according to claim 4, further comprising a substrate and an array film layer on the substrate, wherein the array film layer comprises a plurality of metal layers stacked; The first power signal line and the second power signal line are arranged in at least one of the metal layers.

9. The display panel according to claim 8, wherein: The metal layer comprises a light shielding layer, the light shielding layer is located between the active layer in the array film layer and the substrate, and the first power signal line and the second power signal line are located in the light shielding layer; The orthographic projection of the light shielding layer on the substrate at least covers a portion of the orthographic projection of the active layer on the substrate.

10. The display panel according to claim 8, wherein: The first power signal line is located in a first metal layer, the second power signal line is located in a second metal layer, and the second metal layer is located on a side of the first metal layer close to the substrate. 11 . The display panel according to claim 10 , further comprising a first electrode and a second electrode, wherein the second electrode is disposed on a side of the first electrode away from the array film layer, and the second bus portion is electrically connected to the second electrode.

12. The display panel according to claim 11, wherein: The first power bus is disposed in the same layer as the first electrode, and the first power bus is insulated from the first electrode.

13. The display panel according to claim 11, further comprising: A first adapter wire, wherein the first adapter wire is located at a third metal layer, and the third metal layer is located far away from the first metal layer. A side away from the substrate; The first end of the first adapter wire is electrically connected to the second bus portion, and the second end of the first adapter wire is electrically connected to the first power signal line; the third metal layer is the metal layer closest to the first electrode among the plurality of metal layers; the first metal layer is adjacent to the third metal layer; and / or, A second adapter line, wherein the second adapter line is arranged in the same layer as the first power bus, the first end of the second adapter line is connected to the second power signal line, and the second end of the second adapter line is connected to the first bus portion; the non-display area also includes a second power bus between the first bus portion and the display area, the second power bus is located in at least one layer of the metal layer, and the second adapter line is insulated from the second power bus.

14. The display panel according to claim 4, wherein: The non-display area includes a first side area, a second side area, a third side area and a fourth side area, the first side area and the second side area are arranged opposite to each other in the second direction, the third side area and the fourth side area are arranged opposite to each other in the first direction, and the first bus portion is arranged in the first side area.

15. The display panel according to claim 14, wherein: The non-display area includes a first arc angle area and a second arc angle area, the first arc angle area includes a first lower arc angle area and a second lower arc angle area, the first lower arc angle area is adjacent to the first side edge area and the third side edge area respectively, and the second lower arc angle area is adjacent to the first side edge area and the fourth side edge area respectively; The second arc angle area includes a first upper arc angle area and a second upper arc angle area, the first upper arc angle area is adjacent to the second side edge area and the third side edge area respectively, and the second upper arc angle area is adjacent to the second side edge area and the fourth side edge area respectively.

16. The display panel according to claim 15, wherein: The second bus portion in the first lower arc angle region and the second bus portion in the second lower arc angle region are connected to the same first power signal line.

17. The display panel according to claim 15, wherein: The second bus portion in the first upper arc angle region and the second bus portion in the second upper arc angle region are connected to the same first power signal line.

18. The display panel according to claim 14, wherein: The second bus portions of the third side area and the fourth side area are electrically connected to the first power signal line.

19. The display panel according to claim 14, wherein: The second bus portion of the second side area is electrically connected to the second power signal line.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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