Semiconductor device

Abstract

The present invention reduces on-resistance while ensuring a short circuit withstand time in a trench MOSFET having a vertical channel fin structure.　A semiconductor device 1 comprises: a plurality of trenches 2 arranged in a second direction, each having a longitudinal direction in a first direction and having a lateral direction in the second direction when viewed from above; a first source region 3 of a first conductivity type, at least a portion of which is divided by the plurality of trenches 2; and a second conductivity-type channel region 5 which is in contact with the lower surface of the first source region 3 and is divided by the plurality of trenches 2, wherein the channel region 5 is connected to a body region 9 and a channel current flows in the vertical direction in the channel region 5, the first-direction length of a gate electrode 7 disposed inside the trench 2 is greater than the first-direction length of a JFET region 8, the impurity concentration in the JFET region 8 is higher than the impurity concentration in a drift region 10, and the dimensions of the body region 9 and the JFET region 8 in the depth direction from the bottom of the trench 2 are both greater than 0.5 μm.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] As one type of trench MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] 17 is a perspective view schematically showing a conventional trench MOSFET with a vertical channel fin structure, in which the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are not shown.

[0004] 17 shows a conventional semiconductor device 1 that has a longitudinal direction in a first direction and a lateral direction in a second direction when viewed from above, and has a plurality of trenches 2 arranged in the second direction. Note that the trenches 2 shown by dotted lines in the cross section at the front of Fig. 17 show positions that virtually correspond to the trenches 2 in order to explain the positional relationship between other components and the trenches 2.

[0005] The first conductivity type source region 3B includes a region at least a portion of which has a fin structure separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3B and in contact with the source region 3B. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0006] 17 has a gate insulating film disposed inside the trench 2 and a gate electrode including a region at least partially disposed inside the trench 2, and a channel current flows vertically (in the depth direction) in the channel region 5. The gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2.

[0007] Incidentally, an example of a patent document related to such technology is Patent Document 1. Although the names of the components and the detailed structure are different, paragraphs 0048 to 0052, FIG. 3, and FIG. 14 to FIG. 18 of Patent Document 1 describe a configuration similar to FIG. 17 described above.

[0008] Japanese Patent Application Laid-Open No. 2004-207289

[0009] According to the structure of the conventional semiconductor device 1 shown in Fig. 17, the number of channels can be increased by reducing the trench pitch and increasing the channel density, thereby reducing the on-resistance when viewed from the perspective of the entire semiconductor chip. However, the conventional semiconductor device 1 shown in Fig. 17 has a problem in that, although the on-resistance is low due to the high channel density, the short-circuit resistance is correspondingly low.

[0010] Furthermore, in the conventional semiconductor device 1 shown in FIG. 17, the thickness (dimension in the depth direction) of the JFET region 8 is thin, which causes a problem of low short-circuit resistance.

[0011] Furthermore, in the conventional semiconductor device 1 shown in FIG. 17 , when the impurity concentration of the JFET region 8 is the same as the impurity concentration of the drift region 10, the impurity concentration of the JFET region 8 is as low as the impurity concentration of the drift region 10, which increases the resistance of the JFET region 8 and makes it impossible to sufficiently reduce the on-resistance.

[0012] The problem to be solved by the present invention is to provide a semiconductor device that can reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure.

[0013] In order to achieve the above object, a semiconductor device of the present invention includes a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed from above, the plurality of trenches being arranged in the second direction, a first source region of a first conductivity type at least a portion of which is separated by the plurality of trenches, a channel region of a second conductivity type in contact with a lower surface of the first source region and separated by the plurality of trenches, a gate insulating film disposed inside the trench, a gate electrode including a region at least a portion of which is disposed inside the trench, a JFET region of the first conductivity type disposed below the channel region, a body region of the second conductivity type disposed on a side of the JFET region, and a gate insulating film disposed inside the JFET. a first conductivity type drift region disposed below the trench; and a first conductivity type drain region disposed below the drift region and having a higher impurity concentration than the drift region, wherein the channel region is connected to the body region and a channel current flows vertically through the channel region, the length of the gate electrode disposed inside the trench in the first direction is longer than the length of the JFET region in the first direction, the impurity concentration of the JFET region is higher than the impurity concentration of the drift region, and the dimensions of the body region and the JFET region in the depth direction from the bottom of the trench are both greater than 0.5 μm.

[0014] According to the present invention, in a trench MOSFET with a vertical channel fin structure, it is possible to reduce the on-resistance while ensuring short-circuit resistance.

[0015] 1. A top perspective view of a semiconductor device of Example 1. An X1-X1' cross-sectional view of FIG. 1. An X2-X2' cross-sectional view of FIG. 1. A Y1-Y1' cross-sectional view of FIG. 1. A top perspective view of a semiconductor device of Example 2. A diagram for explaining an example of the characteristics of the semiconductor device of Example 2. A top perspective view of a semiconductor device of Example 3. An X3-X3' cross-sectional view of FIG. 7. A top perspective view of a semiconductor device of Example 4. An X4-X4' cross-sectional view of FIG. 9. A Y2-Y2' cross-sectional view of FIG. 9. A top perspective view of a semiconductor device of Example 5. An X5-X5' cross-sectional view of FIG. 12. A top perspective view of a semiconductor device of Example 6. A top perspective view of a semiconductor device of Example 7. An X6-X6' cross-sectional view of FIG. 15. A perspective view schematically showing a trench MOSFET with a conventional vertical channel fin structure.

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0017] FIG. 1 is a top perspective view of a semiconductor device of Example 1. FIG. 2 is an X1-X1' cross-sectional view of FIG. 1. FIG. 3 is an X2-X2' cross-sectional view of FIG. 1. FIG. 4 is a Y1-Y1' cross-sectional view of FIG. 1. Note that the gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and barrier metal 16 are not shown in FIG. 1. Also, in FIG. 1, the position where a contact plug 15 is disposed is indicated by a dotted line. Note that these are the same in the subsequent top perspective views, so repeated explanation will be omitted.

[0018] The semiconductor device 1 of this embodiment has a plurality of trenches 2, a first source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of the first conductivity type, a body region 9 of the second conductivity type, a drift region 10 of the first conductivity type, and a drain region 11 of the first conductivity type.

[0019] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0020] The plurality of trenches 2 have their longitudinal direction in a first direction (the X1-X1' direction in FIG. 1) when viewed in a plan view, and their lateral direction in a second direction (the Y1-Y1' direction in FIG. 1), and are arranged in a plurality in the second direction. Furthermore, a plurality of trench groups each made up of trenches 2 arranged in the second direction are also arranged in a plurality in the first direction. Note that the trenches 2 indicated by dotted lines in the cross-sectional view of FIG. 2 are hypothetical positions corresponding to the trenches 2 in order to explain the positional relationship between other components and the trenches 2.

[0021] The first conductivity type first source region 3 includes a region having a fin structure at least a portion of which is separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the first source region 3 and in contact with the first source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. Therefore, the width (length in the first direction) of the channel region 5 is the width (length in the first direction) of the trench 2 minus the overlap width between the trench 2 and the body region 9.

[0022] A drift region 10 of the first conductivity type is arranged below the JFET region 8. The drift region 10 is also arranged below the body region 9. In addition, a drain region 11 of the first conductivity type, which has a higher impurity concentration than the drift region 10, is arranged below the drift region 10.

[0023] A gate insulating film 6 is disposed inside the trench 2. At least a portion of a gate electrode 7 is also disposed inside the trench 2. The gate electrodes 7 disposed inside the trench 2 are connected to each other outside the trench 2. The gate electrodes 7 can be formed of, for example, polysilicon.

[0024] In the semiconductor device 1 of this embodiment, a channel current flows vertically (in the depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. In other words, the semiconductor device 1 is a trench MOSFET with a vertical channel fin structure. Therefore, the number of channels can be increased by reducing the trench pitch and increasing the channel density, thereby reducing the on-resistance of the entire semiconductor chip.

[0025] Furthermore, in the semiconductor device 1 of this embodiment, as shown in FIG. 3 , the width (length in the first direction) WTG of the gate electrode 7 disposed inside the trench 2 is longer than the width (length in the first direction) WJ of the JFET region 8. The width WTG of the gate electrode 7 is calculated by subtracting the thickness of the gate insulating film (two portions, one in the first direction) from the width (length in the first direction) WTR of the trench 2. Since WTG > WJ, the ends of the bottom surfaces of the plurality of trenches 2 in the first direction and the ends of the bottom surfaces of the gate electrodes 7 in the trench 2 in the first direction are located within the body region 9. This results in a structure in which three-dimensional corners of the trench 2 and the gate electrode 7 are located within the body region 9. Therefore, even when a high voltage is applied, the concentration of the electric field is alleviated at the three-dimensional corners of the trench 2, where the electric field is likely to concentrate and the gate insulating film 6 is likely to be destroyed, thereby suppressing the destruction of the gate insulating film 6.

[0026] Furthermore, in the semiconductor device 1 of this embodiment, the impurity concentration of the JFET region 8 is set higher than the impurity concentration of the drift region 10, and the thickness (dimension in the depth direction) tJ of the body region 9 and the JFET region 8 from the bottom of the trench 2 is set to be greater than 0.5 μm, as shown in Fig. 3. It is desirable to set the thickness tJ of the body region 9 and the JFET region 8 from the bottom of the trench 2 to be approximately the same thickness.

[0027] When a high voltage is applied between the drain and source, the depletion layer spreads in the JFET region 8, ensuring a breakdown voltage. Here, when the thickness tJ is thin, as in the conventional structure shown in FIG. 17, the depletion layer spreads mainly in the depth direction. The depletion layer spreads more easily when the impurity concentration is low. Therefore, the concentration in the JFET region 8 cannot be increased, and it is set to 1×10, the same as the concentration in the general drift region 10. １６ cm －３ is set to a certain extent.

[0028] In contrast, in this embodiment, by increasing the thickness tJ, when a high voltage is applied between the drain and source, the depletion layer begins to expand laterally from the body region 9 on both sides of the JFET region 8. When a higher voltage is applied, the depletion layer closes and pinches off. This allows the depletion layer to expand only half the width WJ of the JFET region 8, resulting in a depletion layer of thickness tJ. As a result, the expansion of the depletion layer required for complete depletion is small, allowing the impurity concentration of the JFET region 8 to be increased while maintaining a high breakdown voltage. Furthermore, since the impurity concentration of the JFET region 8 can be set high, the resistance of the JFET region 8 can be reduced, thereby reducing the on-resistance. Furthermore, although the temperature characteristic of the resistance of the JFET region 8 is positive, a high impurity concentration reduces the rate of increase in the resistance of the JFET region 8 even in high-temperature environments. Therefore, the on-resistance of the entire semiconductor chip at high temperatures can be maintained at a low level.

[0029] The thickness tJ of both the body region 9 and the JFET region 8 from the bottom of the trench 2 is preferably 0.8 μm or more and 1.3 μm or less. The larger the thickness tJ, the greater the above-mentioned effect. The width WTR of the trench 2 is preferably 1.3 μm or more and 1.6 μm or less. The width WJ of the JFET region 8 is preferably 0.3 μm or more and 1.4 μm or less. The narrower the width WJ, the greater the above-mentioned effect. The impurity concentration of the JFET region 8 is 8×10 １６ cm －３ That's it, 2 x 10 １７ cm －３ This is the concentration of 1×10 １６ cm －３ Greater than the extent.

[0030] As described above, according to this embodiment, it is possible to realize a semiconductor device 1 that can reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure.

[0031] In addition, the semiconductor device 1 of this embodiment also has a source electrode 12 arranged on the front side, a drain electrode 13 arranged on the back side, an interlayer insulating film 14, a second source region 4 of the second conductivity type, a contact plug 15, and a barrier metal 16.

[0032] The source electrode 12 is an electrode made of a metal such as aluminum.

[0033] The drain electrode 13 is an electrode formed of, for example, a laminated metal film (for example, titanium / nickel / gold), and is electrically connected to the drain region 11 .

[0034] The interlayer insulating film 14 is formed between the mutually connected portions of the gate electrodes 7 and the first source region 3. The interlayer insulating film 14 is also formed so as to cover the upper and side portions of the mutually connected portions of the gate electrodes 7.

[0035] In this embodiment, the gate electrodes 7 are connected to each other above the plurality of trenches 2, so that a part of the gate electrode 7 protrudes from the other semiconductor layers to form a step.

[0036] Therefore, in this embodiment, a second source region 4 of the second conductivity type is provided in contact with the upper surface of at least a portion of the body region 9 and has a higher impurity concentration than the body region 9. The gate electrode 7, the first source region 3, and the second source region 4 are covered with an interlayer insulating film 14, and a contact plug 15 is provided that penetrates the interlayer insulating film 14 and is connected to the first source region 3 and the second source region 4. The contact plug 15 can be made of a conductive metal such as tungsten. It is also desirable to connect the first source region 3 and the second source region 4 to the contact plug 15 via a barrier metal 16. The barrier metal 16 can be made of, for example, TiN or Ti.

[0037] By providing the contact plug 15 as in this embodiment, the source electrode 12 can be connected to the first source region 3 and the second source region 4 via the contact plug 15, thereby stabilizing the connection between the source electrode 12 and the first source region 3 and the second source region 4. Furthermore, since the surface of the source electrode 12 can be flattened, the source electrode 12 can also be stabilized when connected to the outside.

[0038] Furthermore, by providing the second source region 4 of the second conductivity type, the body region 9 of the second conductivity type and the source electrode 12 can be connected with lower resistance than by connecting them via the first source region 3 of the first conductivity type or by connecting them directly to the body region 9.

[0039] 1, the first source region 3, the second source region 4, and the contact plug 15 may be arranged such that the contact plug 15 has its longitudinal direction in the second direction, and the first source region 3 and the second source region 4 are arranged alternately at least in the region overlapping with the contact plug 15. The second source region 4 has its longitudinal direction in the first direction and its lateral direction in the second direction, and a plurality of second source regions 4 are arranged in the second direction. The arrangement of the first source region 3, the second source region 4, and the contact plug 15 is not limited to this, and other arrangements may be used.

[0040] Regarding the impurity concentration, in this embodiment, as an example, the JFET region 8 is illustrated as n, the body region 9 and the channel region 5 as p, the drift region 10 as low concentration n-, the first source region 3 and the drain region 11 as high concentration n+, and the second source region 4 as high concentration p+, but the impurity concentration may be changed within a range that can realize the operation intended in this embodiment.

[0041] The semiconductor device 1 of this embodiment can be formed using, for example, an n+ type SiC substrate, but is not limited to this and may also be formed using a Si substrate, etc. Furthermore, for portions of this specification where no special description of the manufacturing method is given, detailed description will be omitted because the semiconductor device can be manufactured using a general semiconductor device manufacturing method, such as forming an n+ type drain region 11 on an n+ type SiC substrate and forming an n- type drift region 10 by epitaxial growth. The same applies to the method of forming contact plugs 15, etc.

[0042] FIG. 5 is a top perspective view of a semiconductor device according to a second embodiment.

[0043] In addition to the configuration of the semiconductor device 1 of the second embodiment, the semiconductor device 1 has, in different locations when viewed in a plane, a region where the width WJ of the JFET region 8 is WJ=WJ1 and a region where the width WJ of the JFET region 8 is WJ=WJ2<WJ1.

[0044] 6 is a diagram illustrating an example of the characteristics of the semiconductor device of Example 2. In Fig. 6, the lower horizontal axis represents the width WJ of the JFET region 8, the upper horizontal axis represents the short-circuit withstand capability, the left vertical axis represents the normalized on-resistance Ron·Aa, and the right vertical axis represents the gate-drain capacitance Cgd.

[0045] The normalized on-resistance Ron·Aa is the on-resistance per unit area, and the smaller this value, the more current can flow per unit area. The JFET region 8 is the current path during MOSFET operation, and the wider the width WJ of the JFET region 8, the easier it is for current to flow, so the normalized on-resistance Ron·Aa decreases. Conversely, if it is made too narrow, the width of the current path becomes too narrow, and the normalized on-resistance Ron·Aa increases sharply. Therefore, the design range is just before the normalized on-resistance Ron·Aa increases sharply.

[0046] As shown in FIG. 3, the gate-drain capacitance Cgd is the capacitance formed by the lower part of the gate electrode 7 inside the trench 2 and the JFET region 8, which is in contact with the gate insulating film 6 via the gate insulating film 6. The gate-drain capacitance Cgd, also known as the feedback capacitance Crss, is a parameter that greatly affects the switching speed of the MOSFET; the smaller this value, the faster the switching speed. The wider the width WJ of the JFET region 8, the higher the gate-drain capacitance Cgd. Since the gate-drain capacitance Cgd increases as the square of the opposing area between the gate and drain, the slope increases sharply if the width WJ of the JFET region 8 is made too wide. Therefore, the design range is just before the slope of the gate-drain capacitance Cgd increases sharply.

[0047] As shown in FIG. 6, the increase and decrease of the normalized on-resistance Ron·Aa and the gate-drain capacitance Cgd with respect to the width WJ of the JFET region 8 behave in contradictory ways.

[0048] Furthermore, if the width WJ of the JFET region 8 is narrow, the depletion layer is more likely to close, so if the width WJ of the JFET region 8 is narrow, the short-circuit resistance improves, and if the width WJ of the JFET region 8 is wide, the short-circuit resistance decreases.

[0049] Therefore, in the region where the width WJ of the JFET region 8 is WJ=WJ1, the width WJ of the JFET region 8 can be made wider to form a cell that actively performs MOSFET operation, and in the region where the width WJ of the JFET region 8 is WJ=WJ2, the width WJ of the JFET region 8 can be made narrower to form a cell that can limit the saturation current more than in the region where the width WJ of the JFET region 8 is WJ=WJ1, thereby improving the short-circuit resistance.

[0050] As in this embodiment, by mixing a region where the width WJ of the JFET region 8 is WJ=WJ1 and a region where the width WJ of the JFET region 8 is WJ=WJ2 and adjusting the ratio, it is possible to adjust the characteristics, thereby responding precisely to various application requirements.

[0051] Furthermore, among the multiple trenches 2, the JFET region 8 corresponding to the trench 2 in the termination portion 17 in the second direction may have an impurity concentration equal to or lower than that of the drift region 10 or lower than that of the other JFET regions 8. Because the depletion layer of this type of cell is easily closed, it can be said to be a cell capable of limiting saturation current and improving short-circuit resistance. In the cell termination portion 17, there are no other cells sharing the same current path, and the current is interrupted there. This results in lower drift resistance than within the cell body, making it easier for current to flow and generate heat. Furthermore, when a drain bias is applied, the cell termination portion 17 is prone to electric field concentration because it is the boundary between the cell body and the chip periphery. By arranging a cell capable of partially limiting saturation current and improving short-circuit resistance in such a location, it is possible to reliably ensure short-circuit resistance while maintaining as low an on-resistance as possible.

[0052] Although an example of placement at the terminal end 17 of the cell has been described here, such a structure may also be applied to the heat generating area if a heat generating area within the chip is identified for various reasons.

[0053] Fig. 7 is a top perspective view of a semiconductor device according to Example 3. Fig. 8 is a cross-sectional view taken along the line X3-X3' in Fig. 7.

[0054] In addition to the configuration of Example 1 or Example 2, the semiconductor device 1 of Example 3 has a third source region 3A, at least in the portion of the first source region 3 separated by a plurality of trenches 2, which has a smaller thickness (dimension in the depth direction) and a lower impurity concentration than other portions of the first source region 3.

[0055] The third source region 3A has a smaller thickness and a lower impurity concentration than the first source region 3, and therefore has a higher resistance. At high temperatures, such as when a short circuit occurs, the resistance increases, and therefore the potential of the third source region 3A becomes higher than that of the first source region 3, and the voltage of the JFET region 8 increases accordingly. This strengthens the reverse bias of the PN junction between the JFET region 8 and the body region 9, and further depletes the JFET region 8. As a result, the saturation current can be reduced compared to Example 1, and the short-circuit resistance is improved.

[0056] Furthermore, since the third source region 3A is thinner than the first source region 3, the overlap capacitance between the gate electrode 7 extending in the depth direction of the trench 2 and the third source region 3A is reduced, thereby reducing the gate capacitance, thereby increasing the switching speed.

[0057] Therefore, according to the semiconductor device 1 of this embodiment, it is possible to improve the short-circuit resistance and reduce the gate capacitance while maintaining a high channel density, and also to increase the switching speed.

[0058] Here, in order to fully obtain the effect of improving the short-circuit resistance, it is desirable that the sheet resistance of the third source region 3A is 10 times or more the sheet resistance of the first source region 3.

[0059] Furthermore, in this embodiment, since the thickness of the third source region 3A is reduced, the trench 2 can be made shallower and the thickness tJ can be increased accordingly.

[0060] Fig. 9 is a top perspective view of a semiconductor device according to Example 4. Fig. 10 is a cross-sectional view taken along line X4-X4' in Fig. 9. Fig. 11 is a cross-sectional view taken along line Y2-Y2' in Fig. 9.

[0061] In this embodiment, an example will be described in which the present invention is applied to the third embodiment, but the present invention is not limited to this and may be applied to the first or second embodiment.

[0062] In this embodiment, the second source region 4 has its longitudinal direction in the second direction. The contact plugs 15 have their longitudinal direction in the first direction and are arranged in multiple rows in the second direction. This allows for low-resistance connection between the body region 9 and the source electrode 12 via the second source region 4, which has its longitudinal direction in the second direction. This enables efficient operation of the built-in body diode of the MOSFET. Furthermore, this low-resistance connection stabilizes the base potential of the parasitic bipolar transistor composed of the drain region 11 (n collector), body region 9 (p base), and first source region 3 (n emitter) (potential fixing effect), making the parasitic transistor less likely to operate and suppressing element destruction due to parasitic transistor operation. Furthermore, by arranging the second source region 4 in a continuous stripe-like layout, problems such as localized disconnection of the second source region 4 due to pattern defects and the like are reduced. This reduces defects resulting from increased drain-source leakage during off-state due to this problem, thereby improving yield.

[0063] Fig. 12 is a top perspective view of a semiconductor device according to Example 5. Fig. 13 is a cross-sectional view taken along the line X5-X5' of Fig. 12.

[0064] In this embodiment, an example will be described in which the present invention is applied to the third embodiment, but the present invention is not limited to this and may be applied to the first or second embodiment.

[0065] In this embodiment, as in the fourth embodiment, the second source region 4 has its longitudinal direction in the second direction. The contact plugs 15 have their longitudinal direction in the first direction and are arranged in plurality in the second direction. This allows the same effects as in the fourth embodiment to be obtained.

[0066] In addition, in this embodiment, in the region between the region where multiple contact plugs 15 are arranged in the second direction and the region where multiple trenches 2 are arranged in the second direction, the area of ​​the second source region 4 is larger than the area of ​​the first source region 3 on one side of the contact plug 15 in the first direction (e.g., the left side of Figure 12), and the area of ​​the second source region 4 is smaller than the area of ​​the first source region 3 on the other side of the contact plug 15 in the first direction (e.g., the right side of Figure 12).

[0067] For example, in Example 4, as shown in FIG. 9 , first source regions 3 each having a longitudinal direction in the second direction are disposed on both sides of second source regions 4 each having a longitudinal direction in the second direction, so that the first source regions 3 form two stripes. However, in Example 5, as shown in FIG. 12 , the first source region 3 each having a longitudinal direction in the second direction is disposed on only one side of the second source region 4. This allows the spacing of trenches 2 in the first direction to be shortened, thereby increasing channel density or reducing the size of the semiconductor chip. Furthermore, the area of ​​the parasitic bipolar transistor formed by the drain region 11 (n collector), body region 9 (p base), and first source region 3 (n emitter) can be reduced, thereby suppressing element breakdown due to parasitic transistor operation.

[0068] 14 is a top perspective view of a semiconductor device according to Example 6. Note that in FIG. 14, the position where the contact plug 15 is to be disposed is not shown.

[0069] In this embodiment, an example will be described in which the present invention is applied to Example 4 based on Example 3, but the present invention is not limited to this, and may be applied to Example 4 based on Example 1 or Example 2, or to Example 5.

[0070] The basic structure of this embodiment is the same as that of embodiment 4. In this embodiment, the first source region 3 is thinned out at a terminal portion 17 in the second direction of a portion separated by a plurality of trenches 2 (this corresponds to a portion of the third source region 3A, which is part of the first source region 3, when based on embodiment 3), to form a thinned-out region 18. In addition, the portion between the portion separated by the plurality of trenches 2 that forms the thinned-out region 18 and a contact plug 15 (not shown) is also thinned out to form a thinned-out region 18.

[0071] According to this embodiment, in the terminal portion 17 where an electric field is likely to concentrate, the saturation current can be limited in the event of a short circuit, thereby improving the short circuit resistance.

[0072] Although an example in which the thinning region 18 is disposed at the terminal end 17 of the cell has been described here, the present invention is not limited to this, and the thinning region 18 may be disposed at a location that is likely to become hot in the event of a short circuit.

[0073] Fig. 15 is a top perspective view of a semiconductor device of Example 7. Fig. 16 is a cross-sectional view taken along line X6-X6' in Fig. 15. Note that Fig. 15 does not show the positions where contact plugs 15 are to be disposed.

[0074] In this embodiment, an example will be described in which the present invention is applied to Example 4 based on Example 3, but the present invention is not limited to this, and may be applied to Example 4 based on Example 1 or Example 2, or to Example 5 or Example 6.

[0075] In this embodiment, the basic structure is the same as in embodiment 4. In this embodiment, in a region between a region in which a plurality of contact plugs 15 are arranged in the second direction and a region in which a plurality of trenches 2 are arranged in the second direction, first source regions 3 are arranged with their longitudinal direction in the second direction, and thinned-out regions 18 are provided by partially thinning out the first source regions 3. In these thinned-out regions 18, the body regions 9 are exposed or the second source regions 4 are arranged.

[0076] According to this embodiment, the area of ​​the parasitic bipolar transistor composed of the drain region 11 (n collector), the body region 9 (p base), and the first source region 3 (n emitter) can be reduced, thereby suppressing element destruction due to the operation of the parasitic transistor.

[0077] In order to avoid an increase in on-resistance as much as possible, it is desirable not to thin out the side opposite to the thinned-out region 18 across the trench 2 .

[0078] Furthermore, by arranging the second source region 4 in the thinning region 18, the potential fixing effect described in Example 4 can be obtained, making it difficult for the parasitic transistor to operate and suppressing element destruction due to the parasitic transistor operation.

[0079] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0080] REFERENCE SIGNS LIST 1...semiconductor device, 2...trench, 3...first source region, 3A...third source region, 3B...source region, 4...second source region, 5...channel region, 6...gate insulating film, 7...gate electrode, 8...JFET region, 9...body region, 10...drift region, 11...drain region, 12...source electrode, 13...drain electrode, 14...interlayer insulating film, 15...contact plug, 16...barrier metal, 17...termination portion, 18...thinning-out region

Claims

a gate insulating film disposed inside the trench; a gate electrode including a region at least a portion of which is disposed inside the trench; a JFET region of the first conductivity type disposed below the channel region; a body region of the second conductivity type disposed to one side of the JFET region; a drift region of the first conductivity type disposed below the JFET region; and a drain region of the first conductivity type disposed below the drift region and having a higher impurity concentration than the drift region, wherein the channel region is connected to the body region and a channel current flows vertically through the channel region; the length in the first direction of the gate electrode disposed inside the trench is longer than the length in the first direction of the JFET region; and the impurity concentration of the JFET region is higher than the impurity concentration of the drift region, a body region and a JFET region each having a depth dimension greater than 0.5 μm from a bottom of the trench; 2. A semiconductor device according to claim 1, wherein the dimensions of the body region and the JFET region in the depth direction from the bottom of the trench are both 0.8 μm or more and 1.3 μm or less.

3. A semiconductor device according to claim 1, wherein the length of the trench in the first direction is 1.3 μm or more and 1.6 μm or less.

4. A semiconductor device according to claim 1, wherein the length of the JFET region in the first direction is 0.3 μm or more and 1.4 μm or less.

5. The method according to claim 1, wherein the impurity concentration of the JFET region is 8×10 １６ cm －３ That's it, 2 x 10 １７ cm －３ A semiconductor device characterized in that:

6. A semiconductor device according to claim 1, characterized in that it has, in different locations when viewed in a plane, a region in which the length of the JFET region in the first direction is a first length, and a region in which the length of the JFET region in the first direction is a second length shorter than the first length.

7. A semiconductor device according to claim 1, wherein the JFET region corresponding to the trench at the end of the plurality of trenches in the second direction has an impurity concentration that is the same as that of the drift region or that is lower than the impurity concentrations of the other JFET regions.

8. A semiconductor device according to claim 1, characterized in that the first source region, at least in the portion separated by the plurality of trenches, has a third source region having a smaller dimension in the depth direction and a lower impurity concentration than other portions of the first source region.

9. A semiconductor device according to claim 1, comprising: a second source region of a second conductivity type contacting an upper surface of at least a portion of the body region and having a higher impurity concentration than the body region; an interlayer insulating film covering the gate electrode, the first source region and the second source region; and a contact plug penetrating the interlayer insulating film and connected to the first source region and the second source region.

10. A semiconductor device according to claim 9, wherein the contact plug has a longitudinal direction in the second direction, and the first source region and the second source region are alternately arranged at least in the region overlapping with the contact plug.

11. A semiconductor device according to claim 9, wherein the second source region has a longitudinal direction in the second direction.

12. A semiconductor device according to claim 11, wherein the contact plug has a longitudinal direction in the first direction and a plurality of contact plugs are arranged in the second direction.

13. A semiconductor device according to claim 12, characterized in that in a region between a region in which the contact plugs are arranged in the second direction and a region in which the trenches are arranged in the second direction, the area of ​​the second source region is larger than the area of ​​the first source region on one side of the contact plug in the first direction, and the area of ​​the second source region is smaller than the area of ​​the first source region on the other side of the contact plug in the first direction.

14. A semiconductor device according to claim 1, wherein the first source region is thinned out at an end portion in the second direction among the portions separated by the plurality of trenches.

15. A semiconductor device according to claim 12, characterized in that in a region between a region in which the contact plugs are arranged in the second direction and a region in which the trenches are arranged in the second direction, the first source region is arranged with its longitudinal direction in the second direction and has a thinned-out region in which the first source region is partially thinned out, and the thinned-out region exposes the body region or has the second source region arranged therein.

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