Control method, network card system, host system and chip system

Abstract

Provided in the embodiments of the present application are a control method, a network card system, a host system and a chip system, which are applied to the technical field of computer virtualization. A first virtual machine and a virtual machine management system run on the host system, the first virtual machine being directly connected to the network card system, and the first virtual machine performing a stateful service interaction on the basis of the network card system. The host system has applied for a memory space at a first physical area address, so as to store service interaction state information of the first virtual machine, the first physical area address having a non-writable attribute for the first virtual machine. The virtual machine management system sends first indication information to the network card system, so as to indicate an identifier of the first virtual machine and the first physical area address. During subsequent service interactions, on the basis of the first indication information, the network card system obtains the service interaction state information from the first physical area address, so as to assist service interactions of the first virtual machine. The present embodiments reduce the difficulty in live migration while avoiding security and reliability issues of first virtual machines.

Description

A control method, network card system, host system and chip system Technical Field

[0001] The present application relates to the field of computer virtualization technology, and in particular to a control method, a network card system, a host system, and a chip system. Background Art

[0002] In today's computer cloud computing landscape, virtualization technology is continuously evolving. Virtualization technology is based on a system-on-a-chip (SoC), which includes a host system and a network interface card (NIC) system. A first virtual machine (VM) and a VM management system (VMMS) run on the host system. The VM interacts with other network nodes via the NIC chip. During this process, the VM management system manages the VM. For example, the VM management system manages and intercepts processing instructions issued by the VM and, if deemed safe, forwards the relevant transactions to the NIC chip. This management of the VM's execution instructions ensures the security and reliability of the SoC system while the VM is running, but it also limits the VM's performance in interacting with the NIC system.

[0003] One way to improve the business interaction performance of virtual machines is to connect the network card system directly to the first virtual machine. At this time, the processing instructions for related business issued by the first virtual machine do not need to be intercepted by the virtual machine management system. However, in the case of virtualization direct connection, when the first virtual machine performs stateful business interaction, if the business interaction state information of the first virtual machine is stored in the kernel state of the host system, the first virtual machine after direct connection can modify the relevant business interaction state information, thereby causing security and reliability problems of the chip system; if the business interaction state information of the first virtual machine is stored in the memory space of the network card system, the first virtual machine can be prevented from causing security and reliability problems of the chip system, but it will greatly increase the difficulty of hot migration of the first virtual machine.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a control method, a network card system, a host system, and a chip system. When virtualization is passed through, the embodiments of the present application reduce the difficulty of hot migration of the first virtual machine while avoiding security and reliability issues of the first virtual machine.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a control method based on a network card system, the control method comprising: receiving first indication information. The first indication information is used to indicate an identifier and a first physical area address of a first virtual machine. The first virtual machine runs on a host system. The first physical area address is a storage address in a host memory of the host system in units of physical pages, and the first physical area address is non-writable for the first virtual machine. First table entry data includes service interaction status information of the first virtual machine. The first indication information is stored.

[0008] In an embodiment of the present application, a host system applies for a first physical area address in host memory. First table entry data for a first virtual machine is stored in the first physical area address. The host system and / or the network interface card system stores the first table entry data in the first physical area address to facilitate storage resource management of the memory space occupied by the first virtual machine. In the case of direct communication between the first virtual machine and the network interface card system, to prevent security and reliability issues caused by the first virtual machine modifying the first table entry data in the host memory, the first physical area address must be non-writable for the first virtual machine. Furthermore, because the host system and the network interface card system process data in units of physical pages during operation, the first physical area address must also be a storage area address in units of physical pages. Otherwise, if a certain memory area in the first physical area address only occupies a portion of the memory area of ​​a physical page, there is a risk that instructions of the first virtual machine will modify the first physical area address when modifying another portion of the memory area of ​​the physical page. During operation of the network interface card system, first indication information is obtained and stored. Subsequently, during operation of the network interface card system, relevant service interaction status information can be directly obtained from the first physical area address in the host system based on the first indication information. Through the above-described implementation, the embodiments of the present application can avoid security and reliability issues associated with the operation of the first virtual machine when the network card system directly communicates with the first virtual machine. Furthermore, the difficulty of hot migration of the first virtual machine is reduced. Finally, storing the first table entry data in the host system also facilitates the management of the first virtual machine's memory resources.

[0009] In some possible implementations, in a control method based on a network card system, after storing the first indication information, the first indication information can be used to assist the first virtual machine in exchanging messages with other network nodes. During the message exchange process, the messages sent by the other network nodes carry the indication information. The indication information can be control indication information or data processing indication information. When the indication information is data processing indication information, a data processing operation is performed on the host memory based on the data processing indication information. The data processing operation can be categorized as a write data operation, a read data operation, or the like, depending on the data type.

[0010] In one possible embodiment, the control method further includes: receiving a first message; discarding the first message; the first message carrying data processing instruction information; the data processing instruction information indicating a data processing type and a second physical area address; the data processing type corresponding to the first message is a write data operation, and the second physical area address partially or entirely belongs to the first physical area address; in an embodiment of the present application, when the instruction information carried by the first message is data processing instruction information and the corresponding data processing memory is a write data operation, to ensure that the write data operation during interaction between the first virtual machine and other network nodes does not modify the first table entry data within the first physical area address, the control method may verify the received message. Specifically, after receiving the first message, the data processing type is determined. If it is a read data operation, the first physical area address will not be modified and the message can be executed normally. If the data processing type of the first message is a write data operation, it is necessary to determine whether the write data operation is a write to the first physical area address. If the write data operation is a write to a memory area outside the first physical area address, the first table entry data will not be modified and can be executed normally. If the data write operation involves writing to part or all of the first physical area address, the write operation may involve writing new data to a blank memory area within the first physical storage area, or it may involve modifying data within the first physical storage area. Both methods carry the risk of modifying the first table entry data. To ensure security and reliability, the first message that writes to the first physical area address needs to be discarded.

[0011] In a possible implementation, the control method further includes: obtaining business interaction status information from the first physical area address of the host memory according to the first message and the first indication information. Obtaining data processing indication information according to the business interaction status information. In an embodiment of the present application, the first table item data is business interaction status information about business interaction between the first virtual machine and other network nodes. Then, when the network card system obtains the first message sent by other network nodes, it is necessary to parse the first message according to the business interaction status information to obtain data processing indication information and control indication information, etc. In this process, the network card system needs to obtain relevant business interaction status information from the corresponding first physical area address in the host memory based on the first physical area address in the first indication information.

[0012] In a possible implementation, the control method further includes: receiving a first instruction. The first instruction is used to instruct a write operation to the first physical area address. According to the first instruction, a second write instruction is sent to the host memory. The second write instruction is used to instruct the host memory to write data to the first physical area address, or to modify the service interaction status information in the first physical area address. In an embodiment of the present application, the host system may send a first instruction to the network card system, and indicate to the network card system through the first instruction that a write operation needs to be performed on the first sequence area address. In the control method based on the network card system, after obtaining the first instruction, a second write instruction is generated according to the first instruction. A write operation is performed on the first physical area address in the host memory through the second write instruction. The write operation can write data to the first physical area address, or modify the service interaction status information in the first physical area address.

[0013] In a second aspect, an embodiment of the present application further provides a control method. The host system includes a host processor and a host memory. A first virtual machine and a virtual machine management system are running on the host processor. The control method is based on the host processor. The control method includes: applying for a first physical area address from the host memory in units of physical pages. The first physical area address is used to store first table entry data, and the first physical area address is non-writable for the first virtual machine. The first table entry data includes business interaction status information of the first virtual machine. First indication information is sent to the network card system based on the virtual machine management system. The first indication information is used to indicate the identifier of the first virtual machine and the first physical area address.

[0014] In an embodiment of the present application, in a host processor-based control method, the host processor requests a first physical area address from a host memory to store service interaction status information of a first virtual machine. A first indication signal is generated based on the first physical area address and an identifier of the first virtual machine. The first indication signal is sent to a network interface card system via a virtual machine management system. The first physical area address is non-writable for the first virtual machine. During subsequent service interactions between the first virtual machine and other network nodes, the network interface card system can obtain service interaction status information based on the first indication signal to assist the first virtual machine in performing service interactions.

[0015] In one possible implementation, the above-mentioned application for the first physical area address from the host memory in units of physical pages includes: based on the first virtual machine, applying for the first physical area address from the host memory in units of physical pages, and sending a second indication message to the virtual machine management system. The second indication message is used to indicate the first physical area address. In an embodiment of the present application, after the first virtual machine is running, it can directly apply for the first physical area address from the host memory after calculating the required memory size of the first physical area address. The first virtual machine then indicates the first physical area address related to the virtual machine management system through the second indication message. This allows the virtual machine management system to manage the first physical area address and generate the first indication message to the network card system.

[0016] In one possible embodiment, the above-mentioned application for the first physical region address from the host memory in units of physical pages includes: based on the first virtual machine, sending second indication information to the virtual machine management system. The second indication information is used to indicate the first physical region address. Based on the virtual machine management system, the first physical region address is applied to the host memory in units of physical pages according to the second indication information. In this embodiment of the present application, after the first virtual machine is running, after calculating the required memory size of the first physical region address, the first physical region address can be notified to the virtual machine management system in the form of the second indication information. The virtual machine management system then applies for the first physical region address from the host memory.

[0017] In some possible implementations, depending on different methods of applying for the first physical area address, the control method may perform different memory resource management methods on the first physical area address:

[0018] In a possible implementation, the control method further includes: performing conversion between virtual addresses and physical addresses according to a first memory mapping table. Based on the virtual machine management system, the first page table entry is configured at a position corresponding to the first virtual machine in the first memory mapping table. The first page table entry is used to indicate the mapping relationship between the first physical area address and the virtual address. The attribute of the first page table entry is set to a non-writable attribute of the first virtual machine. In an embodiment of the present application, the control method can implement the conversion of the virtual address executable by the host processor to the physical address of the host memory based on the first memory mapping table through the first memory manager of the host processor. When applying for the first physical area address based on the first virtual machine or the virtual machine management system, the first page table entry corresponding to the first physical area address can be registered under the memory resources of the first virtual machine. At this time, the first physical area address is actually the memory resource occupied by the business interaction of the first virtual machine. In this way, it is convenient to manage the memory resources actually used by the users of the first virtual machine.

[0019] In one possible implementation, the control method further includes: performing conversion between virtual addresses and physical addresses according to a first memory mapping table. Based on the virtual machine management system, the first page table entry is configured at a position corresponding to the virtual machine management system in the first memory mapping table. The first page table entry is used to indicate the mapping relationship between the first physical area address and the virtual address. In an embodiment of the present application, when applying for the first physical area address based on the virtual machine management system (for example, applying for the first physical area address based on the PF driver of the virtual machine association system), the first page table entry corresponding to the first physical area address is registered under the memory resources of the virtual machine management system.

[0020] Exemplarily, the control method further includes: based on the virtual machine management system, changing the second page table entry to a third page table entry. The second page table entry is a page table entry corresponding to the first virtual machine in the first memory mapping table. The third page table entry is a page table entry corresponding to the virtual machine management system in the first memory mapping table. In an embodiment of the present application, when the first physical area address is registered under the memory resources of the virtual machine management system, the memory resources for the operation of the virtual machine management system are occupied. However, this part of the memory resources is actually used for the operation of the first virtual machine. In order to facilitate the statistics and management of memory resources, a part of the memory resources of the first virtual machine (i.e., the second page table entry) can be changed to the memory resources of the virtual machine management system (i.e., the third page table entry). In this way, it is convenient to manage the memory resources actually used by the user of the first virtual machine.

[0021] In a possible implementation, during an actual operation, the host system-based control method may need to perform a write operation on the first physical area address to write new data or modify data.

[0022] Exemplarily, the control method further includes: sending a third write instruction to the host memory based on the virtual machine management system. The third write instruction is used to instruct the host memory to write data to the first physical area address, or to modify the service interaction status information in the first physical area address. In this embodiment of the present application, the first virtual machine does not have permission to write attributes to the first physical area address. When the host system needs to modify the first physical area address in the host memory, the relevant write operation can be performed through the virtual machine management system running in kernel mode.

[0023] Exemplarily, the control method further includes: sending a first instruction to the network card system based on the first virtual machine and / or the virtual machine management system. The first instruction is used to instruct a write operation to the first physical area address. In an embodiment of the present application, when the first physical area address needs to be modified, the control method can send the first instruction to the network card system based on the host processor. The first instruction instructs the network card system to modify the first physical area address. After receiving the first instruction, the network card system modifies the first physical area address.

[0024] In a third aspect, an embodiment of the present application further provides a network card system, comprising a network card processor and an interface. The network card processor is configured to: input a first indication signal from the interface. The first indication information is configured to indicate an identifier of a first virtual machine and a first physical area address. The first virtual machine runs on a host system. The first physical area address is a storage address in a host memory of the host system in units of physical pages. The first physical area address is configured to store first table entry data, and the first physical area address is a non-writable attribute for the first virtual machine. The first table entry data includes business interaction status information of the first virtual machine. The first indication information is stored. In one possible embodiment, the network card system is further configured to: receive a first message and discard the first message. The first message carries data processing indication information. The data processing indication information is configured to indicate a data processing type and a second physical area address. The data processing type corresponding to the first message is a write data operation, and the second physical area address partially or entirely belongs to the first physical area address.

[0025] In a possible implementation, the network card system is further configured to: obtain service interaction state information from a first physical area address of a host memory according to the first message and the first indication information, and obtain data processing indication information according to the service interaction state information.

[0026] In some possible implementations, during actual service interaction, the host system may update the service interaction state information stored in the first physical area address according to the interaction result of the first message. In this case, the host system may perform relevant update processing through the network card system.

[0027] Exemplarily, the network card system is further configured to: receive a first instruction instructing a write operation to a first physical area address; and send a second write instruction to a host memory based on the first instruction. The second write instruction instructs the host memory to write data to the first physical area address or to modify service interaction status information in the first physical area address.

[0028] Exemplarily, the network card system may be a network card chip, a data processor (DPU) with network offloading and data processing offloading functions, a system on chip (SoC) with network card functions, or a very large scale integration circuit (VLSI) with network card functions, etc.

[0029] Exemplarily, the fourth host system D1 and the fourth network card system D2 can be installed on the same circuit board, or can be separately installed on different circuit boards. Exemplarily, the fourth host system D1 can be installed on a circuit board; and the fourth network card system D2 can be pluggably installed on the circuit board of the fourth host system D1 in a hot-swappable manner.

[0030] In a fourth aspect, an embodiment of the present application further provides a host system comprising a host processor and a host memory. A first virtual machine and a virtual machine management system are running on the host processor. The host processor is configured to request a first physical area address from the host memory in units of physical pages. The first physical area address is used to store first table entry data, and the first physical area address is non-writable for the first virtual machine. The first table entry data includes service interaction status information of the first virtual machine. First indication information is sent to the network card system based on the virtual machine management system. The first indication information is used to indicate an identifier of the first virtual machine and a first physical area address.

[0031] In some possible implementations, the host processor may request a first physical region address from the host memory through the first virtual machine. Exemplarily, the host processor is further configured to: request the first physical region address from the host memory in units of physical pages based on the first virtual machine, and send second indication information to the virtual machine management system. The second indication information is used to indicate the first physical region address.

[0032] In one possible implementation, the host processor may request the first physical region address from the host memory through the virtual machine management system. Exemplarily, the host processor is further configured to: send second instruction information to the virtual machine management system based on the first virtual machine. Based on the second instruction information, the virtual machine management system requests the first physical region address from the host memory in units of physical pages.

[0033] In some possible implementations, depending on different methods of applying for the first physical area address, memory resource management may be performed on the first physical area address in different ways:

[0034] In one possible example, the host processor further includes a first memory manager. The host processor is further configured to: based on the first memory manager, convert between virtual addresses and physical addresses according to a first memory mapping table. Based on the virtual machine management system, configure a first page table entry in the first memory mapping table at a location corresponding to the first virtual machine. The first page table entry is configured to indicate a mapping relationship between a first physical region address and a virtual address. An attribute of the first page table entry is set to be non-writable by the first virtual machine.

[0035] In one possible example, the host processor further includes a first memory manager. The host processor is further configured to: convert between virtual addresses and physical addresses based on a first memory mapping table, based on the first memory manager. Based on the virtual machine management system, configure the first page table entry in the first memory mapping table at a location corresponding to the virtual machine management system. The first page table entry is configured to indicate a mapping relationship between the first physical region address and the virtual address.

[0036] Exemplarily, the host processor is further configured to: based on the virtual machine management system, change the second page table entry to a third page table entry, wherein the second page table entry is a page table entry in the first memory mapping table corresponding to the first virtual machine, and the third page table entry is a page table entry in the first memory mapping table corresponding to the virtual machine management system.

[0037] In some possible implementations, the host system further includes a second memory manager. The second memory manager is used to convert between virtual addresses and physical addresses according to a second memory mapping table. In an embodiment of the present application, the network card system can access the host memory based on the second memory manager in the host system. At this time, the virtual machine management system also needs to write a first page table entry into the second memory mapping table. After the first page table entry is stored in the second memory mapping table, when the network card system accesses the first physical area address based on the first indication information, when the first indication information includes a virtual address (such as the client physical address of the first virtual machine, i.e., GPA), the second memory manager can implement a mapping conversion between the first physical area address and the virtual address to ensure normal execution of the access. Exemplarily, the virtual machine management system can set the first page table entry in the second memory mapping file to a non-writable attribute for the first virtual machine to prevent the first virtual machine from modifying the first page table entry in the second memory mapping file, or to prevent the first virtual machine from implementing a write operation on the first physical area address through the second memory mapping file.

[0038] In a possible implementation, during an actual operation, the host system may need to perform a write operation on the address of the first physical area to write new data or modify data.

[0039] In some possible examples, the host processor may perform a write operation on the first physical area address based on the virtual machine management system. Exemplarily, the host processor is further configured to: send a third write instruction to the host memory based on the virtual machine management system. The third write instruction is configured to instruct the host memory to write data to the first physical area address or to modify service interaction status information in the first physical area address.

[0040] In some possible examples, the host processor may perform a write operation on the first physical area address through the network card system. Exemplarily, the host processor is further configured to: send a first instruction to the network card system based on the first virtual machine and / or the virtual machine management system. The first instruction is configured to instruct the write operation to be performed on the first physical area address.

[0041] In a fifth aspect, an embodiment of the present application further provides a chip system, which includes the network card system as described in the third aspect above and the host system as described in the fourth aspect above. For example, the host system and the network card system can be installed on the same circuit board, or they can be installed separately on different circuit boards. For example, the host system can be installed on a circuit board; the network card system is pluggable and mounted on the circuit board of the host system in a hot-swappable manner.

[0042] In a sixth aspect, an embodiment of the present application further provides an electronic device, which includes a chassis and a chip system as described in the fifth aspect above. Exemplarily, a circuit board is provided in the chassis. In some examples, the host system and the network card system are both installed in the chassis and are installed on the same circuit board. In some examples, the host system and the network card system are both installed in the chassis and are installed on different circuit boards. In some examples, the host system and the network card system are both installed in the chassis, and the network card system is pluggable on the circuit board of the host system in a hot-swappable manner. In some examples, the host system is installed in the chassis. The network card system is pluggable on a hot-swappable interface outside the chassis of the electronic device in a hot-swappable manner, and is coupled to the host system through the hot-swappable interface of the electronic device.

[0043] In a seventh aspect, embodiments of the present application further provide a computer-readable storage medium comprising instructions. When the instructions are executed on a processor, the processor executes the control method described in the first aspect and / or the control method described in the second aspect.

[0044] In an eighth aspect, an embodiment of the present application further provides a computer program product, which, when executed on a computer, enables the computer to execute the control method described in the first aspect and / or the control method described in the second aspect.

[0045] Regarding the technical principles and friendship effects of the third, fourth, fifth, sixth, seventh and eighth aspects, please refer to the relevant descriptions of the first and second aspects above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a schematic structural diagram of a chip system based on a traditional data reading method;

[0047] FIG2 is a schematic structural diagram of a chip system based on DMA;

[0048] FIG3 is a schematic diagram of a service interaction between a first chip system and a second chip system based on DMA;

[0049] FIG4 is a schematic diagram of service interaction between a first chip system and a second chip system based on RDMA;

[0050] FIG5 is a schematic diagram of a non-virtualized system network architecture;

[0051] FIG6 is a schematic diagram of a virtualized system network architecture;

[0052] FIG7 is a schematic diagram of a mapping relationship between virtual addresses and physical addresses under virtualization;

[0053] FIG8 is a schematic diagram of the architecture of a virtualized network card system directly connected to a virtual machine;

[0054] FIG9 is a schematic structural diagram of a third chip system provided in an embodiment of the present application;

[0055] FIG10 is a schematic structural diagram of a fourth chip system provided in an embodiment of the present application;

[0056] FIG11 is a schematic structural diagram of another fourth chip system provided in an embodiment of the present application;

[0057] FIG12 is a flow chart of a control method according to an embodiment of the present application;

[0058] FIG13 is a second flow chart of another control method provided in an embodiment of the present application;

[0059] FIG14 is a third flow chart of another control method provided in an embodiment of the present application;

[0060] FIG15 is a fourth flow chart of another control method provided in an embodiment of the present application;

[0061] FIG16 is a fifth flow chart of another control method provided in an embodiment of the present application;

[0062] FIG17 is a sixth flow chart of another control method provided in an embodiment of the present application;

[0063] FIG18 is a seventh flow chart of another control method provided in an embodiment of the present application;

[0064] FIG19 is a flow chart of another control method provided in an embodiment of the present application;

[0065] FIG20 is a ninth flowchart of another control method provided in an embodiment of the present application;

[0066] FIG21 is a flowchart diagram 10 of another control method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc. The terms "exemplary" or "for example" involved in the embodiments of the present application are used to indicate examples, illustrations or explanations. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. To be precise, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific way. The terms "coupling" and "connection" involved in the embodiments of the present application should be understood in a broad sense. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices. The "bus" involved in the embodiments of the present application can be understood as one bus or multiple buses. At the same time, it can be a data bus, a control bus, etc.

[0068] First, some basic concepts involved in the embodiments of this application are explained:

[0069] Processing chips can be based on different chip architectures, such as the Advanced RISC Machine (ARM) architecture and the X86 architecture. To ensure standardized, efficient, and fast operation of the processing chips, these chip architectures all have an instruction set (ISA). This ISA is a standardized language required for the processing chip's operation, consisting of a variety of pre-defined instructions, broadly categorized as arithmetic instructions, data movement instructions, and control instructions. Applications (APPs) run on the processing chips. The operations of the APPs on the processing chips are compiled and interpreted as individual instructions, which are ultimately executed by the processing chips. Because of the instruction set, failures in some instructions have minimal impact on the processing chip's operating system, while failures in other instructions can cause significant issues, such as crashes and reboots. Therefore, different permissions should be assigned to different instructions based on their importance. Lower-privilege instructions should be made available to APPs to ensure the stability of the processing system. Taking the X86 architecture as an example, instruction permissions can be divided into four levels, from highest to lowest: Ring0, Ring1, Ring2, and Ring3. Ring0 instructions generally have the highest permissions, also known as privileged instructions, and are available to kernel mode. Ring1 and Ring2 instructions have higher permissions and are available to processor drivers and other devices. Ring3 instructions have the lowest permissions, also known as unprivileged instructions, and are available to user mode. Kernel mode and user mode represent different operating states of the processor. Applications run in user mode. In some operating systems (such as Linux), only Ring0 and Ring3 instructions exist. Ring0 instructions correspond to kernel mode and driver programs, while Ring3 instructions correspond to user mode. In real-world applications, when an application running in user mode needs to run a higher-privilege service, it must initiate a request from user mode to kernel mode via a system call. After initiating the system call, the processor switches to kernel mode to execute the corresponding higher-privilege service.

[0070] Memories can be divided into two categories: main memory and auxiliary memory. The main memory directly exchanges information with the processing chip. A memory management unit (MMU) program is installed in the processing chip. The MMU manages the mapping between virtual addresses and physical addresses based on the address mapping page table, dividing the physical address into physical pages, and each physical page is mapped to a corresponding virtual address page table. When the processing chip is working, the MMU provides the processing chip with the logical address (i.e., virtual address) for the program to run, using each virtual address page table as a unit. The process of the processing chip accessing the main memory is based on the virtual address. After the virtual address is converted into the corresponding physical address in the main memory by the memory management unit (MMU) program, the main memory is accessed.

[0071] As shown in Figure 1, the chip system includes a first subsystem X1 and a second subsystem X2. The first subsystem X1 includes a processor 100 and a memory 200. The processor 100 and the second subsystem X2 are each coupled to the memory 200 via a first bus, BUS1. The memory 200 is a memory device of the processor 100. When the second subsystem X2 writes data to or reads data from the memory 200 of the first subsystem X1, the data link and control link are shown by the dashed lines in the figure. As can be seen, both write and read operations require the participation of the processor 100. For example, when the second subsystem X2 reads data from the memory 200, the second subsystem X2 sends a data read instruction to the processor 100 via the first bus, BUS1. In response to the data read instruction, the processor 100 reads the relevant data from the memory 200 and caches the data in the processor 100's cache. The second subsystem X2 then reads the relevant data from the processor 100's cache to complete the data read. Similarly, when the second subsystem X2 needs to write data to the memory 200, the processor 100 is also needed as a transfer point to write the data to the memory 200. In this way, the processor 100 acts as a data transfer point between the memory 200 and the second subsystem X2, and needs to perform data transfer tasks, that is, writing the data that the second subsystem X2 needs to write from the cache to the memory 200 to assist in completing the data write process of the second subsystem X2 to the memory 200; or, caching the data in the memory 200 into the cache to assist in completing the data read process of the second subsystem X2 to the memory 200. This data transfer operation will occupy a certain performance of the processor 100, and the proportion of performance occupied varies with the frequency of data transfer, the size of the data being transferred, etc. However, in actual scenarios, the processor 100 mainly serves as a device for data processing and logical operations of the first subsystem X1. Excessive data transfer operations will reduce the performance of the first subsystem X1, and thus reduce the performance of the chip system. To this end, the industry has proposed a direct memory access (DMA) technology.

[0072] DMA refers to the ability of the second subsystem X2 to read and write data from the memory of the first subsystem X1 without requiring the processor 100 in the first subsystem X1 to perform data transfer operations. Instead, a separate data controller is provided to assist in the data transfer operations. As shown in Figure 2, the data controller 300 is coupled to devices such as the memory 200 via the first bus BUS1. In an application scenario based on DMA technology, the second subsystem X2 establishes a data link with the memory 200 through the data controller 300, and a control link with the processor 100 through the data controller 300. When the second subsystem X2 needs to write data to the memory 200, the data controller 300 writes the data to the memory 200 via the data link. Simultaneously, the data controller 300 and the processor 100 exchange information related to the data write operation, such as control commands. In some instances, the data controller 300 can be located in either the first subsystem X1 or the second subsystem X2. Taking the data controller 300 disposed in the second subsystem X2 as an example, the first subsystem X1 can be the host system in the chip system, performing data processing and logical operations. The second subsystem X2 can be a network interface card (NIC) system with integrated DMA and network interface card (NIC) functions. This implementation method, which offloads data handling tasks from the processor 100 in the host system to the NIC system, is also referred to as data processing offloading. Offloading, in this context, refers to transferring functions and / or transactions required by a device to another device to improve its performance. This NIC system can also be referred to as an offload NIC.

[0073] A chip system based on a network card system can serve as a network node. Messages can be exchanged between multiple network nodes. As shown in Figure 3, a first chip system A includes a first host system A1 and a first network card system A2. The first host system A1 includes a first host processor A11 and a first host memory A12. A second chip system B includes a second host system B1 and a second network card system B2. The second host system B1 includes a second host processor B11 and a second host memory B12. The first chip system A interacts internally via the first bus BUS1. The second chip system B interacts internally via the second bus BUS2. The first chip system A and the second chip system B can serve as two communication nodes and exchange messages via the first network card system A2 and the second network card system B2.

[0074] When the first node corresponding to the first chip system A and the second node corresponding to the second chip system B as shown in Figure 3 perform business interaction based on the traditional message interaction method, in the case of DMA technology, the interaction between the two nodes still relies heavily on the host system's processor to encapsulate and parse the message. To this end, the industry has proposed the TCP Offload Engine (TOE), remote direct memory access (RDMA) and unified bus (UB) protocols. TOE offloads protocols such as the transport layer and network layer from the host system's processor network to the network card system, and presents the message encapsulation and parsing on the network card system, and performs message encapsulation and parsing based on the network card system to improve the work efficiency of the host system's host processor. RDMA also offloads the message encapsulation and parsing from the host system's processor network to the network card system. The kernel bypass mechanism of RDMA enables the APP and the network card system to read and write memory data directly over the data link. RDMA's zero-copy memory mechanism enables direct memory data reads between two network nodes, reducing the processor's operational burden and improving processing efficiency. However, within the control link, a small number of control signals still need to be processed in kernel mode by the host system's processor. In RDMA, apps can access the memory of remote network nodes, and remote network nodes can be read without the involvement of processes or processors on the remote network nodes. Common RDMA technologies include the Ethernet-based RDMA over converged Ethernet (RoCE) protocol. UB and RDMA have similar implementation functions. For example, consider the case of a first node corresponding to a first chip system A sending a message to a second node corresponding to a second chip system B based on RDMA technology. As shown in Figure 4, the first network card system A2, based on a DMA read data processing operation, reads the data to be transmitted from the user-mode storage space of the first host memory A12. The first network card system A2 encapsulates the data to be transmitted into a message, generating a message, and then sends the message to the second network card system B2 of the second chip system B. The second network card system B2 parses the received message to obtain the data to be transmitted and writes the data to be transmitted into the user-mode memory space of the second host memory B12 based on the DMA write data processing operation.

[0075] Virtualization is the foundation of cloud computing technology. In cloud computing, virtualization is used to virtualize the physical hardware resources (including computing, storage, and network resources) of electronic devices (such as server devices) to create multiple independently running virtual machines (VMs). A VM is an independent virtual processing device built by utilizing the computing, storage, and network resources of an electronic device. As shown in Figure 5, before virtualization, the computer system architecture of an electronic device can be divided from top to bottom into the application layer, the operating system (OS) layer, and the hardware layer. The OS layer is also known as the host OS layer. The hardware layer, based on the electronic device's electronic components (such as the host system including the processor and memory, and the network interface card system), provides computing, storage, and network resources to the upper layers of the architecture. The OS layer can run in the kernel state of the electronic device, while the application layer can run in the user state of the electronic device. After virtualization, as shown in Figure 6, a resource management layer and a virtualization layer are virtualized above the hardware layer. The virtualization layer contains at least one VM. The resource management layer includes a virtual machine manager (VMM) to manage each VM. In some scenarios, the VMM is also called a hypervisor. Different operating systems correspond to different hypervisors. As shown in Figure 6, each VM includes a guest operating system (OS) and an application.

[0076] Memory virtualization refers to the virtualization of a guest virtual address (GVA) and guest physical address (GPA) for each VM. Each VM operates based on independent virtual computer logic. The GVA is the virtual address of the processing chip when the VM is operating. The GPA is the physical address of the memory when the VM is operating. In addition, memory virtualization introduces the concepts of the host virtual address (HVA) and the host physical address (HPA). The HVA is the virtual address of the processing chip when the VM is operating. The HPA is the physical address of the memory when the VM is operating. As shown in Figure 7, when a VM is operating, the application program in the VM sends instructions to the virtual memory management unit (VMMU) program in the VM based on the GVA. The VMMU converts the GVA to the GPA. The host OS, where the VMM resides, then converts the GPA to the HVA based on the virtual extended page tables (EPT). The hardware-layer MMU then maps the HVA to the HPA in the memory. Because each VM operates as an independent processing system, the following issues may arise when issuing instructions within a VM's app: The VM's guest OS may issue Ring 0 privileged instructions. The guest OS considers issuing Ring 0 privileged instructions normal, but in reality, VMs are only authorized to issue Ring 3 privileged instructions. To prevent privileged instructions issued by a VM from impacting other VMs, the VMM must intercept and manage instructions issued by the VM, as shown in Figure 6.

[0077] Virtualization passthrough allows VMs to directly connect to the network interface card (NIC). One approach is to assign the actual NIC system to the VM on the physical architecture. Another approach is single root I / O virtualization (SR-IOV). SR-IOV is a standard for sharing PCIe interface functions with virtual machines. SR-IOV provides VMs with independent memory spaces, interrupts, and DMA streams, bypassing the VMM for data access. The SR-IOV protocol introduces two types of functions: physical functions (PFs) and virtual functions (VFs). PFs contain full PCIe functionality, including SR-IOV expansion capabilities, and can be used for SR-IOV configuration and management. VFs contain lightweight PCIe functions. Each VF has its own dedicated PCI configuration area and may share the same physical resources with other VFs. PF drivers vary depending on the hypervisor and generally require higher privileges than ordinary VMs to operate them. The PF driver incorporates all the functionality of traditional data interface drivers, enabling the hypervisor to access the I / O resources of electronic devices. By calling the PF driver, relevant operations can be executed, thereby affecting the entire electronic device. As shown in Figure 8, the network card system 2 includes a network card processor 21 and multiple interfaces. Among these multiple interfaces, the network card processor 21 can provide multiple PCIe function interfaces to the host system 1 side through SR-IOV technology. The PCIe interface in the network card system 2 that directly interacts with the PF driver of the host system 1 is the PF interface. The PCIe interface in the network card system 2 that directly connects to the VM in the host system 1 is the VF interface. SR-IOV technology can be considered the virtualization of the network card system 2. The direct connection between the VM and the network card system 2 can maximize the performance of the VM's related data communication and processing. However, with the direct connection between the VM and the network card 21, the instructions issued by the VM through the VF interface are not intercepted and managed by the VMM, which may affect the security and reliability of the VF interfaces of other VMs.

[0078] Stateless service interaction refers to the exchange of messages between two network nodes, where the processing of these messages by the network nodes does not depend on specific state information and can be processed independently without being affected. Stateful service interaction refers to the exchange of messages between two network nodes, where different messages are processed with dependencies. The processing of these messages requires a specific working state. In actual processing, message processing relies on relevant state information. Furthermore, the content of this state information may change during the message processing process. When a network node's VM interacts with another network node Q1 based on the network card system, this state information may include address mappings (such as mappings between GVA, GPA, HVA, and HPA addresses), relevant network protocol control information, and network state control information. Generally, this state information can be stored in a mapping state table. In stateful interactions, before virtualization is implemented, due to the limited memory space of the network card system, service interaction state information is typically stored in kernel-mode memory within the host system's storage. This prevents apps from modifying this state information, thereby ensuring the reliability and security of stateful service interactions. However, in public cloud applications, if the network card system is not virtualized (i.e., the VM does not directly communicate with the network card system), relevant state information can still be stored in kernel-mode memory within the storage system. VM users do not modify this state information. However, if virtualization is accelerated based on the network card system, that is, when the network card system is directly connected to the VM, numerous issues arise. For example, VM users can launch network attacks through the corresponding VF driver and VF interface. Furthermore, after virtualization is directly connected, VM users can modify any information in kernel-mode memory. This creates the possibility of malicious modification by VM users and the possibility of the modified information affecting other VMs. Therefore, for stateful interactions, after the network card system is directly connected to the VM, how to save the VM's related business interaction status information and ensure that the VM's stateful business interaction does not cause security issues to the chip system is a difficult problem.

[0079] Virtual machine migration, a technology that moves a VM running on a source electronic device to a destination electronic device, allows the VM to run normally on the destination device. A complete computer system consists of a processor, memory, disk, and network interface card (NIC), with disks and NICs both considered I / O devices. Virtual machine migration technology migrates the processor state information, memory data, and I / O device state information of a VM from one physical electronic device to another. Virtual machine migration technology is widely used in server cluster management in cloud computing data centers, enabling load balancing, disaster recovery, and online upgrades. Virtual machine migration can reduce cloud data center operating costs and improve server cluster management efficiency. Virtual machine migration can be divided into static migration and dynamic migration. Static migration, also known as cold migration, involves shutting down the VM on the source electronic device and then copying the VM's processor state information, memory data, and I / O device state information from the source device to the destination device. The VM is then started and run on the destination device. Cold migration typically requires interrupting the VM's service for several minutes or even longer. Live migration, also known as hot migration, involves migrating part of a VM's data while downtime is brief (e.g., a few milliseconds). All other data is dynamically copied while the VM is operating normally. The VM's memory data accounts for the vast majority of the data involved in hot migration. During hot migration, memory data is typically copied and migrated during the dynamic copy phase. Processor status information and I / O device status information are also copied and migrated during the relatively short downtime. Hot migration does not interrupt the services running on the virtual machine, and can improve service availability compared to cold migration.

[0080] In order to solve the data security and system reliability issues brought about by VM during virtualization pass-through, the embodiment of the present application also proposes a first electronic device. The first electronic device includes a third chip system. As shown in Figure 9, the third chip system C includes a third host system C1 and a third network card system C2. The third host system C1 includes a third host processor C11 and a third host memory C12. The third chip system C internally communicates via a third bus BUS3. The first virtual machine VM1 runs in the third host processor C11. The third host memory C12 stores memory data related to the operation of the first virtual machine VM1. The third network card system C2 includes a third network card processor C21 and a third network card memory C22. The third network card memory C22 stores first table entry data. The first table entry data includes business interaction status information corresponding to the first virtual machine VM1 when performing business interaction. The business interaction status information may include relevant table entry data of state control information, and relevant table entry data of the storage address of the state control information.

[0081] For example, the first virtual machine VM1 is configured with a send queue (SQ) and a receive queue (RQ). When the first virtual machine VM1 needs to send a transaction to another network node Q1, the SQ is used to store relevant information related to the transaction sent by the first virtual machine VM1 to the other network node Q1. The RQ is used to store relevant information related to the transaction received by the first virtual machine VM1 from the other network node Q1. When the first virtual machine VM1 needs to receive relevant messages from the other network node Q1, the relevant received transaction information that needs to be placed in the RQ is placed in the RQ, and all other relevant service interaction status information is stored in the third network card memory C22 of the network card system C2. The third network card processor C21 obtains the relevant received transaction information from the RQ of the first virtual machine VM1. After receiving the corresponding message, it obtains the service interaction status information from the third network card memory C22 and performs message parsing on the received message based on the service interaction status information. It then obtains the indication information sent by the other network node Q1. This indication information may be control indication information for a control link or data processing indication information for a data link. Based on the service interaction status information and indication information, the third NIC processor C21 can exchange control information on the control link with the first virtual machine VM1 and / or exchange data information on the data link with the first virtual machine VM1. Similarly, when the first virtual machine VM1 needs to send relevant messages to other network nodes Q1, the relevant send transaction information that needs to be placed in the SQ is placed in the SQ, and all other relevant service interaction status information is stored in the third NIC memory C22 of the NIC system C2. The third NIC processor C21 obtains the relevant receive transaction information from the SQ of the first virtual machine VM1, performs relevant message encapsulation, and then sends the encapsulated message to the other network node Q1.

[0082] In the embodiment of the present application as shown in FIG9 , the third network card processor C21 of the third network card system C2 only needs to pay attention to the security issues of transactions in SQ and RQ during the execution of business interactions between the first virtual machine VM1 and other network nodes Q1. Because the business interaction status information is stored in the third network card memory C22 carried by the third network card processor C21, during the business interaction process, the relevant operations of the first virtual machine VM1 will not modify these business interaction status information, and the third network card processor C21 does not need to verify and pay attention to the legitimacy of these business interaction status information. Through the embodiment shown in FIG9 , it is possible to solve the security issues brought about by the running operations of the first virtual machine VM1 in the case of virtualization pass-through. However, under this implementation method, there are the following problems:

[0083] Problem 1: Reduced feasibility of hot migration. For example: Hot migration of the first virtual machine VM1 will be very troublesome. A special program needs to be set up to control the third network card processor C21 to read the business interaction status information of the first virtual machine VM1 from the third network card memory C22. When there are many business interaction connections created between the first virtual machine VM1 and other network nodes Q1, the amount of business interaction status information that needs to be synchronized during the hot migration process will also increase. Too much business interaction status information will increase the downtime of the first virtual machine VM1, resulting in a decline in service experience, and even causing hot migration failure. For example: When the business interaction status information of multiple VMs running in the third host system C1 is stored in the third network card memory C22 of the third network card system C2, how to distinguish the corresponding relationship between the stored business interaction status information and the VM is also a problem. And, after hot migration, how to distinguish the corresponding relationship between the business interaction status information and the VM on the destination electronic device is also a problem.

[0084] Problem 2: Storage resources are crucial assets in public cloud services. VMs provide users with computing and storage resources. Service interaction status information contains data related to service interactions between the first virtual machine VM1 and other network nodes Q1. This data is actually used by VM users. However, this data occupies the storage resources of the third network interface card system C2. This situation can lead to confusion in memory resource management for public cloud operations.

[0085] In order to reduce the difficulty of hot migration of VM1 while avoiding the data security and system reliability issues brought about by VM1 under virtualization pass-through, an embodiment of the present application also provides a second electronic device. The second electronic device includes a chassis and a fourth chip system. The fourth chip system can be arranged in whole or in part in the chassis. As shown in Figure 10, the fourth chip system D includes a fourth host system D1 and a fourth network card system D2. The fourth host system D1 includes a fourth host processor D11 and a fourth host memory D12. The fourth network card system D2 includes a fourth network card processor D21 and an interface. The fourth network card processor D21 is coupled to the fourth host processor D11 and the fourth host memory D12 respectively through the interface and the fourth bus BUS4. Interactive communication is achieved within the fourth chip system D through the fourth bus BUS4. The first virtual machine VM1 and the virtual machine management system VMM1 are running on the fourth host processor D11. Wherein: the fourth host processor D11 is used to: apply for the first physical area address M1 from the fourth host memory D12 in units of physical pages; the first physical area address is used to store the first table entry data, and the first physical area address M1 is a non-writable attribute for the first virtual machine VM1. The first table entry data includes the business interaction status information of the first virtual machine VM1. The first virtual machine VM1 cannot write data to the first physical area address M1. The first indication information is sent to the fourth network card system D2 based on the virtual machine management system VMM1. The first indication information is used to indicate the identifier and the first physical area address of the first virtual machine VM1. The fourth network card processor D21 is used to: input the first indication information from the interface; and store the first indication information.

[0086] In some examples, the first indication information may include a virtual address running within the fourth host system D1, and the first physical area address is indicated by the virtual address. For example, the first indication information is a GVA, GPA, or HVA that is mapped to the first physical area address. In the embodiment of the present application, the operation of the first virtual machine VM1 is based on GVA and GPA. The operation of the virtual machine management system VMM1 on the fourth host processor D11 is based on HVA. There is a set mapping relationship between GVA, GPA, HVA, and HGA. In actual applications, when the mapping relationship is determined, the mapping relationship between the three types of addresses, GVA, GPA, and HVA, and the HPA address can be obtained based on different types of query mapping methods. Therefore, depending on the application scenario, etc., at least one of GVA, GPA, and HVA can be included in the first indication information. The first physical area address is indicated based on the mapping relationship between these virtual addresses and the first physical area address.

[0087] In some examples, the first indication information may include a first physical area address. The first physical area address is the HPA corresponding to the fourth host memory D12. The fourth network card processor D21 may directly access the fourth host memory D12 according to the HPA in the first indication information.

[0088] Illustratively, the interface in the fourth network card system D2 that receives the first indication signal may be a PF interface.

[0089] Exemplarily, the virtual machine management system VMM1 can be a virtual machine manager (VMM) or a hypervisor. In many application scenarios, the VMM and hypervisor are generally considered equivalent. However, in actual applications, the VMM is a software program that manages virtualized processors, memory, I / O devices, interrupts, and instruction sets in a virtualized environment. The hypervisor, on the other hand, is an operating system with the VMM. In the embodiments of the present application, the functions of the VMM and hypervisor can be considered equivalent.

[0090] Exemplarily, the service interaction state information may include at least one of memory management table entry information, service interaction control state information, host processor interaction state information, and network card system interaction state information.

[0091] Exemplarily, the identifier of the first virtual machine VM1 may be the Mac address of the VF interface corresponding to the first virtual machine VM1, the queue nodes of the SQ and RQ of the first virtual machine VM1, the virtual machine label of the first virtual machine VM1, etc., which may indicate information of the first virtual machine VM1.

[0092] In the embodiment of the present application shown in FIG10 , the fourth host processor D11 requests a memory area (i.e., a first physical area address M1) from the fourth host memory D12. This memory area can be a user-mode memory area or a kernel-mode user area. The first physical area address M1 is used to store service interaction state information for the first virtual machine VM1. Since the first virtual machine VM1 cannot write data to the first physical area address M1, the operation of the first virtual machine VM1 will not affect data security or system reliability. Simultaneously, the fourth host processor D11 in the fourth host system D1 sends first indication information to the fourth network card processor D21 via the fourth bus BUS4 and the PF interface based on the virtual machine management system VMM1. The first indication information indicates the identifier and first physical area address of the first virtual machine VM1 to the fourth network card processor D21. During subsequent stateful service interactions with the first virtual machine VM1, the fourth network card system D2 receives a message sent by another network node Q1 to the first virtual machine VM1 based on the receive transaction in the RQ of the first virtual machine VM1. The fourth network card system D2 parses the message to obtain relevant indication information and performs corresponding processing based on the indication information.

[0093] In some possible implementations, as shown in FIG11 , the fourth host processor D11 further includes a first memory manager MMU1. The fourth host processor D11 is further configured to: perform conversion between virtual addresses and physical addresses according to the first memory mapping table based on the first memory manager MMU1. In an embodiment of the present application, in the fourth host processor D11, the virtual addresses (e.g., GVA, GPA, and HVA) running in the fourth host processor D11 can be converted into physical addresses (e.g., HGA) of the fourth host memory D12 through the first memory manager MMU1. The first memory mapping table is a mapping table entry obtained based on the address mapping relationship determined during the design. The first memory mapping table can be stored in the fourth host memory D12, or it can be stored in whole or in part in the relevant registers or caches of the first memory manager MMU1. In actual applications, the first memory mapping table generally stores the mapping relationship between HVA and HPA.

[0094] In some possible implementations, as shown in FIG11 , the fourth chip system further includes a second memory manager MMU2. The second memory manager MMU2 is configured to convert between virtual addresses and physical addresses according to a second memory mapping table. The fourth network card processor D21 in the fourth network card system D2 is coupled to the fourth host memory D12 via the second memory manager MMU2. In some examples, the second memory manager MMU2 may be provided in the fourth host system D1. In some examples, the second memory manager MMU2 may be provided in the fourth network card system D2. For example, when the first indication information includes a GVA, GPA, or HVA that is mapped to the first physical region address, if the fourth network card system D2 needs to access the fourth host memory D12, conversion between virtual addresses and physical addresses is also required. This conversion may be achieved through the second memory manager MMU2. For example, the second memory manager MMU2 may be an input / output memory management unit (I / O MMU).

[0095] Exemplarily, the fourth network card system D2 can be a network card chip, a data processor (DPU) with network offload and data processing offload functions, a system on chip (SoC) with network card functions, or a very large scale integration circuit (VLSI) with network card functions, etc.

[0096] Exemplarily, the fourth host system D1 and the fourth network card system D2 can be installed on the same circuit board, or can be separately installed on different circuit boards. Exemplarily, the fourth host system D1 can be installed on a circuit board; and the fourth network card system D2 can be pluggably installed on the circuit board of the fourth host system D1 in a hot-swappable manner.

[0097] In some possible implementations, the second electronic device may be a network server device configured with an RDMA over converged ethernet (RoCE) protocol; or a network server device configured with a TCP offload engine (TOE) protocol; or a network server device configured with a unified bus (UB) protocol. Exemplarily, the second electronic device further includes a chassis. A circuit board is provided in the chassis. In some examples, the fourth host system D1 and the fourth network card system D2 are both installed in the chassis and on the same circuit board. In some examples, the fourth host system D1 and the fourth network card system D2 are both installed in the chassis and on different circuit boards. In some examples, the fourth host system D1 and the fourth network card system D2 are both installed in the chassis, and the fourth network card system D2 is pluggably installed on the circuit board of the fourth host system D1 in a hot-swappable manner. In some examples, the fourth host system D1 is installed in the chassis. The fourth network card system D2 is pluggably installed on a hot-plug interface outside the chassis of the second electronic device in a hot-plug manner, and is coupled to the fourth host system D1 through the hot-plug interface of the second electronic device.

[0098] The second electronic device and / or the fourth chip system including the structures shown in FIG. 10 and FIG. 11 may be used to execute the following control method including steps S100 to S400 as shown in FIG. 12 :

[0099] S100 , the fourth host processor D11 applies for a first physical region address M1 from the fourth host memory D12 .

[0100] In some possible implementations, as shown in Figures 12 and 20, before the first virtual machine VM1 begins running and interacts with other network nodes Q1, the fourth host processor D11 must first apply for a first physical region address M in units of physical pages. The first physical region address M is used to store first table entry data, and the first physical region address M is non-writable for the first virtual machine VM1. The first table entry data includes the first virtual machine's service interaction status information. In this embodiment of the present application, because the storage resources of the fourth host memory D12 are limited, in order to improve the processing performance of the fourth host processor D11, the fourth host processor D11 saves unused memory data from certain processes to the hard disk through a paging mechanism during operation. When the process needs to be run and used, the memory data on the hard disk is moved back to the fourth host memory D12. Therefore, during the operation of the fourth host memory D12, the mapping relationship between the HVA and HPA or the mapping relationship between the GVA and GPA of different processes may change. In order to ensure that the fourth network card system D2 can accurately obtain relevant business interaction status data from the fourth host memory D12, the fourth host processor D11 is required to perform memory registration (memory region, MR). The mapping relationship between the first physical region address M and the virtual address is locked through memory registration to ensure that the fourth network card system D2 can access the first physical region address M based on normal access. Because the business interaction status information is stored in the fourth host memory D12 of the fourth host system D1, it does not occupy the memory space of the fourth network card system D2. At the same time, compared to the solution of storing the business interaction status information in the fourth host system D1, the embodiment of the present application does not require additional software programs to control the business interaction status for hot migration during the hot migration process, which reduces the difficulty of hot migration of the first virtual machine VM1.

[0101] In the embodiment of the present application, since the operation of the fourth host processor D11 is based on a virtual address in units of virtual pages, the virtual page corresponds to a physical page (page size) in the fourth host memory D12. Therefore, for the first physical area address required by the first virtual machine VM1 to store business interaction status information, it is necessary to have a storage space in units of physical pages. Because when the chip provides address services, it provides address services in units of physical pages. When a physical page is partially occupied, when calling the address of the occupied part of the physical page, a complete physical page will still be obtained. In this case, the caller may modify all the contents of the physical page. In order to ensure the security and reliability of the first physical area address for storing business interaction status information, the first physical area address needs to exclusively occupy one or more physical pages.

[0102] In some possible implementations, the first physical region address M1 may be requested from the fourth host memory D12 in units of physical pages based on the first virtual machine VM1. For example, as shown in FIG13 , step S100 includes the operations shown in steps S110 to S140:

[0103] S110 : Determine the size of the first physical region address M1 .

[0104] Exemplarily, when the VF driver on the first virtual machine VM1 is loaded, the size of the first physical area address M1 is determined according to the size of the memory space required for service interaction of the first virtual machine VM1 .

[0105] S120 : The VF driver applies for the corresponding first physical region address M1 from the fourth host memory D12 .

[0106] Exemplarily, the VF driver generates second indication information according to the determined size of the first physical region address M1, and based on the second indication information, applies to the fourth host memory D12 for the corresponding first physical region address M1.

[0107] S130: The first virtual machine VM1 sends second indication information to the virtual machine management system VMM1. The second indication information is used to indicate the first physical area address M1.

[0108] Exemplarily, as shown in Figures 10 and 11, the first virtual machine VM1 can send the second instruction information to the virtual machine management system VMM1 via a communication channel between the VF driver of the first virtual machine VM1 and the PF driver of the virtual machine management system VMM1. For example, the communication channel can be a mailbox channel. Exemplarily, the first virtual machine VM1 can send the second instruction information to the virtual machine management system VMM1 via a communication channel between the first virtual machine VM1 and the virtual machine management system VMM1. For example, the communication channel can be a memory-shared communication channel between the first virtual machine VM1 and the virtual machine management system VMM1.

[0109] S140 . The virtual machine management system VMM1 sets the first physical area address M1 as a non-writable attribute for the first virtual machine VM1 .

[0110] In some examples, the first physical region address M1 can be set to a read-only attribute for the first virtual machine VM1. In this case, the first physical region address M1 is not writable by the first virtual machine VM1. In some examples, the first physical region address M1 can be set to an invisible state for the first virtual machine VM1. In this case, the first physical region address M1 is neither writable nor readable by the first virtual machine VM1.

[0111] Exemplarily, as shown in FIG11 , the fourth host processor D11 converts virtual addresses and physical addresses based on the first memory mapping table based on the first memory manager MMU1. The virtual machine management system VMM1 configures a first page table entry in the first memory mapping table at a location corresponding to the first virtual machine VM1; the first page table entry is used to indicate the mapping relationship between the first physical region address M1 and the virtual address. The first page table entry is set to have a read-only attribute for the first virtual machine VM1. In this embodiment of the present application, after the first virtual machine VM1 applies for the first physical region address M1, the first physical region address M1 is registered in the available memory of the first virtual machine VM1. At this point, the first virtual machine VM1 has read and write permissions to the first physical region address M1. To avoid security and reliability issues caused by the first virtual machine VM1 writing data to the first physical region address M1, the virtual machine management system VMM1 sets the first page table entry to have a read-only attribute for the first virtual machine VM1, thereby preventing the first virtual machine VM1 from modifying the first physical region address M1.

[0112] For example, as shown in FIG11 , the second memory manager MMU2 converts virtual addresses to physical addresses based on the second memory mapping table. The fourth network card system D2 can access the memory of the fourth host memory D12 through the second memory manager MMU2. The virtual machine management system VMM1 can also store the relevant content of the first page table entry in the second memory mapping table, so that the fourth network card system D2 has read and write permissions for the first physical region address M1.

[0113] For example, the first page table entry in the second memory mapping table can be set to a non-writable state for the first virtual machine VM1. For instructions on setting the first page table entry in the second memory mapping table corresponding to MMU2 to a non-writable state for the first virtual machine VM1, refer to the description on setting the first page table entry in the first memory mapping table corresponding to MMU1 to a non-writable state for the first virtual machine VM1, and no further details are given here.

[0114] In the embodiment of the present application, as shown in FIG13 , a first physical area address M1 is requested based on the first virtual machine VM1. This first physical area address M1 occupies the memory space of the first virtual machine VM1. In this embodiment, the first physical area address required for service interaction status information does not occupy the memory space of the fourth network card system D2, but instead occupies the memory space of the first virtual machine VM1 itself, facilitating memory resource management for the first virtual machine VM1. Furthermore, the service interaction status information is stored in the fourth host memory D12, facilitating hot migration of the first virtual machine VM1.

[0115] In some possible implementations, based on the virtual machine management system VMM1 , an application for the first physical region address M1 may be made to the fourth host memory D12 in units of physical pages.

[0116] In some examples, when applying for the first physical region address M1 based on the virtual machine management system VMM1, the first physical region address M1 can be registered in the memory space belonging to the first virtual machine VM1. For example, as shown in FIG14, step S100 may include the operations shown in steps S110' to S140':

[0117] S110 ′: Determine the size of the first physical region address M1 .

[0118] For the description of step S110 ′, reference may be made to the content of step S110 in the aforementioned embodiment, which will not be repeated here.

[0119] S120': The first virtual machine VM1 sends second instruction information to the virtual machine management system VMM1.

[0120] Exemplarily, the VF driver generates the second indication information based on the determined size of the first physical region address M1. The first virtual machine VM1 can send the second indication information to the virtual machine management system VMM1 via a communication channel between the VF driver of the first virtual machine VM1 and the PF driver of the virtual machine management system VMM1. For example, the communication channel can be a mailbox channel.

[0121] For example, the first virtual machine VM1 may send the second instruction information to the virtual machine management system VMM1 via a communication channel between the first virtual machine VM1 and the virtual machine management system VMM1. For example, the communication channel may be a memory-shared communication channel between the first virtual machine VM1 and the virtual machine management system VMM1.

[0122] S130 ′: The virtual machine management system VMM1 applies for a first physical region address M1 from the fourth host memory D12 in units of physical pages according to the second instruction information.

[0123] S140 ′: The virtual machine management system VMM1 sets the first physical area address M1 as a non-writable attribute for the first virtual machine VM1 .

[0124] For example, as shown in FIG11 , when a first physical region address M1 is requested based on a virtual machine management system VMM1, the virtual machine management system VMM1 may configure a first page table entry in the first memory mapping table at a location corresponding to the first virtual machine VM1. To prevent the first virtual machine VM1 from directly modifying the first physical region address M1, in some examples, as shown in FIG11 , the virtual machine management system VMM1 may set the attributes of the first page table entry to be read-only and non-writable for the first virtual machine VM1. In this embodiment of the present application, by setting the attributes of the first page table entry to be non-writable for the first virtual machine VM1, security and reliability issues caused by the operation of the first virtual machine VM1 modifying the service interaction state data of the first physical region address M1 are prevented. In some examples, the virtual machine management system VMM1 may set the attributes of the first page table entry to be non-readable and non-writable for the first virtual machine VM1. In this embodiment of the present application, by setting the attributes of the first page table entry to be non-readable and non-writable for the first virtual machine VM1, the first physical region address M1 is completely invisible to the first virtual machine VM1. This can more safely prevent the security and reliability issues caused by the operation of the first virtual machine VM1 modifying the service interaction state data of the first physical area address M1.

[0125] For example, as shown in FIG11 , when the first indication information includes a GVA, GPA, or HVA mapped to the first physical region address, the virtual machine management system VMM1 also stores the relevant content of the first page table entry in the second memory mapping table, so that the fourth network card system D2 can have read and write permissions for the first physical region address M1. For the relevant description of the first page table entry in the embodiment shown in FIG14 of the present application, reference can be made to the description of the first page table entry in the embodiment shown in FIG13 , and no further details will be given here.

[0126] In the embodiment of the present application, as shown in FIG14 , a first physical area address M1 is requested based on the first virtual machine VM1. This first physical area address M1 occupies the memory space of the first virtual machine VM1. In this embodiment, the first physical area address required for service interaction status information does not occupy the memory space of the fourth network card system D2, but instead occupies the memory space of the first virtual machine VM1 itself, facilitating memory resource management for the first virtual machine VM1. Furthermore, the service interaction status information is stored in the fourth host memory D12, facilitating hot migration of the first virtual machine VM1.

[0127] In some examples, when applying for the first physical region address M1 based on the virtual machine management system VMM1, the first physical region address M1 can be registered in the memory space belonging to the virtual machine management system VMM1. For example, as shown in FIG15, step S110 may include the operations shown in steps S110" to S130":

[0128] S110 ”, determine the size of the first physical area address M1.

[0129] For the relevant description of step S110, reference can be made to the content of step S110 in the aforementioned embodiment, which will not be repeated here.

[0130] S120 ”: The first virtual machine VM1 sends second instruction information to the PF driver of the virtual machine management system VMM1 .

[0131] For example, the first virtual machine VM1 may send the second instruction information to the virtual machine management system VMM1 via a communication channel between a VF driver of the first virtual machine VM1 and a PF driver of the virtual machine management system VMM1. For example, the communication channel may be a mailbox channel of the VF.

[0132] For example, the first virtual machine VM1 may send the second instruction information to the virtual machine management system VMM1 via a communication channel between the first virtual machine VM1 and the virtual machine management system VMM1. For example, the communication channel may be a memory-shared communication channel between the first virtual machine VM1 and the virtual machine management system VMM1.

[0133] S130 ”: The PF driver based on the virtual machine management system VMM1 applies for a first physical area address M1 from the fourth host memory D12 .

[0134] Exemplarily, the PF driver performs an initialization operation after completing the application of the first physical region address M1.

[0135] In the embodiment of the present application, the first physical region address M1 requested by the PF driver is a memory address of the virtual machine management system VMM1. That is, the first page table entry for the first physical region address M1 is registered in the memory space of the virtual machine management system VMM1.

[0136] Exemplarily, when the first indication information includes GVA, GPA or HVA mapped to the first physical area address, the virtual machine management system VMM1 stores the relevant content of the first page table entry in the second memory mapping table, so that the fourth network card system D2 can have read and write permissions for the first physical area address M1.

[0137] In some possible implementations, the virtual machine management system VMM1 changes the second page table entry to a third page table entry; the second page table entry is the page table entry corresponding to the first virtual machine VM1 in the first memory mapping table; the third page table entry is the page table entry corresponding to the virtual machine management system VMM1 in the first memory mapping table. In this embodiment of the present application, because the first page table entry corresponding to the first physical region address M1 is registered in the memory belonging to the virtual machine management system VMM1, the first physical region address M1 occupies the memory resources of the virtual machine management system VMM1. These memory resources are used by the user of the first virtual machine VM1. Therefore, to facilitate memory resource management, part of the memory resources of the first virtual machine VM1 (i.e., the second page table entry) can be changed to the memory resources of the virtual machine management system VMM1 (i.e., the third page table entry), thereby achieving precise management of the memory resources used by the user of the first virtual machine VM1. For example, the first virtual machine VM1 can request the physical region address for the second page table entry, and the virtual machine management system VMM1 does not actually allocate this physical region address to the first virtual machine VM1. Instead, it is registered in the memory belonging to the virtual machine management system VMM1 as a third page table entry. For example, the memory space corresponding to the second page table entry can also be deducted when the first virtual machine VM1 is initialized. In the embodiment of the present application, the operation of obtaining the memory space corresponding to the second page table entry from the first virtual machine VM1 to compensate for the memory resources of the virtual machine relationship system VMM1 is not limited to the operation sequence of the control method described in the embodiment of the present application. In actual applications, this operation can be performed at any available time.

[0138] S200 : The fourth host processor D11 sends a first instruction signal to the fourth network card processor D21 , and the fourth network card processor D21 receives the first instruction signal.

[0139] In some possible implementations, as shown in Figures 12 and 20, the fourth host processor D11 sends first indication information to the fourth network card system D2 based on the virtual machine management system VMM1. The first indication information is used to indicate the identifier and first physical area address M1 of the first virtual machine VM1. In some possible implementations, as shown in Figures 12 and 21, the fourth network card processor D21 receives the first indication signal. Exemplarily, the fourth network card processor D21 can receive the first indication signal via the PF interface. In an embodiment of the present application, after the fourth network card processor D21 stores the first indication information, when the fourth network card processor D21 assists the first virtual machine VM1 in performing service interaction through the VF interface corresponding to the first virtual machine VM1, it is necessary to obtain service interaction status information from the first physical area address M to assist the first virtual machine VM1 in performing service interaction. Therefore, the fourth host processor D11 of the fourth host system D1 is required to send a first indication signal to the fourth network card processor D21 of the fourth network card system D2 to indicate the identifier and first physical area address of the first virtual machine VM1.

[0140] S300: The fourth network card processor D21 stores first indication information.

[0141] For example, as shown in Figures 12 and 21, the fourth network card processor D21 of the fourth host system D1 stores the first indication information after receiving it. In some examples, the fourth network card processor D21 may store the first indication information in a relevant register, cache, or memory in the fourth host system D1. When the fourth network card processor D21 subsequently assists the first virtual machine VM1 in performing service interaction, the fourth network card processor D21 may access the first physical area address M1 in the fourth host system D1 using the stored first indication information to obtain relevant service interaction status information. The fourth network card processor D21 may then assist the first virtual machine VM1 in service interaction based on the service interaction status information.

[0142] S400 : The fourth network card system D2 performs service interaction with the first virtual machine VM1 based on the service interaction state information.

[0143] In some possible implementations, as shown in Figures 10 and 11, the first virtual machine VM1 in the fourth host system D1 performs service interaction with another network node Q1 via the fourth network card processor D21. During stateful service interaction, the fourth network card processor D21 obtains a first message sent by the other network node Q1 to the first virtual machine VM1. This first message carries interaction indication information. This interaction indication information may be control indication information for a control link or data processing indication information for a data link. The fourth network card processor D21 parses the obtained message to obtain interaction indication information. In this case, the interaction indication information is interaction indication information that the fourth network card processor D21 cannot process. The fourth network card processor D21 is also required to obtain service interaction status information from the first physical area address M1 based on the first indication information and determine the service that the interaction indication information actually needs to execute based on the service interaction status information. For example, when the interaction indication information is control indication information, the service that needs to be executed may include feedback of handshake control information, setting up an interaction node connection, and so on. Exemplarily, when the interaction indication information is data processing indication information, the service to be executed may be performing a DMA write operation and / or a DMA read operation on the fourth host memory D12.

[0144] In some possible implementations, when the interaction instruction information is data processing instruction information, the data processing operation included in the data processing instruction information may be data processing performed on the first physical area address M1. When the fourth network card processor D21 performs a data-related DMA operation according to the data processing instruction information, the relevant data in the first physical area address M1 may be modified, thereby causing security and reliability issues. To address this issue, as shown in FIG16 , step S400 may further include the following steps S410-S430:

[0145] S410: Receive a first message. The first message carries data processing instruction information, which is used to indicate a data processing type and an address of a second physical area.

[0146] For example, the other network node Q1 sends a first message to the fourth network card processor D21. The first message is used to perform service interaction with the first virtual machine VM1. For example, the other network node Q1 instructs the fourth network card processor D21 to perform a DMA operation on the second physical area address based on the corresponding data processing type through the first message.

[0147] S420. Obtain data processing instruction information from the first message according to the service interaction state information.

[0148] Exemplarily, the fourth network card processor D21 parses the first message, obtains service interaction status information from the first physical area address M1 based on the first indication information, and obtains the data processing type and the second physical area address of the data processing indication information through the service interaction status information.

[0149] Exemplarily, as shown in FIG11 , the fourth network card processor D21 accesses the first physical area address M1 in the fourth host memory D12 through the second memory manager MMU2 according to the stored first indication information to obtain relevant service interaction state information.

[0150] S430: Execute the data processing instruction information according to the data processing type.

[0151] In some examples, when the data processing type is a write operation and the second physical area address partially or entirely belongs to the first physical area address, the fourth network card processor D21 discards the first message. In some examples, if the data processing type is a write operation and the second physical area address does not belong to the first physical area address, the fourth network card processor D21 sends a first write instruction to the fourth host memory D12; the first write instruction is used to instruct the writing of data to the second physical area address in the fourth host memory D12 of the fourth host system D1, or to modify the data in the second physical area address. In an embodiment of the present application, when the first message carries data processing instruction information, the data processing type and data area virtual address of the data processing instruction information can be confirmed. When the data processing type is a DMA read operation, the first message will not modify the data in the first physical area address M1 and can be executed directly. When the data processing type is a DMA write operation, the first message may modify the data in the first physical area address M1. In this case, it is necessary to determine the relationship between the second physical area address and the first physical area address M1. When the second physical area address does not belong to the first physical area address M1, executing the DMA write operation will not modify the data in the first physical area address M1, and the first message can be executed. However, when the second physical area address partially or completely belongs to the first physical area address M1, executing the DMA write operation will modify the data in the first physical area address M1; in this case, the fourth network card processor D21 discards the first message and does not execute the corresponding DMA service.

[0152] Exemplarily, the first physical region address M1 may be a continuous address or a discontinuous multi-segment address. For example, in the embodiment of FIG. 13 above, the first physical region address M1 applied for by the first virtual machine VM1 may be a discontinuous multi-segment address. However, in FIG. 14 and FIG. 15 above, the first physical region address M1 applied for by the virtual machine management system VMM1 may be a continuous address. When determining the region between the second physical region address and the first physical region address M1, if the first physical region address M1 is a discontinuous address: in some examples, the relationship of the multiple discontinuous addresses to the second physical region address can be determined separately. In some examples, the multiple discontinuous addresses can be split into fixed-length memory pages aligned with the first address. A hash address table is generated based on the split memory pages. The subordinate relationship between the second physical region address and the first physical region address M1 is determined by querying the hash address table.

[0153] In some examples, after discarding the first message, the fourth network card processor D21 may send a feedback message to the counterpart network node that initiated the first message, informing the counterpart network node through the feedback message that the first message was not executed.

[0154] In some possible implementations, after executing step S300, as shown in FIG17 , the control method further includes step S500:

[0155] S500: Perform a write operation on the first physical area address M1.

[0156] In some examples, the fourth network card system D2 may perform a DMA write operation on the first physical area address M1. As shown in FIG18 , step S500 may include the following operations: S510 to S520:

[0157] S510: The fourth host system D1 sends a first instruction to the fourth network card system D2. The first instruction is used to instruct a write operation to the first physical area address M1.

[0158] For example, a first instruction can be sent to the fourth network card system D2 based on the first virtual machine VM1 and / or the virtual machine management system VMM1. In this embodiment of the present application, when a DMA write operation is required to the first physical area address M1, the first instruction can be sent to the fourth network card system D2 via the first virtual machine VM1 and / or the virtual machine management system VMM1. The first instruction includes data modification information and the first physical area address M1. The data modification information and the first physical area address M1 are used to instruct the fourth network card system D2 to perform a DMA write operation on the first physical area address M1.

[0159] S520 : The fourth network card system D2 sends a second write instruction to the fourth host memory D12 according to the first instruction.

[0160] Exemplarily, after receiving the first instruction, the fourth network card processor D21 of the fourth network card system D2 obtains the data modification information and the first physical area address M1 in the first instruction. Based on the data modification information and the first physical area address M1, the fourth network card system D2 generates a second write instruction. The fourth network card system D2 sends the second write instruction to the fourth host memory D12 in the fourth host system D1. The second write instruction is used to instruct the fourth host memory D12 to write data to the first physical area address M1 or to modify the service interaction status information in the first physical area address M1.

[0161] In some examples, the fourth host system D1 may perform a write operation on the first physical region address M1. As shown in FIG19 , step S500 may include the following steps S510 ′:

[0162] S510′, based on the virtual machine management system VMM1, send a third write instruction to the fourth host memory D12; the third write instruction is used to instruct the fourth host memory D12 to write data to the first physical area address M1, or to modify the service interaction state information in the first physical area address M1.

[0163] For example, when the first virtual machine VM1 needs to write to the first physical region address M1, the virtual machine management system VMM1 can send a third write instruction to the fourth host memory D12. Alternatively, the PF driver of the virtual machine management system VMM1 can send the third write instruction to the fourth host memory D12.

[0164] Embodiments of the present application provide a network card system, a host system, a control method, and a chip system. The chip system includes the aforementioned network card system and host system. The host system includes a host processor and host memory. A first virtual machine and a virtual machine management system run on the host processor. The host memory stores the operating data of the first virtual machine. The network card system can directly connect to the first virtual machine to assist the first virtual machine in stateful service interaction with other network nodes Q1. This stateful service interaction requires the use of service interaction state information. In embodiments of the present application, a first physical area address is requested based on the host processor. This first physical area address is a memory address in the host memory, and the first physical area address is used to store the service interaction state information of the first virtual machine. Compared to storing the service interaction state information in the network card system, storing the service interaction state information in the host memory can reduce the difficulty of hot migrating the first virtual machine. Furthermore, if the first virtual machine does not have write permission to the first physical area address, security and reliability issues associated with the operation of the first virtual machine when the first virtual machine and the network card system are directly connected can be avoided.

[0165] An embodiment of the present application also provides a computer-readable storage medium, which includes instructions; when the instructions are executed on a processor, the processor executes the control method described in the above embodiments (for example, executes the control method described in the above embodiments such as Figures 12, 13, 14, 15, 16, 17, 18, 19, 20 and 21).

[0166] The embodiments of the present application further provide a computer program product, which, when the computer program product is run on the chip system described in the above embodiments (e.g., the fourth chip system described in Figures 10 and 11), causes the chip system to execute the control method described in the above embodiments (e.g., the control method described in the embodiments of Figures 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21). When the computer program product is run on a computer, causes the computer to execute the control method described in the above embodiments (e.g., the control method described in the embodiments of Figures 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21).

[0167] The processor involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0168] The memory involved in the embodiment of the present application can be a volatile memory, or can include both volatile and non-volatile memory. Among them, the volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM). It should be noted that the memory of the system and method described herein is intended to include but is not limited to these and any other suitable types of memory.

[0169] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0170] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0171] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0172] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0173] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0174] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0175] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0176] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A control method for a network card system, characterized in that: The control method comprises: Receive first indication information; the first indication information is used to indicate an identifier of a first virtual machine and a first physical area address; the first virtual machine runs on a host system; the first physical area address is a storage address in a host memory of the host system in units of physical pages; the first physical area address is used to store first table entry data, and the first physical area address is a non-writable attribute for the first virtual machine; the first table entry data includes service interaction state information of the first virtual machine; The first indication information is stored.

2. The control method according to claim 1, characterized in that: The control method further comprises: A first message is received and the first message is discarded; the first message carries data processing indication information; the data processing indication information is used to indicate a data processing type and a second physical area address; the data processing type corresponding to the first message is a write data operation, and the second physical area address partially or completely belongs to the first physical area address.

3. The control method according to claim 2, characterized in that: The control method further comprises: Acquire the service interaction state information from the first physical area address of the host memory according to the first message and the first indication information; The data processing indication information is obtained according to the service interaction status information.

4. The control method according to any one of claims 1 to 3, characterized in that: The control method further comprises: receiving a first instruction; the first instruction is used to instruct to perform a write operation on the first physical area address; According to the first instruction, a second write instruction is sent to the host memory; the second write instruction is used to instruct the host memory to write data to the first physical area address, or to modify the service interaction state information in the first physical area address.

5. A control method, characterized in that: The host system includes a host processor and a host memory; A first virtual machine and a virtual machine management system are running on the host processor; The control method is based on the host processor; the control method includes: Applying for a first physical area address from the host memory in units of physical pages; the first physical area address is used to store first table entry data, and the first physical area address is a non-writable attribute for the first virtual machine; the first table entry data includes service interaction state information of the first virtual machine; Sending first indication information to the network card system based on the virtual machine management system; the first indication information is used to indicate the identifier of the first virtual machine and the first physical area address.

6. The control method according to claim 5, characterized in that: The applying for the first physical region address from the host memory in units of physical pages includes: Based on the first virtual machine, applying for the first physical area address from the host memory in units of physical pages, and sending second indication information to the virtual machine management system, where the second indication information is used to indicate the first physical area address.

7. The control method according to claim 5, characterized in that: The applying for the first physical region address from the host memory in units of physical pages includes: Based on the first virtual machine, sending second indication information to the virtual machine management system; the second indication information is used to indicate the first physical area address; Based on the virtual machine management system, applying for the first physical area address from the host memory in units of physical pages according to the second indication information.

8. The control method according to claim 6 or 7, characterized in that: The control method further comprises: Convert between virtual addresses and physical addresses according to the first memory mapping table; Based on the virtual machine management system, configuring a first page table entry in a position corresponding to the first virtual machine in the first memory mapping table; the first page table entry is used to indicate a mapping relationship between the first physical region address and the virtual address; The attribute of the first page table entry is set to be a non-writable attribute of the first virtual machine.

9. The control method according to claim 7, characterized in that: The control method further comprises: Convert between virtual addresses and physical addresses according to the first memory mapping table; Based on the virtual machine management system, a first page table entry is configured in a position in the first memory mapping table corresponding to the virtual machine management system; the first page table entry is used to indicate a mapping relationship between the first physical area address and the virtual address.

10. The control method according to claim 9, characterized in that: The control method further comprises: Based on the virtual machine management system, the second page table entry is changed to a third page table entry; the second page table entry is a page table entry in the first memory mapping table corresponding to the first virtual machine; the third page table entry is a page table entry in the first memory mapping table corresponding to the virtual machine management system.

11. The control method according to any one of claims 5 to 10, characterized in that: The control method further comprises: Based on the virtual machine management system, a third write instruction is sent to the host memory; the third write instruction is used to instruct the host memory to write data to the first physical area address, or to modify the service interaction state information in the first physical area address.

12. The control method according to any one of claims 5 to 11, characterized in that: The control method further comprises: Based on the first virtual machine and / or the virtual machine management system, a first instruction is sent to the network card system; the first instruction is used to instruct a write operation to the first physical area address.

13. A network card system, characterized in that: The network card system includes a network card processor and an interface; the network card processor is used to: A first indication signal is input from the interface; the first indication information is used to indicate an identifier of a first virtual machine and a first physical area address; the first virtual machine runs on a host system; the first physical area address is a storage address in a host memory of the host system in units of physical pages; the first physical area address is used to store first table entry data, and the first physical area address is a non-writable attribute for the first virtual machine; the first table entry data includes service interaction state information of the first virtual machine; The first indication information is stored.

14. The network card system according to claim 13, characterized in that: The network card system is also used for: A first message is received and the first message is discarded; the first message carries data processing indication information; the data processing indication information is used to indicate a data processing type and a second physical area address; the data processing type corresponding to the first message is a write data operation, and the second physical area address partially or completely belongs to the first physical area address.

15. The network card system according to claim 14, characterized in that: The network card processor is also used for: Acquire the service interaction state information from the first physical area address of the host memory according to the first message and the first indication information; The data processing indication information is obtained according to the service interaction status information.

16. The network card system according to any one of claims 13 to 15, characterized in that: The network card processor is also used for: receiving a first instruction; the first instruction is used to instruct to perform a write operation on the first physical area address; According to the first instruction, a second write instruction is sent to the host memory; the second write instruction is used to instruct the host memory to write data to the first physical area address, or to modify the service interaction state information in the first physical area address.

17. A host system, characterized in that: The host system includes a host processor and a host memory; a first virtual machine and a virtual machine management system are running on the host processor; the host processor is used to: Applying for a first physical area address from the host memory in units of physical pages; the first physical area address is used to store first table entry data, and the first physical area address is a non-writable attribute for the first virtual machine; the first table entry data includes service interaction state information of the first virtual machine; Sending first indication information to the network card system based on the virtual machine management system; The first indication information is used to indicate the identifier of the first virtual machine and the first physical area address.

18. The host system according to claim 17, characterized in that: The host processor is specifically used for: Based on the first virtual machine, applying for the first physical area address from the host memory in units of physical pages, and sending second indication information to the virtual machine management system; the second indication information is used to indicate the first physical area address.

19. The host system according to claim 17, characterized in that: The host processor is specifically used for: Based on the first virtual machine, sending second indication information to the virtual machine management system; the second indication information is used to indicate the first physical area address; Based on the virtual machine management system, applying for the first physical area address from the host memory in units of physical pages according to the second indication information.

20. The host system according to claim 17 or 19, characterized in that: The host processor also includes a first memory manager; The host processor is further configured to: Based on the first memory manager, converting between virtual addresses and physical addresses according to a first memory mapping table; Based on the virtual machine management system, configuring a first page table entry in a position corresponding to the first virtual machine in the first memory mapping table; the first page table entry is used to indicate a mapping relationship between the first physical region address and the virtual address; The attribute of the first page table entry is set to be a non-writable attribute of the first virtual machine.

21. The host system according to claim 19, characterized in that: The host processor also includes a first memory manager; The host processor is further configured to: Based on the first memory manager, converting between virtual addresses and physical addresses according to a first memory mapping table; Based on the virtual machine management system, a first page table entry is configured in a position in the first memory mapping table corresponding to the virtual machine management system; the first page table entry is used to indicate a mapping relationship between the first physical area address and the virtual address.

22. The host system according to claim 21, characterized in that: The host processor is further configured to: Based on the virtual machine management system, the second page table entry is changed to a third page table entry; the second page table entry is a page table entry in the first memory mapping table corresponding to the first virtual machine; the third page table entry is a page table entry in the first memory mapping table corresponding to the virtual machine management system.

23. The host system according to any one of claims 17 to 22, characterized in that: The host processor is further configured to: Based on the virtual machine management system, a third write instruction is sent to the host memory; the third write instruction is used to instruct the host memory to write data to the first physical area address, or to modify the service interaction state information in the first physical area address.

24. The host system according to any one of claims 17 to 23, characterized in that: The host processor is further configured to: Based on the first virtual machine and / or the virtual machine management system, a first instruction is sent to the network card system; the first instruction is used to instruct a write operation to the first physical area address.

25. A chip system, characterized in that: The chip system includes the network card system as described in any one of claims 13-16 and the host system as described in any one of claims 17-24.

26. An electronic device, characterized in that: It comprises a chassis and a chip system as claimed in claim 25; the chip system is partially or completely arranged in the chassis.

27. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes instructions; when the instructions are executed on a processor, the processor executes the control method as described in any one of claims 1 to 4, and / or executes the control method as described in any one of claims 5 to 12.

28. A computer program product, characterized in that When the computer program product runs on a computer, the computer is enabled to execute the control method according to any one of claims 1 to 4, and / or execute the control method according to any one of claims 5 to 12.

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