Shield-gate-trench mosfet structure, shield-gate-trench power device, and preparation method

Abstract

Provided in the present invention are a shield-gate-trench MOSFET structure, a shield-gate-trench power device, and a preparation method. The shield-gate-trench MOSFET structure comprises a source doping region and a cell trench, which are formed in a substrate, wherein the source doping region is located outside the cell trench, a polycrystalline-silicon gate electrode and a polycrystalline-silicon source electrode which are spaced apart and insulated from each other are formed in the cell trench, the polycrystalline-silicon gate electrode is arranged surrounding the polycrystalline-silicon source electrode, and the polycrystalline-silicon gate electrode is spaced apart and insulated from the source doping region, so as to enhance the depletion capability of a shield-gate-trench power device, thereby reducing the on-resistance.

Description

Shielded gate MOSFET structure, shielded gate power device and preparation method Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a shielded gate MOSFET structure, a shielded gate power device and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor integrated circuits, shielded-gate (SGT) metal oxide semiconductor field-effect transistors (MOSFETs) can reduce the on-resistance of traditional trench MOSFETs by half or even one-fifth. While traditional trench MOSFETs primarily increase the device's trench density to improve current handling capability, SGT MOSFETs reduce trench density and lower drift region resistance.

[0003] As shown in FIG1 , the conventional shielded gate MOSFET structure is a long strip structure having a long strip body region 4 and a source doping region 5 . This structure makes the on-resistance of the shielded gate MOSFET relatively high.

[0004] Summary of the Invention

[0005] An object of the present invention is to provide a shielded gate MOSFET structure that can increase the depletion capability of the device.

[0006] Another object of the present invention is to provide a shielded gate power device and a manufacturing method thereof, which can reduce the on-resistance of the shielded gate MOSFET.

[0007] In order to solve the above problems, the present invention provides a shielded gate MOSFET structure, including a source doping region and a cell trench formed in a substrate, the source doping region is located outside the cell trench, and a polysilicon gate and a polysilicon source are formed in the cell trench, which are spaced and insulated. The polysilicon gate is arranged around the outside of the polysilicon source, and the polysilicon gate and the source doping region are spaced and insulated.

[0008] Optionally, the shape of the cellular groove is a central radial pattern, the central radial pattern includes a central part and a radial part that are interconnected, the radial part is located outside the central part, the central part is circular, and the radial part is composed of multiple straight line segments arranged around the central part.

[0009] Optionally, the diameter of the central portion is greater than the width of each straight line segment in the radiation portion.

[0010] Furthermore, the polysilicon source is located in the central portion, a portion of the polysilicon gate is located in the radiation portion, and another portion is located in the central portion and is arranged in a ring outside the polysilicon source.

[0011] Optionally, a source metal is further included, wherein the source metal is located above the source doping region and the polysilicon source, and is connected to the polysilicon source and the source doping region respectively, and is spaced and insulated from the polysilicon gate.

[0012] Furthermore, it also includes an interval dielectric layer, a first dielectric layer and a gate oxide layer, the interval dielectric layer covers the surface of the polysilicon gate, and the interval dielectric layer has a first opening above the source doping region, the first opening exposes the source doping region, and has a second opening above the polysilicon source, the second opening exposes the polysilicon source, so that the source metal is connected to the source doping region at the first opening and to the polysilicon source at the second opening; the first dielectric layer and the gate oxide layer are both formed on the inner wall of the cell trench, and the first dielectric layer is arranged around the outside of the polysilicon source, and the gate oxide layer is arranged around the outside of the polysilicon gate.

[0013] Furthermore, the shapes of the first opening and the second opening are circular or rectangular respectively.

[0014] On the other hand, the present invention also provides a method for preparing a shielded gate MOSFET structure, comprising the following steps:

[0015] providing a substrate, and forming a cell trench in the substrate;

[0016] A polysilicon gate and a polysilicon source are formed in the cell trench and are spaced apart and insulated, wherein the polysilicon gate is arranged around the outside of the polysilicon source;

[0017] A source doping region is formed in the substrate outside the cell trench, and the polysilicon gate is spaced apart from and insulated from the source doping region.

[0018] Optionally, the shape of the cellular groove is a central radial pattern, the central radial pattern includes a central part and a radial part that are interconnected, the radial part is located outside the central part, the central part is circular, and the radial part is composed of multiple straight line segments.

[0019] Optionally, the diameter of the central portion is greater than the width of each straight line segment in the radiation portion.

[0020] Furthermore, the method of forming the polysilicon gate and the polysilicon source is:

[0021] forming a first dielectric layer, wherein the first dielectric layer fills the radiation portion and is deposited on an inner wall of the central portion;

[0022] forming a polysilicon source electrode in the cell trench of the central portion;

[0023] Etching the first dielectric layer to form a gate trench, wherein a portion of the gate trench is located in the radiation portion and another portion is located in the central portion;

[0024] forming a gate oxide layer on an inner wall of the gate trench;

[0025] A polysilicon gate is formed in the gate trench.

[0026] Optionally, after forming the source doping region, the method further includes:

[0027] A source metal is formed on the substrate. The source metal is located above the source doping region and the polysilicon source, and is connected to the polysilicon source and the source doping region respectively, and is spaced and insulated from the polysilicon gate.

[0028] Furthermore, the method of forming the source metal is:

[0029] forming a spacer dielectric layer on the surface of the substrate, the spacer dielectric layer covering the polysilicon gate and the polysilicon source, and having a first opening above the source doping region, the first opening exposing the source doping region, and a second opening above the polysilicon source, the second opening exposing the polysilicon source;

[0030] A source metal is formed, wherein the source metal is connected to the source doping region at the first opening and is connected to the polysilicon source at the second opening.

[0031] Furthermore, the shapes of the first opening and the second opening are circular or rectangular respectively.

[0032] On the other hand, the present invention further provides a shielded gate power device, comprising a plurality of the shielded gate MOSFET structures, all of which are distributed in an array.

[0033] Optionally, the shielded gate power device includes a cell region and a terminal region, the terminal region is arranged around the cell region, and the shielded gate MOSFET structure is located in the cell region.

[0034] Furthermore, a groove structure is formed in the substrate of the cell region, the groove structure consisting of a plurality of parallel first grooves and a plurality of parallel second grooves, the first grooves and the second grooves being arranged perpendicularly to each other, so that the groove structure is a cross-shaped grid structure; or the groove structure consisting of a plurality of parallel first grooves, a plurality of parallel second grooves, and a plurality of parallel third grooves, the first grooves, the second grooves, and the third grooves being arranged to intersect at the same point, so that the groove structure is a hexagonal star-shaped grid structure;

[0035] Wherein, each grid node region of the grid structure forms a shielded gate MOSFET structure.

[0036] Furthermore, the first trench, the second trench and the third trench all have an extension portion, and the extension portion extends from the cell region to the terminal region. A gate metal is formed in the terminal region, and the gate metal is connected to the polysilicon gate in the extension portion.

[0037] According to one aspect, the present invention provides a method for preparing a shielded gate power device, comprising the following steps:

[0038] providing a substrate;

[0039] A plurality of shielded gate MOSFET structures are formed in the substrate, and all the shielded gate MOSFET structures are distributed in an array.

[0040] Optionally, the method of forming a plurality of array-distributed shielded gate MOSFET structures includes:

[0041] A trench structure is formed in the substrate of the cell region, wherein the trench structure is composed of a plurality of first trenches arranged in parallel and a plurality of second trenches arranged in parallel, wherein the first trenches and the second trenches are arranged to intersect perpendicularly, so that the trench structure is a cross-shaped grid structure; or the trench structure is composed of a plurality of first trenches arranged in parallel, a plurality of second trenches arranged in parallel, and a plurality of third trenches arranged in parallel, wherein the first trenches, the second trenches, and the third trenches are arranged to intersect at the same point, so that the trench structure is a hexagonal star-shaped grid structure;

[0042] A polysilicon source and a polysilicon gate are formed in the trench structure, wherein the polysilicon gate is arranged around the outside of the polysilicon source, and the polysilicon gate and the polysilicon source are spaced and insulated;

[0043] forming a source doping region in the substrate of the cell region, wherein the source doping region is located in a grid surrounded by the grid-like structure;

[0044] A source metal and a gate metal are formed, wherein the source metal is located above the source doping region and the polysilicon source, and is connected to the source doping region and the polysilicon source respectively. The gate metal is in the terminal region, and the first trench, the second trench, and the third trench all have an extension portion, which extends from the cell region to the terminal region and is connected to the polysilicon gate in the extension portion.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] The present invention provides a shielded-gate MOSFET structure, a shielded-gate power device, and a method for manufacturing the same. The shielded-gate MOSFET structure includes a source doped region and a cell trench formed in a substrate. The source doped region is located outside the cell trench. A polysilicon gate and a polysilicon source are formed in the cell trench and are spaced and insulated. The polysilicon gate is disposed around the outside of the polysilicon source, and the polysilicon gate is spaced and insulated from the source doped region to enhance the depletion capability of the shielded-gate power device and thereby reduce on-resistance. Furthermore, the shielded-gate power device of the present invention achieves a densest packing effect of cells, increases channel density, and reduces on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram of a layout of a conventional shielded gate MOSFET structure;

[0048] FIG2 is a schematic diagram of the cross-sectional structure of a conventional SGT;

[0049] 3 to 6 are partial structural diagrams of a shielded gate power device provided in one embodiment of the present invention;

[0050] 7-8 are schematic structural diagrams of source metals of different shapes provided by one embodiment of the present invention;

[0051] FIG9 is a schematic diagram of a partial structure of a shielded gate power device provided in one embodiment of the present invention;

[0052] FIG10 is a perspective schematic diagram of a substrate provided in one embodiment of the present invention;

[0053] 11 is a longitudinal cross-sectional view of the cell of FIG. 3 along line MM′ of a substrate provided by one embodiment of the present invention;

[0054] FIG12 is a longitudinal cross-sectional view of the cell of FIG3 along line MN of the substrate provided by one embodiment of the present invention;

[0055] FIG13 is a perspective schematic diagram of forming a first dielectric layer according to an embodiment of the present invention;

[0056] 14 is a longitudinal cross-sectional view of the cell along line MM' in FIG. 3 when forming the first dielectric layer according to one embodiment of the present invention;

[0057] FIG15 is a longitudinal cross-sectional view of the cell along line MN in FIG3 when forming a first dielectric layer according to one embodiment of the present invention;

[0058] FIG16 is a three-dimensional schematic diagram of forming a polysilicon source electrode according to an embodiment of the present invention;

[0059] 17 is a longitudinal cross-sectional view of the cell along line MM' in FIG. 3 when forming a polysilicon source according to one embodiment of the present invention;

[0060] FIG18 is a longitudinal cross-sectional view of the cell of FIG3 along line MN when forming a polysilicon source according to one embodiment of the present invention;

[0061] FIG19 is a perspective diagram of forming a gate trench according to an embodiment of the present invention;

[0062] 20 is a longitudinal cross-sectional view of the cell of FIG. 3 along line MM′ when forming a gate trench according to one embodiment of the present invention;

[0063] FIG21 is a longitudinal cross-sectional view of the cell of FIG3 along line MN when forming a gate trench according to one embodiment of the present invention;

[0064] FIG22 is a perspective schematic diagram of forming a polysilicon gate according to an embodiment of the present invention;

[0065] 23 is a longitudinal cross-sectional view of the cell of FIG. 3 along line MM′ when forming a polysilicon gate according to one embodiment of the present invention;

[0066] FIG24 is a longitudinal cross-sectional view of the cell of FIG3 along line MN when forming a polysilicon gate according to one embodiment of the present invention;

[0067] FIG25 is a perspective schematic diagram of a shielded gate MOSFET structure provided by an embodiment of the present invention;

[0068] 26 is a longitudinal cross-sectional view of the shielded gate MOSFET structure provided in one embodiment of the present invention, taken along line MM' of the cell in FIG3 ;

[0069] FIG27 is a longitudinal cross-sectional view of the shielded gate MOSFET structure provided by one embodiment of the present invention, taken along line MN of the cell of FIG3 ;

[0070] FIG. 28 is an Id-BV curve diagram of a shielded gate MOSFET structure provided by an embodiment of the present invention and the prior art.

[0071] In Figures 1 and 2: 1-source metal; 2-polysilicon source; 3-polysilicon gate; 4-body region; 5-source doped region;

[0072] In Figures 3 to 28: I-cell region; II-terminal region; 10-shielded gate MOSFET structure; 11-gate metal; 100-substrate; 101-cell trench; 102-first trench; 103-second trench; 104-third trench; 105-gate trench; 110-body region; 120-source doped region; 130-first dielectric layer; 210-polysilicon source; 220-polysilicon gate; 300-spacer dielectric layer; 310-first opening; 400-source metal. DETAILED DESCRIPTION

[0073] The following is a further detailed description of a shielded gate MOSFET structure, shielded gate power device, and method for manufacturing the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as being generally known to those skilled in the art and not intended to limit the present invention.

[0074] For the sake of clarity, not all features of actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as adapting from one embodiment to another to accommodate system or business constraints. Furthermore, it should be understood that such development work may be complex and time-consuming, but is nevertheless a routine undertaking for those skilled in the art.

[0075] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific embodiments of the present invention are further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0076] As shown in Figure 2 (also referring to Figure 1 ), a conventional SGT (shielded gate trench field-effect transistor) comprises a trench formed in a substrate, with a dielectric layer deposited on the trench sidewalls. A polysilicon source 2 is filled in the trench within the dielectric layer. A polysilicon gate 3 is embedded in the dielectric layer and spaced and insulated outside the polysilicon source 2. A body region 4 and a source doping region 5 are formed in the substrate outside the polysilicon gate 3. The source doping region 5 is located within the body region 4 and close to the substrate surface. The dielectric layer exposes the polysilicon source 2 and the source doping region 5. A source metal 1 is formed on the substrate, communicating with the source doping region 5 and the polysilicon source 2, respectively. Conventional SGTs have low trench density and high on-resistance.

[0077] As shown in Figures 3-6, and with reference to Figures 25-27, this embodiment provides a shielded gate MOSFET structure 10. The shielded gate MOSFET structure 10 includes a source doped region 120 and a cell trench 101 formed in a substrate 100. The source doped region 120 is located outside the cell trench 101. A polysilicon gate 220 and a polysilicon source 210 are formed in the cell trench 101, spaced apart and insulated. The polysilicon gate 220 surrounds the polysilicon source 210 and is spaced apart and insulated from the source doped region 110. The shielded gate MOSFET structure 10 also includes a body region 110. The source doped region 120 is located in the body region 110 and is disposed close to the substrate surface.

[0078] The cell trench 101 is shaped like a center-radiating pattern, such as a cross-shaped center-radiating pattern (as shown in Figures 3-5) or a hexagonal center-radiating pattern (as shown in Figure 6). The center-radiating pattern includes a central portion and a radial portion that are interconnected. The radial portion is located outside the central portion. The central portion is circular and consists of multiple straight segments arranged around the central portion. The diameter of the central portion is greater than the width of each straight segment in the radial portion. The polysilicon source 210 is located in the central portion. A portion of the polysilicon gate 220 is located in the radial portion, while another portion is located in the central portion and is arranged around the outside of the polysilicon source 210.

[0079] The shielded gate MOSFET structure 10 further includes a source metal 400 , which is located above the source doping region 120 and the polysilicon source 210 , and is connected to the polysilicon source 210 and the source doping region 120 , respectively, and is spaced apart from and insulated from the polysilicon gate 220 .

[0080] The shielded gate MOSFET structure 10 further includes a spacer dielectric layer 300, a first dielectric layer 130, and a gate oxide layer. The spacer dielectric layer 300 covers the surface of the polysilicon gate 220 to insulate the source metal 400 from the polysilicon gate 220. The spacer dielectric layer 300 has a first opening 310 above the source doped region 120, exposing the source doped region 120, and a second opening (not shown) above the polysilicon source 210, exposing the polysilicon source 210. The source metal 400 fills the first opening 310 and the second opening and covers a portion of the surface of the spacer dielectric layer 300, such that the source metal 400 is connected to the source doped region 120 at the first opening 310 and to the polysilicon source 210 at the second opening.

[0081] The cross-sectional shapes of the first opening 310 and the second opening can be regular shapes such as rectangles and circles, respectively, and the cross-sectional shapes of the first opening 310 and the second opening can be the same (i.e., both are rectangles or circles), or different (for example, the cross-sectional shape of the first opening 310 is a circle, and the cross-sectional shape of the second opening is a square).

[0082] In this embodiment, the cross-sectional shapes of the first opening 310 and the second opening are the same, for example, both are rectangular, such as a square with inner arc chamfers as shown in FIG3 , or a square as shown in FIG7 , or a circle as shown in FIG8 . Of course, the cross-sectional shapes of the first opening 310 and the second opening can also be other regular shapes.

[0083] The first dielectric layer 130 and the gate oxide layer are both formed on the inner walls (side walls and bottom walls) of the cell trench 101, and the first dielectric layer 130 is arranged around the outside of the polysilicon source 210, and the gate oxide layer is arranged around the outside of the polysilicon gate 220, so that the polysilicon source 210 and the polysilicon gate 220 are insulated and spaced apart.

[0084] Compared to the traditional two-dimensional cell layout (ie, the elongated shielded gate MOSFET structure 10 ), the three-dimensional cell layout of this embodiment utilizes the three-dimensional charge compensation effect to enhance the depletion capability of the shielded gate power device.

[0085] This embodiment also provides a method for preparing a shielded gate MOSFET structure 10, comprising the following steps:

[0086] Step S11: providing a substrate 100 and forming a cell trench 101 in the substrate 100;

[0087] Step S12: forming a polysilicon gate 220 and a polysilicon source 210 spaced apart and insulated from each other in the cell trench 101 , wherein the polysilicon gate 220 is arranged around the outside of the polysilicon source 210 ;

[0088] Step S13: forming a source doping region 120 in the substrate 100 outside the cell trench 101 , wherein the polysilicon gate 220 is spaced apart from and insulated from the source doping region 120 ;

[0089] Step S14: forming a source metal 400 on the substrate 100 , wherein the source metal 400 is located above the source doping region 120 and the polysilicon source 210 , and is connected to the source doping region 120 and the polysilicon source 210 , respectively, and is spaced apart from and insulated from the polysilicon gate 220 .

[0090] A method for preparing a shielded gate MOSFET structure 10 provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0091] As shown in FIG. 10 to FIG. 12 , step S11 is first performed to provide a substrate 100 , and a cell trench 101 is formed in the substrate 100 .

[0092] This step specifically includes:

[0093] First, a substrate 100 is provided. The substrate 100 includes a base and an epitaxial layer located on the base. The base includes a semiconductor material, wherein the semiconductor material includes silicon, silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. In this embodiment, the base includes silicon, and the epitaxial layer includes silicon.

[0094] Next, a cell trench 101 is formed in the substrate 100. Specifically, the cell trench 101 is formed in the substrate 100 by an etching process.

[0095] The shape of the cellular groove is a central radial pattern, which includes a central part and a radial part that are interconnected. The radial part is located outside the central part, the central part is circular, and the radial part is composed of multiple straight line segments arranged around the central part, and the diameter of the central part is greater than the width of each straight line segment in the radial part.

[0096] Then, step S12 is performed to form a polysilicon gate 220 and a polysilicon source 210 that are spaced apart and insulated in the cell trench 101 , wherein the polysilicon gate 220 is disposed around the outside of the polysilicon source 210 .

[0097] This step specifically includes:

[0098] As shown in Figures 13 to 15, first, a first dielectric layer 130 is deposited on the inner wall (i.e., the side wall and bottom wall) of the cell groove 101. The first dielectric layer 130 fills the radiation part and is deposited on the inner wall of the central part. The first dielectric layer 130 also covers the surface of the substrate 100.

[0099] As shown in FIG. 16 to FIG. 18 , a polysilicon material layer is then deposited in the cell trench 101 , and the polysilicon material layer and the first dielectric layer 130 are etched to expose the substrate outside the cell trench 101 to form a polysilicon source 210 .

[0100] As shown in Figures 19-21, and also referring to Figure 12, the first dielectric layer 130 is then etched to form a gate trench 105. A portion of the gate trench 105 is located in the radiating portion, and another portion is located in the central portion. The depth of the gate trench 105 is less than the depth of the cell trench 101.

[0101] Next, a gate oxide layer is formed on the inner wall (side wall and bottom wall) of the gate trench 105 to prevent the polysilicon gate 220 subsequently formed in the gate trench 105 from being connected to the polysilicon source 210 and the source doping region 120 respectively.

[0102] As shown in FIG. 22 to FIG. 24 , a polysilicon material layer is then deposited on the surface of the gate oxide layer, and the polysilicon material layer is etched until the substrate outside the cell trench is exposed, thereby forming a polysilicon gate 220 .

[0103] 22 to 24 , step S13 is then performed to form a source doping region 120 in the substrate 100 outside the cell trench 101. Specifically, a body region 110 and a source doping region 120 are sequentially formed in the substrate 100 outside the cell trench 101, wherein the source doping region 120 is located in the body region 110 and is disposed close to the surface of the substrate 100.

[0104] As shown in Figures 25 to 27, step S14 is then performed to form a source metal 400 on the substrate 100. The source metal 400 is located above the source doping region 120 and the polysilicon source 210, and is connected to the source doping region 120 and the polysilicon source 210 respectively, and is spaced and insulated from the polysilicon gate 220.

[0105] This step specifically includes:

[0106] First, a spacer dielectric layer 300 is formed on the surface of the substrate 100. The spacer dielectric layer 300 covers the polysilicon gate 220, the polysilicon source 210 and the source doping region 120, and has a first opening 310 above the source doping region 120, and the first opening 310 exposes the source doping region 120. A second opening is provided above the polysilicon source 210, and the second opening exposes the polysilicon source 210.

[0107] Next, a source metal 400 is formed. Specifically, the source metal 400 is connected to the source doping region 120 at the first opening 310 and is connected to the polysilicon source 210 at the second opening.

[0108] In FIG28 , curve a is the Id-BV curve of the conventional shielded gate MOSFET structure 10 in FIG2 , and curve b is the Id-BV curve of the shielded gate MOSFET structure 10 of this embodiment. As can be seen from the figure, at the same voltage, the shielded gate MOSFET structure 10 of this embodiment has a larger current, that is, the shielded gate MOSFET structure 10 of this embodiment has a smaller on-capacitance Ron.

[0109] As shown in Fig. 9, this embodiment further provides a shielded gate power device, comprising a cell region I and a terminal region II, wherein the terminal region II is disposed around the cell region I. The cell region I is formed with a plurality of shielded gate MOSFET structures 10 distributed in an array.

[0110] A gate electrode is formed in terminal region II, which is connected to the polysilicon gate 220 of cell region I near terminal region II. Compared to the traditional two-dimensional cell layout (i.e., the elongated shielded gate MOSFET structure), the three-dimensional cell layout of this embodiment utilizes a three-dimensional charge compensation effect to enhance the depletion capability of the shielded gate power device. At the same time, the array-distributed cell trenches 101 achieve a densest packing effect, increasing channel density and reducing on-resistance (e.g., by 25%).

[0111] Continuing to refer to FIG4 , in this embodiment, a trench structure is formed in the substrate 100 of the cell region I. The trench structure is composed of a plurality of parallel first trenches 102 and a plurality of parallel second trenches 103. The first trenches 102 and the second trenches 103 are arranged perpendicularly to each other, so that the trench structure is a cross-shaped grid structure. The trench structure can also be composed of a plurality of parallel first trenches 102, a plurality of parallel second trenches 103, and a plurality of parallel third trenches 104. The first trenches 102, the second trenches 103, and the third trenches 104 are arranged to intersect at the same point, so that the trench structure is a hexagonal grid structure. Each grid node region of the grid structure constitutes a shielded gate MOSFET structure 10.

[0112] The cross section of the first groove 102 and the second groove 103 at the intersection is circular, and the cross section of the first groove 102 and the second groove 103 outside the intersection is strip-shaped.

[0113] The first trench 102 , the second trench 103 and the third trench 104 all have extensions, which extend from the cell region I to the terminal region II. A gate metal is formed in the terminal region II, and the gate metal is connected to the polysilicon gate in the extension.

[0114] This embodiment provides a method for manufacturing a shielded gate power device, comprising the following steps:

[0115] Step S21: providing a substrate 100;

[0116] Step S22: forming a plurality of shielded gate MOSFET structures 10 distributed in an array in the cell region I.

[0117] Step S22 specifically includes:

[0118] First, a groove structure is formed in the substrate 100 of the cell area I, and the groove structure consists of a plurality of parallel first grooves 102 and a plurality of parallel second grooves 103, and the first grooves 102 and the second grooves 103 are arranged to intersect vertically, so that the groove structure is a cross-shaped grid structure; or, the groove structure consists of a plurality of parallel first grooves 102, a plurality of parallel second grooves 103 and a plurality of parallel third grooves 104, and the first grooves 102, the second grooves 103 and the third grooves 104 are arranged to intersect at the same point, so that the groove structure is a hexagonal grid structure.

[0119] Then, a body region 110 and a source doping region 120 are formed in sequence in the substrate 100 of the cell region I. The source doping region 120 is located in the body region 110, and the source doping region 120 is arranged close to the substrate surface. The body region 110 and the source doping region 120 are located in a grid surrounded by the grid structure.

[0120] Next, a source metal 400 and a gate metal 11 are formed. The source metal 400 is located above the source doping region 120 and the polysilicon source 210, and is connected to the source doping region 120 and the polysilicon source 210 respectively. The gate metal 11 is located in the terminal region II and is connected to the extension of the polysilicon gate 220.

[0121] In summary, the present invention provides a shielded gate MOSFET structure, a shielded gate power device, and a preparation method. The shielded gate MOSFET structure includes a source doped region and a cell trench formed in a substrate, the source doped region being located outside the cell trench, and a polysilicon gate and a polysilicon source being formed in the cell trench in a spaced and insulated manner. The polysilicon gate is disposed around the outside of the polysilicon source, and the polysilicon gate is spaced and insulated from the source doped region to enhance the depletion capability of the device and thereby reduce on-resistance. In addition, the shielded gate power device of the present invention achieves the densest packing effect of cells, increases channel density, and reduces on-resistance.

[0122] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0123] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A shielded gate MOSFET structure, characterized in that: It includes a source doping region and a cell trench formed in a substrate, wherein the source doping region is located outside the cell trench, and a polysilicon gate and a polysilicon source are formed in the cell trench and are spaced and insulated, the polysilicon gate is arranged around the outside of the polysilicon source, and the polysilicon gate and the source doping region are spaced and insulated.

2. The shielded gate MOSFET structure according to claim 1, wherein: The shape of the cellular groove is a central radial pattern, which includes a central part and a radial part that are interconnected. The radial part is located outside the central part. The central part is circular and consists of a plurality of straight line segments arranged around the central part.

3. The shielded gate MOSFET structure according to claim 2, wherein: The polysilicon source is located in the central part, a part of the polysilicon gate is located in the radiation part, and another part is located in the central part and is arranged in a ring outside the polysilicon source.

4. The shielded gate MOSFET structure according to claim 1, wherein: It also includes a source metal, which is located above the source doping region and the polysilicon source, and is connected to the polysilicon source and the source doping region respectively, and is spaced and insulated from the polysilicon gate.

5. The shielded gate MOSFET structure of claim 4, wherein: It also includes an interval dielectric layer, a first dielectric layer and a gate oxide layer, wherein the interval dielectric layer covers the surface of the polysilicon gate, and the interval dielectric layer has a first opening above the source doping region, the first opening exposes the source doping region, and has a second opening above the polysilicon source, the second opening exposes the polysilicon source, so that the source metal is connected to the source doping region at the first opening and connected to the polysilicon source at the second opening; the first dielectric layer and the gate oxide layer are both formed on the inner wall of the cell trench, and the first dielectric layer is arranged around the outside of the polysilicon source, and the gate oxide layer is arranged around the outside of the polysilicon gate.

6. The shielded gate MOSFET structure of claim 2, wherein: The diameter of the central portion is greater than the width of each straight line segment in the radiating portion.

7. A method for preparing a shielded gate MOSFET structure, characterized in that: The following steps are involved: providing a substrate, in which a cell trench is formed; A polysilicon gate and a polysilicon source are formed in the cell trenches and are spaced and insulated. The polysilicon gate ring is arranged outside the polysilicon source; A source doping region is formed in the substrate outside the cell trench, and the polysilicon gate is spaced apart from and insulated from the source doping region.

8. The method for preparing a shielded gate MOSFET structure according to claim 7, wherein: The shape of the cellular groove is a central radial pattern, which includes a central part and a radial part that are interconnected. The radial part is located outside the central part. The central part is circular, and the radial part is composed of multiple straight line segments.

9. The method for preparing a shielded gate MOSFET structure according to claim 8, wherein: The method of forming the polysilicon gate and the polysilicon source is: forming a first dielectric layer, wherein the first dielectric layer fills the radiation portion and is deposited on an inner wall of the central portion; forming a polysilicon source electrode in the cell trench of the central portion; Etching the first dielectric layer to form a gate trench, wherein a portion of the gate trench is located in the radiation portion and another portion of the gate trench is located in the central portion; forming a gate oxide layer on the inner wall of the gate trench; A polysilicon gate is formed in the gate trench.

10. The method for preparing a shielded gate MOSFET structure according to claim 7, wherein: After forming the source doping region, the method further includes: A source metal is formed, wherein the source metal is located above the source doping region and the polysilicon source, and is connected to the polysilicon source and the source doping region respectively, and is spaced and insulated from the polysilicon gate.

11. The method for preparing a shielded gate MOSFET structure according to claim 10, wherein: The method of forming the source metal is: A spacer dielectric layer is formed on the surface of the substrate, the spacer dielectric layer covers the polysilicon gate and has a first opening above the source doping region, the first opening exposes the source doping region, and a second opening above the polysilicon source, the second opening exposes the polysilicon source; A source metal is formed, wherein the source metal is connected to the source doping region at the first opening and is connected to the polysilicon source at the second opening.

12. The method for preparing a shielded gate MOSFET structure according to claim 8, wherein: The diameter of the central portion is greater than the width of each straight line segment in the radiating portion.

13. A shielded gate power device, characterized in that: The invention comprises a plurality of shielded gate MOSFET structures according to any one of claims 1 to 6, wherein all the shielded gate MOSFET structures are distributed in an array.

14. The shielded gate power device according to claim 13, characterized in that: The shielded gate power device comprises a cell region and a terminal region, wherein the terminal region is arranged around the cell region, and the shielded gate MOSFET structure is located in the cell region.

15. The shielded gate power device according to claim 14, characterized in that: A groove structure is formed in the substrate of the cell region, the groove structure is composed of a plurality of first grooves arranged in parallel and a plurality of second grooves arranged in parallel, the first grooves and the second grooves are arranged to intersect vertically, so that the groove structure is a cross-shaped grid structure; Alternatively, the groove structure is composed of a plurality of first grooves arranged in parallel, a plurality of second grooves arranged in parallel, and a plurality of third grooves arranged in parallel, and the first grooves, the second grooves, and the third grooves are arranged to intersect at the same point, so that the groove structure is a hexagonal star-shaped grid structure; Wherein, a shielded gate MOSFET structure is formed in each grid node region of the grid structure.

16. The shielded gate power device according to claim 15, characterized in that: The first trench, the second trench and the third trench all have an extension portion, and the extension portion extends from the cell region to the terminal region. A gate metal is formed in the terminal region, and the gate metal is connected to the polysilicon gate in the extension portion.

17. A method for preparing a shielded gate power device, characterized in that: The following steps are involved: providing a substrate; A plurality of shielded gate MOSFET structures according to any one of claims 1 to 6 are formed in the substrate, and all the shielded gate MOSFET structures are distributed in an array.

18. The method for preparing a shielded gate power device according to claim 17, characterized in that: The method of forming a plurality of array-distributed shielded gate MOSFET structures comprises: A groove structure is formed in the substrate of the cell region, wherein the groove structure is composed of a plurality of first grooves arranged in parallel and a plurality of second grooves arranged in parallel, wherein the first grooves and the second grooves are arranged to intersect each other vertically, so that the groove structure is a cross-shaped grid structure; or the groove structure is composed of a plurality of The first grooves are arranged in parallel, a plurality of second grooves are arranged in parallel, and a plurality of third grooves are arranged in parallel, wherein the first grooves, the second grooves, and the third grooves are arranged to intersect at the same point, so that the groove structure is a hexagonal star-shaped grid structure; A polysilicon source and a polysilicon gate are formed in the trench structure, wherein the polysilicon gate is arranged around the outside of the polysilicon source, and the polysilicon gate and the polysilicon source are spaced and insulated; forming a source doping region in the substrate of the cell region, wherein the source doping region is located in a grid surrounded by the grid-like structure; A source metal and a gate metal are formed, wherein the source metal is located above the source doping region and the polysilicon source and is respectively connected to the source doping region and the polysilicon source, and the gate metal is located in the terminal region, and the first trench, the second trench and the third trench all have an extension portion, and the extension portion extends from the cell region to the terminal region and is connected to the polysilicon gate in the extension portion.

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