Refresh control circuit and memory

Abstract

The present invention relates to a refresh control circuit and a memory. The refresh control circuit comprises: a switching identifier signal generation circuit, configured to: when a refresh operation indication signal indicates that a belonging memory is in a fine granularity refresh mode, count all-bank refresh commands received by the belonging memory when in the fine granularity refresh mode, and when the count value of the all-bank refresh commands is an odd number, generate and output a switching control identifier at an effective level; and a mode switching control circuit, configured to: on the basis of a refresh mode indication signal and the switching control identifier, generate and output the refresh operation indication signal, wherein when the refresh mode indication signal indicates that the belonging memory is switched to a normal refresh mode, and if a switching control signal is at an effective level, the level of the output refresh operation indication signal remains unchanged.

Description

Refresh control circuit and memory

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202310919532.4, filed on July 25, 2023, entitled “Refresh Control Circuit and Memory,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of semiconductor circuit design, and in particular to a refresh control circuit and a memory. Background Art

[0004] DDR5 SDRAM (Double Data Rate fifth-generation Synchronous Dynamic Random-Access Memory) is a high-bandwidth memory. DDR5 typically includes two refresh modes and two types of refresh commands. The two refresh modes include normal refresh mode and fine-grained refresh mode. (Compared to normal refresh mode, fine-grained refresh mode activates fewer word lines per tRFC. For example, in normal refresh mode, one tRFC performs four ACTIVE operations, while in fine-grained refresh mode, one tRFC performs two ACTIVE operations.) The two types of refresh commands include full-array refresh command REFab and same-array refresh command REFsb. (The full-array refresh command REFab is used to refresh all arrays of the memory, while the same-array refresh command REFsb is used to refresh a target array of the memory.) The full-array refresh command REFab can typically be executed in both refresh modes, while the same-array refresh command REFsb can only be executed in fine-grained refresh mode. If a same-array refresh command is issued in normal refresh mode, it will be blocked because it cannot be executed.

[0005] For DDR5, before the memory switches from fine-grained refresh mode to normal refresh mode, it is recommended that the memory controller issue an even number of full-array refresh commands REFab or an even number of identical array refresh commands REFsb. If the conditions are not met, the memory controller will issue an additional full-array refresh command REFab before the memory refresh mode is changed. This additional full-array refresh command REFab is not included in the calculation of the average refresh interval (tREFI1).

[0006] In addition, this additional full array refresh command REFab may cause the memory to repeatedly refresh some arrays when the refresh mode is frequently switched, resulting in a waste of memory refresh resources.

[0007] Summary of the Invention

[0008] An embodiment of the present disclosure provides a refresh control circuit, comprising: a switch flag signal generating circuit, receiving a refresh operation indication signal and a full array refresh command, the refresh operation indication signal instructing a corresponding memory to perform a normal refresh or a fine-grained refresh; the switch flag signal generating circuit being configured to, when the refresh operation indication signal indicates that the corresponding memory is in a fine-grained refresh mode, count the number of full array refresh commands received by the corresponding memory while in the fine-grained refresh mode, and, when the count value of the full array refresh commands is an odd number, generate and output a switch control flag at an active level; a mode switching control circuit, coupled to the switch flag signal generating circuit, receiving the refresh mode indication signal and the switch control flag, and generating and outputting a refresh operation indication signal based on the refresh mode indication signal and the switch control flag; wherein the refresh mode indication signal indicates whether the corresponding memory is currently in a normal refresh mode or a fine-grained refresh mode; and the mode switching control circuit being configured to, when the refresh mode indication signal instructs the corresponding memory to switch to a normal refresh mode, maintain the level of the output refresh operation indication signal unchanged if the switch control signal is at an active level, thereby instructing the corresponding memory to continue performing a fine-grained refresh based on a next full array refresh command.

[0009] Optionally, the switching identification signal generating circuit includes: a first AND logic circuit, a first input end for receiving a refresh operation indication signal, and a second input end for receiving a full array refresh command, and is configured to generate and output a counting identification based on the full array refresh command when the refresh operation indication signal instructs the corresponding memory to perform a fine-grained refresh; a counting circuit, configured to receive the counting identification and count based on the counting identification to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control identification.

[0010] Optionally, the counting circuit includes: a first trigger, a clock end for receiving a counting flag, an input end connected to an inverting output end, an output end for outputting a switching control flag, and in an initial state, the switching control flag output by the first trigger is at an invalid level.

[0011] Optionally, the mode switching control circuit includes: a first OR logic circuit, a first input end for receiving a refresh mode indication signal, and a second input end for receiving a switching control identifier; a first delay circuit, an input end connected to the output end of the first OR logic circuit, and an output end for outputting a refresh operation indication signal.

[0012] Optionally, the mode switching control circuit is further configured to flip the level of the output refresh operation indication signal when the fine-grained refresh operation executed based on the next full array refresh command is completed.

[0013] Optionally, the mode switching control circuit includes: a first OR logic circuit, a first input end for receiving a refresh mode indication signal, and a second input end for receiving a switching control identifier; a first delay circuit, an input end connected to the output end of the first OR logic circuit; a latch, an input end connected to the output end of the first delay circuit, a control end for receiving a refresh window signal, and an output end for outputting a refresh operation indication signal.

[0014] Optionally, the switching identification signal generating circuit is further used to receive an identical array refresh identification signal, wherein, when the memory to which it belongs performs a refresh operation based on the identical array refresh command and each time the last array in the storage array group performs a refresh, an identical array refresh identification signal is generated; the switching identification signal generating circuit is configured to, when the refresh operation indication signal indicates that the memory to which it belongs is in the fine-grained refresh mode, count the identical array refresh identification signals received by the memory to which it belongs during the fine-grained refresh mode, and when the count value of the identical array refresh identification signal is an odd number, generate and output a switching control identification at a valid level.

[0015] Optionally, the switching identification signal generating circuit includes: a first AND logic circuit, a first input end for receiving a refresh operation indication signal, and a second input end for receiving a full array refresh command; a second OR logic circuit, a first input end connected to the output end of the first AND logic circuit, a second input end for receiving the same array refresh identification signal, and an output end for outputting a counting identification; a counting circuit, configured to receive the counting identification and count based on the counting identification to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control identification.

[0016] Optionally, the counting circuit includes: a first trigger, a clock end for receiving a counting flag, an input end connected to an inverting output end, an output end for outputting a switching control flag, and in an initial state, the switching control flag output by the first trigger is at an invalid level.

[0017] Optionally, the refresh control circuit further includes: a refresh identification signal generating circuit, configured to generate an identical array refresh identification signal.

[0018] Optionally, the refresh identification signal generating circuit includes: N latches, N is the number of storage arrays in each storage array group in the corresponding memory, and the N latches are arranged in a one-to-one correspondence with the N storage arrays in each storage array group, the set end of each latch is used to receive the same array refresh command corresponding to the corresponding storage array, and the output end of each latch is used to output the corresponding array refresh identification signal; a second AND logic circuit includes N input ends, and the N input ends are connected to the output ends of the N latches in a one-to-one correspondence, and the output end is used to output the same array refresh identification signal; a second delay circuit, the input end is used to receive the same array refresh identification signal, and the output end is connected to the input end of the first inverter; the output end of the first inverter is used to output a reset control signal, and the reset end of each latch is coupled to the output end of the first inverter.

[0019] Optionally, the latch includes: a first OR-NOT logic circuit, a first input end serving as a set end of the latch, for receiving the same array refresh command corresponding to the corresponding storage array, a second input end connected to the output end of the second OR-NOT logic circuit, and an output end connected to the first input end of the second OR-NOT logic circuit; a second input end of the second OR-NOT logic circuit serving as a reset end of the latch, connected to the output end of a second inverter, the input end of the second inverter serving as an output end of the latch, for outputting a corresponding array refresh identification signal.

[0020] Optionally, the refresh identification signal generating circuit also includes: a third OR-NOT logic circuit, the first input end of which is used to receive a full array refresh command, and the second input end of which is used to receive a self-refresh command; a third AND logic circuit, the first input end of which is connected to the output end of the third OR-NOT logic circuit, the second input end of which is used to receive a reset control signal, and the output end of which is connected to the reset end of each latch.

[0021] Another embodiment of the present disclosure further provides a memory, comprising the refresh control circuit provided by the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] FIG1 is a schematic structural diagram of a refresh control circuit based on a full array refresh command according to an embodiment of the present disclosure;

[0024] FIG2 is a schematic diagram illustrating a principle of performing a refresh operation using an additional full array refresh command as a full array refresh command in a fine-grained refresh mode in the example of FIG1 according to an embodiment of the present disclosure;

[0025] FIG3 is a schematic structural diagram of the switching identification signal generating circuit shown in FIG1 according to an embodiment of the present disclosure;

[0026] FIG4 is a schematic structural diagram of a counting circuit shown in FIG3 according to an embodiment of the present disclosure;

[0027] FIG5 is a schematic structural diagram of a mode switching control circuit provided in an embodiment of the present disclosure;

[0028] FIG6 is a schematic structural diagram of another refresh control circuit based on a full array refresh command according to an embodiment of the present disclosure;

[0029] FIG7 is a schematic structural diagram of a mode switching control circuit including a latch provided in one embodiment of the present disclosure;

[0030] FIG8 is a schematic diagram illustrating a principle of generating a refresh operation indication signal by the mode switching control circuit shown in FIG7 according to an embodiment of the present disclosure;

[0031] FIG9 is a schematic structural diagram of a refresh control circuit based on a full array refresh command and a same array refresh command according to an embodiment of the present disclosure;

[0032] FIG10 is a schematic diagram illustrating a principle of performing a refresh operation using an additional full array refresh command as a full array refresh command in a fine-grained refresh mode in the example of FIG9 according to an embodiment of the present disclosure;

[0033] FIG11 is a schematic structural diagram of the switching identification signal generating circuit shown in FIG9 according to an embodiment of the present disclosure;

[0034] FIG12 is a schematic structural diagram of another refresh control circuit based on a full array refresh command and a same array refresh command according to an embodiment of the present disclosure;

[0035] FIG13 is a schematic diagram showing the principle of the refresh control circuit of FIG12 according to an embodiment of the present disclosure;

[0036] FIG14 is a schematic structural diagram of a refresh identification signal generating circuit provided by an embodiment of the present disclosure;

[0037] FIG15 is a schematic structural diagram of a latch provided by an embodiment of the present disclosure;

[0038] FIG16 is a schematic diagram showing the working principle of a refresh flag signal generating circuit according to an embodiment of the present disclosure;

[0039] FIG17 is a schematic structural diagram of another refresh identification signal generating circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] As known from the background, before switching from fine-grained refresh mode to normal refresh mode, the memory controller is recommended to issue an even number of full-array refresh commands REFab or an even number of identical array refresh commands REFsb. If these conditions are not met, the memory controller will issue an additional full-array refresh command REFab before the memory refresh mode is changed. This additional full-array refresh command REFab is not included in the calculation of the average refresh interval (tREFI1). In addition, this additional full-array refresh command REFab will cause some arrays to be repeatedly refreshed when the memory frequently switches between refresh modes, resulting in a waste of memory refresh resources.

[0041] An embodiment of the present disclosure provides a refresh control circuit that uses an additional full-array refresh command as a full-array refresh command in a fine-grained refresh mode to perform a refresh operation. This ensures that the number of full-array refresh commands executed by a memory in the fine-grained refresh mode is even, thereby better managing the frequent switching of the memory between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full-array refresh commands.

[0042] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0043] The refresh control circuit provided in this embodiment is described in detail below with reference to the accompanying drawings, specifically as follows:

[0044] For refresh control of existing circuits, the memory refresh mode is changed by coding the MRW command to MR4_OP <4> Specifically, when MR4_OP <4> = "0", the memory performs normal refresh (Normal Refresh); when MR4_OP <4> = "1", the memory performs fine-grained refresh (FGR). This disclosure <4> The signal is processed to control the refresh of the memory.

[0045] 1 , the refresh control circuit 100 includes: a switch identification signal generating circuit 101 for receiving a refresh operation indication signal MR4_OP <4> _1 and full array refresh command CMD_REFab, wherein the refresh operation instruction signal MR4_OP <4> _1 is used to indicate that the memory to which it belongs performs normal refresh or fine-grained refresh.

[0046] In one example, when the refresh operation indication signal MR4_OP <4> _1="1", the memory performs fine-grained refresh. When the refresh operation indication signal MR4_OP <4> When the refresh operation indication signal is set to "1", the memory performs a normal refresh. This example configuration is used in the subsequent description of this embodiment to facilitate understanding of the technical solution of this disclosure by those skilled in the art, and does not limit this embodiment. In other embodiments, the memory can also be configured to perform a normal refresh when the refresh operation indication signal is set to "1", and to perform a fine-grained refresh when the refresh operation indication signal is set to "0".

[0047] The switch identification signal generating circuit 101 is configured to generate a refresh operation indication signal MR4_OP when the refresh operation indication signal MR4_OP <4> _1 indicates that the memory is in fine-grained refresh mode, the full array refresh commands CMD_REFab received by the memory during the fine-grained refresh mode are counted, and when the count value of the full array refresh command CMD_REFab is an odd number, a switching control flag FGR_CMD_ODD at a valid level is generated and output.

[0048] Regarding the switching control flag, in the example of the present disclosure, the effective level of the switching control flag FGR_CMD_ODD is taken as a high level "1" as an example to illustrate so that those skilled in the art can understand the technical solution of the present disclosure, and it does not constitute a limitation of this embodiment; in other embodiments, the effective level of the switching control flag can also be set to a high level "0".

[0049] Continuing with reference to FIG1 , the refresh control circuit 100 further includes: a mode switching control circuit 102 coupled to the switching flag signal generating circuit 101 for receiving the switching control flag FGR_CMD_ODD generated by the flag signal generating circuit 101 and receiving the refresh mode indication signal MR4_OP <4> _0, wherein the refresh mode indication signal MR4_OP <4> _0 is used to indicate that the memory is currently in normal refresh mode or in fine-grained refresh mode, which is the MR4_OP mentioned above. <4> signal, accordingly, when the refresh mode indication signal MR4_OP <4> _0="0", the memory is currently in fine-grained refresh mode. When the refresh mode indication signal MR4_OP <4> _0="1", the memory is currently in normal refresh mode.

[0050] The mode switching control circuit 102 is configured to, based on the refresh mode indication signal MR4_OP <4> _0 and the switch control flag FGR_CMD_ODD generate and output the refresh operation instruction signal MR4_OP <4> _1, wherein the refresh mode indication signal MR4_OP <4> _0 indicates that the memory is switched to normal mode. If the switch control signal is at a valid level, the refresh operation indication signal MR4_OP is maintained. <4> The level of _1 remains unchanged to instruct the corresponding memory to continue to perform fine-grained refresh based on the next full array refresh command CMD_REFab.

[0051] 2, during the normal execution of the refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 value and refresh mode indication signal MR4_OP <4> _0 is the same, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the full array refresh command CMD_REFab issued by the storage controller is an even number, and the refresh mode switching of the memory is performed normally; when the full array refresh command CMD_REFab issued by the storage controller is an odd number, the memory will issue an additional full array refresh command CMD_REFab before the refresh mode is changed, and the flag generating circuit 101 generates a switching control flag FGR_CMD_ODD at a valid level based on the odd number of full array refresh commands CMD_REFab, and the switching control flag FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of _0 is extended (the level extension instructing the memory to perform fine-grained refresh) to generate the refresh operation indication signal MR4_OP <4> _1, wherein the specific delay duration is t1, t1 includes the time when the switching control flag FGR_CMD_ODD is at an effective level and the refresh time based on the next full array refresh command CMD_REFab of the memory, so that when the memory controller issues an additional (next) full array refresh command CMD_REFab, the refresh operation indication signal MR4_OP of the memory <4> _1 instructs the memory to perform a fine-grained refresh; at this time, the memory performs a fine-grained refresh based on the additional (next) full-array refresh command CMD_REFab, so that the full-array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, and the refresh mode switching of the memory is then performed normally. As can be seen, this embodiment uses the additional full-array refresh command CMD_REFab as the full-array refresh command CMD_REFab in the fine-grained refresh mode for refresh operations, so that the full-array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the memory from frequently switching between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full-array refresh command.

[0052] Regarding the switching identification signal generating circuit, in some embodiments, referring to FIG3 , the switching identification signal generating circuit 101 includes: a first AND logic circuit 201 , a first input terminal for receiving a refresh operation indication signal MR4_OP <4> _1, the second input terminal is used to receive the full array refresh command CMD_REFab, the first AND logic circuit 201 is configured to, when the refresh operation indication signal MR4_OP <4> When _1 indicates that the memory to which it belongs is performing fine-grained refresh, a counting flag MR4_OP_OR is generated and output based on the full array refresh command CMD_REFab. The counting circuit 203 is configured to receive the counting flag MR4_OP_OR and count based on the counting flag to generate a counting result. When the counting result is an odd number, it generates and outputs a valid switching control flag FGR_CMD_ODD.

[0053] In one example, referring to Figure 4, the counting circuit 203 can be set based on the first trigger 204. Specifically, the clock terminal CK of the first trigger 204 is used to receive the counting flag MR4_OP_OR, the input terminal D is connected to the inverting output terminal Q-, and the output terminal Q is used to output the switching control flag FGR_CMD_ODD. In the initial state, the switching control flag FGR_CMD_ODD output by the first trigger 204 is in an invalid state.

[0054] As for the working principle of the first flip-flop 204, specifically, the counting flag MR4_OP_OR received by the clock terminal is at the valid edge, that is, when the memory performs fine-grained refresh, it receives the full array refresh command CMD_REFab, and the first flip-flop 204 outputs based on the input data. When the input data of the input terminal D is "0", the output terminal Q output switching control flag FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1"; when the input data of the input terminal D is "1", the output terminal Q output switching control flag FGR_CMD_ODD is "0". _ODD is "1", and the output data of the inverting output terminal Q-connected to the input terminal is "0", that is, the switching control flag FGR_CMD_ODD output by the first flip-flop 204 realizes the jump between "0" and "1" based on the valid edge of the input signal MR4_OP_OR of the clock terminal CK. When the control receives an odd number of the full array refresh command CMD_REFab, the switching control flag FGR_CMD_ODD output by the first flip-flop 204 is "1", thereby realizing the counting of the full array refresh command CMD_REFab received when performing fine-grained refresh on the memory.

[0055] For the mode switching control circuit, in some embodiments, referring to FIG5 , the mode switching control circuit 102 includes: a first OR logic circuit 401 , a first input terminal for receiving the refresh mode indication signal MR4_OP <4> _0, the second input end is used to receive the switching control flag FGR_CMD_ODD; the first delay circuit 402, the input end is connected to the output end of the first OR logic circuit 401, and the output end is used to output the refresh operation indication signal MR4_OP <4> _1.

[0056] Based on the above, it can be known that the switch control flag FGR_CMD_ODD at the valid level will refresh the mode indication signal MR4_OP <4> The level of _0 is extended (the level extension instructing the memory to perform fine-grained refresh) to generate the refresh operation indication signal MR4_OP <4> _1, wherein the specific delay duration is t1, t1=t11+t12, t11 is the refresh mode indication signal MR4_OP <4> _0 indicates the time that the switching control flag FGR_CMD_ODD remains at an active level after the associated memory switches to normal refresh mode, and t12 is the time the memory refreshes based on the next full array refresh command CMD_REFab. In the circuit shown in Figure 5, the level extension of t11 is implemented based on the first OR logic circuit 401, and the level extension of t12 is implemented based on the first delay circuit 402. That is, the delay time of the input signal of the first delay circuit 402 is set to the refresh time of the memory based on the next full array refresh command CMD_REFab, so as to enable the memory to perform fine-grained refresh based on the additional (next) full array refresh command CMD_REFab.

[0057] In other embodiments, since both the delay circuit and the refresh control circuit are greatly affected by PVT (process, voltage, temperature) factors, the delay time of a single delay unit in different memories is different, and the pulse width time of the refresh window signal generated by the refresh control circuit is also different. Therefore, the time of tl2 cannot be accurately controlled; in addition, the execution time of the refresh operation corresponding to different refresh modes is also different (because each refresh command can select to perform one or more refresh operations according to the refresh mode, the execution time of the refresh operation corresponding to different modes is also different). Therefore, the time of t12 is uncontrollable. If the time set to t12 is very short, it cannot completely cover the refresh operation window corresponding to the next refresh command. If the time set to t12 is very long, it may increase the power consumption of the circuit and may even cover the next multiple refresh commands. On this basis, the mode switching control circuit 102 is further configured to output the refresh operation indication signal MR4_OP when the fine-grained refresh operation executed based on the next full-array refresh command is completed. <4> _1 level flip, that is, refresh operation indication signal MR4_OP <4> _1 will instruct the memory to perform normal refresh operation, and the memory refresh mode change is completed.

[0058] 6, the mode switching control circuit 102 is further configured to receive a refresh window signal WIN_REF. Specifically, the mode switching control circuit 102 includes: a first OR logic circuit 401, a first input terminal for receiving a refresh mode indication signal MR4_OP; <4> _1, the second delay circuit 402, the input end is connected to the output end of the first OR logic circuit 401, the latch, the input end of the latch is connected to the output end of the first delay circuit 401, the control end is used to receive the refresh window signal WIN_REF, and the output end is used to output the refresh operation indication signal MR4_OP <4> _1.

[0059] The refresh window signal WIN_REF is a refresh window opened by the memory based on each full array refresh command CMD_REFab, and corresponding memory cells are opened within the refresh window to perform a refresh operation of the memory.

[0060] Referring to FIG. 7 , in one example, the latch may be implemented based on a D latch 403. Specifically, the input terminal D of the D latch 403 is connected to the output terminal of the first delay circuit 401, and the output terminal Q is used to output the refresh operation indication signal MR4_OP. <4> _1, the control terminal CK, i.e., the control terminal of the latch, is used to receive the refresh window signal WIN_REF, and the control terminal CK of the D latch 403 is configured to output the signal of the input terminal D from the output terminal Q based on the low-level refresh window signal WIN_REF (i.e., after the current refresh operation is completed), that is, when the memory completes the refresh operation and the refresh window signal WIN_REF jumps to a low level, based on the extended refresh mode indication signal received at the input terminal D (at this time, the extended refresh mode indication signal has been set to a low level based on the current full array refresh command REFab), the output refresh operation indication signal MR4_OP is set to a low level. <4> _1 level flip.

[0061] For the example of Figure 7, its working principle is shown in Figure 8. The output signal A of the first OR logic circuit 401 generates the output signal B after the first delay 402. The output signal B is used as the input signal of the D latch 403. The output signal B received by the input terminal D is sampled based on the low-level refresh window signal WIN_REF to generate the refresh operation indication signal MR4_OP. <4> _1, at this time, the refresh operation execution signal MR4_OP <4> The high level time of _1 covers the refresh window signal WIN_REF opened by the additional (next) full array refresh command CMD_REFab, so as to realize the fine-grained refresh of the memory based on the additional (next) full array refresh command CMD_REFab; in addition, based on the low level refresh window signal WIN_REF sampling output signal B to make the refresh operation indication signal MR4_OP <4> The level of _1 is flipped, making the time of t12 mentioned above controllable.

[0062] It should be noted that, for the example in FIG7 , the delay time t2 of the first delay circuit 402 needs to be set to be greater than the delay time between the additional (next) full array refresh command CMD_REFab and its corresponding refresh window signal WIN_REF, so as to ensure that the output signal B remains at a high level before the corresponding refresh window signal WIN_REF is at a valid level (high level); in addition, the delay time t2 can also be set to any value not greater than the refresh time of the memory based on the next full array refresh command CMD_REFab, that is, the valid time of the refresh window signal WIN_REF.

[0063] In some embodiments, the refresh control circuit 100 is further used to control the refresh of the memory when the refresh mode of the same array switches to the normal refresh mode.

[0064] Specifically, referring to FIG9 , the switching flag signal generating circuit 101 is further configured to receive a same-array refresh flag signal REFsb_CNT. The same-array refresh flag signal REFsb_CNT is generated when the memory to which it belongs performs a refresh operation based on the same-array refresh command CMD_REFsb and each time the last array in the memory array group performs a refresh. In other words, the same-array refresh flag signal REFsb_CNT indicates that the memory has completed a full array refresh in the same-array refresh mode.

[0065] The switch identification signal generating circuit 101 is configured to generate a refresh operation indication signal MR4_OP when the refresh operation indication signal MR4_OP <4> _1 indicates that the memory is in the fine-grained refresh mode, the same array refresh identification signal REFsb_CNT received by the memory during the fine-grained refresh mode is counted, and when the count value of the same array refresh identification signal is an odd number, a switching control flag FGR_CMD_ODD at a valid level is generated and output.

[0066] The function of the mode control circuit 102 is the same as that of the mode control circuit 102 shown in FIG. 1 , which can be seen in the above description and will not be repeated in this embodiment.

[0067] 11, during the normal execution of the refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 value and refresh mode indication signal MR4_OP <4> _0 has the same value, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the same array refresh command CMD_REFsb issued by the storage controller is an even array (that is, the number of the same array refresh identification signal REFsb_CNT is an even number). At this time, the refresh mode switching of the memory is executed normally; when the same array refresh command CMD_REFsb issued by the storage controller is an odd array (that is, the number of the same array refresh identification signal REFsb_CNT is an odd number), before the refresh mode of the memory is changed, the storage controller will issue an additional full array refresh command CMD_REFab, and the identification generation circuit 101 generates a switching control identification FGR_CMD_ODD at a valid level based on the odd number of the same array refresh identification signal REFsb_CNT. The switching control identification FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of _0 is extended (the level extension instructing the memory to perform fine-grained refresh) to generate the refresh operation indication signal MR4_OP <4> _1, wherein the specific delay duration is t3, t3 includes the time when the switching control flag FGR_CMD_ODD is at an effective level and the refresh time based on the next full array refresh command CMD_REFab of the memory, so that when the memory controller issues an additional full array refresh command CMD_REFab, the refresh operation indication signal MR4_OP of the memory <4> _1 instructs the memory to perform a fine-grained refresh; at this time, the memory performs a fine-grained refresh based on the additional full-array refresh command CMD_REFab, so that the full-array refresh command CMD_REFab and the same-array refresh command CMD_REFsb executed by the memory in the fine-grained refresh mode are an even number, and the refresh mode switching of the memory is then performed normally. As can be seen, this embodiment uses the additional full-array refresh command CMD_REFab as the full-array refresh command CMD_REFab in the fine-grained refresh mode to perform a refresh operation, so that the full-array refresh command CMD_REFab and the same-array refresh command CMD_REFsb executed by the memory in the fine-grained refresh mode are an even number, thereby better maintaining the memory from frequently switching between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full-array refresh command.

[0068] For the switching identification signal generating circuit shown in FIG9 , in some embodiments, referring to FIG10 , the identification signal generating circuit 101 includes: a first AND logic circuit 201 , a first input terminal for receiving a refresh operation indication signal MR4_OP <4> _1, and a second input terminal for receiving the full array refresh command CMD_REFab. A second OR logic circuit 202 has a first input terminal connected to the output terminal of the first AND logic circuit 201, a second input terminal for receiving the same array refresh flag signal REFsb_CNT, and an output terminal for outputting a count flag MR4_OP_OR. A counting circuit 203 is configured to receive the count flag MR4_OP_OR and count based on the count flag to generate a count result. When the count result is an odd number, it generates and outputs a valid switching control flag FGR_CMD_ODD.

[0069] In one example, referring to Figure 4, the counting circuit 203 can be set based on the first trigger 204. Specifically, the clock terminal CK of the first trigger 204 is used to receive the counting flag MR4_OP_OR, the input terminal D is connected to the inverting output terminal Q-, and the output terminal Q is used to output the switching control flag FGR_CMD_ODD. In the initial state, the switching control flag FGR_CMD_ODD output by the first trigger 204 is in an invalid state.

[0070] As for the working principle of the first flip-flop 204, specifically, the counting flag MR4_OP_OR received by the clock terminal is at the valid edge, that is, when the memory performs fine-grained refresh, it receives the full array refresh command CMD_REFab, and the first flip-flop 204 outputs based on the input data. When the input data of the input terminal D is "0", the output terminal Q output switching control flag FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1"; when the input data of the input terminal D is "1", the output terminal Q output switching control flag FGR_CMD_ODD is "0". _ODD is "1", and the output data of the inverting output terminal Q-connected to the input terminal is "0", that is, the switching control flag FGR_CMD_ODD output by the first flip-flop 204 realizes the jump between "0" and "1" based on the valid edge of the input signal MR4_OP_OR of the clock terminal CK. When the control receives an odd number of the full array refresh command CMD_REFab, the switching control flag FGR_CMD_ODD output by the first flip-flop 204 is "1", thereby realizing the counting of the full array refresh command CMD_REFab received when performing fine-grained refresh on the memory.

[0071] Among them, the functions of the first AND logic circuit 201 and the counting circuit 203 are the same as those in the example of Figure 3, and are not repeated in this embodiment. The example of Figure 10 implements the joint counting of the full array refresh command CMD_REFab and the same array refresh identification signal REFsb_CNT through the OR logic circuit 202, so that the number of groups of the full array refresh command CMD_REFab and the same array refresh command CMD_REFsb executed by the memory in the fine-grained refresh mode is an even number.

[0072] Based on the above, it can be known that the switch control flag FGR_CMD_ODD at the valid level will refresh the mode indication signal MR4_OP <4> The level of _0 is extended (the level extension instructing the memory to perform fine-grained refresh) to generate the refresh operation indication signal MR4_OP <4> _1, wherein the specific delay time is t1, t1=t31+t32, t31 is the refresh mode indication signal MR4_OP <4> _0 indicates the time during which the switching control flag FGR_CMD_ODD remains at a valid level after the memory switches to the normal refresh mode, and t32 is the refresh time of the memory based on the next full array refresh command CMD_REFab.

[0073] In some embodiments, both the delay circuit and the refresh control circuit are greatly affected by PVT (process, voltage, temperature) factors. The delay time of a single delay unit in different memories is different, and the pulse width time of the refresh window signal generated by the refresh control circuit is also different. Therefore, the time of t32 cannot be accurately controlled; in addition, the execution time of the refresh operation corresponding to different refresh modes is also different (because each refresh command can select to perform one or more refresh operations according to the refresh mode, the execution time of the corresponding refresh operation in different modes is also different). Therefore, the time of t32 is uncontrollable. If the time set to t32 is very short, it cannot completely cover the refresh operation window corresponding to the next refresh command. If the time set to t32 is very long, it may increase the power consumption of the circuit and may even cover the next multiple refresh commands. On this basis, the mode switching control circuit 102 is also configured to output the refresh operation indication signal MR4_OP when the fine-grained refresh operation executed based on the next full-array refresh command is completed. <4> _1 level flip, that is, refresh operation indication signal MR4_OP <4> _1 will instruct the memory to perform normal refresh operation, and the memory refresh mode change is completed.

[0074] Specifically, referring to FIG12, the mode switching control circuit 102 is further configured to receive a refresh window signal WIN_REF. Specifically, the mode switching control circuit 102 includes: a first OR logic circuit 401, a first input terminal for receiving a refresh mode indication signal MR4_OP <4> _1, the second delay circuit 402, the input end is connected to the output end of the first OR logic circuit 401, the latch, the input end of the latch is connected to the output end of the first delay circuit 401, the control end is used to receive the refresh window signal WIN_REF, and the output end is used to output the refresh operation indication signal MR4_OP <4> _1.

[0075] Referring to FIG. 7 , in one example, the latch may be implemented based on a D latch 403. Specifically, the input terminal D of the D latch 403 is connected to the output terminal of the first delay circuit 401, and the output terminal Q is used to output the refresh operation indication signal MR4_OP. <4> _1, the control terminal CK, i.e., the control terminal of the latch, is used to receive the refresh window signal WIN_REF, and the control terminal CK of the D latch 403 is configured to output the signal of the input terminal D from the output terminal Q based on the low-level refresh window signal WIN_REF (i.e., after the current refresh operation is completed), that is, when the memory completes the refresh operation and the refresh window signal WIN_REF jumps to a low level, based on the extended refresh mode indication signal received at the input terminal D (at this time, the extended refresh mode indication signal has been set to a low level based on the current full array refresh command REFab), the output refresh operation indication signal MR4_OP is set to a low level. <4> _1 level flip.

[0076] For the example of FIG12, its working principle is referred to FIG13, based on the low level refresh window signal WIN_REF sampling input terminal D receiving signal to generate the refresh operation indication signal MR4_OP <4> _1, at this time, the refresh operation execution signal MR4_OP <4> The high level time of _1 covers the refresh window signal WIN_REF opened by the additional (next) full array refresh command CMD_REFab, so as to realize the fine-grained refresh of the memory based on the additional (next) full array refresh command CMD_REFab; in addition, the output signal B is sampled based on the low level refresh window signal WIN_REF to trigger the refresh operation indication signal MR4_OP <4> The level flip of _1 makes the time of t32 mentioned above controllable.

[0077] In some embodiments, the refresh control circuit 100 further includes a refresh flag signal generating circuit configured to generate the same array refresh flag signal REFsb_CNT.

[0078] In one example, referring to FIG14 , the refresh flag signal generating circuit 103 includes: N latches 301, where N is the number of memory arrays in each memory array group within the memory to which it belongs, and the N latches 301 are provided in a one-to-one correspondence with the N memory arrays in each memory array group. The set terminal of each latch 301 is used to receive the same array refresh command CMD_REFsb corresponding to the corresponding memory array, and the output terminal of each latch 301 is used to output the corresponding array refresh flag signal WIN_SB_REF. A second AND logic circuit 302 includes N input terminals, which are connected in a one-to-one correspondence with the output terminals of the N latches 301, and the output terminal is used to output the same array refresh flag signal REFsb_CNT. The second delay circuit 303 has an input terminal for receiving the same array refresh identification signal REFsb_CNT, and an output terminal connected to the input terminal of the first inverter 304. The output terminal of the first inverter 304 is used to output the reset control signal REFsb_CNT_PULL, and the reset terminal of each latch 301 is coupled to the output terminal of the first inverter.

[0079] Referring to Figures 14 to 16 , each memory includes M memory array groups (Bank Groups), each memory array group (Bank Group) includes N memory arrays (Banks), meaning each memory includes M*N memory arrays. The example in Figure 14 illustrates a case where each memory array group includes four memory arrays (memory array A, memory array B, memory array C, and memory array D) to facilitate understanding of the technical solutions disclosed herein by those skilled in the art and does not constitute a limitation of this embodiment.

[0080] The set end of latch S1 is used to receive the same array refresh command CMD_REFsb corresponding to storage array A <0> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF0. The set terminal of latch S2 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array B. <1> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF1. The set terminal of latch S3 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array C. <2> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF2. The set terminal of latch S4 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array D. <3> The reset end is used to receive the reset control signal REFsb_CNT_PULL, and the output end is used to output the array refresh identification signal WIN_SB_REF3.

[0081] For each latch 301, in one example, latch 301 is implemented based on an SR latch. Specifically, referring to FIG15 , latch 301 includes: a first OR logic circuit 310, wherein a first input terminal serves as a set terminal of latch 301 for receiving the same array refresh command CMD_REFsb corresponding to the corresponding memory array; a second input terminal is connected to the output terminal of a second OR logic circuit 320, and an output terminal is connected to the first input terminal of the second OR logic circuit 320; a second input terminal of the second OR logic circuit 320 serves as a reset terminal of latch 301 and is connected to the output terminal of a second inverter 330; the input terminal of the second inverter is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal serves as the output terminal of latch 301 for outputting the corresponding array refresh flag signal WIN_SB_REF. It should be noted that FIG15 illustrates the signal flow of latch S1 as an example, and those skilled in the art can replace it with the signal flow of latch S2, latch S3, or latch S4.

[0082] It should also be noted that, in other embodiments, the latch can also be implemented based on the RS latch. Those skilled in the art can modify the connection method of the latch 301 based on the example of Figure 15. If there is no effect different from that of this embodiment, it should all fall within the scope of protection of this disclosure.

[0083] 16 , the latch 301 sets the output terminal based on the same array refresh command CMD_REFsb to generate the corresponding array refresh identification signal WIN_SB_REF. A single same array refresh command CMD_REFsb is used to refresh the same memory array of all memory array groups. Four corresponding same array refresh commands CMD_REFsb are required to complete four refreshes of the same memory array group. When the last memory array is refreshed, the same array refresh identification signal REFsb_CNT output by the second AND logic circuit 302 is set to “1”. After a delay of t4 by the second delay circuit 303, the reset control signal REFsb_CNT_PULL output by the first inverter is set to “0”. The reset control signal REFsb_CNT_PULL feedback controls the latch 301 so that the corresponding array refresh identification signal WIN_SB_REF is set to “0”. The same array refresh identification signal REFsb_CNT output by the second AND logic circuit 302 is set to “1”. Set to "0", that is, the memory completes the refresh of a memory array group, and the refresh identification signal generating circuit 103 generates a valid pulse of the same array refresh identification signal REFsb_CNT. Among them, the delay t4 of the second delay circuit 303 can be set to any value.

[0084] In addition, the same array refresh identification signal REFsb_CNT must complete the refresh of a storage array group for the memory. In order to prevent the refresh mode change from interfering with the generation of the same array refresh identification signal REFsb_CNT, in some embodiments, referring to Figure 17, the refresh identification signal generating circuit 103 also includes: a third OR logic circuit 304, a first input end for receiving the full array refresh command CMD_REFab, and a second input end for receiving the self-refresh command CMD_SREF; a third AND logic circuit 305, a first input end connected to the output end of the third OR logic circuit 304, a second input end for receiving the reset control signal REFsb_CNT_PULL, and an output end connected to the reset end of each latch 301. That is, if the refresh mode of the memory changes during the process of refreshing based on the same array refresh command CMD_REFsb, the refresh flag signal generating circuit 103 directly resets the latch 301 based on the self-refresh command CMD_SREF and the full array refresh command CMD_REFab, thereby not generating the same array refresh flag signal REFsb_CNT, so as to ensure that the memory completes the refresh of one storage array group before generating the same array refresh flag signal REFsb_CNT.

[0085] In this embodiment, an additional (next) full-array refresh command CMD_REFab is used as the full-array refresh command CMD_REFab in the fine-grained refresh mode for the refresh operation. This ensures that the number of full-array refresh commands CMD_REFab and the same array refresh command CMD_REFsb executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the memory from frequently switching between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full-array refresh command.

[0086] It should be noted that the features disclosed in the refresh control circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new refresh control circuit embodiments.

[0087] Another embodiment of the present disclosure provides a memory, including the refresh control circuit provided by the above embodiment, for performing a refresh operation by using an additional (next) full-array refresh command as a full-array refresh command in a fine-grained refresh mode. This ensures that the number of full-array refresh commands executed by the memory in the fine-grained refresh mode is even, thereby better maintaining the memory from frequently switching between different refresh modes and avoiding waste of memory refresh resources caused by additional full-array refresh commands.

[0088] 2, during the normal execution of the refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 value and refresh mode indication signal MR4_OP <4> _0 is the same, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the full array refresh command CMD_REFab issued by the storage controller is an even number, and the refresh mode switching of the memory is performed normally; when the full array refresh command CMD_REFab issued by the storage controller is an odd number, the memory will issue an additional full array refresh command CMD_REFab before the refresh mode is changed, and the flag generating circuit 101 generates a switching control flag FGR_CMD_ODD at a valid level based on the odd number of full array refresh commands CMD_REFab, and the switching control flag FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of _0 is extended (the level extension instructing the memory to perform fine-grained refresh) to generate the refresh operation indication signal MR4_OP <4> _1, wherein the specific delay duration is t1, t1 includes the time when the switching control flag FGR_CMD_ODD is at the valid level and the signal transmission delay, so that when the memory controller issues the next full array refresh command CMD_REFab, the memory refresh operation indication signal MR4_OP <4> _1 instructs the memory to perform a fine-grained refresh; at this time, the memory performs a fine-grained refresh based on the additional full-array refresh command CMD_REFab, so that the full-array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, and the memory refresh mode switch is then executed normally. As can be seen, this embodiment uses the additional full-array refresh command CMD_REFab as the full-array refresh command CMD_REFab in the fine-grained refresh mode to perform a refresh operation, so that the full-array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the memory from frequently switching between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full-array refresh command.

[0089] 10, during the normal execution of the refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 value and refresh mode indication signal MR4_OP <4> _0 has the same value, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the same array refresh command CMD_REFsb issued by the storage controller is an even array (that is, the number of the same array refresh identification signal REFsb_CNT is an even number). At this time, the refresh mode switching of the memory is executed normally; when the same array refresh command CMD_REFsb issued by the storage controller is an odd array (that is, the number of the same array refresh identification signal REFsb_CNT is an odd number), before the refresh mode of the memory is changed, the storage controller will issue an additional full array refresh command CMD_REFab, and the identification generation circuit 101 generates a switching control identification FGR_CMD_ODD at a valid level based on the odd number of the same array refresh identification signal REFsb_CNT. The switching control identification FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of _0 is extended (the level extension instructing the memory to perform fine-grained refresh) to generate the refresh operation indication signal MR4_OP <4> _1, wherein the specific delay duration is t3, t3 includes the time when the switching control flag FGR_CMD_ODD is at an effective level and the refresh time based on the next full array refresh command CMD_REFab of the memory, so that when the memory controller issues an additional full array refresh command CMD_REFab, the refresh operation indication signal MR4_OP of the memory <4> _1 instructs the memory to perform a fine-grained refresh; at this time, the memory performs a fine-grained refresh based on the additional full-array refresh command CMD_REFab, so that the full-array refresh command CMD_REFab and the same-array refresh command CMD_REFsb executed by the memory in the fine-grained refresh mode are an even number, and the refresh mode switching of the memory is then performed normally. As can be seen, this embodiment uses the additional full-array refresh command CMD_REFab as the full-array refresh command CMD_REFab in the fine-grained refresh mode to perform a refresh operation, so that the full-array refresh command CMD_REFab and the same-array refresh command CMD_REFsb executed by the memory in the fine-grained refresh mode are an even number, thereby better maintaining the memory from frequently switching between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full-array refresh command.

[0090] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A refresh control circuit (100), comprising: The switch identification signal generating circuit (101) receives the refresh operation indication signal (MR4_OP <4> _1) and the full array refresh command (CMD_REFab), the refresh operation indication signal (MR4_OP <4> _1) Instruct the memory to perform normal refresh or fine-grained refresh; The switching identification signal generating circuit (101) is configured to generate a switching identification signal when the refresh operation indication signal (MR4_OP <4> _1) when indicating that the memory is in the fine-grained refresh mode, counting the full array refresh commands (CMD_REFab) received by the memory during the fine-grained refresh mode, and when the count value of the full array refresh command (CMD_REFab) is an odd number, generating and outputting a switching control flag (FGR_CMD_ODD) at a valid level; The mode switching control circuit (102) is coupled to the switching identification signal generating circuit (101) and receives the refresh mode indication signal (MR4_OP <4> _0) and the switching control flag (FGR_CMD_ODD), and based on the refresh mode indication signal (MR4_OP <4> _0) and the switching control flag (FGR_CMD_ODD) to generate and output the refresh operation instruction signal (MR4_OP <4> _1); wherein the refresh mode indication signal (MR4_OP <4> _0) indicates that the memory is currently in normal refresh mode or in fine-grained refresh mode; The mode switching control circuit (102) is configured to, when the refresh mode indication signal (MR4_OP <4> _0) indicates that the memory is switched to the normal refresh mode. If the switching control signal (FGR_CMD_ODD) is at a valid level, the refresh operation indication signal (MR4_OP <4> _1) remains unchanged to instruct the corresponding memory to continue to perform fine-grained refresh based on the next full array refresh command (CMD_REFab).

2. The refresh control circuit according to claim 1, wherein: The switching identification signal generating circuit (101) comprises: The first AND logic circuit (201) has a first input terminal for receiving the refresh operation indication signal (MR4_OP <4> _1), the second input terminal is used to receive the full array refresh command (CMD_REFab), and is configured to, when the refresh operation indication signal (MR4_OP <4> _1) when instructing the memory to perform fine-grained refresh, generating and outputting a count mark (MR4_OP_OR) based on the full array refresh command (CMD_REFab); The counting circuit (203) is configured to receive the counting flag (MR4_OP_OR) and perform counting based on the counting flag (MR4_OP_OR) to generate a counting result, and when the counting result is an odd number, generate and output the valid switching control flag (FGR_CMD_ODD).

3. The refresh control circuit according to claim 1 or 2, wherein: The mode switching control circuit (102) comprises: The first OR logic circuit (401) has a first input terminal for receiving the refresh mode indication signal (MR4_OP <4> _0), the second input terminal is used to receive the switching control identifier (FGR_CMD_ODD); The first delay circuit (402) has an input end connected to the output end of the first OR logic circuit (401), and an output end for outputting the refresh operation indication signal (MR4_OP <4> _1).

4. The refresh control circuit according to any one of claims 1 to 3, wherein: The mode switching control circuit (102) is further configured to, when the fine-grained refresh operation executed based on the next full array refresh command (CMD_REFab) is completed, output the refresh operation indication signal (MR4_OP <4> _1) level flip.

5. The refresh control circuit according to claim 4, wherein: The mode switching control circuit (102) comprises: The first OR logic circuit (401) has a first input terminal for receiving the refresh mode indication signal (MR4_OP <4> _0), the second input terminal is used to receive the switching control identifier (FGR_CMD_ODD); A first delay circuit (402), an input end of which is connected to the output end of the first OR logic circuit (401); The latch (403) has an input end connected to the output end of the first delay circuit (402), a control end for receiving a refresh window signal (WIN_REF), and an output end for outputting the refresh operation indication signal (MR4_OP <4> _1).

6. The refresh control circuit according to any one of claims 1 to 5, characterized in that: include: The switching identification signal generating circuit (101) is also used to receive the same array refresh identification signal (REFsb_CNT), wherein The memory performs a refresh operation based on a same array refresh command (CMD_REFsb), and generates a same array refresh identification signal (REFsb_CNT) each time the last array in the storage array group performs a refresh; The switching identification signal generating circuit (101) is configured to generate a switching identification signal when the refresh operation indication signal (MR4_OP <4> _1) when indicating that the memory to which it belongs is in the fine-grained refresh mode, the same array refresh identification signal (REFsb_CNT) received by the memory to which it belongs during the fine-grained refresh mode is counted, and when the count value of the same array refresh identification signal (REFsb_CNT) is an odd number, the switching control identification (FGR_CMD_ODD) at the valid level is generated and output.

7. The refresh control circuit according to claim 6, wherein: The switching identification signal generating circuit (101) comprises: The first AND logic circuit (201) has a first input terminal for receiving the refresh operation indication signal (MR4_OP <4> _1), the second input terminal is used to receive the full array refresh command (CMD_REFab); A second OR logic circuit (202), wherein the first input end is connected to the output end of the first AND logic circuit (201), the second input end is used to receive the same array refresh identification signal (REFsb_CNT), and the output end is used to output a count identification (MR4_OP_OR); The counting circuit (203) is configured to receive the counting flag (MR4_OP_OR) and perform counting based on the counting flag (MR4_OP_OR) to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control flag (FGR_CMD_ODD).

8. The refresh control circuit according to claim 2 or 7, wherein: The counting circuit (203) comprises: a first trigger (204), a clock terminal (CK) for receiving the counting mark (MR4_OP_OR), an input terminal (D) connected to an inverting output terminal (Q-), an output terminal (Q) for outputting the switching control mark (FGR_CMD_ODD), and in an initial state, the switching control mark (FGR_CMD_ODD) output by the first trigger is at an invalid level.

9. The refresh control circuit according to claim 6 or 7, wherein: Also includes: The refresh identification signal generating circuit (103) is used to generate the same array refresh identification signal (REFsb_CNT).

10. The refresh control circuit according to claim 9, wherein: The refresh identification signal generating circuit (103) comprises: N latches (301), N being the number of storage arrays in each storage array group in the memory, and the N latches (301) being arranged in one-to-one correspondence with the N storage arrays in each storage array group, the set end of each latch (301) being used to receive the same array refresh command (CMD_REFsb) corresponding to the corresponding storage array, and the output end of each latch (301) being used to output the corresponding array refresh identification signal (WIN_SB_REF); A second AND logic circuit (302) comprises N input terminals, wherein the N input terminals are connected to the output terminals of the N latches (301) in a one-to-one correspondence, and the output terminal is used to output the same array refresh identification signal (REFsb_CNT); A second delay circuit (303), the input end of which is used to receive the same array refresh identification signal (REFsb_CNT), and the output end of which is connected to the input end of the first inverter (304); The output end of the first inverter (304) is used to output a reset control signal (REFsb_CNT_PULL), and the reset end of each latch (301) is coupled to the output end of the first inverter (304).

11. The refresh control circuit according to claim 10, wherein: The latch (301) comprises: A first OR logic circuit (310), wherein the first input terminal is used as the set terminal of the latch (301) and is used to receive the same array refresh command (CMD_REFsb) corresponding to the corresponding storage array, the second input terminal is connected to the output terminal of the second OR logic circuit (320), and the output terminal is connected to the first input terminal of the second OR logic circuit (320); The second input end of the second OR-N logic circuit (320) serves as the reset end of the latch (301) and is connected to the output end of the second inverter (330); the input end of the second inverter (330) is used to receive the reset control signal (REFsb_CNT_PULL), and the output end serves as the output end of the latch (301) and is used to output the corresponding array refresh identification signal (WIN_SB_REF).

12. The refresh control circuit according to claim 10 or 11, wherein: The refresh identification signal generating circuit (103) further comprises: A third NOR logic circuit (304), a first input terminal for receiving the full array refresh command (CMD_REFab), and a second input terminal for receiving a self-refresh command (CMD_SREF); A third AND logic circuit (305) has a first input terminal connected to the output terminal of the third OR NOT logic circuit (304), and a second input terminal It is used to receive the reset control signal (REFsb_CNT_PULL), and the output end is connected to the reset end of each latch (301).

13. A memory, comprising the refresh control circuit (100) according to any one of claims 1 to 12.

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