Pixel circuit and display panel

Abstract

The present application provides a pixel circuit and a display panel. The pixel circuit comprises an initialization module, a control end thereof inputting a control signal; a control end of a light-emitting control module inputs a first light-emitting control signal; the duration of an extinguishing signal of the first light-emitting control signal overlaps the duration of a pulse signal of the control signal; the interval between the first level jump moment of the control signal and the third level jump moment of the first light-emitting control signal is gradually changed, or the interval between the second level jump moment of the control signal and the fourth level jump moment of the first light-emitting control signal is gradually changed.

Description

Pixel circuit and display panel

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 26, 2023, with application number 202310928942.5, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to pixel circuits and display panels. Background Art

[0003] With the development of display technology, people have higher and higher requirements on display panels. When display panels display images, there is a problem of screen flickering.

[0004] Summary of the Invention

[0005] The present application provides a pixel circuit and a display panel to solve the problem of screen flickering when the display panel displays an image.

[0006] The present application provides a pixel circuit, comprising:

[0007] A driving module connected between the first power supply terminal and the light-emitting module;

[0008] An initialization module is connected between the light emitting module and the initialization line, and a control terminal of the initialization module is configured to input a control signal;

[0009] Two light control modules are connected between the first power supply terminal and the second power supply terminal, and the control terminals of the light control modules are both configured to input a first light control signal;

[0010] The pulse width of the extinguishing signal of the first light-emitting control signal shows a decreasing trend; the duration of the extinguishing signal of the first light-emitting control signal overlaps with the duration of the pulse signal of the control signal;

[0011] The interval between the first level transition moment of the control signal and the third level transition moment of the first light emitting control signal gradually changes; or, the interval between the second level transition moment of the control signal and the fourth level transition moment of the first light emitting control signal gradually changes.

[0012] This arrangement can increase the on-time of the light control module, thereby increasing the light emitting time of the light emitting module, thereby improving the light emitting brightness of the light emitting module and solving the problem of flickering of the display panel.

[0013] According to another aspect of the present application, the present application provides a display panel, including: the pixel circuit proposed above.

[0014] The pixel circuit provided in the present application gradually reduces the pulse width of the extinguishing signal of the first light-emitting control signal by setting the interval between the first level jump moment of the control signal and the third level jump moment of the first light-emitting control signal to gradually change; or gradually changes the interval between the second level jump moment of the control signal and the fourth level jump moment of the first light-emitting control signal. By setting the pulse width of the extinguishing signal of the first light-emitting control signal to gradually reduce, the lighting signal of the light-emitting control module can be increased. The conduction time of the light-emitting control module can be increased, and the light-emitting time of the light-emitting module can be increased, thereby improving the light-emitting brightness of the light-emitting module, solving the problem of flickering of the display panel display screen, especially the flickering of the low grayscale display screen of the always on display (AOD). BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0016] FIG2a is a schematic diagram of a driving timing of a pixel circuit provided in an embodiment of the present application;

[0017] FIG2 b is a schematic diagram of a driving timing of another pixel circuit provided in an embodiment of the present application;

[0018] FIG3 is a schematic diagram of a driving timing of another pixel circuit provided in an embodiment of the present application;

[0019] FIG4 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0020] FIG5 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0021] FIG6 is a schematic diagram of a driving timing of another pixel circuit provided in an embodiment of the present application;

[0022] FIG7 is a schematic diagram of a driving timing of another pixel circuit provided in an embodiment of the present application;

[0023] FIG8 is a schematic structural diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application is described below in conjunction with the accompanying drawings and embodiments. The specific embodiments described herein are merely for explaining the present application. For ease of description, only the parts relevant to the present application are shown in the accompanying drawings.

[0025] Based on the above technical problems, this embodiment proposes the following solutions:

[0026] Figure 1 is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application. Figure 2a is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present application. Figure 2b is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of the present application. In conjunction with Figures 1 to 2b, the pixel circuit 10 provided in the embodiment of the present application includes a driving module 100, which is connected between the first power supply terminal ELVDD and the light-emitting module D1; an initialization module 2, which is connected between the light-emitting module D1 and the initialization line Vrefn, and the control end of the initialization module 2 is set to input the control signal C1; two light-emitting control modules 4, which are connected between the first power supply terminal ELVDD and the second power supply terminal ELVSS, and the control ends of the two light-emitting control modules 4 are both input with the first light-emitting control signal EM; the pulse width of the extinction signal of the first light-emitting control signal EM shows a decreasing trend; the duration of the extinction signal of the first light-emitting control signal EM overlaps with the duration of the pulse signal of the control signal C1; the interval between the first level jump moment t1 of the control signal C1 and the third level jump moment t3 of the first light-emitting control signal EM gradually changes; or, the interval between the second level jump moment t2 of the control signal C1 and the fourth level jump moment t4 of the first light-emitting control signal EM gradually changes.

[0027] The extinguishing signal of the first light emitting control signal EM refers to a signal indicating that the corresponding light emitting control module 4 is not conducting.

[0028] The first power supply terminal ELVDD is configured to input a first-level signal, and the second power supply terminal ELVSS is configured to input a second-level signal. The second power supply terminal ELVSS is connected to the second electrode of the light-emitting module D1. The first-level signal is typically a high level, and the second-level signal is typically a low level. The first electrode of the light-emitting module D1 can be an anode, and the second electrode of the light-emitting module D1 can be a cathode.

[0029] When the display device is displaying, data is written during the write frame and not during the hold frame. The write frame includes a data write phase. Because data writing in the pixel circuit during the data write phase requires the driver module 100, the driver module 100 operates differently during the write frame and the hold frame. Long-term research has revealed that during the data write phase, the data write module 1 of the pixel circuit is turned on in response to the first scan signal S1. The data voltage is written to the gate of the driver module 100. Because the hold frame lasts longer than the write frame, the gate voltage of the driver module 100 is maintained for a longer period during the hold frame, causing the compensation module 3 to leak current to the gate of the driver module 100. During the hold frame, the gate voltage of the driver module 100 increases, reducing the drive current of the driver module 100 and lowering the brightness of the light-emitting module D1. Within a frame of display, the brightness of the light-emitting module D1 gradually decreases, causing screen flickering when switching between adjacent frames.

[0030] In the light emitting stage, the light emitting control module 4 is turned on according to the first light emitting control signal EM.

[0031] Before the light-emitting phase, an initialization phase is also included. In the initialization phase, the initialization module 2 is connected between the light-emitting module D1 and the initialization line Vrefn. The initialization module 2 is turned on according to the control signal C1 input to its control terminal to transmit the initialization voltage to the first electrode of the light-emitting module D1.

[0032] The level transition moment refers to the moment when a level signal transitions from a level below a certain level to a level equal to or above the certain level, or the moment when a level signal transitions from a level above a certain level to a level equal to or below the certain level. The first level transition moment t1 of the control signal C1 precedes the second level transition moment t2. For example, the first level transition moment t1 may correspond to a falling edge, and the second level transition moment t2 may correspond to a rising edge. Alternatively, the first level transition moment t1 may correspond to a rising edge, and the second level transition moment t2 may correspond to a falling edge.

[0033] The third level transition time t3 of the first light emitting control signal EM is before the fourth level transition time t4. For example, the third level transition time t3 may correspond to a rising edge, and the fourth level transition time t4 may correspond to a falling edge.

[0034] Using the control signal C1 as a reference, the pulse width of the first emission control signal EM is adjusted for each frame by gradually adjusting the interval between the first level transition time t1 of the control signal C1 and the third level transition time t3 of the first emission control signal EM, or by gradually adjusting the interval between the second level transition time t2 of the control signal C1 and the fourth level transition time t4 of the first emission control signal EM. This arrangement allows the pulse width of the first emission control signal EM to be adjusted, and the pulse width of the extinguishing signal of the first emission control signal EM to be gradually reduced.

[0035] FIG2a exemplifies a case where the pulse width T1>T2>T3>T4 of the extinguishing signal of the first light-emitting control signal EM is greater than or equal to T1. The case where the interval T1'>T2'>T3'>T4' between the second level transition moment t2 of the control signal C1 and the fourth level transition moment t4 of the first light-emitting control signal EM is greater than or equal to T1 is not limited herein. FIG2b exemplifies a case where the pulse width T1>T2>T3>T4 of the extinguishing signal of the first light-emitting control signal EM is greater than or equal to T1. The case where the interval T1'>T2'>T3'>T4' between the first level transition moment t1 of the control signal C1 and the third level transition moment t3 of the first light-emitting control signal EM is greater than or equal to T1 is not limited herein.

[0036] During the hold frame, the drive current of the driver module 100 decreases due to leakage from the compensation module 3 to the gate of the driver module 100. While the frame frequency of the first light-emission control signal EM is constant, gradually decreasing the pulse width of the extinguishing signal of the first light-emission control signal EM increases the turn-on signal of the light-emission control module 4. This increases the on-time of the light-emission control module 4, thereby increasing the light-emission time of the light-emission module D1. This in turn stabilizes the brightness of the light-emission module D1 during the hold frame, thereby reducing flickering issues during display.

[0037] The duration of the extinguishing signal of the first light-emitting control signal EM overlaps with the duration of the pulse signal of the control signal C1, allowing the valid signal of the control signal C1 to reach the initialization module 2 during the non-luminous period of the light-emitting module D1. The valid signal of the control signal C1 turns on the initialization module 2, and the reference voltage transmitted on the initialization line Vrefn initializes the first electrode of the light-emitting module D1. Because the initialization voltage is a negative voltage, the potential of the second node N2 is reduced to the initialization voltage, thereby initializing the first electrode of the light-emitting module D1. Because the conduction frequency of the initialization module 2 in response to the control signal C1 is relatively high during the frame maintenance, it is lower than the frequency that can be detected by the human eye, thereby improving the screen flickering problem of the display panel.

[0038] The decreasing trend of the pulse width of the extinguishing signal of the first light-emitting control signal EM may include that the pulse width of the extinguishing signal of the first light-emitting control signal EM is first reduced, the pulse width of the extinguishing signal of the first light-emitting control signal EM is then kept unchanged, and the pulse width of the extinguishing signal of the first light-emitting control signal EM is further reduced. There is no limitation on this.

[0039] The pixel circuit 10 provided in this embodiment gradually reduces the pulse width of the extinguishing signal of the first light control signal EM by gradually varying the interval between the first level transition time t1 of the control signal C1 and the third level transition time t3 of the first light control signal EM; or by gradually varying the interval between the second level transition time t2 of the control signal C1 and the fourth level transition time t4 of the first light control signal EM. By gradually reducing the pulse width of the extinguishing signal of the first light control signal EM, the turn-on signal of the light control module 4 can be increased. This can increase the on-time of the light control module 4, thereby increasing the light-emitting time of the light-emitting module D1, thereby improving the brightness of the light-emitting module D1 and resolving the flickering problem of the display panel.

[0040] FIG2 a exemplarily shows a case where the frame frequency of the first light emitting control signal EM is 60 Hz, the frame frequencies of the control signal C1 are 60 Hz and 30 Hz, and the case where the control signal C1 includes a single pulse signal in each frame, without any limitation herein.

[0041] Figures 2a and 2b exemplarily show a case where the writing frame is 1 data frame, i.e., 1frame, and the holding frame includes 3 frames, i.e., 3 data frames, i.e., 3 frames. The holding frame can adjust the number of data frames included in the holding frame according to the display frequency of the display device, and no limitation is made here.

[0042] In one embodiment, FIG3 is a schematic diagram of a driving timing of another pixel circuit provided by an embodiment of the present application. In conjunction with FIG1 and FIG3, the interval between the first level transition moment t1 of the control signal C1 and the third level transition moment t3 of the first light-emitting control signal EM gradually decreases; or, the interval between the second level transition moment t2 of the control signal C1 and the fourth level transition moment t4 of the first light-emitting control signal EM gradually decreases. For example, within a frame, the control signal C1 includes at least two pulse signals; within each frame, the interval between the first level transition moment t1 of the last pulse signal of the at least two pulse signals of the control signal C1 and the third level transition moment t3 of the first light-emitting control signal EM within the same frame gradually decreases; or, the interval between the second level transition moment t2 of the last pulse signal and the fourth level transition moment t4 of the first light-emitting control signal EM within the same frame gradually decreases; wherein, the first level transition moment t1 is before the second level transition moment t2; and the third level transition moment t3 is before the fourth level transition moment t4.

[0043] This setting allows the initialization module 2 to be initialized separately according to at least two pulse signals of the control signal C1 in each frame in the maintenance frame. In this way, the first pole of the light-emitting module D1 can be initialized multiple times in each frame, thereby increasing the frequency of initialization of the first pole of the light-emitting module D1 and solving the screen flickering problem when the display panel displays the picture.

[0044] In each frame, the last pulse signal of the at least two pulse signals of the control signal C1 refers to the pulse signal with the longest time interval from the write frame among the at least two pulse signals of the control signal C1 in each data frame of the multiple data frames included in the hold frame.

[0045] FIG3 exemplarily shows a case where the frame frequency of the first light emitting control signal EM is 60 Hz, the frame frequencies of the control signal C1 are 60 Hz and 30 Hz, and the control signal C1 includes three pulse signals in each frame, without any limitation herein.

[0046] On the basis of the above embodiment, referring to FIG. 2 a and FIG. 3 , the duration of the extinguishing signal of the first light emitting control signal EM completely covers the duration of the multiple pulse signals of the control signal C1 .

[0047] This configuration ensures that the control signal C1 that controls the initialization module 2 to turn on corresponds to the extinguishing signal of the first light-emitting control signal EM. That is, during the light-emitting phase of the light-emitting module D1, the initialization module 2 is turned off. Only during the non-light-emitting phase of the light-emitting module D1 will the initialization module 2 be turned on in response to the control signal C1 to initialize the first electrode of the light-emitting module D1. This increases the frequency of initialization of the light-emitting module D1 by the initialization module 2, avoids affecting the normal display of the light-emitting module D1, and improves the display effect of the display panel.

[0048] In one embodiment, referring to Figure 1 , based on the above embodiment, the pixel circuit 10 may further include: a data writing module 1, connected between the first pole of the driving module 100 and the data line Data, and the control end of the data writing module 1 inputs the first scanning signal S1; a compensation module 3, the compensation module 3 is connected between the first pole of the light-emitting module D1 and the gate of the driving module 100.

[0049] The driver module 100 and the first power supply terminal ELVDD are connected to a first node N1. A light control module 4 may be disposed between the driver module 100 and the first power supply terminal ELVDD. The light emitting module D1 and the driver module 100 are connected to a second node N2. The light control module 4 may be disposed between the driver module 100 and the light emitting module D1. The data write module 1 is connected between the first node N1 and the data line Data. The control terminal of the data write module 1 receives a first scan signal S1. The compensation module 3 is connected between the second electrode of the driver module 100 and the gate of the driver module 100.

[0050] FIG4 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application. Based on the above embodiment, and in conjunction with FIG2a and FIG4 , control signal C1 includes a second scanning signal S1′; the pulse width of second scanning signal S1′ in the write frame is the same as the pulse width of second scanning signal S1′ in the hold frame.

[0051] This arrangement facilitates controlling the conduction state of the initialization module 2 according to the second scan signal S1'. The control signal C1 includes the second scan signal S1', which facilitates using the scan circuit in the display panel to generate the second scan signal S1', thereby reducing the cost of the display panel.

[0052] On the basis of the above embodiment, in combination with FIG. 3 and FIG. 4 , in each frame, the second scanning signal S1 ′ includes at least two first pulse signals, and the pulse widths of different first pulse signals are equal.

[0053] This configuration allows the initialization module 2 to perform initialization based on at least two first pulse signals of the second scanning signal S1' in each frame. This allows the first electrode of the light-emitting module D1 to be initialized multiple times within each frame, increasing the frequency of initialization of the first electrode of the light-emitting module D1 and resolving screen flickering issues when the display panel displays images.

[0054] Figure 5 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Figure 6 is a schematic diagram of the drive timing of another pixel circuit provided in an embodiment of the present application. Based on the above embodiment, and in conjunction with Figures 5 and 6 , control signal C1 includes a second light-emitting control signal EM2; the pulse width of the second light-emitting control signal EM2 in the write frame is smaller than the pulse width of the second light-emitting control signal EM2 in the hold frame; for example, within each hold frame, the pulse width of the second light-emitting control signal EM2 increases.

[0055] As shown in Figure 6, the wider the pulse width of the second light-emitting control signal EM2, the longer the on-time of the initialization module 2, and the more thorough the initialization of the first electrode of the light-emitting module D1. The pulse width of the second light-emitting control signal EM2 of the light-emitting module D1 during the write frame is shorter than the pulse width of the second light-emitting control signal EM2 during the hold frame. This shortens the reset time of the first electrode of the light-emitting module D1 during the write frame. Since the initialization voltage is set to a negative voltage, the voltage at the first electrode of the light-emitting module D1 is higher, improving the brightness of the light-emitting module D1 and significantly alleviating the low-frequency flicker problem of the display panel.

[0056] Referring to Figure 5 , the driver module 100 includes a driver transistor T1, the data writing module 1 includes a second transistor T2, the compensation module 3 includes a third transistor T3, the initialization module 2 includes a seventh transistor T7, and the two light emission control modules 4 include a fifth transistor T5 and a sixth transistor T6, respectively. The pixel circuit 10 may further include a gate reset module 5. The gate reset module 5 includes a fourth transistor T4, which is connected between the initialization line Vrefn and the gate of the driver module 100. The control terminal of the fourth transistor T4 receives the third scan signal S2.

[0057] In each frame of the hold frame, the increasing trend of the pulse width of the second light-emitting control signal EM2 may include: the pulse width of the second light-emitting control signal EM2 first increases, the pulse width of the second light-emitting control signal EM2 then remains unchanged, and the pulse width of the second light-emitting control signal EM2 increases again. There is no limitation on this.

[0058] On the basis of the above embodiment, in each frame, the second light emitting control signal EM2 may include at least two second pulse signals, and the pulse widths of the plurality of second pulse signals may be set to gradually increase.

[0059] Because the brightness of the light-emitting module D1 gradually decreases as the hold time increases during the hold frame, the pulse widths of the multiple second pulse signals included in the second light-emitting control signal EM2 gradually increase within each frame. This allows the second pulse signal corresponding to the second light-emitting control signal EM2 to have a larger pulse width at moments of severe brightness drop. This arrangement prolongs the reset time of the initialization module 2. This arrangement facilitates gradually decreasing the pulse width of the first light-emitting control signal EM by gradually increasing the pulse width of the second pulse signal of the second light-emitting control signal EM2, providing a new approach to improving the brightness of the light-emitting module D1 and resolving the problem of flickering on the display panel.

[0060] Based on the above embodiment, referring to FIG6 , within each frame of the hold frame, the time interval between the moment corresponding to the falling edge of the extinguishing signal of the last second pulse signal and the moment corresponding to the falling edge of the first light-emitting control signal EM gradually decreases.

[0061] This configuration can effectively reduce the pulse width of the first light-emitting control signal EM, thereby increasing the lighting signal duration of the first light-emitting control module 4, thereby increasing the on-time of the light-emitting control module 4 and, in turn, increasing the light-emitting duration of the light-emitting module D1. This provides a new approach to improving the brightness of the light-emitting module D1 and resolving the flickering problem of the display panel.

[0062] FIG6 exemplifies a case where, within each frame of a hold frame, the time interval T2'>T3'>T4' between the moment corresponding to the falling edge of the extinguishing signal of the last second pulse signal and the moment corresponding to the falling edge of the first light-emitting control signal EM is greater than or equal to the time interval T1' between the moment corresponding to the falling edge of the extinguishing signal of the last second pulse signal and the moment corresponding to the falling edge of the first light-emitting control signal EM within each frame of a hold frame. This is not intended to limit the case.

[0063] FIG7 is a schematic diagram of another driving timing sequence for a pixel circuit provided in an embodiment of the present application. Based on the above embodiment, referring to FIG7 , a hold frame includes multiple sub-hold frames, and in each sub-hold frame, the first light-emitting control signal EM includes M third pulse signals; M is an integer greater than or equal to 2; for example, the pulse widths of the M third pulse signals in each sub-hold frame are equal; the pulse widths of the third pulse signals in adjacent sub-hold frames are different.

[0064] The number of the third pulse signals in each sub-holding frame may be different, that is, different M. Preferably, the number of the third pulse signals in each sub-holding frame is the same, which can facilitate setting.

[0065] The holding frame is divided into equal parts to produce multiple sub-holding frames. For example, 1 Hz is divided into 8 equal parts. Each equal part contains 8 or 64 frames. The pulse width of the first light control signal EM in each of the 8 or 64 frames is the same. The pulse width of the first light control signal EM is gradually varied between the multiple equal parts. This can effectively increase the average brightness of the holding frame and improve the brightness decay problem of the display panel.

[0066] Based on the above embodiment, referring to FIG7 , as the duration of the sub-hold frame increases from the write frame, the pulse width of the third pulse signal of the multiple sub-hold frames gradually decreases. For example, as the duration of the sub-hold frame increases from the write frame, the pulse width of the third pulse signal of the multiple sub-hold frames gradually decreases.

[0067] This configuration facilitates differential compensation for the brightness attenuation of the light-emitting module D1 according to the brightness curve, thereby improving the brightness uniformity of the display panel.

[0068] On the basis of the above embodiment, referring to FIG. 7 , as the duration of the sub-holding frame increases from the writing frame, the difference between the pulse widths of the third pulse signals included in adjacent sub-holding frames gradually decreases.

[0069] In the holding frame, as the degree of brightness attenuation of the light-emitting module D1 tends to be gentle as time goes by, by setting the difference between the pulse widths of the third pulse signal of the first light-emitting control signal EM included in multiple sub-holding frames to gradually decrease, the compensation accuracy of the differentiated compensation for the brightness attenuation degree of the light-emitting module D1 can be improved, thereby improving the display effect of the display panel.

[0070] Figure 7 illustrates an exemplary raw transient brightness curve of light-emitting module D1 when the display panel frame rate is 1 Hz and the pulse width of the third pulse signal of the first light-emitting control signal EM remains unchanged. The first light-emitting control signal EM is denoted as base in Figure 7 . Scan in Figure 7 refers to a scan signal, including the first scan signal S1 and the third scan signal S2.

[0071] FIG7 exemplarily shows the transient brightness curve of the light-emitting module D1 when the pulse width of the third pulse signal of the first light-emitting control signal EM gradually decreases when the frame frequency of the display panel is 1 Hz. In FIG7 , N is the pulse width of the third pulse signal of the first light-emitting control signal EM of the write frame. The pulse width of the third pulse signal of the first light-emitting control signal EM of each sub-holding frame of the hold frame is equal to kN, where k is a positive number less than 1. In the direction from the write frame to the sub-holding frame, the value of k can be set to gradually decrease as needed. FIG7 exemplarily shows the cases where the values ​​of k are 0.85, 0.75, 0.7, 0.65, 0.63, 0.61 and 0.6, which are not limited here.

[0072] On the basis of the above embodiment, referring to FIG. 7 , the frame frequency of the control signal C1 is less than or equal to the frame frequency of the first light emitting control signal EM.

[0073] This configuration facilitates setting the frame rate of control signal C1 according to the refresh frequency of the display panel. When the refresh frequency of the display panel is high, the frame hold time is short, and the display panel screen flicker problem is relatively minor. In this case, the frame rate of control signal C1 can be set to a lower level, which not only meets the brightness compensation requirements of the display panel but also effectively conserves the hardware resources of the display panel. When the refresh frequency of the display panel is low, the frame hold time is long, and the display panel screen flicker problem is relatively severe. In this case, the frame rate of control signal C1 can be set to a higher level, which effectively meets the brightness compensation requirements of the display panel and improves the display effect.

[0074] On the basis of the above embodiment, referring to FIG6 , the frame frequency of the control signal C1 is greater than or equal to 30 Hz, and the frame frequency of the first light emitting control signal EM is greater than or equal to 60 Hz.

[0075] The control signal C1 may include 30 Hz, 60 Hz, or 90 Hz. The frame frequency of the first light emitting control signal EM may include 60 Hz or 90 Hz.

[0076] In the embodiment of the present application, the seventh transistor T7 is an N-type transistor, and the other transistors are P-type transistors, which are not limited here and can be set according to actual conditions.

[0077] FIG8 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Based on the above embodiments, referring to FIG8 , the display panel 20 provided in this embodiment includes the pixel circuit 10 provided in any of the above embodiments, and has the effects of the pixel circuit 10 provided in any of the above embodiments, which will not be described in detail here.

Claims

1. A pixel circuit, comprising: A driving module connected between the first power supply terminal and the light emitting module; An initialization module, connected between the light emitting module and the initialization line, wherein a control terminal of the initialization module is configured to input a control signal; Two light-emitting control modules are connected between the first power supply terminal and the second power supply terminal, and control terminals of the two light-emitting control modules are both configured to input a first light-emitting control signal; The pulse width of the extinguishing signal of the first light-emitting control signal shows a decreasing trend; the duration of the extinguishing signal of the first light-emitting control signal overlaps with the duration of the pulse signal of the control signal; The interval between the first level transition moment of the control signal and the third level transition moment of the first light emitting control signal changes gradually; or, the interval between the second level transition moment of the control signal and the fourth level transition moment of the first light emitting control signal changes gradually.

2. The pixel circuit according to claim 1, wherein: The interval between the first level transition moment of the control signal and the third level transition moment of the first light-emitting control signal gradually decreases; or, the interval between the second level transition moment of the control signal and the fourth level transition moment of the first light-emitting control signal gradually decreases.

3. The pixel circuit according to claim 2, wherein: In one frame, the control signal includes at least two pulse signals; In each frame, the interval between the first level transition moment of the last pulse signal of at least two pulse signals of the control signal and the third level transition moment of the first light-emitting control signal in the same frame gradually decreases; or, the interval between the second level transition moment of the last pulse signal and the fourth level transition moment of the first light-emitting control signal in the same frame gradually decreases; Among them, the first level jump time is before the second level jump time; the third level jump time is before the fourth level jump time.

4. The pixel circuit according to claim 2, wherein: The duration of the extinguishing signal of the first light emitting control signal completely covers the duration of the pulse signal of the control signal.

5. The pixel circuit according to claim 2, further comprising: A data writing module is connected between the first electrode of the driving module and the data line, and a control end of the data writing module is configured to input a first scanning signal; A compensation module is connected between the first electrode of the light emitting module and the gate of the driving module.

6. The pixel circuit according to claim 1, wherein: The control signal includes a second scanning signal; a pulse width of the second scanning signal of the write frame is the same as a pulse width of the second scanning signal of the hold frame.

7. The pixel circuit according to claim 6, wherein: In each frame, the second scanning signal includes at least two first pulse signals, and the pulse widths of the at least two first pulse signals are equal.

8. The pixel circuit according to claim 1, wherein: The control signal includes a second light emitting control signal; A pulse width of the second light emitting control signal of a write frame is smaller than a pulse width of the second light emitting control signal of a hold frame.

9. The pixel circuit according to claim 8, wherein: In each of the holding frames, the pulse width of the second light emitting control signal shows an increasing trend.

10. The pixel circuit according to claim 9, wherein: In each frame, the second light emitting control signal includes at least two second pulse signals, and the pulse widths of the at least two second pulse signals gradually increase.

11. The pixel circuit according to claim 10, wherein: In each of the holding frames, the time interval between the moment corresponding to the falling edge of the extinguishing signal of the last second pulse signal and the moment corresponding to the falling edge of the first light-emitting control signal gradually decreases.

12. The pixel circuit according to claim 1, wherein: The holding frame includes multiple sub-holding frames. In each sub-holding frame, the first light emitting control signal includes M third pulse signals; M is an integer greater than or equal to 2.

13. The pixel circuit according to claim 12, wherein: The pulse widths of the M third pulse signals in each sub-holding frame are equal; The pulse widths of the third pulse signals located in adjacent sub-holding frames are different.

14. The pixel circuit according to claim 13, wherein: As the duration of the sub-holding frame increases from the writing frame, the pulse width of the third pulse signal of the plurality of sub-holding frames tends to decrease.

15. The pixel circuit according to claim 14, wherein: The duration of the sub-holding frame increases from the writing frame, and the pulse width of the third pulse signal of the plurality of sub-holding frames gradually decreases.

16. The pixel circuit according to claim 14, wherein: The duration of the sub-holding frame increases from the writing frame, and the difference between the pulse widths of the third pulse signals of adjacent sub-holding frames gradually decreases.

17. The pixel circuit according to claim 1, wherein: The frame rate of the control signal is less than or equal to the frame rate of the first light emitting control signal.

18. The pixel circuit according to claim 17, wherein: The frame frequency of the control signal is greater than or equal to 30 Hz.

19. The pixel circuit according to claim 17, wherein: The frame frequency of the first light emitting control signal is greater than or equal to 60 Hz.

20. A display panel, comprising: The pixel circuit according to any one of claims 1 to 19.

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