Construction method and apparatus for assertion equivalence hardware library, electronic device, and storage medium

Abstract

The present application relates to the technical field of computers, and provides a construction method and apparatus for an assertion equivalence hardware library, an electronic device, a computer program, and a computer readable storage medium. The method comprises: determining logical relations between input signals and output signals of assertion operators to be processed, wherein said assertion operators are operators for implementing a basic assertion function in an assertion statement; on the basis of the logical relations, determining logic devices corresponding to said assertion operators and a connection mode of the logic devices; on the basis of the connection mode, connecting the logic devices corresponding to said assertion operators, and obtaining basic circuit modules corresponding to said assertion operators; and adding the basic circuit modules corresponding to said assertion operators into an assertion equivalence hardware library. The embodiments of the present application can improve the circuit synthesis efficiency of the assertion statement, thereby realizing assertion-based hardware verification.

Description

Method, device, electronic device and storage medium for constructing assertion equivalent hardware library

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 27, 2023, with application number 202310934158.5 and application name “Method, device, electronic device and storage medium for constructing assertion equivalent hardware library”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a method, device, electronic device, computer program, and computer-readable storage medium for constructing an assertion equivalent hardware library. Background Art

[0004] Hardware verification is often a bottleneck in the overall chip development cycle because simulation and debugging using traditional software simulators are extremely time-consuming. Assertions-based verification has been widely adopted in the verification process to provide better observability of design details and automatically catch unexpected behavior. Assertions are statements that describe design behavior and properties, used to check whether the design satisfies these properties at runtime. Using assertions, it is possible to verify that a design meets specific specifications and requirements. While assertion-based verification significantly improves verification efficiency, running assertions in software simulators is still time-consuming. To further enhance verification efficiency, FPGA prototyping can be used. Compared to traditional ASIC design flows, FPGA prototyping can convert the design under test into a logic gate-level description for the FPGA using high-level synthesis tools or hardware description languages ​​(such as VHDL or Verilog), completing the verification process faster and saving significant time and resources.

[0005] However, assertion statements are often written using complex procedural constructs, time operators, or functions that cannot be directly translated into hardware elements. This is because when designing from RTL (such as SystemVerilog, Verilog, etc.) and synthesizing it into hardware, synthesis tools need to convert the code into the corresponding hardware implementation. The goal is to generate an optimized circuit netlist that represents the expected behavior of the design. However, assertions may involve concepts that are difficult to map to hardware, such as complex algorithms, dynamic data structures, or non-deterministic behavior. Another reason why assertions cannot be synthesized is that they rely on simulation-specific functions such as $past. These system functions are very useful for capturing time-related behavior and history information during simulation, but they have no direct hardware equivalent. Therefore, assertion statements containing these constructs cannot be directly synthesized. This inability to synthesize means that the assertions cannot be generated into RTL circuits; without a corresponding actual RTL circuit, accelerated verification using FPGAs is impossible.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a method, apparatus, electronic device, computer program, and computer-readable storage medium for constructing an assertion equivalent hardware library to solve the problem in the prior art that assertion statements cannot be synthesized.

[0008] In a first aspect, an embodiment of the present application provides a method for constructing an assertion equivalent hardware library, the method comprising:

[0009] Determining a logical relationship between an input signal and an output signal of an assertion operator to be processed; the assertion operator is an operator that implements a basic assertion function in the assertion statement;

[0010] Determining a connection mode between the logic device corresponding to the assertion operator and the logic device according to the logical relationship;

[0011] Connecting the logic devices corresponding to the assertion operator in the connection manner to obtain a basic circuit module corresponding to the assertion operator;

[0012] Add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

[0013] In a second aspect, an embodiment of the present application provides a device for constructing an assertion equivalent hardware library, the device comprising:

[0014] A first determination module is configured to determine a logical relationship between an input signal and an output signal of an assertion operator to be processed; the assertion operator is an operator that implements a basic assertion function in the assertion statement;

[0015] A second determining module is used to determine the connection mode between the logic device corresponding to the assertion operator and the logic device according to the logical relationship;

[0016] a connection module, configured to connect the logic devices corresponding to the assertion operator in the connection manner to obtain a basic circuit module corresponding to the assertion operator;

[0017] An adding module is used to add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

[0018] In a third aspect, an embodiment of the present application provides an electronic device, including a processor;

[0019] a memory for storing instructions executable by the processor;

[0020] The processor is configured to execute the instructions to implement the method of the first aspect.

[0021] In a fourth aspect, an embodiment of the present application provides a computer program, comprising a computer-readable code, which, when executed on a computing and processing device, causes the computing and processing device to execute the method of the first aspect.

[0022] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program as described in the fourth aspect. When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is able to perform the method of the first aspect.

[0023] In summary, the method for constructing an assertion equivalent hardware library provided in the embodiment of the present application can determine the logic devices corresponding to the assertion operator and the connection method between each logic device according to the logical relationship between the input signal and the output signal of the assertion operator, and connect each logic device according to the determined connection method, so that the assertion operator can be converted into an equivalent basic circuit module; the obtained basic circuit module is added to the assertion equivalent hardware library, so that when the assertion statement is subjected to circuit synthesis processing, the non-synthesizable assertion statement can be directly converted into a synthesizable assertion circuit based on the basic circuit modules corresponding to each assertion operator in the assertion statement, thereby improving the circuit synthesis efficiency of the assertion statement, and further realizing assertion-based hardware verification.

[0024] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] FIG1 is a flowchart of an embodiment of a method for constructing an assertion equivalent hardware library of the present application;

[0027] FIG2 is a schematic structural diagram of a basic circuit module corresponding to a signal detection operator of the present application;

[0028] FIG3 is a schematic diagram of a $rose function of the present application;

[0029] FIG4 is a schematic diagram of a $past function of the present application;

[0030] FIG5 is a schematic diagram of a non-overlapping implication operator of the present application;

[0031] FIG6 is a schematic diagram of a delay operator of the present application;

[0032] FIG7 is a schematic diagram of an OR operator of the present application;

[0033] FIG8 is a structural block diagram of a device for constructing an assertion equivalent hardware library of the present application;

[0034] FIG9 schematically shows a block diagram of a computing processing device for executing the method according to the present application;

[0035] FIG10 schematically shows a storage unit for holding or carrying program codes for implementing the method according to the present application;

[0036] FIG11 is a block diagram of an electronic device provided in an embodiment of the present application. Specific embodiments

[0037] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0039] An embodiment of the present application provides a method for constructing an assertion equivalent hardware library, which can generate basic circuit modules corresponding to various assertion operators in assertion statements, and then construct an assertion equivalent hardware library based on the basic circuit modules corresponding to the assertion operators, so as to convert non-synthesizable assertion statements into equivalent synthesizable assertion circuits, improve the circuit synthesis efficiency of assertion statements, and thus realize assertion-based hardware verification.

[0040] To facilitate understanding of the embodiments provided in this application, the following points are explained:

[0041] 1. SV language (SystemVerilog) and SV assertion (SystemVerilog Assertion, SVA)

[0042] SystemVerilog is a hardware description language (HDL) used to design and verify digital circuits. It extends Verilog HDL, providing many new features and capabilities, making it more suitable for complex hardware design and verification tasks.

[0043] SVA is a key feature of SystemVerilog, used to describe and verify the behavior and properties of a system during the design and verification process. SVA allows designers to insert assertions into the hardware description to express properties about the design's behavior and state. SVA uses a syntax similar to sequential logic, which has rich expressive capabilities and can describe properties such as time correlation, sequence, and concurrency. SVA statements can be used for design verification, formal verification, and error debugging. SVA statements typically include the following:

[0044] i. Property: describes an expected or specified system behavior.

[0045] ii. Sequence: describes a sequence of events or states.

[0046] iii. Assertion: Combine attributes and sequences and specify when they are true

[0047] iv. Clocking Block: defines the clock and sampling timing.

[0048] v. Coverage: Used to evaluate the property coverage of the design.

[0049] 2. Assertion-based Verification

[0050] Assertions are an effective hardware design verification method used to ensure that a design meets specific specifications and requirements. Assertions are statements that describe the behavior and properties of a design and are used to verify that the design meets these properties at runtime. Assertion-based verification uses assertions to verify that a design meets specific specifications and requirements. It can improve verification efficiency, reduce errors, and help design teams quickly identify and resolve design issues.

[0051] In assertion verification, the design is divided into two parts: the Design Under Test (DUT) and the test environment (Testbench). The test environment includes components such as test vector generators, clocks, monitors, and assertion checkers. The test vector generator generates input data, the clock provides timing information, the monitor is used to detect the output of the design, and the assertion checker is used to check whether the design meets the specified assertions. The basic principle of assertion verification is that when the test vector drives the design to run, the monitor monitors the output of the design and compares it with the expected results. At the same time, the assertion checker evaluates the assertion statement and issues a verification error if the assertion fails (that is, the assertion is false). This method can quickly discover errors in the design during the verification process and help developers confirm whether the design meets the specification requirements.

[0052] 3. Circuit synthesis

[0053] In hardware circuit design, "synthesize" is used to describe whether hardware description language code can be converted into properties of equivalent hardware circuits. This conversion process is usually completed by circuit synthesis tools (such as logic synthesizers).

[0054] Synthesizable code is code that can be converted into hardware circuits using a logic synthesizer. Logic synthesis is the process of converting high-level, abstract code written in a hardware description language (such as SystemVerilog) into low-level hardware elements such as basic logic gates and registers. Synthesizable code should be clearly structured and timed, using only hardware primitives and constructs supported by the synthesis tool.

[0055] Non-synthesizable code is code that cannot be directly converted into hardware using a logic synthesizer. It contains features that make sense at a high level of abstraction but cannot be mapped to hardware, such as delays, loops, and conditional branches. This code is often used for non-synthesizable purposes such as simulation, verification, and testing.

[0056] Some syntax and features in SVA are not synthesizable because they are mainly used to describe and verify the behavior and properties of the system rather than directly describe the hardware structure. For example:

[0057] i. Behaviors with delays. The delays cannot be directly mapped to the hardware's sequential logic during synthesis.

[0058] ii. Sampling functions, such as "$rose()," "$stable()," and "$past()," are typically used in simulation environments to verify and debug designs. However, these sampling functions are generally unsynthesizable during synthesis because they cannot be directly mapped to equivalent elements in hardware circuits. Synthesis tools cannot directly convert these functions into hardware logic.

[0059] iii. Sequence operation keywords, such as intersect and firstmatch, are often used in the verification phase to check whether the design meets specific timing properties. Synthesis tools cannot directly convert these operators into hardware logic.

[0060] Because these features cannot be directly mapped to hardware circuits, synthesis tools cannot convert SVA code containing non-synthesizable features into equivalent hardware circuits. In actual designs, SVA is typically used in the verification phase rather than for direct hardware generation. Synthesizable hardware description language code and non-synthesizable verification code are usually written and used separately.

[0061] 4. Register-Transfer Level (RTL) circuit

[0062] RTL circuits are a common type of hardware description-level circuit. RTL circuits describe the behavior and structure of digital circuits and are represented using the register transfer level (RTL). RTL circuit descriptions are typically written in a hardware description language (HDL), such as VHSIC Hardware Description Language (VHDL), Verilog HDL, and SystemVerilog HDL. Designers can use RTL-level descriptions to define and implement the desired digital circuit functionality, and then use synthesis tools to convert the RTL-level descriptions into physical implementations in field-programmable gate arrays (FPGAs). In the field of FPGA and chip design and verification, RTL-level descriptions are crucial for design, verification, and debugging. They provide a level of abstraction that enables designers to describe circuit behavior at a higher level of abstraction and use appropriate tools for simulation, verification, and synthesis, ultimately generating a bitstream file that can be configured into the FPGA chip to implement the specific digital circuit functionality.

[0063] 5. FPGA

[0064] FPGAs are reconfigurable integrated circuits with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs, adapting them to different applications and functions. FPGAs consist of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, and can perform various logic functions. Programmable interconnect resources are used to connect logic blocks to form the desired circuit structure. Using FPGAs, designers can describe the desired circuit functionality using a hardware description language (HDL) and, using programming tools, convert this into a bitstream compatible with the FPGA chip. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the main advantages of FPGAs is their programmability and flexibility. They allow designers to implement customized functions and algorithms at the hardware level without the traditional custom IC design and manufacturing process. This makes FPGAs crucial for prototyping and rapid design iteration.

[0065] FPGA prototyping refers to the process of verifying and testing electronic system or chip designs using field-programmable gate array (FPGA) technology. During FPGA prototyping, circuit designs are converted into logic gate-level descriptions and mapped onto the FPGA chip using specialized software tools. By loading the design under test into the FPGA, designers can verify the circuit's functionality and performance and perform various tests and debugging. FPGA prototyping helps designers verify the correctness of their designs on actual hardware and identify and resolve potential issues early, thereby reducing subsequent design remediation costs. FPGA prototyping can also be used to evaluate the design's performance in real-world application environments and facilitate performance optimization and system integration. In summary, FPGA prototyping is an effective method for verifying and testing electronic system and chip designs, improving design quality and development efficiency.

[0066] 6. Dynamic Partial Reconfiguration (DPR)

[0067] Dynamic partial reconfiguration (DPR) of FPGAs refers to the ability to reconfigure portions of a circuit while the FPGA is running. In traditional FPGA designs, the entire circuit typically needs to be reprogrammed and reloaded into the FPGA to change its functionality. However, DPR technology allows only portions of the circuit to be reconfigured while the FPGA is running, without affecting other running circuits. The main advantages of dynamic partial reconfiguration lie in its flexibility and improved resource utilization. By using DPR, multiple functional modules can be implemented in the FPGA, each of which can be independently reconfigured as needed without reloading the entire design. This flexibility enables FPGAs to adapt to a variety of application requirements while reducing reprogramming and reloading time and accelerating design iterations.

[0068] 7. Abstract Syntax Tree

[0069] An Abstract Syntax Tree (AST) is a tree-like data structure used to represent the structure of program code. It is widely used in compilers and parsers to convert source code into a form that is easy to process and analyze. The AST reflects the grammatical structure of the code and discards unnecessary details such as whitespace, comments, and specific tags. It captures the logical structure and semantics of the code and provides a convenient way to analyze, transform, and optimize the code. In the AST, each code element (such as an expression, statement, function declaration, etc.) is represented as a node, and the nodes are connected through parent-child and sibling relationships. The root node of the tree represents the entire code, while the leaf nodes represent the most basic code units.

[0070] The advantages of AST include:

[0071] a. Structured representation: AST provides a structured way to represent code, making code parsing and analysis more intuitive and flexible.

[0072] b. Syntax independence: AST does not depend on the grammatical rules of a specific programming language, so it can be used to parse and process multiple programming languages.

[0073] c. Easy to analyze and transform: By traversing and manipulating AST nodes, static analysis, code optimization, refactoring, and other operations can be performed.

[0074] In short, an abstract syntax tree is a tree-shaped data structure used to represent the structure of program code. It provides a convenient way to analyze, transform, and optimize code.

[0075] 1 , there is shown a flowchart of an embodiment of a method for constructing an assertion equivalent hardware library of the present application. The method may specifically include the following steps:

[0076] Step 101: Determine the logical relationship between the input signal and the output signal of the assertion operator to be processed; the assertion operator is an operator that implements the basic assertion function in the assertion statement;

[0077] Step 102: Determine a connection mode between the logic device corresponding to the assertion operator and the logic device according to the logical relationship;

[0078] Step 103: Connect the logic devices corresponding to the assertion operator according to the connection mode to obtain a basic circuit module corresponding to the assertion operator;

[0079] Step 104: Add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

[0080] Among them, the assertion operator is an operator that implements the basic assertion function in the assertion statement. The assertion operator in the embodiment of the present application may include but is not limited to: immediate assertion, sequence sampling signal, sequence operator, signal detection (signal_check) operator, basic operator, timing operator (delay and repetition), each category contains several non-synthesizable keywords and operators, etc.

[0081] The main reason why assertion statements are not synthesizable is that they are usually written using complex procedural structures, time operators, functions, etc. These assertion operators cannot be directly converted into hardware elements. To convert assertion statements into synthesizable hardware equivalent circuits, these assertion operators need to be converted.

[0082] Specifically, the logical relationships between the input and output signals of various assertion operators can be used to determine the logic devices corresponding to each operator and the connection method between these logic devices. By connecting the logic devices according to the determined connection method, the basic circuit module corresponding to the assertion operator can be obtained. The generated basic circuit module is added to the assertion equivalent hardware library to complete the construction of the assertion equivalent hardware library.

[0083] A basic circuit module typically includes an enable terminal, an input terminal, and an output terminal. In an embodiment of the present application, the basic circuit module typically has two output terminals, one for outputting a "Match" signal indicating a successful assertion, and one for outputting a "Fail" signal indicating a failed assertion. Referring to FIG2 , a schematic diagram of the structure of a basic circuit module corresponding to a signal detection operator (signal_check) is shown. The signal detection operator is used to detect whether the input signal is true. As shown in FIG2 , "EN" is the enable signal port of the basic circuit module. Only when the previous level basic circuit module matches, that is, when the output signal of the previous level basic circuit module satisfies the method in the assertion statement, can the previous level match signal (that is, the output signal of the previous level basic circuit module) enable the current basic circuit module to input the result. "MATCH" and "FAIL" are the output ports of the basic circuit module. After the current module is activated, it is output to the next level or the entire assertion circuit. The three port structures in the basic circuit module ensure that the clock signal transmitted in the assertion circuit maintains normal timing.

[0084] The signal transmission mode, level change and other information between the input signal and the output signal in the basic circuit module are controlled by the underlying logic devices. The basic circuit module can realize the function of the corresponding assertion operator. For example, the basic circuit module signal_check corresponds to the signal detection operator, which is used to detect whether the input signal is true; the basic circuit module nonoverlapped implication operators is used to realize the function of the non-overlapping implication operator (|=>). Among them, the logic devices that make up the basic circuit module may include but are not limited to: gate circuits and inverters, selectors, decoders, counters, registers, triggers, latches, buffer drivers, transceivers, bus switches, state machines, etc. The logic devices contained in the basic circuit module are determined according to the functions it implements. The functions of the basic circuit module are different, and the logic devices contained are also different.

[0085] The various basic circuit modules in the embodiments of this application can be freely combined through a unified interface and support multi-bit-width input signals, the bit width of which can be specified at compile time. Using the assertion equivalent hardware library constructed in the embodiments of this application, the basic circuit modules corresponding to each assertion operator in the assertion statement to be synthesized can be directly obtained. By connecting the obtained basic circuit modules, the equivalent assertion circuit of the assertion statement can be obtained.

[0086] The method for constructing an assertion equivalent hardware library provided in an embodiment of the present application can determine the logic devices corresponding to the assertion operator and the connection method between each logic device based on the logical relationship between the input signal and the output signal of the assertion operator. By connecting each logic device according to the determined connection method, the assertion operator can be converted into an equivalent basic circuit module; the obtained basic circuit module is added to the assertion equivalent hardware library, so that when the assertion statement is subjected to circuit synthesis processing, the non-synthesizable assertion statement can be directly converted into a synthesizable assertion circuit based on the basic circuit modules corresponding to each assertion operator in the assertion statement, thereby improving the circuit synthesis efficiency of the assertion statement and realizing assertion-based hardware verification.

[0087] Take the following assertion statement SVA1 as an example:

[0088] This assertion statement involves multiple non-synthesizable assertion operators, which are categorized as "&&," "==", "|=>," and "!=", which are basic operators; "$rose" and "$past," which are sequence sampling signals; "or," which is a sequence operator; and "##4" and "[*3]," which are timing operators. These assertion operators cannot directly generate RTL circuits and can only be used for software RTL simulation. However, the method provided in the embodiments of this application allows each assertion operator to be converted into an RTL circuit, thereby enabling hardware accelerated simulation.

[0089] Different types of assertion operators have different operating logics. In the embodiment of the present application, the logical relationship between its input signals can be determined according to the type of the assertion operator.

[0090] Optionally, the predicate operator includes a basic operator or a sequence sampling signal; and the step 101 of determining the logical relationship between the input signal and the output signal of the predicate operator to be processed includes:

[0091] The logical relationship between the input signal and the output signal of the predicate operator is determined according to the logical operation rule corresponding to the predicate operator and the bit width of the input signal.

[0092] It should be noted that the basic operators in the assertion statement may include but are not limited to: the equality operator “==”, the inequality operator “!=”, the greater than operator ">”, the less than operator “<”, the greater than or equal to operator ">=”, the less than or equal to operator “<=”, the logical AND operator “&&”, the logical OR operator “||”, the logical NOT operator “!”, the logical XOR operator “^”, the logical negation operator “~^”, etc.

[0093] The logical operations implemented by these basic operators are relatively simple. Based on their logical operation rules and the bit width of the input signals, the logical relationship between the input and output signals can be determined. When implementing these basic operators in hardware, they can be implemented using assignment statements (e.g., assign statements) in hardware description languages ​​(such as Verilog HDL). In an assignment statement, any wire or other wire-like data type can be continuously driven by a value, which can be a constant or an expression composed of a set of signals.

[0094] For example, the basic operator "&&" has symmetrical inputs; swapping the left and right sides does not affect the output. When both inputs are 1 bit wide, if both are 1, the output is 1; if different inputs are 1 at the same time, the output is 0. When the inputs are multiple bits wide, simply performing a logical AND on the two inputs yields the correct result. Therefore, this operator can be solved simply by combining logical relationships, using only assign statements in the code. This principle applies to most operators in the simple operator category, such as the basic operators "==", "!=", and so on.

[0095] Sequence sampling signals are used to define sampling points in temporal properties. Sequence sampling signals in assertion statements can include but are not limited to:

[0096] $rose: Indicates sampling when the signal transitions from low level to high level. It is used to check the state after the rising edge of the signal.

[0097] $fell: Indicates sampling when the signal transitions from high level to low level. It is used to check the state after the falling edge of the signal.

[0098] $stable: Indicates sampling when the signal remains stable. It is used to check whether the signal remains unchanged within a given time window.

[0099] $past: Indicates sampling in the past clock cycle. It is used to check the state of the signal in the previous clock cycle.

[0100] These sequence sampling signals can be combined with other basic operators (such as &&, ||, etc.) to define more complex timing properties. They play a key role in verifying hardware designs and are used to describe and verify timing behavior.

[0101] The processing logic for sequentially sampled signals essentially determines the state of the sampled signals. Hardware implementation requires only sampling the signals at defined sampling points and performing simple logical operations on the sampling results. Different input signal bit widths necessitate different logical operations. Therefore, the logical relationship between the input and output signals can be determined based on the logical operation rules corresponding to the sequentially sampled signals and the input signal bit width, and then implemented using logic devices.

[0102] As an example, the implementation of the three serial sampling signals "$rose," "$fell," and "$stable" is very similar. "$rose" is used as an example for illustration. "$past" differs slightly from these three functions. Figure 3 shows a schematic diagram of a $rose function operator. As shown in Figure 3, the rose operator supports input signals signal_in with multiple bit widths. Just as "binary_out[7:0]" in the above statement is multi-bit wide, the method for handling multi-bit widths here is to use the bitwise AND symbol "&" to obtain an 8-bit signal, where "[7:1]" is 0 and "[0]" is 0 / 1. The rose function is used to detect whether there is a 0-1 transition. To do this, simply save the signal from the previous cycle and compare it with the value of the current cycle to obtain the match and fail values. Only when there is a 0-1 transition does the match output be 1 and the fail output be 0. In all other cases, the match output is 0 and the fail output is 1. The "en" signal is the start signal, which can be understood as the signal that activates the operator. Operators at this level are activated only when the previous level matches. This principle applies to all operators, unless they are combinational logic operators. Under this principle, the "rose" operator uses registers, gates, and wires, all of which exist in real circuits, thus becoming a synthesizable expression. The implementations of "$fell" and "$stable" differ from "$rose" in the slightly different types of gates, but are largely the same, thus enabling conversion to RTL circuits.

[0103] Referring to Figure 4, a schematic diagram of a $past function is shown. $past's function is to provide the past several cycles of the sampled signal. To provide a historical signal, it can only be recorded in advance. Therefore, the $past function uses a shift register to delay the input signal. For a signal that needs to be delayed for n cycles, $past will provide n multi-bit registers. The registers are connected in stages, and each register takes the value of the previous register as input. The first register takes the input signal_in as input, and the output is connected to signal_out. $past does not have an enable signal en because the operator needs to sample the signal in advance.

[0104] Optionally, the predicate operator includes an overlapping implication operator or a non-overlapping implication operator; and the step 101 of determining the logical relationship between the input signal and the output signal of the predicate operator to be processed includes:

[0105] Step S11: determining signal connection information between a cause sequence and a result sequence of the assertion operator according to a verification rule of the assertion operator;

[0106] Step S12: Determine the logical relationship between the input signal and the output signal of the assertion operator according to the signal connection information.

[0107] Overlapping implication operators (|->) and non-overlapping implication operators (|=>) are used to define implication relationships in timing attributes. Overlapping implication operators assert a match (success) if, within one clock cycle, the current state satisfies the conditions of the causal sequence on the left side of the overlapping implication operator, and the state in the next clock cycle satisfies the conditions of the result sequence on the right side of the overlapping implication operator.

[0108] The sequence on the left side of nonoverlapped implication operators is called the cause sequence, and the sequence on the right side is called the result sequence. Assertion statements containing nonoverlapped implication operators have the following situations:

[0109] If the cause sequence does not match (that is, there is a conflict, and the actual running logic of the cause sequence is inconsistent with the logic in the assertion statement), the assertion does not take effect; if the result sequence also matches in the next clock cycle after the cause sequence matches (that is, there is no conflict, and the actual running logic of the result sequence is consistent with the logic in the assertion statement), the assertion matches (that is, the assertion succeeds); if the result sequence conflicts in the next clock cycle after the cause sequence matches, the assertion fails.

[0110] Taking the assertion statement "@(posedge clk)SIG_IN1 ##2 SIG_IN2[*2]##1 SIG_IN3|=>SIG_IN4 ##2 SIG_IN5" as an example, at each rising edge of the clock signal, it is determined whether SIG_IN1 in the causal sequence is true. If it is true, SIG_IN2 must remain true for two clock cycles after two clock cycles (##2). If it is true, SIG_IN3 must also be true after one clock cycle. If all the above conditions are met, the entire causal sequence of SIG_IN1 ##2 SIG_IN2[*2]##1 SIG_IN3 matches.

[0111] The logic for determining whether the result sequence matches is the same as the cause sequence. Taking the result sequence in the above assertion statement as an example, in the next clock cycle after the cause sequence matches, check whether SIG_IN4 is clear. If true, SIG_IN5 must also be true two clock cycles later (##2). If all these conditions are met, the result sequence "SIG_IN4 ##2 SIG_IN5" is considered a match.

[0112] For overlapping implication operators or non-overlapping implication operators, the signal connection information between the cause sequence and the result sequence of the assertion operator can be determined according to the verification rules of the assertion operator, and then the logical relationship between the input signal and the output signal of the assertion operator can be determined according to the signal connection information. The difference between overlapping implication operators and non-overlapping implication operators is that overlapping implication operators require the cause sequence and the result sequence to be determined simultaneously. Obviously, these two operators are different from other simple operators. The clock cycle is introduced here, which means that a clock signal is definitely required to satisfy the logical relationship between the two operators. Referring to Figure 5, a schematic diagram of a non-overlapping implication operator is shown. As shown in Figure 5, op_input_left is the output of the statement "en&&$rose(binary_out[7:0])&&(binary_out[31:8]==24'b110)", and op_input_right is the output of the statement "(gray_in[2][*3]##4 gray_in[2])or($past(gray_in,4)!=32'hfe)". Only when the output of op_input_left is 1, the output of op_input_right is assigned to match and fail; otherwise, match and fail are directly assigned to 0. This output method implements the logical function of the non-overlapping implication operator, and only introduces registers and wires, thus realizing the RTL circuit of these two non-synthesizable operators.

[0113] Optionally, the assertion operator includes a timing operator; and determining the logical relationship between the input signal and the output signal of the assertion operator to be processed in step 101 includes:

[0114] Step S21, determining the delay period and level change corresponding to the input signal and output signal of the timing operator;

[0115] Step S22: Determine the logical relationship between the input signal and the output signal of the timing operator according to the delay period and the level change.

[0116] In SVA, timing operators are used to describe and define timing properties. In the embodiments of this application, timing operators may include, but are not limited to, delay operators and repeat operators. Delay operators, among others, introduce a certain delay into timing properties to simulate actual timing behavior. They are very useful for verifying timing-related properties, such as checking whether data arrives correctly after a specific delay. Delay operators in SVA can include the following two types:

[0117] #n: Indicates that after the current state is satisfied, wait for n clock cycles before sampling again. It is used to introduce a fixed delay.

[0118] #n1,n2: Indicates that after the current state is satisfied, sampling is performed after a random delay between n1 and n2 clock cycles. This is used to introduce a random delay.

[0119] Repeat operators allow sampling of a series of consecutive clock cycles to check for state persistence or repetitiveness. In SVA, repeat operators are often used to verify periodic behavior or detect the occurrence of consecutive events. Commonly used repeat operators include the following three:

[0120] [*]: Indicates repeated sampling over any number of consecutive clock cycles. It is used to check the status over a series of consecutive clock cycles.

[0121] [n:m]: Indicates repeated sampling within n to m consecutive clock cycles. It is used to check the status within the specified clock cycle range.

[0122] [n:$]: Indicates that sampling is repeated until the end after n clock cycles. It is used to check the status after the specified clock cycle until the end.

[0123] For a timing operator, the delay period and level change corresponding to the input signal and output signal of the timing operator can be determined first; then, the logical relationship between the input signal and output signal of the timing operator can be determined based on the delay period and the level change.

[0124] Referring to Figure 6, a schematic diagram of a delay operator is shown. As shown in Figure 6, neither the delay nor the repeat operator has an en signal. This is because the input signal_in of these two operators is the output match of the previous operator signal_check. Since signal_check requires the en signal to be enabled, these two operators are no longer needed. In the example of the assertion statement SVA1 above, "gray[2][*3]" must first pass through the signal_check operator to determine whether match is 0 or 1. The match result is then used as the signal_in of the delay operator. Only when signal_in is 1 will the delay function continue. If signal_in is 0, then the signal_out will be directly output as 0. At this time, the delay function will not be implemented. In this case, the above statement example will ignore "##4" and will not delay by four clock cycles. When signal_in is 1, the function of the delay operator is to delay the input signal for n cycles before outputting it. In the above example, the output is delayed by 4 clock cycles. This function can be implemented in the circuit using a counter. A counting parameter is added, and the value of the counting parameter is related to the value of n in "##n". At the same time, a state machine is added, which is divided into a basic state (IDLE_DELAY) and an active state (READ_DELAY). Only when signal_in is 1 will the state machine change from the basic state to the active state. After entering the active state, as long as the counting variable is not greater than the counting parameter, it will remain in the active state until the count reaches n and the output signal_out is 1. The entire process involves counters and state machines, which all have corresponding RTL circuits, so the conversion of the RTL circuit of the delay operator is realized.

[0125] The schematic diagrams of the repeat operator and the delay operator are the same. The difference is that the repeat operator needs to add a judgment on whether signal_in is 1 at each rising edge of the clock. This means that the judgment of the state machine needs to be modified. However, the overall implementation method is still the counter and state machine, which also corresponds to the RTL circuit, so the conversion of the repeat operator RTL circuit is realized.

[0126] Optionally, the assertion operator includes a signal detection operator; and determining the logical relationship between the input signal and the output signal of the assertion operator to be processed in step 101 includes:

[0127] The logical relationship between the input signal and the output signal of the signal detection operator is determined according to the operator type of the signal detection operator.

[0128] The operator types of the signal detection operator (signal_check) include combinational logic operators and sequential logic operators.

[0129] While the assertion statement SVA1 above doesn't directly implement a signal check operator, every non-synthesizable operator requires a signal_check operator. A signal check operator determines whether an input signal is true. For example, every signal entering a delay operator must first undergo a signal_check. After passing through the signal_check operator, the output of the match operator is passed to the delay operator for further verification. Signal_check can be divided into combinational and sequential logic, with slightly different scopes of application. Combinatorial signal_check is typically used when clock-related operators such as delay and repetition require timing errors, as using sequential signal_check can introduce timing errors. However, when all operators are combinational, such as those in simple operators, these operators lack clock signals, and the entire statement is executed in a clocked context. In this case, sequential signal_check is required to introduce a clock. Combinatorial signal_check uses gates and wires, while sequential signal_check uses registers, gates, and wires—the fundamental building blocks of RTL circuits.

[0130] Optionally, the predicate operator includes a sequence operator; and the determining of the logical relationship between the input signal and the output signal of the predicate operator to be processed in step 101 includes:

[0131] Step S31: determining a matching rule between two input sequences and an output signal of the sequence operator according to the assertion function corresponding to the sequence operator;

[0132] Step S32: Determine the logical relationship between the input signal and the output signal of the sequence operator according to the matching rule.

[0133] The sequence operators in SVA can include but are not limited to: or, and, intersect, first_match, and fail. Among them, the "or" operator is used to combine multiple timing attributes, indicating that any one of them can be satisfied. If any timing attribute is satisfied, the entire combination attribute is satisfied. The "and" operator is used to combine multiple timing attributes, indicating that they must be satisfied at the same time. Only when all timing attributes are satisfied, the entire combination attribute is satisfied. The "intersect" operator is used to combine multiple timing attributes, indicating that they must be satisfied at the same time within the same clock cycle. Only when all timing attributes are satisfied within the same clock cycle, the entire combination attribute is satisfied. The "first_match" operator is used to combine multiple timing attributes, indicating that they are checked one by one in sequence. As long as the first satisfied timing attribute is found, subsequent attributes will no longer be checked; if a satisfied timing attribute is found, the entire combination attribute is satisfied. The "fail" operator is used to specify the negation of a timing attribute. If the specified timing attribute is not satisfied, that is, fails, the entire fail attribute is satisfied.

[0134] For sequence operators, the matching rules between the two input sequences and the output signal of the sequence operator can be determined based on the assertion function corresponding to the sequence operator. Then, the logical relationship between the input signal and the output signal of the sequence operator can be determined based on the matching rules. Taking the "or" operator in the above assertion statement as an example, FIG7 shows a schematic diagram of an or operator. As shown in FIG7, the left input of the or operator is a sequence, and the right input is also a sequence. Therefore, the two input signals seqop_input_left and seqop_input_right can be multi-bit wide. In the above example, they are (gray_in[2][*3]##4 gray_in[2]) and ($past(gray_in,4)!=32'hfe) respectively. The function of the or operator is to detect whether at least one of the two sequences is true. When at least one of the two sequences is true, the output match is 1. This logical relationship is very similar to the or in digital circuits, but there are some differences. Because in SVA software simulation, there is no need to consider resource consumption and occupied area, the length of time for this judgment can be very long, even infinitely long; but this is impossible to achieve in hardware, so the en signal is added to enable this operator, and a counting clock cycle parameter NUM_CNT is also needed to be added. This parameter is used to limit the length of the judgment cycle so that this operator does not occupy too many resources. The same is true for the other three sequence operators and, intersect, and first_match. This is essentially due to hardware limitations. In software simulation, "or" only has one output. However, in hardware, if an output cannot be determined to be in three states: valid, invalid, and reset, match and fail need to be added. Unlike the above operators, match and fail here are often not simply inverse relationships. In the "or" operator, assuming the counting clock cycle parameter NUM_CNT is 5, only when both sequences remain in the false state for 5 cycles within the five cycles after being enabled by "en" will "match" be 0 and "fail" be 1. As long as any sequence is true for one clock cycle within the five cycles enabled by "en", the output will be "match" 1 and "fail" 0. The reset state is when both "match" and "fail" are 0. To implement such logic, match and fail need to be implemented separately. To implement the "match" function, you need to first obtain the result of the "|" of the two inputs, seq_or, and then extend the "en" signal to be valid high for NUM_CNT cycles. To achieve this step, you need to add a counter, and then "match" is the result of the extended "seq_or" and "en" signals.The fail state output requires the use of a state machine, which is divided into a basic state (IDLE_FAIL) and an active state (READ_FAIL). The state change is based on the input of the en signal. As long as seq_or is 1 at least once in a cycle, the fail output will no longer be 1. These two methods can implement the functionality of the or operator. The entire process primarily utilizes counters and state machines, functions that can be implemented in RTL circuits, making the or operator synthesizable.

[0135] Other sequence operators, such as the and operator and the intersect operator, are implemented similarly to the or operator, differing in their logic. The and operator differs from the "and" operator in digital circuits; intersect is more similar to "and," requiring both sequences to be 1 simultaneously for the match operator to output 1. The and operator's logic is to detect that both sequences are true at once, initially outputting match as 1, and only returning match as 0 when both sequences are no longer true. The fail operator's logic is essentially the same as the or operator's: it outputs fail as 1 only if the conditions are not met within the entire determination cycle.

[0136] The logic of the first_match operator is that if there are multiple cycles of high-level input, it will only output a high level for one cycle. This logic is different from the above three operators, but the basic implementation methods are state machines and counters, which are functions that can be implemented by RTL circuits.

[0137] According to the above processing logic, each assertion operator is converted into a synthesizable basic circuit module, and the basic circuit module corresponding to each assertion operator is stored in the assertion equivalent hardware library. Therefore, in the process of circuit synthesis processing of the assertion statement, the corresponding basic circuit module is directly obtained from the assertion equivalent hardware library, and the non-synthesizable assertion statement is converted into a synthesizable assertion circuit.

[0138] In an optional embodiment of the present application, the method further includes:

[0139] Step S41: Obtain a design file, wherein the design file includes a design under test and an assertion statement; the assertion statement is used to verify whether the design under test meets the test conditions;

[0140] Step S42: performing hardware simulation on the assertion statement based on the assertion equivalent hardware library to obtain an assertion circuit;

[0141] Step S43: generating a target netlist according to the design under test and the assertion circuit, and configuring the integrated circuit chip according to the target netlist;

[0142] Step S44: running the integrated circuit chip to perform assertion verification on the design under test.

[0143] In an embodiment of the present application, the constructed assertion equivalent hardware library can be used to convert assertion statements into assertion circuits, and the assertion circuits can be used to perform hardware verification on the design under test.

[0144] Among them, assertion statements are used to verify whether the design under test meets the test conditions. It can be understood that an assertion statement is a statement used to check whether a specific condition is met during the test process, and a test project is a series of test activities performed to verify the correctness of the software or system. A test project for the design under test can include multiple assertion statements. Through these assertion statements, the test objectives and expected results can be defined, thereby guiding the design and execution of the test. Specifically, by inserting assertion statements in the test code, various conditions and constraints in the test process can be automatically verified to ensure the correctness of the test results. When problems or errors occur in the test project, the failure information of the assertion statement can be used to quickly identify the specific conditions that caused the problem, thereby speeding up the troubleshooting and repair of the problem.

[0145] Assertion statements are not synthesizable and cannot be directly configured in FPGA to realize hardware simulation of the design under test. Therefore, in an embodiment of the present application, the assertion statement is first simulated using the assertion equivalent hardware library to obtain an assertion circuit. The assertion circuit can achieve the same function as the assertion statement. For example, the assertion statement can be parsed to identify the non-synthesizable keywords in the assertion statement, such as behaviors containing delays, sampling functions, sequence operation keywords, etc., and then the basic circuit modules corresponding to each keyword are searched from the assertion equivalent hardware library. According to the overall verification logic of the assertion statement, the basic circuit modules corresponding to these keywords are connected to obtain the assertion circuit corresponding to the assertion statement. It can be understood that the assertion circuit generated in the embodiment of the present application can be composed of logic devices such as logic registers, state machines, triggers, etc., which are used to monitor and report errors or abnormal conditions in the design under test.

[0146] Next, a target netlist is generated based on the design under test and the asserted circuits. It should be noted that in electronic design automation, a netlist refers to a method for describing the connections of digital circuits using basic logic gates. Because a logic gate array has a similar arrangement to a wirelist, it is called a "netlist." A netlist typically conveys information about circuit connections, such as module instances, nets, and related properties. If more hardware information is required, a hardware description language such as Verilog, VHDL, or other specialized languages ​​is typically used for description, verification, and simulation. High-level abstraction hardware descriptions (such as the register transfer level) can be converted into a low-level abstraction (logic gate level) circuit connection netlist through logic synthesis. This step can now be automated using tools, significantly reducing the complexity for designers working with very large-scale integrated circuits (VLSIs). Hardware manufacturers use this netlist to manufacture specific application-specific integrated circuits or other circuits. Some relatively small circuits can also be implemented on field-programmable gate arrays.

[0147] In an embodiment of the present application, the target netlist is used to describe the connection between the design under test and the assertion connection using logic gates. Specifically, in the target netlist, the input end of the assertion circuit is connected to the output end of the signal to be monitored in the design under test.

[0148] Based on the target netlist, the design under test and the assertion circuit can be configured into an integrated circuit chip. The integrated circuit chip in the embodiment of the present application is an FPGA. It is understandable that to run a design on an FPGA, it is necessary to first generate a corresponding bitstream file using the software provided by the FPGA manufacturer, and then use the bitstream file to import the design into the FPGA. A bitstream file is a binary file used to store and transmit configuration information of a programmable logic device (such as an FPGA). It contains bit information that configures the FPGA to perform hardware verification of the design under test using the assertion circuit. Specifically, the target bitstream file contains the logic gate configuration, register settings, and connection information of the FPGA. Using the target bitstream file, the assertion circuit and the design under test can be burned into the FPGA board to realize the configuration of the FPGA. In the FPGA, the signal input terminal of the assertion circuit is connected to the output terminal of the signal to be monitored in the RTL circuit design of the design under test.

[0149] Run the FPGA and monitor the assertion results of the design under test. If the monitored signal in the design under test behaves in a manner that violates the assertion statement, the assertion circuit automatically flags the issue and outputs an assertion failure signal. Furthermore, the assertion circuit can locate the moment of assertion failure and the associated signal. This failure information from the assertion circuit allows for quick identification of the specific conditions that caused the problem, accelerating troubleshooting and repair.

[0150] Specifically, when the assertion coverage of the design under test meets the preset conditions, it can be determined that the design under test has passed the verification. Among them, the assertion coverage is a test metric indicator used to measure the extent to which assertion statements are executed during the test process. Assertion coverage is usually expressed as a percentage, specifically the ratio between the number of assertion statements that have been correctly executed and the total number of assertion statements. For example, if there are 100 assertion statements in the design file, and 80 assertion statements are correctly executed in the test, then the assertion coverage is 80%. A higher assertion coverage indicates that the test covers more assertion statements, thereby providing a more comprehensive test guarantee. In an embodiment of the present application, the preset conditions can be set according to specific verification requirements. For example, the preset condition can be that the assertion coverage of the design under test is greater than or equal to a preset threshold, and so on.

[0151] After constructing the assertion equivalent hardware library, the embodiment of the present application can use the basic circuit modules in the assertion equivalent hardware library to simulate the function of the assertion statement, convert the assertion statement into a synthesizable assertion circuit, and generate a target bitstream file based on the assertion circuit and the design under test. The assertion circuit and the design under test are then burned into the FPGA through the target bitstream file, and the design under test is debugged and accelerated using hardware, so that the assertion failure moment can be quickly reached, thereby improving verification efficiency.

[0152] Optionally, the step S42 of performing hardware simulation on the assertion statement based on the assertion equivalent hardware library to obtain an assertion circuit includes:

[0153] Sub-step S421: parsing the assertion statement to identify keywords and verification methods corresponding to the assertion statement;

[0154] Sub-step S422: determining a target assertion operator included in the assertion statement according to the keyword;

[0155] Sub-step S423: obtaining a target basic circuit module corresponding to the target assertion operator from the assertion equivalent hardware library;

[0156] Sub-step S424: determining, according to the verification method, a connection method between target basic circuit modules corresponding to the assertion statement;

[0157] Sub-step S425 : connecting the target basic circuit modules according to the connection mode to obtain an assertion circuit corresponding to the assertion statement.

[0158] Keywords are used to reflect non-synthesizable feature operators or operators in assertion statements, such as clock signals, sampling functions, and sequence operator keywords. Based on the identified keywords, the target assertion operator contained in the assertion statement can be determined, and the target basic circuit module corresponding to the target assertion operator can be obtained from the assertion equivalent hardware library.

[0159] The assertion statement verification method reflects the assertion verification rules for the assertion statement, that is, the conditions that must be met for the assertion to be correct. Based on the assertion statement verification method, the corresponding connection method for each basic circuit module can be determined. Specifically, the assertion statement verification method can determine information such as the execution order of each assertion operator in the assertion statement, the clock signal transmission logic, and the state matching rules. Based on this information, the input and output signals of each basic circuit module are connected to obtain the corresponding connection method for each basic circuit module.

[0160] By connecting the basic circuit modules corresponding to the assertion statement according to the determined connection mode, the assertion circuit corresponding to the assertion statement can be obtained. It is understood that the assertion circuit in the embodiment of the present application can be represented by RTL code.

[0161] In addition, the tested design and assertion statements in the design file are usually described using a hardware description language (such as HDL), which is not easy to process and analyze. In an embodiment of the present application, the design file can be parsed first, and the design file can be converted into an abstract syntax tree that is easier to process and analyze. The abstract syntax tree can reflect the logical structure and semantics of the design file (including the tested design and assertion statements). In practical applications, the design file can be converted into an abstract syntax tree by using an abstract syntax tree generation tool, such as a syntax analyzer (Parser). Then, the converted abstract syntax tree is traversed to find the assertion sentence tree corresponding to the assertion statement, and each assertion sentence tree in the abstract syntax tree is parsed to identify keywords (such as clock signals, sampling functions, sequence operation keywords, etc.) and the verification method of the assertion statement.

[0162] In summary, the embodiments of the present application provide a method for constructing an assertion equivalent hardware library. The logic devices corresponding to the assertion operator and the connection method between each logic device can be determined according to the logical relationship between the input signal and the output signal of the assertion operator. By connecting each logic device according to the determined connection method, the assertion operator can be converted into an equivalent basic circuit module; the obtained basic circuit module is added to the assertion equivalent hardware library, so that when the assertion statement is subjected to circuit synthesis processing, the non-synthesizable assertion statement can be directly converted into a synthesizable assertion circuit based on the basic circuit modules corresponding to each assertion operator in the assertion statement, thereby improving the circuit synthesis efficiency of the assertion statement and realizing assertion-based hardware verification.

[0163] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0164] Device embodiment

[0165] 8 , there is shown a structural block diagram of a device for constructing an assertion equivalent hardware library of the present application. The device may specifically include:

[0166] A first determining module 801 is configured to determine a logical relationship between an input signal and an output signal of a to-be-processed assertion operator; the assertion operator is an operator that implements a basic assertion function in the assertion statement;

[0167] A second determining module 802 is configured to determine, based on the logical relationship, a connection mode between the logic device corresponding to the assertion operator and the logic device;

[0168] A connection module 803 is configured to connect the logic devices corresponding to the assertion operator in the connection manner to obtain a basic circuit module corresponding to the assertion operator;

[0169] The adding module 804 is configured to add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

[0170] Optionally, the assertion operator includes a basic operator or a sequence sampling signal; and the first determination module includes:

[0171] The first determining submodule is configured to determine a logical relationship between an input signal and an output signal of the predicate operator according to a logical operation rule corresponding to the predicate operator and a bit width of the input signal.

[0172] Optionally, the assertion operator includes an overlapping implication operator or a non-overlapping implication operator; and the first determination module includes:

[0173] A second determining submodule, configured to determine signal connection information between a cause sequence and a result sequence of the assertion operator according to a verification rule of the assertion operator;

[0174] The third determining submodule is configured to determine a logical relationship between an input signal and an output signal of the assertion operator according to the signal connection information.

[0175] Optionally, the assertion operator includes a timing operator; and the first determination module includes:

[0176] A fourth determining submodule, configured to determine a delay period and level change corresponding to an input signal and an output signal of the timing operator;

[0177] A fifth determining submodule is configured to determine a logical relationship between an input signal and an output signal of the timing operator according to the delay period and the level change.

[0178] Optionally, the assertion operator includes a signal detection operator; and the first determination module includes:

[0179] a sixth determining submodule, configured to determine a logical relationship between an input signal and an output signal of the signal detection operator according to an operator type of the signal detection operator;

[0180] The operator types of the signal detection operator include combinational logic operators and sequential logic operators.

[0181] Optionally, the assertion operator includes a sequence operator; and the first determination module includes:

[0182] a seventh determining submodule, configured to determine, according to the assertion function corresponding to the sequence operator, a matching rule corresponding to two input sequences and an output signal of the sequence operator;

[0183] An eighth determining submodule is configured to determine a logical relationship between an input signal and an output signal of the sequence operator according to the matching rule.

[0184] Optionally, the device further comprises:

[0185] A file acquisition module is used to acquire a design file, wherein the design file includes a design under test and an assertion statement; the assertion statement is used to verify whether the design under test meets the test conditions;

[0186] A hardware simulation module, configured to perform hardware simulation on the assertion statement based on the assertion equivalent hardware library to obtain an assertion circuit;

[0187] a netlist generation module, configured to generate a target netlist based on the design under test and the assertion circuit, and configure an integrated circuit chip based on the target netlist;

[0188] An assertion verification module is used to run the integrated circuit chip to perform assertion verification on the design under test.

[0189] Optionally, the hardware simulation module includes:

[0190] An assertion parsing submodule, configured to parse the assertion statement and identify keywords and verification methods corresponding to the assertion statement;

[0191] An assertion operator determination submodule, configured to determine a target assertion operator included in the assertion statement according to the keyword;

[0192] A circuit acquisition submodule, configured to acquire a target basic circuit module corresponding to the target assertion operator from the assertion equivalent hardware library;

[0193] a connection mode determination submodule, configured to determine, according to the verification mode, a connection mode between target basic circuit modules corresponding to the assertion statement;

[0194] The connection submodule is used to connect the target basic circuit modules according to the connection mode to obtain the assertion circuit corresponding to the assertion statement.

[0195] Optionally, the integrated circuit chip is an FPGA, and the assertion verification module includes:

[0196] A generating submodule, configured to generate a target bitstream file using the target netlist;

[0197] The verification submodule is used to use the target bitstream file to import the design under test into the FPGA and run it to perform assertion verification on the design under test.

[0198] Optionally, the device further comprises:

[0199] A monitoring module, configured to monitor the assertion results of the design under test;

[0200] An alarm module is used to automatically mark a problem and output an assertion failure signal when a signal to be monitored in the design under test runs in a manner that violates the manner described by the assertion statement; the assertion failure signal includes the time when the assertion failed.

[0201] Optionally, the device further comprises:

[0202] A coverage module, used for obtaining the assertion coverage of the design under test;

[0203] The determination module is configured to determine that the design under test passes verification when the assertion coverage is greater than or equal to a preset threshold.

[0204] Optionally, the assertion circuit includes one or more of a logic register, a state machine, and a trigger, and the assertion circuit is used to monitor and report errors or abnormal conditions in the design under test.

[0205] In summary, the apparatus for constructing an assertion equivalent hardware library provided in the embodiment of the present application can determine the logic devices corresponding to the assertion operator and the connection method between each logic device according to the logical relationship between the input signal and the output signal of the assertion operator, and connect each logic device according to the determined connection method, so that the assertion operator can be converted into an equivalent basic circuit module; the obtained basic circuit module is added to the assertion equivalent hardware library, so that when performing circuit synthesis processing on the assertion statement, the basic circuit modules corresponding to each assertion operator in the assertion statement can be directly used to convert the non-synthesizable assertion statement into a synthesizable assertion circuit, thereby improving the circuit synthesis efficiency of the assertion statement, and further realizing assertion-based hardware verification.

[0206] The various component embodiments of the present application can be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the computing processing equipment according to the embodiment of the present application. The application can also be implemented as a device or apparatus program (for example, a computer program and a computer program product) for performing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0207] For example, FIG9 illustrates a computing device that can implement the methods according to the present application. The computing device typically includes a processor 1010 and a computer program product or computer-readable medium in the form of a memory 1020. Memory 1020 can be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, a hard disk, or ROM. Memory 1020 has storage space 1030 for program code 1031 for executing any of the method steps described above. For example, the storage space 1030 for program code can include individual program codes 1031 for implementing various steps in the method described above. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks. Such computer program products are typically portable or fixed storage units, as described with reference to FIG10. The storage unit can have storage segments, storage space, and the like arranged similarly to memory 1020 in the computing device of FIG9. The program code can, for example, be compressed in a suitable form. Typically, the storage unit includes computer-readable codes 1031 ′, ie, codes that can be read by a processor such as 1010 , which, when executed by a computing device, cause the computing device to perform the steps of the method described above.

[0208] Figure 11 is a block diagram of an electronic device according to an embodiment of the present invention. As shown in Figure 11 , the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores executable instructions that cause the processor to execute the method for constructing an assertion equivalent hardware library according to the aforementioned embodiment.

[0209] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0210] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG11 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0211] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0212] An embodiment of the present application also provides a computer program product, including a computer program, and a method for constructing an assertion equivalent hardware library implemented when the computer program is executed by a processor.

[0213] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0214] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0215] In the claims, any reference signs placed between brackets shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0216] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0217] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0218] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

[0219] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0220] The above is a detailed introduction to the method, device, electronic device, computer program and computer-readable storage medium for constructing an assertion equivalent hardware library provided by this application. Specific examples are used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method of this application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A method for constructing an assertion equivalent hardware library, wherein: The method comprises: Determining a logical relationship between an input signal and an output signal of an assertion operator to be processed; the assertion operator is an operator in the assertion statement that implements a basic assertion function; Determine, according to the logical relationship, a connection mode between the logic device corresponding to the assertion operator and the logic device; Connecting the logic devices corresponding to the assertion operator in the connection manner to obtain a basic circuit module corresponding to the assertion operator; Add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

2. The method according to claim 1, wherein: The predicate operator includes a basic operator or a sequence sampling signal; The determining of the logical relationship between the input signal and the output signal of the predicate operator to be processed includes: The logical relationship between the input signal and the output signal of the predicate operator is determined according to the logical operation rule corresponding to the predicate operator and the bit width of the input signal.

3. The method according to claim 1, wherein: The predicate operator comprises an overlapping implication operator or a non-overlapping implication operator; The determining of the logical relationship between the input signal and the output signal of the predicate operator to be processed includes: Determine signal connection information between a cause sequence and a result sequence of the assertion operator according to a verification rule of the assertion operator; A logical relationship between an input signal and an output signal of the assertion operator is determined according to the signal connection information.

4. The method according to claim 1, wherein: The assertion operator includes a timing operator; and the determining of the logical relationship between the input signal and the output signal of the assertion operator to be processed includes: Determine the delay period and level change of the input signal and output signal of the timing operator; The logical relationship between the input signal and the output signal of the timing operator is determined according to the delay period and the level change.

5. The method according to claim 1, wherein: The assertion operator includes a signal detection operator; the determining the logical relationship between the input signal and the output signal of the assertion operator to be processed includes: Determining a logical relationship between an input signal and an output signal of the signal detection operator according to an operator type of the signal detection operator; Among them, the operator types of the signal detection operator include combinational logic operators and sequential logic operators.

6. The method according to claim 1, wherein: The predicate operator includes a sequence operator; the determining the logical relationship between the input signal and the output signal of the predicate operator to be processed includes: According to the assertion function corresponding to the sequence operator, determine the two input sequences of the sequence operator Matching rules corresponding to the output signal; The logical relationship between the input signal and the output signal of the sequence operator is determined according to the matching rule.

7. The method according to claim 1, wherein: The method further comprises: Obtain a design file, wherein the design file includes a design under test and an assertion statement; the assertion statement is used to verify whether the design under test meets a test condition; Performing hardware simulation on the assertion statement based on the assertion equivalent hardware library to obtain an assertion circuit; Generate a target netlist according to the design under test and the assertion circuit, and configure the integrated circuit chip according to the target netlist; The integrated circuit chip is run to perform assertion verification on the design under test.

8. The method according to claim 7, wherein: The step of performing hardware simulation on the assertion statement based on the assertion equivalent hardware library to obtain an assertion circuit comprises: Parsing the assertion statement to identify keywords and verification methods corresponding to the assertion statement; Determine a target assertion operator included in the assertion statement according to the keyword; Acquire a target basic circuit module corresponding to the target assertion operator from the assertion equivalent hardware library; Determine, according to the verification method, the connection method between each target basic circuit module corresponding to the assertion statement; The target basic circuit modules are connected according to the connection mode to obtain an assertion circuit corresponding to the assertion statement.

9. The method according to claim 7, wherein: The integrated circuit chip is an FPGA, and the operating the integrated circuit chip to perform assertion verification on the design under test includes: Generate a target bitstream file through the target netlist; The target bitstream file is used to import the design under test into the FPGA and run the design under test to perform assertion verification on the design under test.

10. The method according to claim 7, wherein: The method further comprises: monitoring assertion results of the design under test; When the signal to be monitored in the design under test operates in a manner that violates the manner described by the assertion statement, the problem is automatically marked and an assertion failure signal is output; the assertion failure signal includes the time when the assertion failed.

11. The method according to claim 7, wherein: The method further comprises: Obtaining assertion coverage of the design under test; When the assertion coverage is greater than or equal to a preset threshold, it is determined that the design under test passes the verification.

12. The method according to any one of claims 1 to 11, wherein: The assertion circuit includes: one or more of a logic register, a state machine, and a trigger, and the assertion circuit is used to monitor and report errors or abnormal conditions in the design under test.

13. A device for constructing an assertion equivalent hardware library, wherein: The device comprises: A first determination module, used to determine the logical relationship between the input signal and the output signal of the assertion operator to be processed; the assertion operator is an operator that implements the basic assertion function in the assertion statement; A second determination module, used to determine the connection mode between the logic device corresponding to the assertion operator and the logic device according to the logical relationship; A connection module, used to connect the logic devices corresponding to the assertion operator according to the connection mode to obtain a basic circuit module corresponding to the assertion operator; An adding module is used to add the basic circuit module corresponding to the assertion operator to the assertion equivalent hardware library.

14. The device according to claim 13, wherein: The predicate operator includes a basic operator or a sequence sampling signal; The first determining module includes: The first determination submodule is used to determine the logical relationship between the input signal and the output signal of the predicate operator according to the logical operation rule corresponding to the predicate operator and the bit width of the input signal.

15. The device according to claim 13, wherein: The predicate operator comprises an overlapping implication operator or a non-overlapping implication operator; The first determining module includes: A second determination submodule, configured to determine signal connection information between a cause sequence and a result sequence of the assertion operator according to a verification rule of the assertion operator; The third determining submodule is used to determine the logical relationship between the input signal and the output signal of the assertion operator according to the signal connection information.

16. The device according to claim 13, wherein: The assertion operator includes a timing operator; the first determination module includes: A fourth determination submodule, used to determine the delay period and level change corresponding to the input signal and output signal of the timing operator; The fifth determination submodule is used to determine the logical relationship between the input signal and the output signal of the timing operator according to the delay period and the level change.

17. The device according to claim 13, wherein: The assertion operator includes a signal detection operator; the first determination module includes: a sixth determination submodule, configured to determine a logical relationship between an input signal and an output signal of the signal detection operator according to an operator type of the signal detection operator; Among them, the operator types of the signal detection operator include combinational logic operators and sequential logic operators.

18. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement any one of claims 1 to 12. One of the methods described.

19. A computer program comprising computer readable code which, when executed on a computing processing device, causes the computing processing device to execute the method according to any one of claims 1 to 12.

20. A computer-readable storage medium storing the computer program according to claim 19, wherein when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method according to any one of claims 1 to 12.

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