Display panel and driving method therefor, and display apparatus

Abstract

A display panel and a driving method therefor, and a display apparatus. The display panel comprises: a plurality of gate drive circuits, and further comprises a plurality of sub-pixels that are arranged in an array, wherein each sub-pixel comprises a pixel drive circuit and a light-emitting element, the pixel drive circuit comprising a plurality of transistors. The plurality of gate drive circuits are configured to output a plurality of gate drive signals to the plurality of transistors in the pixel drive circuit, wherein each gate drive circuit outputs a gate drive signal, and the plurality of gate drive signals are divided into at least two groups, the gate drive signals in the same group having the same high-level voltage, the gate drive signals in the same group having the same low-level voltage, the gate drive signals in different groups having different high-level voltages, and / or, the gate drive signals in different groups having different low-level voltages; and the pixel drive circuit is configured to receive the plurality of gate drive signals, and drive, on the basis of the received plurality of gate drive signals, the light-emitting element to emit light.

Description

Display panel, driving method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 26, 2023, with application number 202310926864.5 and invention name “Display panel, driving method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display panel, a driving method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present disclosure provides a display panel, including: multiple gate drive circuits, and multiple sub-pixels arranged in an array, wherein the sub-pixels include a pixel drive circuit and a light-emitting element, and the pixel drive circuit includes multiple transistors, wherein:

[0007] The multiple gate drive circuits are configured to output multiple gate drive signals to multiple transistors in the pixel drive circuit, wherein each gate drive circuit outputs one gate drive signal, and the multiple gate drive signals are divided into at least two groups, the high-level voltages of the gate drive signals in the same group are the same, and the low-level voltages of the gate drive signals in the same group are the same; the high-level voltages of the gate drive signals in different groups are different, and / or the low-level voltages of the gate drive signals in different groups are different;

[0008] The pixel driving circuit is configured to receive the multiple gate driving signals and drive the light emitting element to emit light according to the received multiple gate driving signals.

[0009] An embodiment of the present disclosure further provides a display device, comprising the display panel as described in any embodiment of the present disclosure.

[0010] The present disclosure also provides a method for driving a display panel, including:

[0011] Control multiple groups of gate drive circuits to output multiple gate drive signals to multiple transistors in the pixel drive circuit, wherein the multiple gate drive signals are divided into at least two groups, the high-level voltages of the gate drive signals in the same group are the same, and the low-level voltages of the gate drive signals in the same group are the same; the high-level voltages of the gate drive signals in different groups are different, and / or the low-level voltages of the gate drive signals in different groups are different.

[0012] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0014] FIG1 is a schematic structural diagram of a display device;

[0015] FIG2 is a schematic plan view of a display panel;

[0016] FIG3A is a schematic structural diagram of a pixel driving circuit;

[0017] FIG3B is a schematic diagram of a working process of the pixel driving circuit provided in FIG3A ;

[0018] FIG4A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

[0019] FIG4B is a schematic structural diagram of a display panel in some technologies;

[0020] FIG5A is a schematic structural diagram of another pixel driving circuit;

[0021] FIG. 5B is a schematic diagram of a working process of the pixel driving circuit provided in FIG. 5A . DETAILED DESCRIPTION

[0022] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0023] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true to scale. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0024] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0025] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0026] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0027] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0028] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0029] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0030] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0031] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0032] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0033] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0034] FIG1 is a schematic diagram of the structure of a display device. In some examples, as shown in FIG1 , the display device may include: a timing controller 21, a data driver 22, a scan driver circuit 23, a light-emitting driver circuit 24, and a subpixel array 25. In some examples, the subpixel array 25 may include a plurality of subpixels PX arranged in a regular pattern. The scan driver circuit 23 may be configured to provide scan signals to the subpixels PX along scan signal lines; the data driver 22 may be configured to provide data voltages to the subpixels PX along data lines; the light-emitting driver circuit 24 may be configured to provide light-emitting control signals to the subpixels PX along light-emitting control lines; and the timing controller 21 may be configured to control the scan driver circuit 23, the light-emitting driver circuit 24, and the data driver 22.

[0035] In some examples, as shown in FIG1 , the timing controller 21 can provide grayscale values ​​and control signals suitable for the specifications of the data driver 22 to the data driver 22. The timing controller 21 can also provide scan clock signals, scan start signals, and other signals suitable for the specifications of the scan driver 23 to the scan driver 23. The timing controller 21 can also provide light-emission clock signals, light-emission start signals, and other signals suitable for the specifications of the light-emission driver 24 to the light-emission driver 24. The data driver 22 can use the grayscale values ​​and control signals received from the timing controller 21 to generate data voltages to be provided to the data lines D1 to Di. For example, the data driver 22 can sample grayscale values ​​using clock signals and apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Di on a sub-pixel row basis. The scan driver 23 can generate scan signals to be provided to the scan lines S1 to Sj using the scan clock signals, scan start signals, and other signals received from the timing controller 21. For example, the scan driver 23 can sequentially provide scan signals having on-level pulses to the scan lines. In some examples, the scan drive circuit 23 may include a shift register that can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next-stage circuit under the control of a scan clock signal. The light-emitting drive circuit 24 can generate a light-emitting control signal to be provided to the light-emitting control lines EM1 to Eo based on the light-emitting clock signal, light-emitting start signal, etc. received from the timing controller 21. For example, the light-emitting drive circuit 24 can sequentially provide a light-emitting control signal having an off-level pulse to the light-emitting control lines. The light-emitting drive circuit 24 may include a shift register that generates a light-emitting control signal by sequentially transmitting a light-emitting start signal provided in the form of an off-level pulse to the next-stage circuit under the control of a clock signal. Wherein, i, j, and o are all natural numbers.

[0036] In some examples, a display device may include a display panel. The subpixel array, scan driver circuit, and light driver circuit may be directly disposed on the display panel. For example, the scan driver circuit may be disposed on the left frame of the display panel, and the light driver circuit may be disposed on the right frame of the display panel; alternatively, the scan driver circuit and the light driver circuit may be disposed on both the left and right frames of the display panel. In some examples, the scan driver circuit and the light driver circuit may be formed together with the subpixels during the process of forming the subpixels.

[0037] In some examples, the data driver can be provided on a separate chip or printed circuit board. For example, the data driver can be formed using a chip-on-glass, chip-on-plastic, or chip-on-film, etc., and disposed on the lower bezel of the display panel to connect to the driver chip pins. The timing controller can be provided separately from the data driver or integrated with the data driver. However, this embodiment is not limited to this.

[0038] Figure 2 is a planar schematic diagram of a display panel. In some examples, as shown in Figure 2, the display panel may include: a display area AA, a binding area B1 located on one side of the display area AA, and a border area B2 located on the other side of the display area AA. The binding area B1 may be, for example, the lower border of the display panel, and the border area B2 may include the upper border, left border, and right border of the display panel. In some examples, the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX are configured to display dynamic images or still images. The display area may be referred to as an active area. In some examples, the display panel may be a flexible substrate, and thus the display panel may be deformable, such as curling, bending, folding, or rolling up.

[0039] In some examples, the border area B2 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged in sequence along the direction of the display area AA. The circuit area can be connected to the display area AA and can include at least a plurality of cascaded gate drive circuits, and the gate drive circuit is electrically connected to a plurality of gate lines in the display area AA. The power line area is connected to the circuit area and can include at least a low-level power line, which can extend in a direction parallel to the edge of the display area and be connected to the cathode of the display area. The crack dam area can be connected to the power line area and can include at least a plurality of cracks provided on the composite insulating layer. The cutting area can be connected to the crack dam area and can include at least a cutting groove provided on the composite insulating layer. The cutting groove can be configured so that after all the film layers of the display panel are prepared, the cutting arrangement can be cut along the cutting groove respectively.

[0040] In some examples, a first isolation dam and a second isolation dam may be provided in the binding area B1 and the border area B2. The first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area AA. The edge of the display area is the edge of the display area close to the binding area B1 or the border area B2.

[0041] In some examples, as shown in Figure 2, the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines Gate, and a plurality of data lines Data. The plurality of gate lines Gate may extend along a first direction X, and the plurality of data lines Data may extend along a second direction Y. The orthographic projections of the plurality of gate lines Gate and the plurality of data lines Data on the substrate intersect to form a plurality of sub-pixel areas, and a sub-pixel PX is arranged in each sub-pixel area. The plurality of data lines Data are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines Data can be configured to provide data signals to the plurality of sub-pixels PX. The plurality of data lines Data can extend to the binding area B1. The plurality of gate lines Gate are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines Gate can be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals may include scan signals and light-emitting control signals.

[0042] In some examples, as shown in FIG2 , the first direction X may be an extension direction (row direction) of the gate line Gate in the display area AA, and the second direction Y may be an extension direction (column direction) of the data line Data in the display area AA. The first direction X and the second direction Y may intersect, and illustratively, the first direction X and the second direction Y may be perpendicular to each other.

[0043] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0044] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0045] In some examples, a sub-pixel may include: a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit may include multiple transistors and at least one capacitor. For example, the pixel driving circuit may have a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure.

[0046] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel driving circuit. The color of the light emitted by the light-emitting element may be determined according to needs. In some examples, the light-emitting element may include: a first electrode, a second electrode, and an organic light-emitting layer located between the first electrode and the second electrode. The first electrode of the light-emitting element may be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited to this.

[0047] Figure 3A is a schematic diagram of the structure of a pixel driving circuit. Figure 3A is illustrated using 8T1C as an example. As shown in Figure 3A, the pixel driving circuit can be connected to 11 signal lines (data line Data, first scan line Gate-P, second scan line Gate-N, first reset line Reset-P, second reset line Reset-H, emission control line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD, and second power line VSS). Among them, the gate lines include: first scan line Gate-P, second scan line Gate-N, first reset line Reset-P, second reset line Reset-H, and emission control line EM.

[0048] In an exemplary embodiment, as shown in FIG3A , a control electrode of the first transistor M1 is connected to the first reset line Reset-P, a first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor is connected to a third node N3. A control electrode of the second transistor M2 is connected to the second scan line Gate-N, a first electrode of the second transistor M2 is connected to the first node N1, and a second electrode of the second transistor M2 is connected to the third node N3. A control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to the second node N2, and a second electrode of the third transistor M3 is connected to the third node N3. A control electrode of the fourth transistor M4 is connected to the first scan line Gate-P, a first electrode of the fourth transistor M4 is connected to the data line Data, and a second electrode of the fourth transistor M4 is connected to the second node N2. A control electrode of the fifth transistor M5 is connected to the emission control line EM, a first electrode of the fifth transistor M5 is connected to the first power line VDD, and a second electrode of the fifth transistor M5 is connected to the second node N2. A control electrode of the sixth transistor M6 is connected to the emission control line EM, a first electrode of the sixth transistor M6 is connected to the third node N3, and a second electrode of the sixth transistor M6 is connected to the fourth node N4. A control electrode of the seventh transistor M7 is connected to the second reset line Reset-H, a first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor M7 is connected to the fourth node N4. A control electrode of the eighth transistor M8 is connected to the second reset line Reset-H, a first electrode of the eighth transistor M8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor M8 is connected to the second node N2. A first end of the capacitor C is connected to the first power supply line VDD, and a second end of the capacitor C is connected to the first node N1.

[0049] In an exemplary embodiment, a first electrode of the light emitting device is electrically connected to the fourth node N4, a second electrode of the light emitting device is connected to the second power line VSS,

[0050] In an exemplary embodiment, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0051] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0052] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor M1 to the eighth transistor M8 may include P-type transistors and N-type transistors.

[0053] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel to form a low-temperature polycrystalline oxide (LTPO) display panel can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0054] In an exemplary embodiment, as shown in FIG. 3A , the second transistor M2 may be an N-type transistor, and the first transistor M1 and the third transistor M3 to the eighth transistor M8 may be P-type transistors.

[0055] In this exemplary embodiment, the first transistor M1, the seventh transistor M7 and the eighth transistor M8 can all be called reset transistors, the second transistor M2 can be called a compensation transistor, the second transistor M3 can be called a driving transistor, the fourth transistor M4 can be called a data writing transistor, and the fifth transistor M5 and the sixth transistor M6 can be called light emitting control transistors.

[0056] FIG3B illustrates an operation process of the pixel driving circuit provided in FIG3A. In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0057] The first phase P1 is called the first reset phase. The signal on the second reset line Reset-H is a low-level signal, while the signals on the first reset line Reset-P, the first scan line Gate-P, the second scan line Gate-N, and the light-emission control line EM are high-level signals. The signal on the second reset line Reset-H is a low-level signal, turning on the seventh transistor M7 and the eighth transistor M8. The signal on the second initialization signal line INIT2 is supplied to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device L and clearing the existing charge in the first electrode of the light-emitting device L. The signal on the third initialization signal line INIT3 is supplied to the second node N2, initializing (resetting) the second node N2 and clearing the existing charge in the second node N2. During this phase, the third transistor M3 is turned on. The signal on the second scan line Gate-N is a high-level signal, turning on the second transistor M2. The signal of the second node N2 is provided to the first node N1 and the third node N3. The first node N1 and the third node N3 are initialized. The signals of the first reset line Reset-P, the first scan line Gate-P, and the emission control line EM are high-level signals. The first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off. At this stage, the light-emitting device L does not emit light.

[0058] The second phase P2, known as the second reset phase, is characterized by a low signal on the first reset line Reset-P, while the signals on the second reset line Reset-H, the first scan line Gate-P, the second scan line Gate-N, and the emission control line EM are high. The low signal on the first reset line Reset-P causes the first transistor M1 to supply the signal from the first initial signal line INIT1 to the third node N3, reinitializing (resetting) the third node N3 and clearing any charge in the third node N3. During this phase, the third transistor M3 remains on. The signal on the second scan line Gate-N remains high, turning on the second transistor M2. The signal from the third node N3 to the first node N1 continues to initialize the first node N1. The signals on the second reset line Reset-H, the first scan line Gate-P, and the emission control line EM are high, turning off the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. During this phase, the light-emitting device L does not emit light.

[0059] In the third phase P3, also known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate-P is low, while the signals on the first reset line Reset-P, the second reset line Reset-H, the second scan line Gate-N, and the emission control line EM are high. The data line Data outputs a data voltage. During this phase, the third transistor M3 is continuously on. The signal on the first scan line Gate-P is low, turning on the fourth transistor M4. The signal on the second scan line Gate-N is high, turning on the second transistor M2. The data voltage output by the data line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C. The voltage at the second end of the capacitor C (the first node N1) is Vd-|Vth|, where Vd is the data voltage output by the data line Data and Vth is the threshold voltage of the third transistor M3. The signals of the first reset line Reset-P, the second reset line Reset-H and the light emitting control line EM are high level signals, and the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned off. In this stage, the light emitting device L does not emit light.

[0060] In the fourth phase P4, known as the continuous compensation phase, the signals on the first reset line Reset-P, the second reset line Reset-H, the first scan line Gate-P, the second scan line Gate-N, and the emission control line EM are high. The signal on the second scan line Gate-N is high, the second transistor M2 is continuously turned on, the signals on the first scan line Gate-P, the first reset line Reset-P, the second reset line Reset-H, and the emission control line EM are high, and the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off. Although the data line Data signal is no longer being written, the second node N2 is still supplied to the first node N1 via the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, continuously compensating for the threshold voltage of the third transistor M3.

[0061] In the fifth phase P5, referred to as the bias phase, the signals on the second scan line Gate-N and the second reset line Reset-H are low-level signals, while the signals on the first reset line Reset-P, the first scan line Gate-P, and the emission control line EM are high-level signals. The signal on the second scan line Gate-N is low-level, while the signals on the first scan line Gate-P, the first reset line Reset-P, and the emission control line EM are high-level signals. The first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned off. The signal on the second reset line Reset-H is low-level, the seventh transistor M7 and the eighth transistor M8 are turned on, the signal on the third initial signal line INIT3 is written to the second node N2 and the third node N3, and the signal on the second initial signal line INIT2 is written to the fourth node N3. During this phase, the third transistor M3 is in a biased state, and the light-emitting device L does not emit light.

[0062] In the sixth phase P6, also known as the light-emitting phase, the signals on the emission control line EM and the second scan line Gate-N are low-level signals, while the signals on the first reset line Reset-P, the second reset line Reset-H, and the first scan line Gate-P are high-level signals. The low signal on the emission control line EM turns on the fifth transistor M5 and the sixth transistor M6. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0063] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor M3 is:

[0064] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2 ;

[0065] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0066] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0067] Currently, the mainstream image resolution (Pixels Per Inch, PPI) of OLED display panels is between 400 and 450. However, as display technology matures, the market demand for higher PPI products is becoming increasingly urgent. Currently, the PPI of some display panels has increased to between 500 and 550. A higher PPI reduces the charging time of each row of sub-pixels (for example, the sub-pixel charging time of some high-PPI products is approximately 1.6us, while the sub-pixel charging time of some mainstream PPI products is approximately 2.5us). This can lead to problems related to insufficient charging, such as poor low-grayscale image quality, poor image uniformity, color cast, and other image quality issues.

[0068] Improving the charging time and charging rate of high-PPI products is an urgent issue. Some high-PPI products improve charging rates by reducing the resistance and capacitance (RC) loading of signal lines, such as data and scan lines. However, reducing RC loading on signal lines is primarily achieved by increasing the thickness of the insulating and planar layers during processing to minimize the overlap capacitance between signal lines in different layers. This approach increases the size of the display panel, hindering its thinness and lightness.

[0069] As shown in FIG4A , an embodiment of the present disclosure provides a display panel including multiple gate drive circuits and a plurality of sub-pixels arranged in an array. The sub-pixels include a pixel drive circuit and a light-emitting element. The pixel drive circuit includes a plurality of transistors, wherein:

[0070] Multiple gate drive circuits are configured to output multiple gate drive signals to multiple transistors in the pixel drive circuit, wherein each gate drive circuit outputs a gate drive signal, and the multiple gate drive signals are divided into at least two groups, and the high-level voltages of the gate drive signals in different groups are different, and / or the low-level voltages of the gate drive signals in different groups are different;

[0071] The pixel driving circuit is configured to receive a plurality of gate driving signals and drive the light emitting element to emit light according to the received plurality of gate driving signals.

[0072] The display panel of the embodiment of the present disclosure divides multiple gate drive signals into at least two groups, and the high-level voltages of different groups of gate drive signals are different, and / or the low-level voltages of different groups of gate drive signals are different. The high and low levels of the gate drive signals can be adjusted according to the impact of each group of gate drive signals on the charging rate, thereby achieving an optimal charging rate and power consumption combination.

[0073] In some exemplary embodiments, the gate driving circuit may be a Gate Driver On Array (GOA) circuit, and accordingly, the gate driving signal may be a GOA driving signal.

[0074] For example, Table 1 is a table showing the data voltage Vdata, the voltage value VN1@RP of the first node N1 corresponding to the voltage jump point of the first reset line Reset-P, the voltage value VN1@EM of the first node N1 corresponding to the low level stage of the light-emitting control line EM, the ratio of the voltage value of the first node N1 corresponding to the low level stage of the light-emitting control line EM to the data voltage VN1@EM / Data, and the current change rate I for a type of display panel, when the grayscale value is 10 and when the grayscale value is 128, the high-level voltages of the first scan line Gate-P, the second scan line Gate-N, the first reset line Reset-P, the second reset line Reset-H, and the light-emitting control line EM are respectively set to change from 6.0V to 10.5V.

[0075] Table 1

[0076] Based on the data in Table 1, the influence of the VGH voltage of each GOA driving signal on the charging rate of the first node N1 is shown in Table 2.

[0077] Table 2

[0078] As can be seen from Table 2, the higher the signal voltage of the first scan line Gate-P, the higher the charging rate of the first node N1. Therefore, the high-level voltage VGH_Gate-P of the first scan line Gate-P should be set higher, such as 9V~10V. The lower the high-level voltage VGH_Gate-N of the second scan line Gate-N, the higher the charging rate of the first node N1. Therefore, the high-level voltage VGH_Gate-N of the second scan line Gate-N should be set lower, such as 6V~7V. The high-level voltages of the first reset line Reset-P, the first reset line Reset-H, and the emission control line EM have little effect on the charging rate of the first node N1 and can be designed according to conventional values, such as 7.5~8.5V.

[0079] As shown in FIG4B , in some technologies, the high and low level signals of multiple GOA drive signals are set to the same signal and can only be changed uniformly. For example, the high level voltage VGH_Gate-P of the first scan line Gate-P, the high level voltage VGH_Gate-N of the second scan line Gate-N, and the high level voltage VGH_EM of the light emitting control line EM are the same high level signal, that is, the high level voltages of the multiple GOA drive signals can only be set to the same high level voltage value and the low level voltages of the multiple GOA drive signals can only be set to the same low level voltage value. In the embodiment of the present disclosure, multiple GOA driving signals are divided into multiple groups according to their different effects on the charging rate of the first node N1. The multiple groups of GOA driving signals can be set differently and combined as needed to achieve the best high and low level voltage configuration; compared with unified high and low level signals, the separately set high and low level signals can avoid the negative impact of a certain GOA driving signal. For example, increasing the high level voltage increases the charging rate of the first node N1 from the perspective of the first scan line Gate-P, but reduces the charging rate of the first node N1 from the perspective of the second scan line Gate-N; by controlling the multiple GOA driving signals separately, the best charging rate and power consumption combination can be achieved.

[0080] In some exemplary embodiments, the multiple GOA driving signals can be divided into three groups, wherein the first group of GOA driving signals includes a first gate control signal provided by the first scan line Gate-P, the second group of GOA driving signals includes a second gate control signal provided by the second scan line Gate-N, and the third group of GOA driving signals includes a first reset control signal provided by the first reset line Reset-P, a second reset control signal provided by the second reset line Reset-N, and a light-emitting control signal provided by the light-emitting control line EM.

[0081] In some exemplary embodiments, a high level voltage of the first group of GOA drive signals is greater than a high level voltage of the third group of GOA drive signals, and / or a low level voltage of the first group of GOA drive signals is greater than a low level voltage of the third group of GOA drive signals;

[0082] The high level voltage of the second group of GOA drive signals is lower than the high level voltage of the third group of GOA drive signals, and / or the low level voltage of the second group of GOA drive signals is lower than the low level voltage of the third group of GOA drive signals.

[0083] In some exemplary embodiments, the high level voltage of the first group of GOA drive signals is between 9V and 10V; the high level voltage of the second group of GOA drive signals is between 6V and 7V; and the high level voltage of the third group of GOA drive signals is between 7.5V and 8.5V.

[0084] For example, the high-level voltage of the first group of GOA driving signals may be 9.5V; the high-level voltage of the second group of GOA driving signals may be 6.5V; and the high-level voltage of the third group of GOA driving signals may be 8V.

[0085] In some exemplary embodiments, the low-level voltage of the first group of GOA drive signals is between -6V and -7V; the low-level voltage of the second group of GOA drive signals is between -8V and -9V; and the low-level voltage of the third group of GOA drive signals is between -7V and -8V.

[0086] For example, the low-level voltage of the first group of GOA driving signals may be -6.5V; the low-level voltage of the second group of GOA driving signals may be -8.5V; and the low-level voltage of the third group of GOA driving signals may be -7.5V.

[0087] In other exemplary embodiments, the multiple GOA drive signals can be divided into five groups, wherein the first group of GOA drive signals includes a first gate control signal provided by the first scan line Gate-P, the second group of GOA drive signals includes a second gate control signal provided by the second scan line Gate-N, the third group of GOA drive signals includes a first reset control signal provided by the first reset line Reset-P, the fourth group of GOA drive signals includes a second reset control signal provided by the second reset line Reset-N, and the fifth group of GOA drive signals includes a light-emitting control signal provided by the light-emitting control line EM.

[0088] In other exemplary embodiments, the high level voltage of the first group of GOA drive signals is greater than the high level voltage of the third group of GOA drive signals, and / or the low level voltage of the first group of GOA drive signals is greater than the low level voltage of the third group of GOA drive signals;

[0089] The high level voltage of the second group of GOA drive signals is lower than the high level voltage of the third group of GOA drive signals, and / or the low level voltage of the second group of GOA drive signals is lower than the low level voltage of the third group of GOA drive signals.

[0090] In other exemplary embodiments, the high-level voltage of the fourth group of GOA drive signals is equal to or approximately equal to the high-level voltage of the third group of GOA drive signals, and / or the low-level voltage of the fourth group of GOA drive signals is equal to or approximately equal to the low-level voltage of the third group of GOA drive signals.

[0091] In other exemplary embodiments, the high-level voltage of the fifth group of GOA drive signals is equal to or approximately equal to the high-level voltage of the third group of GOA drive signals, and / or the low-level voltage of the fifth group of GOA drive signals is equal to or approximately equal to the low-level voltage of the third group of GOA drive signals.

[0092] In the embodiment of the present disclosure, A and B being approximately equal means that the difference between A and B is within a preset difference threshold. For example, the preset difference threshold may be 1.

[0093] In other exemplary embodiments, the high-level voltage of the first group of GOA drive signals is between 9V and 10V; the high-level voltage of the second group of GOA drive signals is between 6V and 7V; the high-level voltage of the third group of GOA drive signals is between 7.5V and 8.5V; the high-level voltage of the fourth group of GOA drive signals is between 7.5V and 8.5V; and the high-level voltage of the fifth group of GOA drive signals is between 7.5V and 8.5V.

[0094] Exemplarily, the high-level voltage of the first group of GOA drive signals can be 9.5V; the high-level voltage of the second group of GOA drive signals can be 6.5V; the high-level voltage of the third group of GOA drive signals can be 8V; the high-level voltage of the fourth group of GOA drive signals can be 8V; and the high-level voltage of the fifth group of GOA drive signals can be 8V.

[0095] In other exemplary embodiments, the low-level voltage of the first group of GOA drive signals is between -6V and -7V; the low-level voltage of the second group of GOA drive signals is between -8V and -9V; the low-level voltage of the third group of GOA drive signals is between -7V and -8V; the low-level voltage of the fourth group of GOA drive signals is between -7V and -8V; and the low-level voltage of the fifth group of GOA drive signals is between -7V and -8V.

[0096] Exemplarily, the low-level voltage of the first group of GOA drive signals may be -6.5V; the low-level voltage of the second group of GOA drive signals may be -8.5V; the low-level voltage of the third group of GOA drive signals may be -7.5V; the low-level voltage of the fourth group of GOA drive signals may be -7.5V; and the low-level voltage of the fifth group of GOA drive signals may be -7.5V.

[0097] FIG5A is a schematic diagram of an equivalent circuit of another pixel driving circuit according to an exemplary embodiment of the present disclosure. In other exemplary embodiments, as shown in FIG5A , the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7), a storage capacitor C, and multiple signal lines (a data line Data, a scan line Gate, a reset line Reset, an initial signal line INIT, a first power line VDD, a second power line VSS, and an emission control line EM).

[0098] In some exemplary embodiments, a control electrode of the first transistor T1 is connected to a reset line Reset, a first electrode of the first transistor T1 is connected to an initial signal line INIT, and a second electrode of the first transistor T1 is connected to a first node N1. A control electrode of the second transistor T2 is connected to a scan line Gate, a first electrode of the second transistor T2 is connected to a third node N3, and a second electrode of the second transistor T2 is connected to the first node N1. A control electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to a second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. A control electrode of the fourth transistor T4 is connected to a scan line Gate, a first electrode of the fourth transistor T4 is connected to a data line Data, and a second electrode of the fourth transistor T4 is connected to a second node N2. A control electrode of the fifth transistor T5 is connected to an emission control line EM, a first electrode of the fifth transistor T5 is connected to a first power line VDD, and a second electrode of the fifth transistor T5 is connected to a second node N2. The control electrode of the sixth transistor T6 is connected to the emission control line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first electrode of the light-emitting element). The control electrode of the seventh transistor T7 is connected to the scan line Gate or the reset line Reset, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. The first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the first node N1.

[0099] In some exemplary embodiments, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0100] In some exemplary embodiments, the second electrode of the light-emitting element is connected to a second power line VSS. The signal of the second power line VSS continuously provides a low-level signal, and the signal of the first power line VDD continuously provides a high-level signal. The scan line Gate is a scan signal line in the pixel driving circuit of the current display row, and the reset line Reset is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the scan line Gate is Gate(n) and the reset line Reset is Gate(n-1). The reset line Reset of the current display row and the scan line Gate of the pixel driving circuit of the previous display row can be the same signal line, thereby reducing the number of signal lines of the display panel and achieving a narrow bezel of the display panel.

[0101] In some exemplary embodiments, the scan line Gate, the reset line Reset, the emission control line EM, and the initial signal line INIT all extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data line Data extend in a vertical direction.

[0102] In some exemplary embodiments, the light emitting element may be an organic light emitting diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0103] In this exemplary embodiment, the first transistor T1 and the seventh transistor T7 can both be called reset transistors, the second transistor T2 can be called a compensation transistor, the third transistor T3 can be called a driving transistor, the fourth transistor T4 can be called a data writing transistor, and the fifth transistor T5 and the sixth transistor T6 can be called light emitting control transistors.

[0104] FIG5B is an operating timing diagram of the pixel driving circuit shown in FIG5A. Below, assuming that all seven transistors in FIG5A are P-type transistors, the operating process of the pixel driving circuit illustrated in FIG5B is used to illustrate exemplary embodiments of the present disclosure. Exemplarily, the operating process of the pixel driving circuit may include:

[0105] The first phase A1, known as the reset phase, has the reset line Reset signal at a low level, while the scan line Gate and the emission control line EM signals are high. The reset line Reset signal is low, turning on the first transistor T1. The initial signal line INIT signal is supplied to the first node N1, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The scan line Gate and the emission control line EM signals are high, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0106] In the second phase A2, known as the data writing phase or threshold compensation phase, the signal on the scan line Gate is a low-level signal, the signals on the reset line Reset and the emission control line EM are high-level signals, and the data line Data outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the scan line Gate turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second and fourth transistors T2 and T4 are turned on, causing the data voltage output by the data line Data to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The sum of the data voltage output by the data line Data and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vdata+Vth, where Vdata is the data voltage output by the data line Data and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the initial voltage of the initialization signal line INIT to be supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing the initialization and ensuring that the OLED does not emit light. The signal of the reset line Reset is a high-level signal, turning off the first transistor T1. The signal of the emission control line EM is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0107] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting control line EM is low, while the signals on the scan line Gate and the reset line Reset are high. The low signal on the light-emitting control line EM turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0108] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the second node N2 is Vdata+Vth, the driving current of the third transistor T3 is:

[0109] I=K*(Vgs-Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdata-Vdd)] 2

[0110] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line Data, and Vdd is the power supply voltage output by the first power line VDD.

[0111] It can be seen from the above formula that the current I flowing through the light emitting element is independent of the threshold voltage Vth of the third transistor T3 , eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring uniform brightness.

[0112] Based on the above working timing, the pixel circuit eliminates the positive charge remaining in the light-emitting element after the last light emission, realizes compensation for the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light-emitting element, and improves the uniformity of the displayed image and the display quality of the display panel.

[0113] In some exemplary embodiments, the multiple GOA driving signals include a gate control signal for controlling the opening and closing of a data writing transistor, a reset control signal for controlling the opening and closing of a reset transistor, and a light emission control signal for controlling the opening and closing of a light emission control transistor;

[0114] The various GOA driving signals are divided into two groups, wherein the first group includes gate control signals and the second group includes light emitting control signals.

[0115] In some exemplary embodiments, when the reset control signal and the gate control signal are related signals, the first set of GOA driving signals includes the reset control signal;

[0116] When the reset control signal and the gate control signal are unrelated signals, the second group of GOA driving signals includes the reset control signal.

[0117] In some exemplary embodiments, the high level voltage of the first group of GOA drive signals is greater than the high level voltage of the second group of GOA drive signals, and / or the low level voltage of the first group of GOA drive signals is greater than the low level voltage of the second group of GOA drive signals.

[0118] In yet other exemplary embodiments, the pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light emission control transistor, and a compensation transistor;

[0119] The multiple GOA drive signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor;

[0120] The various GOA driving signals are divided into three groups, wherein the first group includes the first gate control signal, the second group includes the second gate control signal, and the third group includes the reset control signal and the light emitting control signal.

[0121] In some exemplary embodiments, a high level voltage of the first group of GOA drive signals is greater than a high level voltage of the third group of GOA drive signals, and / or a low level voltage of the first group of GOA drive signals is greater than a low level voltage of the third group of GOA drive signals;

[0122] The high level voltage of the second group of GOA drive signals is lower than the high level voltage of the third group of GOA drive signals, and / or the low level voltage of the second group of GOA drive signals is lower than the low level voltage of the third group of GOA drive signals.

[0123] In some exemplary embodiments, the high level voltage of the first group of GOA drive signals is between 9V and 10V; the high level voltage of the second group of GOA drive signals is between 6V and 7V; and the high level voltage of the third group of GOA drive signals is between 7.5V and 8.5V.

[0124] For example, the high-level voltage of the first group of GOA driving signals may be 9.5V; the high-level voltage of the second group of GOA driving signals may be 6.5V; and the high-level voltage of the third group of GOA driving signals may be 8V.

[0125] In some exemplary embodiments, the low-level voltage of the first group of GOA drive signals is between -6V and -7V; the low-level voltage of the second group of GOA drive signals is between -8V and -9V; and the low-level voltage of the third group of GOA drive signals is between -7V and -8V.

[0126] For example, the low-level voltage of the first group of GOA driving signals may be -6.5V; the low-level voltage of the second group of GOA driving signals may be -8.5V; and the low-level voltage of the third group of GOA driving signals may be -7.5V.

[0127] An embodiment of the present disclosure further provides a display device, including: a display panel.

[0128] The display panel is the display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0129] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described in detail here, nor should they be construed as limitations of this application.

[0130] The present disclosure also provides a method for driving a display panel, including:

[0131] Control multiple groups of gate drive circuits to output multiple gate drive signals to multiple transistors in the pixel drive circuit, wherein the multiple gate drive signals are divided into at least two groups, the high-level voltages of the gate drive signals in the same group are the same, and the low-level voltages of the gate drive signals in the same group are the same; the high-level voltages of the gate drive signals in different groups are different, and / or the low-level voltages of the gate drive signals in different groups are different.

[0132] In some exemplary embodiments, the pixel driving circuit includes a data writing transistor, a driving transistor, and a light emitting control transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a gate control signal provided by a scan line is valid; the driving transistor is configured to generate a driving current according to the data voltage; and the light emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is valid.

[0133] The plurality of gate driving signals include a gate control signal for controlling the on / off of the data writing transistor and a light emitting control signal for controlling the on / off of the light emitting control transistor;

[0134] The plurality of gate driving signals are divided into two groups, wherein a first group of gate driving signals includes the gate control signals, and a second group of gate driving signals includes the light emitting control signals.

[0135] In some exemplary embodiments, a high-level voltage of the first group of gate drive signals is greater than a high-level voltage of the second group of gate drive signals, and / or a low-level voltage of the first group of gate drive signals is greater than a low-level voltage of the second group of gate drive signals.

[0136] In some exemplary embodiments, the pixel driving circuit further includes a reset transistor, wherein the reset transistor is configured to reset at least one of the following when a reset control signal is valid: an anode of the light-emitting element, a first electrode of the driving transistor, and a second electrode of the driving transistor; the multiple gate driving signals include a reset control signal for controlling the switching of the reset transistor;

[0137] When the reset control signal and the gate control signal are related signals, the first group of gate drive signals includes the reset control signal;

[0138] When the reset control signal and the gate control signal are unrelated signals, the second group of gate driving signals includes the reset control signal.

[0139] In some exemplary embodiments, the pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light emitting control transistor, and a compensation transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scan line is valid; the driving transistor is configured to generate a driving current according to the data voltage; the light emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is valid; the reset transistor is configured to reset at least one of the following when the reset control signal is valid: an anode of the light emitting element, a first electrode of the driving transistor, and a second electrode of the driving transistor; the compensation transistor is configured to perform threshold compensation on the driving transistor when a second gate control signal provided by a second scan line is valid;

[0140] The plurality of gate driving signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor;

[0141] The multiple gate driving signals are divided into three groups, wherein the first group of gate driving signals includes the first gate control signal, the second group of gate driving signals includes the second gate control signal, and the third group of gate driving signals includes the reset control signal and the light emitting control signal.

[0142] In some exemplary embodiments, the high-level voltage of the first group of gate driving signals is greater than the high-level voltage of the third group of gate driving signals, and / or the low-level voltage of the first group of gate driving signals is greater than the low-level voltage of the third group of gate driving signals;

[0143] The high level voltage of the second group of gate driving signals is lower than the high level voltage of the third group of gate driving signals, and / or the low level voltage of the second group of gate driving signals is lower than the low level voltage of the third group of gate driving signals.

[0144] In some exemplary embodiments, the high-level voltage of the first group of gate drive signals is between 9V and 10V; the high-level voltage of the second group of gate drive signals is between 6V and 7V; and the high-level voltage of the third group of gate drive signals is between 7.5V and 8.5V.

[0145] In some exemplary embodiments, the low-level voltage of the first group of gate driving signals is between -6V and -7V; the low-level voltage of the second group of gate driving signals is between -8V and -9V; and the low-level voltage of the third group of gate driving signals is between -7V and -8V.

[0146] In some exemplary embodiments, the pixel driving circuit includes a driving transistor, a data writing transistor, a first reset transistor, a second reset transistor, a light emitting control transistor, and a compensation transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scan line is valid; the driving transistor is configured to generate a driving current according to the data voltage; the light emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is valid; the first reset transistor is configured to reset the second electrode of the driving transistor when the first reset control signal is valid; the second reset transistor is configured to reset the anode of the light emitting element and the first electrode of the driving transistor when the second reset control signal is valid; and the compensation transistor is configured to perform threshold compensation on the driving transistor when the second gate control signal provided by the second scan line is valid;

[0147] The plurality of gate drive signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a first reset control signal for controlling the opening and closing of the first reset transistor, a second reset control signal for controlling the opening and closing of the second reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor;

[0148] The multiple gate driving signals are divided into five groups, wherein the first group includes the first gate control signal, the second group includes the second gate control signal, the third group includes the first reset control signal, the fourth group includes the second reset control signal, and the fifth group includes the light emitting control signal.

[0149] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0150] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0151] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display panel, comprising: A plurality of gate drive circuits further include a plurality of sub-pixels arranged in an array, wherein the sub-pixels include a pixel drive circuit and a light-emitting element, and the pixel drive circuit includes a plurality of transistors, wherein: The multiple gate driving circuits are configured to output multiple gate driving signals to multiple transistors in the pixel driving circuit, wherein each of the gate driving circuits outputs a gate driving signal, and the multiple gate driving signals are divided into at least two groups, the high level voltages of the gate driving signals in the same group are the same, and the low level voltages of the gate driving signals in the same group are the same; the high level voltages of the gate driving signals in different groups are different, and / or the low level voltages of the gate driving signals in different groups are different; The pixel driving circuit is configured to receive the multiple gate driving signals and drive the light emitting element to emit light according to the received multiple gate driving signals.

2. The display panel according to claim 1, wherein: The pixel driving circuit comprises a data writing transistor, a driving transistor and a light emitting control transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a gate control signal provided by a scanning line is valid; the driving transistor is configured to generate a driving current according to the data voltage; and the light emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is valid. The plurality of gate driving signals include a gate control signal for controlling the opening and closing of the data writing transistor and a light emission control signal for controlling the opening and closing of the light emission control transistor; The plurality of gate driving signals are divided into two groups, wherein a first group of gate driving signals includes the gate control signals, and a second group of gate driving signals includes the light emitting control signals.

3. The display panel according to claim 2, wherein: The high level voltage of the first group of gate driving signals is greater than the high level voltage of the second group of gate driving signals, and / or the low level voltage of the first group of gate driving signals is greater than the low level voltage of the second group of gate driving signals.

4. The display panel according to claim 2, wherein: The pixel driving circuit further includes a reset transistor, wherein the reset transistor is configured to reset at least one of the following when a reset control signal is valid: an anode of the light emitting element, a first electrode of the driving transistor, and a second electrode of the driving transistor; The plurality of gate drive signals include a reset control signal for controlling the switching of the reset transistor; When the reset control signal and the gate control signal are related signals, the first group of gate drive signals includes the reset control signal; When the reset control signal and the gate control signal are unrelated signals, the second group of gate driving signals includes the reset control signal.

5. The display panel according to claim 1, wherein: The pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light emitting control transistor and a compensation transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scanning line is valid; the driving transistor is configured to generate a driving current according to the data voltage; the light emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element when a light emitting control signal provided by a light emitting line is valid, so as to drive the light emitting element to emit light; the reset transistor is configured to reset at least one of the following when the reset control signal is valid: an anode of the light emitting element, a first electrode of the driving transistor, and a second electrode of the driving transistor; the compensation transistor is configured to perform threshold compensation on the driving transistor when a second gate control signal provided by a second scanning line is valid; The plurality of gate driving signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor; The multiple gate driving signals are divided into three groups, wherein the first group of gate driving signals includes the first gate control signal, the second group of gate driving signals includes the second gate control signal, and the third group of gate driving signals includes the reset control signal and the light emitting control signal.

6. The display panel according to claim 5, wherein: The high level voltage of the first group of gate driving signals is greater than the high level voltage of the third group of gate driving signals, and / or the low level voltage of the first group of gate driving signals is greater than the low level voltage of the third group of gate driving signals; The high level voltage of the second group of gate driving signals is lower than the high level voltage of the third group of gate driving signals, and / or the low level voltage of the second group of gate driving signals is lower than the low level voltage of the third group of gate driving signals.

7. The display panel according to claim 6, wherein: The high level voltage of the first group of gate driving signals is between 9V and 10V; the high level voltage of the second group of gate driving signals is between 6V and 7V; and the high level voltage of the third group of gate driving signals is between 7.5V and 8.5V.

8. The display panel according to claim 6, wherein: The low level voltage of the first group of gate driving signals is between -6V and -7V; the low level voltage of the second group of gate driving signals is between -8V and -9V; and the low level voltage of the third group of gate driving signals is between -7V and -8V.

9. The display panel according to claim 1, wherein: The pixel driving circuit includes a driving transistor, a data writing transistor, a first reset transistor, a second reset transistor, a light emitting control transistor and a compensation transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scanning line is valid; the driving transistor is configured to generate a driving current according to the data voltage; the light emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is valid; the first reset transistor is configured to reset the second electrode of the driving transistor when the first reset control signal is valid; the second reset transistor is configured to reset the anode of the light emitting element and the first electrode of the driving transistor when the second reset control signal is valid; the compensation transistor is configured to perform threshold compensation on the driving transistor when a second gate control signal provided by a second scanning line is valid; The plurality of gate driving signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a first reset control signal for controlling the opening and closing of the first reset transistor, a second reset control signal for controlling the opening and closing of the second reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor; The multiple gate driving signals are divided into five groups, wherein the first group includes the first gate control signal, the second group includes the second gate control signal, the third group includes the first reset control signal, the fourth group includes the second reset control signal, and the fifth group includes the light emitting control signal.

10. A display device, comprising the display panel according to any one of claims 1 to 9.

11. A method for driving a display panel, comprising: Control multiple groups of gate driving circuits to output multiple gate driving signals to multiple transistors in a pixel driving circuit, wherein the multiple gate driving signals are divided into at least two groups, the high level voltages of the gate driving signals in the same group are the same, and the low level voltages of the gate driving signals in the same group are the same; the high level voltages of the gate driving signals in different groups are different, and / or the low level voltages of the gate driving signals in different groups are different.

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