Display substrate and display apparatus

Abstract

A display substrate, comprising: a substrate, and a driver circuit layer and a light emitting structure layer which are sequentially arranged on the substrate, wherein the substrate comprises a first display area and a second display area, and the first display area is located on at least one side of the second display area; the driver circuit layer is located in the first display area, and comprises a plurality of first pixel circuits and a plurality of second pixel circuits; and the light emitting structure layer comprises a plurality of first light emitting elements located in the first display area, and a plurality of second light emitting elements located in the second display area. At least one first pixel circuit is electrically connected to at least one first light emitting element, and at least one second pixel circuit is electrically connected to at least one second light emitting element. The size of the at least one first pixel circuit is different from the size of the at least one second pixel circuit.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 25, 2023, with application number 202310923033.2 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. Under-display camera technology is a new technology designed to increase the screen-to-body ratio of displays.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] On the one hand, this embodiment provides a display substrate, comprising: a substrate, a driving circuit layer, and a light-emitting structure layer. The substrate comprises a first display area and a second display area, wherein the first display area is located on at least one side of the second display area. The driving circuit layer is located in the first display area and comprises a plurality of first pixel circuits and a plurality of second pixel circuits. The light-emitting structure layer is located on a side of the driving circuit layer away from the substrate and comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements. The size of at least one first pixel circuit is different from the size of at least one second pixel circuit.

[0008] In some exemplary embodiments, the plurality of first pixel circuits have the same size, the plurality of second pixel circuits have the same size, and the size of the plurality of first pixel circuits is different from the size of the plurality of second pixel circuits.

[0009] In some exemplary embodiments, the driving circuit layer further includes: a plurality of invalid pixel circuits; and a size of at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than a size of the at least one first pixel circuit.

[0010] In some exemplary embodiments, the plurality of second pixel circuits are arranged in a first direction with intervals between the plurality of first pixel circuits. A length of at least one first pixel circuit in the first direction is greater than a length of at least one second pixel circuit in the first direction, a length of the at least one first pixel circuit in the second direction is less than a length of the at least one second pixel circuit in the second direction, and the first direction intersects the second direction.

[0011] In some exemplary embodiments, the driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits being arranged alternately between the plurality of first pixel circuits in the first direction, and at least one of the plurality of invalid pixel circuits being adjacent to the at least one second pixel circuit in the second direction. A length of the at least one invalid pixel circuit in the first direction is the same as a length of the at least one second pixel circuit in the first direction, and a length of the at least one invalid pixel circuit in the second direction is less than a length of the at least one first pixel circuit in the second direction.

[0012] In some exemplary embodiments, the sum of the length of the at least one invalid pixel circuit in the second direction and the length of the adjacent second pixel circuit in the second direction is 1.8 times to 2.2 times the length of the at least one first pixel circuit in the second direction.

[0013] In some exemplary embodiments, the at least one second pixel circuit and the at least one invalid pixel circuit are spaced apart in the second direction. Four first pixel circuits and one invalid pixel circuit are spaced apart in the first direction, or four first pixel circuits and one second pixel circuit are spaced apart in the first direction; or four first pixel circuits, one invalid pixel circuit, four first pixel circuits and one second pixel circuit are spaced apart in the first direction.

[0014] In some exemplary embodiments, the sum of four times the length of the at least one first pixel circuit in the first direction and the length of the at least one invalid pixel circuit in the first direction is 1.8 to 2.2 times the length of the at least one first pixel circuit in the second direction.

[0015] In some exemplary embodiments, the plurality of first pixel circuits, the plurality of second pixel circuits, and the plurality of invalid pixel circuits of the driving circuit layer are divided into a plurality of circuit repetition units, each circuit repetition unit including: a plurality of first pixel circuits arranged in two rows and four columns, and a second pixel circuit and an invalid pixel circuit arranged in two rows and one column. Within the circuit repetition unit, the second pixel circuit and the invalid pixel circuit are located on the same side of the plurality of first pixel circuits, or, within the circuit repetition unit, the second pixel circuit and the invalid pixel circuit are located between four columns of first pixel circuits, or, the second pixel circuit and the invalid pixel circuit are located between one column of first pixel circuits and three columns of first pixel circuits.

[0016] In some exemplary embodiments, the arrangement order of the second pixel circuits and the invalid pixel circuits in the second direction is different in adjacent circuit repeating units in the first direction.

[0017] In some exemplary embodiments, one second pixel circuit is electrically connected to one second light-emitting element; or, two second light-emitting elements emitting light of the same color are electrically connected to the same second pixel circuit.

[0018] In some exemplary embodiments, the plurality of second light-emitting elements include: a plurality of second light-emitting elements emitting red light, a plurality of second light-emitting elements emitting blue light, and a plurality of second light-emitting elements emitting green light. The second pixel circuit connected to the second light-emitting elements emitting green light is located on a side of the second pixel circuits connected to the second light-emitting elements emitting red and blue light that is closer to the second display area. The second pixel circuit connected to the second light-emitting element emitting red light is located on a side of the second pixel circuit connected to the second light-emitting element emitting blue light that is closer to the second display area.

[0019] In some exemplary embodiments, two adjacent second light-emitting elements emitting green light located in the same column are electrically connected to the same second pixel circuit; two second light-emitting elements emitting blue light located in adjacent rows but different columns are electrically connected to the same second pixel circuit; and two second light-emitting elements emitting red light located in adjacent rows but different columns are electrically connected to the same second pixel circuit. One of the two second light-emitting elements emitting blue light and one of the two second light-emitting elements emitting red light are located in the same row and in the same column as the other second light-emitting element emitting red light; the other second light-emitting element emitting blue light is located in the same column as the one second light-emitting element emitting red light and in the same row as the other second light-emitting element emitting red light.

[0020] In some exemplary embodiments, in a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on a substrate. The semiconductor layer includes at least: an active layer of transistors of the plurality of first pixel circuits and the plurality of second pixel circuits. The first conductive layer includes at least: gate electrodes of transistors of the plurality of first pixel circuits and first electrodes of storage capacitors, and gate electrodes of transistors of the plurality of second pixel circuits and first electrodes of storage capacitors. The second conductive layer includes at least: second electrodes of storage capacitors of the plurality of first pixel circuits and the plurality of second pixel circuits. The third conductive layer includes at least: a plurality of connection electrodes. The fourth conductive layer includes at least: a data line and a first power line.

[0021] In some exemplary embodiments, the first display area includes a transition area located on at least one side of the second display area and a sub-display area located on at least one side of the transition area, and the plurality of second pixel circuits are located in the transition area. Alternatively, the plurality of second pixel circuits are located in the transition area and the sub-display area.

[0022] In some exemplary embodiments, the light transmittance of the first display area is less than that of the second display area; or, the light transmittance of the sub-display area of ​​the first display area is less than or equal to the light transmittance of the transition area, and the light transmittance of the transition area is less than that of the second display area.

[0023] In some example embodiments, the pixel density of the first display area is greater than or equal to the pixel density of the second display area.

[0024] On the other hand, this embodiment provides a display device including the display substrate described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate overlaps with the second display area of ​​the display substrate.

[0025] On the other hand, this embodiment provides a display substrate, comprising: a substrate, a driving circuit layer, and a light-emitting structure layer. The substrate comprises a first display area and a second display area, the first display area being located on at least one side of the second display area. The driving circuit layer is located in the first display area, and comprises a plurality of first pixel circuits and a plurality of second pixel circuits. The light-emitting structure layer is located on a side of the driving circuit layer away from the substrate, and comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements. The area of ​​at least one first pixel circuit is different from the area of ​​at least one second pixel circuit.

[0026] In some exemplary embodiments, the driving circuit layer further includes: a plurality of invalid pixel circuits; and an area of ​​at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than an area of ​​the at least one first pixel circuit.

[0027] In some exemplary embodiments, the plurality of second pixel circuits are arranged in a first direction with intervals between the plurality of first pixel circuits. A length of at least one first pixel circuit in the first direction is greater than a length of at least one second pixel circuit in the first direction, a length of the at least one first pixel circuit in the second direction is less than a length of the at least one second pixel circuit in the second direction, and the first direction intersects the second direction.

[0028] In some exemplary embodiments, the driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits being arranged alternately between the plurality of first pixel circuits in the first direction, and at least one of the plurality of invalid pixel circuits being adjacent to the at least one second pixel circuit in the second direction. A length of the at least one invalid pixel circuit in the first direction is the same as a length of the at least one second pixel circuit in the first direction, and a length of the at least one invalid pixel circuit in the second direction is less than a length of the at least one first pixel circuit in the second direction.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0030] Summary of the Figures

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0032] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0033] FIG2 is a schematic planar structural diagram of a display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0034] FIG3 is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure;

[0035] FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] FIG5 is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure;

[0037] FIG6 is a partial plan view of a first display area according to at least one embodiment of the present disclosure;

[0038] FIG7 is a schematic plan view of the display substrate after the semiconductor layer is formed in FIG6 ;

[0039] FIG8A is a schematic plan view of the display substrate after the first conductive layer is formed in FIG6 ;

[0040] FIG8B is a schematic diagram of the first conductive layer in FIG8A ;

[0041] FIG9A is a schematic plan view of the display substrate after the second conductive layer is formed in FIG6 ;

[0042] FIG9B is a schematic diagram of the second conductive layer in FIG9A ;

[0043] FIG10 is a schematic plan view of the display substrate after the third insulating layer is formed in FIG6 ;

[0044] FIG11A is a schematic plan view of the display substrate after the third conductive layer is formed in FIG6 ;

[0045] FIG11B is a schematic diagram of the third conductive layer in FIG11A ;

[0046] FIG12 is a schematic plan view of the display substrate after the fifth insulating layer is formed in FIG6 ;

[0047] FIG13 is a schematic diagram of the fourth conductive layer in FIG6;

[0048] FIG14 is a schematic diagram showing the connection between a second pixel circuit and a second light-emitting element according to at least one embodiment of the present disclosure;

[0049] FIG15 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0050] FIG16 is another schematic diagram illustrating the connection between the second pixel circuit and the second light-emitting element according to at least one embodiment of the present disclosure;

[0051] FIG17 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0052] FIG18 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0053] FIG19 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0054] FIG20 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0055] FIG21 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0056] FIG22 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0057] FIG23 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0058] FIG24 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0059] FIG25 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0060] FIG26 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0061] FIG27 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0062] FIG28 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0063] FIG. 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0064] Details

[0065] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0066] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0067] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In this disclosure, "plurality" means two or more.

[0068] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0069] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0070] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0071] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0072] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0073] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0074] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0075] In this disclosure, the terms "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" can include both complete consistency and substantially the same, where "substantially the same" means a difference of less than 10% in value.

[0076] In this disclosure, the size of A refers to the size of the orthographic projection of A on the substrate. When the orthographic projection of A on the substrate is rectangular, the size of A may include at least one of the following: the length of the orthographic projection of A on the substrate along a first direction, the length of the orthographic projection of A on the substrate along a second direction, or the area of ​​the orthographic projection of A on the substrate; the first direction may be perpendicular to the second direction. When the orthographic projection of A on the substrate is circular or elliptical, the size of A may include at least one of the following: the radius of the orthographic projection of A on the substrate or the area of ​​the orthographic projection of A on the substrate.

[0077] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and in-screen hollowing have emerged one after another. These technologies are achieved by digging holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technology requires digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit externalization method is usually adopted in the camera area under the screen.

[0078] The external pixel circuit method refers to setting the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area, and improving the light transmittance of the under-screen camera area by arranging the light-emitting element and the pixel circuit separately. Since there is no pixel circuit in the under-screen camera area, there is no other light-shielding layer in this area except the anode of the light-emitting element, so a higher light transmittance can be achieved. However, as the pixel density (PPI, Pixels Per Inch) of the display device increases, the compression space of the pixel circuit in the normal display area becomes smaller, making the compression of the pixel circuit more and more difficult. For example, when the PPI of the display device is greater than 430PPI, there is insufficient space for the pixel circuit in the normal display area to meet the market demand for high-PPI full-screen display devices.

[0079] This embodiment provides a display substrate and a display device, which can be beneficial for realizing a high PPI full-screen display product.

[0080] This embodiment provides a display substrate, comprising: a substrate, a driving circuit layer, and a light-emitting structure layer. The substrate comprises a first display area and a second display area, wherein the first display area is located on at least one side of the second display area. The driving circuit layer is located in the first display area and comprises a plurality of first pixel circuits and a plurality of second pixel circuits. The light-emitting structure layer is located on a side of the driving circuit layer away from the substrate and comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements. The size of at least one first pixel circuit is different from the size of at least one second pixel circuit.

[0081] In this example, the size of the pixel circuit refers to the size of the orthographic projection of the pixel circuit on the substrate. The size of the orthographic projection of the pixel circuit on the substrate can be understood as the size of the circumscribed rectangle of the active layer of the pixel circuit. In some examples, the size of the pixel circuit may include: the length of the pixel circuit along the first direction and the length along the second direction. The difference between the size of the first pixel circuit and the size of the second pixel circuit may include at least one of the following: the lengths of the first pixel circuit and the second pixel circuit along the first direction are different; the lengths of the first pixel circuit and the second pixel circuit along the second direction are different; the areas of the orthographic projections of the first pixel circuit and the second pixel circuit on the substrate are different. The first direction intersects the second direction, for example, the first direction may be perpendicular to the second direction. The area of ​​the orthographic projection of the pixel circuit on the substrate may be approximately the product of the length of the pixel circuit along the first direction and the length along the second direction.

[0082] The display substrate provided in this embodiment, without increasing the area of ​​the second display area (that is, without increasing the number of second pixel circuits), is beneficial to increasing the setting space of the first pixel circuit by setting the first pixel circuit and the second pixel circuit of different sizes, thereby facilitating meeting the high PPI requirements of the first display area.

[0083] In some exemplary embodiments, the sizes of the multiple first pixel circuits in the first display area can be the same, the sizes of the multiple second pixel circuits can be the same, or the sizes of the multiple first pixel circuits can be different from the sizes of the multiple second pixel circuits. In this example, by setting the sizes of the multiple first pixel circuits and the multiple second pixel circuits to be the same, and designing the first pixel circuits and the second pixel circuits to be size-zoned, it is possible to increase the space for the first pixel circuits without increasing the area of ​​the second display area, thereby helping to meet the high PPI requirements of the first display area.

[0084] In some exemplary embodiments, the driving circuit layer may further include: a plurality of inactive pixel circuits, at least one of which may be smaller than at least one first pixel circuit. For example, the length of the inactive pixel circuit along the first direction may be smaller than the length of the first pixel circuit along the first direction; alternatively, the length of the inactive pixel circuit along the second direction may be smaller than the length of the second pixel circuit along the second direction; alternatively, the length of the inactive pixel circuit along the first direction may be smaller than the length of the first pixel circuit along the first direction, and the length of the inactive pixel circuit along the second direction may be smaller than the length of the first pixel circuit along the second direction. In this example, by reducing the size of the inactive pixel circuit, the space occupied by the inactive pixel circuit can be used to dispose the first pixel circuit and the second pixel circuit.

[0085] In some exemplary embodiments, a plurality of second pixel circuits are spaced apart in the first direction between the plurality of first pixel circuits. The length of at least one first pixel circuit in the first direction may be greater than the length of at least one second pixel circuit in the first direction, and the length of at least one first pixel circuit in the second direction may be less than the length of at least one second pixel circuit in the second direction, and the first direction intersects the second direction. For example, the ratio of the length of the first pixel circuit in the first direction to the length of the second pixel circuit in the first direction may be less than 1.5, and the ratio of the length of the second pixel circuit in the second direction to the length of the first pixel circuit in the second direction may be less than 1.5. This example can increase the space for the first pixel circuit to be set in the first direction by compressing the size of the second pixel circuit along the first direction.

[0086] In some exemplary embodiments, a plurality of inactive pixel circuits may be spaced apart in a first direction between a plurality of first pixel circuits, and at least one inactive pixel circuit may be adjacent to at least one second pixel circuit in a second direction. The length of the at least one inactive pixel circuit in the first direction may be substantially the same as the length of the at least one second pixel circuit in the first direction, and the length of the at least one inactive pixel circuit in the second direction may be less than the length of the at least one first pixel circuit in the second direction. In this example, by compressing the size of the inactive pixel circuit along the second direction, the space available for the second pixel circuit in the second direction may be increased, and by compressing the size of the inactive pixel circuit along the first direction, the space available for the first pixel circuit in the first direction may be increased.

[0087] The solution of this embodiment is illustrated below through some examples.

[0088] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include: a display area AA and a peripheral area BB surrounding the periphery of the display area AA. The display area AA of the display substrate may include: a first display area A1 and a second display area A2. The first display area A1 may at least partially surround the second display area A2. For example, the second display area A2 may be located in the top center of the display area AA, and the first display area A1 may surround the second display area A2. However, this embodiment is not limited to this. For example, the second display area A2 may be located in other positions such as the upper left corner or upper right corner of the display area AA, and the first display area A1 may surround at least one side of the second display area A2.

[0089] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The second display area A2 may be a circle or an ellipse. However, this embodiment is not limited thereto. For example, the second display area A2 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0090] In some examples, as shown in Figure 1, the second display area A2 can be a light-transmitting display area, and can also be called a full display with camera (FDC) area under the screen, which is configured to display images and transmit light; the first display area A1 can be a normal display area, which is configured to display images. For example, the orthographic projection of the sensor (such as hardware such as a camera) on the display substrate can be located in the second display area A2 of the display substrate. In some examples, as shown in Figure 1, the second display area A2 can be circular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the second display area A2. However, this embodiment is not limited to this. In other examples, the second display area A2 can be rectangular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the inscribed circle of the second display area A2.

[0091] In some examples, as shown in FIG1 , the pixel density of the first display area A1 may be greater than or equal to the pixel density of the second display area A2. For example, the pixel density of the first display area A1 may be equal to the pixel density of the second display area A2. This embodiment is not limited to this.

[0092] In some examples, the ratio of the resolution of the second display area A2 to the resolution of the first display area A1 can be approximately 0.8 to 1.2. Alternatively, the resolution of the second display area A2 can be substantially the same as the resolution of the first display area A1. This embodiment is not limited to this.

[0093] Figure 2 is a schematic planar structural diagram of a display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2 , the display area may include multiple pixel units P, and at least one pixel unit P may include: a first subpixel P1 emitting a first color light, a second subpixel P2 emitting a second color light, and third and fourth subpixels P3 and P4 emitting a third color light. In some examples, first subpixel P1 may be a red subpixel (R) emitting red light, second subpixel P2 may be a blue subpixel (B) emitting blue light, and third and fourth subpixels P3 and P4 may be green subpixels (G) emitting green light.

[0094] In some examples, each sub-pixel may include a circuit unit and a light-emitting element. The circuit unit may include at least a pixel circuit. The pixel circuit is respectively connected to a scan line, a data line, and a light-emitting control line. The pixel circuit may be configured to receive a data voltage transmitted by the data line and output a corresponding current to the light-emitting element under the control of the scan line and the light-emitting control line. The light-emitting element in at least one sub-pixel is respectively connected to the pixel circuit of the sub-pixel in which it is located. The light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which it is located.

[0095] In some examples, a pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin-film transistor, and C refers to a capacitor. The number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0096] In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield. In other examples, the multiple transistors in the pixel circuit can include P-type transistors and N-type transistors.

[0097] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0098] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0099] In some examples, the shape of the light-emitting element can be a rectangle, a rhombus, a pentagon, or a hexagon. The light-emitting elements of the four sub-pixels of a pixel unit can be arranged horizontally, vertically, or in a square. However, this embodiment is not limited to this. In other examples, a pixel unit can include three sub-pixels, and the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern.

[0100] Figure 3 is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the display substrate may include at least: a plurality of pixel circuits and a plurality of first light-emitting elements 52 located in a first display area A1; and a plurality of second light-emitting elements 54 located in a second display area A2. The plurality of pixel circuits in the first display area A1 may include: a plurality of first pixel circuits 51, a plurality of second pixel circuits 53, and a plurality of inactive pixel circuits 55.

[0101] In some examples, as shown in FIG3 , at least one first pixel circuit 51 among the plurality of first pixel circuits 51 can be electrically connected to at least one first light-emitting element 52 among the plurality of first light-emitting elements 52, and an orthographic projection of the at least one first pixel circuit 51 on the substrate can at least partially overlap with an orthographic projection of the at least one first light-emitting element 52 on the substrate. The first pixel circuit 51 can be configured to provide a drive signal to the connected first light-emitting element 52 to drive the corresponding first light-emitting element 52 to emit light. In some examples, the relationship between multiple first pixel circuits 51 and multiple first light-emitting elements 52 can be one-to-one, that is, one first pixel circuit 51 can be electrically connected to one first light-emitting element 52, and configured to drive the connected one first light-emitting element 52 to emit light; or, the relationship between multiple first pixel circuits 51 and multiple first light-emitting elements 52 can be one-to-many, that is, one first pixel circuit 51 can be electrically connected to multiple first light-emitting elements 52, and configured to drive the connected multiple first light-emitting elements 52 to emit light; or, the relationship between multiple first pixel circuits 51 and multiple first light-emitting elements 52 can be many-to-one, that is, multiple first pixel circuits can be electrically connected to one first light-emitting element 52, and configured to drive the first light-emitting element 52 to emit light.

[0102] In some examples, as shown in FIG3 , at least one of the plurality of second pixel circuits 53 located in the first display area A1 can be electrically connected to at least one of the plurality of second light-emitting elements 54 located in the second display area A2 via a conductive connection line 61. The second pixel circuit 53 can be configured to provide a drive signal to the connected second light-emitting element 54 to drive the corresponding second light-emitting element 54 to emit light. For example, the plurality of second pixel circuits 53 and the plurality of second light-emitting elements 54 can have a one-to-one relationship, a one-to-many relationship, or a many-to-one relationship. For example, a second pixel circuit 53 can be electrically connected to a plurality of second light-emitting elements 54 that emit light of the same color, and configured to drive the plurality of second light-emitting elements 54 that emit light of the same color to emit light. Because the second light-emitting elements 54 and the second pixel circuit 53 are located in different areas, the orthographic projection of at least one second pixel circuit 53 on the substrate and the orthographic projection of at least one second light-emitting element 54 on the substrate can have no overlap. Placing the second pixel circuit 53 in the first display area A1 can help improve light transmittance in the second display area A2. In some examples, the conductive connection line 61 may be made of a transparent conductive material (eg, indium tin oxide (ITO)) to maximize the light transmittance of the second display area A2.

[0103] In some examples, the light-emitting area of ​​a single second light-emitting element 54 can be smaller than the light-emitting area of ​​a single first light-emitting element 52. That is, the light-emitting area of ​​the first light-emitting element 52 can be larger than the light-emitting area of ​​the second light-emitting element 54. The light-emitting area of ​​a single light-emitting element can correspond to the area of ​​the pixel opening of the pixel definition layer. In some examples, in the second display area A2, light-transmitting regions can be provided between adjacent second light-emitting elements 54. For example, multiple light-transmitting regions can be connected to form a continuous light-transmitting region separated by multiple second light-emitting elements 54.

[0104] In some examples, as shown in Figure 3, a plurality of second pixel circuits 53 can be arranged at intervals between a plurality of first pixel circuits 51, and a plurality of invalid pixel circuits 55 can be arranged at intervals between a plurality of first pixel circuits 51. For example, a plurality of first pixel circuits 51 can be arranged between two adjacent second pixel circuits 53 in the first direction X, and a plurality of first pixel circuits 51 can be arranged between two adjacent invalid pixel circuits 55. At least one invalid pixel circuit 55 and at least one second pixel circuit 53 can be arranged at intervals in the second direction Y. The invalid pixel circuit 55 and the second pixel circuit 53 can be located in the same column. By setting the invalid pixel circuit 55, this example can help improve the uniformity of components of multiple film layers in the etching process. For example, the invalid pixel circuit 55 can have a structure substantially the same as the second pixel circuit 53 in its row or column, except that it is not electrically connected to any light-emitting element.

[0105] In some examples, because the first display area A1 is provided with not only the first pixel circuit 51 electrically connected to the first light-emitting element 52 but also the second pixel circuit 53 electrically connected to the second light-emitting element 54, the number of pixel circuits in the first display area A1 is greater than the number of first light-emitting elements 52. In some examples, the area for providing the newly added pixel circuits (including the second pixel circuit 53 and the inactive pixel circuit 55) can be obtained by reducing the size of the first pixel circuit 51 in the first direction X. For example, the size of the pixel circuit in the first direction X can be smaller than the size of the first light-emitting element in the first direction X.

[0106] In some examples, the original h columns of pixel circuits can be compressed along the first direction X to create space for an additional column of pixel circuits, and the space occupied by the h columns of pixel circuits before compression and the h+1 columns of pixel circuits after compression can be the same. Wherein, h can be an integer greater than 1. In this example, h can be equal to 2 or 4. However, this embodiment is not limited to this.

[0107] In some examples, the second pixel circuit 53 and the invalid pixel circuit 55 may be provided in the first display area A1 on both sides (e.g., left and right) of the second display area A2 along the first direction X, and the second pixel circuit and the invalid pixel circuit may not be provided in the first display area A1 on both sides (e.g., upper and lower) of the second display area A2 along the second direction Y, or only the invalid pixel circuit may be provided. This embodiment is not limited to this.

[0108] FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this example may have a 7T1C structure. In some examples, as shown in FIG4 , the pixel circuit of this example may include: first transistors T1 to T7. The pixel circuit may be electrically connected to a scan line GL, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0109] In some examples, as shown in FIG4 , the first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL can be configured to provide a scan signal SCAN to the pixel circuit, the data line DL can be configured to provide a data signal to the pixel circuit, the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset signal RESET2 to the pixel circuit.

[0110] In some examples, in a row of pixel circuits, the second reset control line RST2 can be connected to the scan line GL to be input with the scan signal SCAN. That is, the second reset signal RESET2(n) received by the pixel circuit in the nth row is the scan signal SCAN(n) received by the pixel circuit in the nth row. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 can be input with a second reset control signal RESET2 that is different from the scan signal SCAN. In some examples, in the pixel circuit in the nth row, the first reset control line RST1 can be connected to the scan line GL of the pixel circuit in the n-1th row to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be achieved.

[0111] In some examples, as shown in FIG4 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 may also be referred to as a driving transistor. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The first transistor T1 may also be referred to as a first reset transistor and is configured to reset the gate of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GL, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The second transistor T2 may also be referred to as a threshold compensation transistor. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The fourth transistor T4 may also be referred to as a data write transistor. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The fifth transistor T5 may also be referred to as a first emission control transistor. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The sixth transistor T6 may also be referred to as a second emission control transistor. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The seventh transistor T7 may also be referred to as a second reset transistor and is configured to reset the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1. The cathode of the light-emitting element EL is electrically connected to the second power line PL2.

[0112] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3, the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0113] The following describes the operation process of the pixel circuit shown in Figure 4. The description is made by taking the pixel circuit shown in Figure 4 as an example in which all of the multiple transistors included are P-type transistors.

[0114] In some examples, during a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage. In this example, the second reset control line RST2 and the scan line GL transmit the same signal as an example for description.

[0115] The first phase is called the reset phase. The first reset control signal RESET1 provided by the first reset control line RST1 is low, turning on the first reset transistor T1. The first initial signal provided by the first initial signal line INIT1 is supplied to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is high, and the emission control signal EM provided by the emission control line EML is high, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting element EL does not emit light.

[0116] The second phase is called the data writing phase or the threshold compensation phase. The scan signal SCAN provided by the scan line GL is a low-level signal, the first reset control signal RESET1 provided by the first reset control line RST1, and the emission control signal EM provided by the emission control line EML are both high-level signals, and the data line DL outputs a data signal. During this phase, since the first electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on. The scan signal SCAN is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, causing the data voltage Vdata output by the data line DL to be provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is then charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initialization signal (i.e., anode reset signal) provided by the second initialization signal line INIT2 to be supplied to the anode of the light-emitting element EL, thereby initializing (resetting) the anode of the light-emitting element EL and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, turning off the first transistor T1. The emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0117] The third phase is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0118] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2=K×[VDD-Vdata] 2 ;

[0119] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0120] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0121] FIG5 is a partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, a second pixel circuit 53 or an invalid pixel circuit 55 is arranged for every four first pixel circuits 51 in the first direction X. This example can arrange the second pixel circuit 53 and the invalid pixel circuit 55 by compressing the pixel circuits in the first direction X. FIG5 illustrates a circuit repetition unit in the first display area as an example. The circuit repetition unit in this example may include: two rows and five columns of pixel circuits, wherein a plurality of first pixel circuits 51 are arranged in two rows and four columns, a second pixel circuit 53 and an invalid pixel circuit 55 are arranged in two rows and one column, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 in the second direction Y. The multiple circuit repetition units in the first display area may be arranged in an array along the first direction X and the second direction Y. In this example, a row of pixel circuits includes a plurality of pixel circuits arranged along the first direction X, and a column of pixel circuits includes a plurality of pixel circuits arranged along the second direction Y.

[0122] In some examples, as shown in FIG5 , the sizes of the plurality of first pixel circuits 51 in the first display area may be the same, the sizes of the plurality of second pixel circuits 53 may be the same, and the sizes of the plurality of invalid pixel circuits 55 may be the same. The sizes of the first pixel circuits 51, the second pixel circuits 53, and the invalid pixel circuits 55 may be different from each other.

[0123] In some examples, as shown in FIG5 , the length of the first pixel circuit 51 along the first direction X can be denoted as b, and the length along the second direction Y can be denoted as a; the length of the second pixel circuit 53 along the first direction X can be denoted as d1, and the length along the second direction Y can be denoted as c1; the length of the invalid pixel circuit 55 along the first direction X can be denoted as f1, and the length along the second direction Y can be denoted as e1. The length b of the first pixel circuit 51 along the first direction X can be greater than the length d1 of the second pixel circuit 53 along the first direction X, and the length d1 of the second pixel circuit 53 along the first direction X can be the same as the length f1 of the invalid pixel circuit 55 along the first direction X. The length a of the first pixel circuit 51 along the second direction Y can be less than the length c1 of the second pixel circuit 53 along the second direction Y, and greater than the length e1 of the invalid pixel circuit 55 along the second direction Y.

[0124] In some examples, the length c1 of the second pixel circuit 53 along the second direction Y can be less than 1.5 times the length a of the first pixel circuit 51 along the second direction Y, that is, the ratio of c1 to a can be less than 1.5. The length b of the first pixel circuit 51 along the first direction X can be less than 1.5 times the length d1 of the second pixel circuit 53 along the first direction X, that is, the ratio of b to d1 can be less than 1.5. The size restrictions in this example can reduce the impact of excessive wiring on signal loading caused by traces extending along the first and second directions, thereby ensuring the display effect.

[0125] In some examples, as shown in FIG5 , the sum of four times the length b of the first pixel circuit 51 along the first direction X and the length d1 of the second pixel circuit 53 along the first direction X can be 1.8 to 2.2 times the length a of the first pixel circuit 51 along the second direction Y, for example, approximately 2 times, i.e., 2a = 4b + d1. The sum of four times the length b of the first pixel circuit 51 along the first direction X and the length f1 of the inactive pixel circuit 55 along the first direction X can be 1.8 to 2.2 times the length a of the first pixel circuit 51 along the second direction Y, for example, approximately 2 times, i.e., 2a = 4b + f1. The sum of the length e1 of the inactive pixel circuit 55 along the second direction Y and the length c1 of the second pixel circuit 53 along the second direction Y can be 1.8 to 2.2 times the length a of the first pixel circuit 51 along the second direction Y, for example, approximately 2 times, i.e., c1 + e1 = 2a.

[0126] In this example, since the inactive pixel circuit 55 does not need to be connected to the light-emitting element, a complete pixel circuit design does not need to be formed. It is only necessary to ensure signal connectivity along the first direction X and along the second direction Y. Therefore, the space occupied by the second pixel circuit 53 along the second direction Y can be increased by simplifying the inactive pixel circuit 55 or reducing the space occupied by the inactive pixel circuit 55. Therefore, the space occupied by the second pixel circuit 53 along the first direction X can be reduced while ensuring the driving effect of the second pixel circuit 53. In this way, the arrangement space of the pixel circuit along the first direction X can be increased, which can help meet high PPI requirements. For example, the arrangement space of the first pixel circuit can be increased without increasing the area of ​​the second display area (that is, without increasing the number of second pixel circuits), so as to help meet the high PPI requirements of the first display area.

[0127] Figure 6 is a partial plan view of the first display area of ​​at least one embodiment of the present disclosure. Figure 6 illustrates a partial structure of the driving circuit layer of the first display area. In some examples, multiple circuit units arranged sequentially along the first direction X can be referred to as a unit row, and multiple circuit units arranged sequentially along the second direction Y can be referred to as a unit column.

[0128] In some examples, as shown in FIG6 , the first display area may include: a first circuit area A11 and a second circuit area A12 arranged at intervals along a first direction X. The first circuit area A11 may be provided with a plurality of unit columns (e.g., four unit columns), and the second circuit area A12 may be provided with one unit column. The plurality of unit columns of the first circuit area A11 may include a plurality of first circuit units, each of which may include at least: a first pixel circuit and a wiring electrically connected to the first pixel circuit. A unit column of the second circuit area A12 may include: a second circuit unit and an invalid circuit unit arranged at intervals, the invalid circuit unit may include: an invalid pixel circuit and a wiring connected to the invalid pixel circuit. The second circuit unit may include: a second pixel circuit and a wiring electrically connected to the second pixel circuit.

[0129] In this example, as shown in FIG6 , a circuit repeating unit consisting of circuit units arranged in two rows and five columns (e.g., including columns N to N+4 and rows M and M+1) is used as an example for illustration. The circuit units in columns N, N+1, N+2, and N+3 include: a plurality of first circuit units; and the circuit unit in column N+4 includes: second circuit units and invalid circuit units arranged at intervals along the second direction Y. The following description uses the structure of a first pixel circuit in row M of column N, an invalid pixel circuit in row M of column N+4, and a second pixel circuit in row M+1 of column N+4 as an example.

[0130] In some examples, as shown in FIG6 , the first display area may include at least a substrate, and a driving circuit layer, a conductive connection layer, and a light-emitting structure layer sequentially disposed on the substrate. The driving circuit layer may include at least a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of inactive pixel circuits. The circuit structures of the first pixel circuits, the second pixel circuits, and the inactive pixel circuits may all be the 7T1C structure shown in FIG4 . For example, the first pixel circuit may include a first transistor 11 to a seventh transistor 17 and a storage capacitor 18. The second pixel circuit may include a first transistor 21 to a seventh transistor 27 and a storage capacitor 28. The inactive pixel circuit may include a first transistor 31 to a seventh transistor 37 and a storage capacitor 38. The conductive connection layer may include at least a plurality of conductive connection lines, which may be configured to extend to the second display area to electrically connect corresponding second pixel circuits to second light-emitting elements located in the second display area. The light-emitting structure layer may include at least a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of first light-emitting elements may be electrically connected to the plurality of first pixel circuits, and the plurality of second light-emitting elements and the plurality of second pixel circuits may be electrically connected via the plurality of conductive connection lines.

[0131] The structure of the first display area of ​​the display substrate of this example is illustrated below by referring to Figures 6 to 13 through the preparation process of the display substrate. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be achieved by any one or more of spraying, spin coating, and inkjet printing; and etching can be achieved by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0132] As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0133] In some examples, the preparation process of the display substrate may include the following operations.

[0134] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0135] (2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer disposed on the substrate.

[0136] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the semiconductor layer may include, for example, polycrystalline silicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, doped with impurities, and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as the source electrode or drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this. In other examples, the material of the semiconductor layer may include amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), and the like. This embodiment may be applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0137] FIG7 is a schematic plan view of the display substrate after the semiconductor layer is formed in FIG6 . In some examples, as shown in FIG7 , the semiconductor layer of the first circuit unit may include at least: active layers of multiple transistors of the first pixel circuit (e.g., including the first active layer 110 of the first transistor of the first pixel circuit in the current row, the second active layer 120 of the second transistor, the third active layer 130 of the third transistor, the fourth active layer 140 of the fourth transistor, the fifth active layer 150 of the fifth transistor, the sixth active layer 160 of the sixth transistor, and the seventh active layer 170 of the seventh transistor of the first pixel circuit in the previous row). The active layers of the seven transistors of the first pixel circuit may be an interconnected integrated structure.

[0138] In some examples, as shown in FIG7 , the semiconductor layer of the second circuit unit may include at least: active layers of multiple transistors of the second pixel circuit (for example, including the first active layer 210 of the first transistor of the second pixel circuit in the current row, the second active layer 220 of the second transistor, the third active layer 230 of the third transistor, the fourth active layer 240 of the fourth transistor, the fifth active layer 250 of the fifth transistor, and the sixth active layer 260 of the sixth transistor), and the seventh active layer 370 of the seventh transistor of the invalid pixel circuit in the previous row. The active layers of the seven transistors of the second pixel circuit may be an integrated structure connected to each other.

[0139] In some examples, as shown in FIG7 , the semiconductor layer of the invalid circuit unit may include at least: active layers of multiple transistors of the invalid pixel circuit (for example, including the first active layer 310 of the first transistor of the invalid pixel circuit of the current row, the second active layer 320 of the second transistor, the third active layer 330 of the third transistor, the fourth active layer 340 of the fourth transistor, the fifth active layer 350 of the fifth transistor, and the sixth active layer 360 of the sixth transistor), and the seventh active layer 270 of the seventh transistor of the second pixel circuit of the previous row. The active layers of the seven transistors of the invalid pixel circuit may be an integrated structure connected to each other.

[0140] In some examples, as shown in FIG7 , the invalid pixel circuit and the second pixel circuit may be spaced apart in the second direction Y. The seventh active layer of the seventh transistor of the invalid pixel circuit may extend to the second circuit unit, and the seventh active layer of the seventh transistor of the second pixel circuit may extend to the invalid circuit unit. The seventh active layer of the seventh transistor of a first pixel circuit in a row may extend into the first circuit unit in the next row. The arrangement of the active layers of the pixel circuits in the first display area of ​​this example can facilitate a compact arrangement of the pixel circuits, thereby saving space.

[0141] In some examples, as shown in FIG7 , the first active layers 110, 210, and 310 may be approximately in an “n” shape, the second active layers 120, 220, and 320 and the sixth active layers 160, 260, and 360 may be approximately in an “L” shape, the third active layers 130, 230, and 330 may be approximately in an “Ω” shape, and the fourth active layers 140, 240, and 340, the fifth active layers 150, 250, and 350, and the seventh active layers 170, 270, and 370 may be approximately in an “I” shape. This embodiment is not limited thereto.

[0142] In some examples, as shown in FIG7 , the first region of the first active layer 110, the first region of the fourth active layer 140, the first region of the fifth active layer 150, and the first region of the seventh active layer 170 of the first pixel circuit can be separately provided. The second region of the first active layer 110 of the first pixel circuit can also serve as the first region of the second active layer 120. The first region of the third active layer 130 can also serve as the second region of the fourth active layer 140 and the second region of the fifth active layer 150; the second region of the third active layer 130 can also serve as the second region of the second active layer 120 and the first region of the sixth active layer 160; and the second region of the sixth active layer 160 can also serve as the first region of the seventh active layer 170. The structures of the active layers of the inactive pixel circuit and the second pixel circuit are similar to those of the first pixel circuit and are therefore not further described here.

[0143] In some examples, as shown in FIG7 , the circumscribed rectangle of the active layer of the first pixel circuit may have a first length L11 along the first direction X, where the first length L11 can be understood as the distance between the left and right edges of the circumscribed rectangle of the first pixel circuit. The circumscribed rectangle of the active layer of the second pixel circuit may have a second length L12 along the first direction X, where the second length L12 can be understood as the distance between the left and right edges of the circumscribed rectangle of the second pixel circuit. The circumscribed rectangle of the active layer of the inactive pixel circuit may have a third length L13 along the first direction X, where the third length L13 can be understood as the distance between the left and right edges of the circumscribed rectangle of the inactive pixel circuit. The third length L13 and the second length L12 can be substantially the same, and the first length L11 can be greater than the second length L12. Setting the first length L11 greater than the second length L12 helps reduce the space occupied by the second pixel circuit and the inactive pixel circuit along the first direction X.

[0144] In some examples, the length b of the first pixel circuit along the first direction X may be greater than or equal to the first length L11, the length d1 of the second pixel circuit along the first direction X may be greater than or equal to the second length L12, and the length f1 of the invalid pixel circuit along the first direction X may be greater than or equal to the third length L13.

[0145] In some examples, as shown in FIG7 , the circumscribed rectangle of the active layer of the first pixel circuit may have a fourth length L21 along the second direction Y. The fourth length L21 may be understood as the distance between the circumscribed edge of the first active layer 110 of the first pixel circuit in the current row and the circumscribed edge of the first active layer of the first pixel circuit in the next row in the second direction Y. The circumscribed rectangle of the active layer of the second pixel circuit may have a fifth length L22 along the second direction Y. The fifth length L22 may be understood as the distance between the circumscribed edge of the first active layer 210 of the second pixel circuit and the circumscribed edge of the first active layer 310 of the inactive pixel circuit in the next row in the second direction Y. The circumscribed rectangle of the active layer of the inactive pixel circuit may have a sixth length L23 along the second direction Y. The sixth length L23 may be understood as the distance between the circumscribed edge of the first active layer 310 of the inactive pixel circuit and the circumscribed edge of the first active layer 210 of the second pixel circuit in the next row in the second direction Y.

[0146] In some examples, as shown in FIG7 , the fourth length L21 can be greater than the sixth length L23, and the fifth length L22 can be greater than the fourth length L21. In this example, by setting the fifth length L22 to be greater than the fourth length L21, and the fourth length L21 to be greater than the sixth length L23, the reduced occupied space of the inactive pixel circuit in the second direction Y can be provided to the second pixel circuit, thereby utilizing the occupied space of the second pixel circuit in the second direction Y to compensate for the reduced occupied space in the first direction X.

[0147] In some examples, the fourth length L21 may be the length a of the first pixel circuit in the second direction Y, the fifth length L22 may be the length c1 of the second pixel circuit in the second direction Y, and the sixth length L23 may be the length e1 of the invalid pixel circuit in the second direction Y.

[0148] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The first conductive film is patterned through a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer.

[0149] FIG8A is a plan view schematic diagram of the display substrate after the first conductive layer is formed in FIG6 . FIG8B is a schematic diagram of the first conductive layer in FIG8A . In some examples, as shown in FIG8A and FIG8B , the first conductive layer of the first circuit unit may include at least: gates of multiple transistors of the first pixel circuit (e.g., gates of the first transistor 11 to the sixth transistor 16 of the first pixel circuit in the current row and the gate of the seventh transistor of the first pixel circuit in the previous row), a first plate 181 of the storage capacitor, a first reset control line (e.g., a first reset control line RST1(m) or RST1(m+1) or RST1(m+2)), a scan line (e.g., a scan line GL(m) or GL(m+1)), and a light emitting control line (e.g., a light emitting control line EML(m) or EML(m+1)).

[0150] In some examples, as shown in Figures 8A and 8B, the first conductive layer of the second circuit unit may include at least: gates of multiple transistors of the second pixel circuit (for example, including the gates of the first transistor 21 to the sixth transistor 26 of the second pixel circuit in this row, the first plate 281 of the storage capacitor), the gate of the seventh transistor 37 of the invalid pixel circuit in the previous row, a first reset control line (for example, the first reset control line RST1(m) or RST1(m+1) or RST1(m+2)), a scan line (for example, the scan line GL(m) or GL(m+1)), and a light-emitting control line (for example, the light-emitting control line EML(m) or EML(m+1)).

[0151] In some examples, as shown in Figures 8A and 8B, the first conductive layer of the invalid circuit unit may include at least: gates of multiple transistors of the invalid pixel circuit (for example, the gates of the first transistor 31 to the sixth transistor 36 of the invalid pixel circuit of this row, the first plate 381 of the storage capacitor), the gate of the seventh transistor 27 of the second pixel circuit of the previous row, a first reset control line (for example, the first reset control line RST1(m) or RST1(m+1) or RST1(m+2)), a scan line (for example, the scan line GL(m) or GL(m+1)), and a light-emitting control line (for example, the light-emitting control line EML(m) or EML(m+1)).

[0152] In some examples, the first reset control line RST1(m) is located on one side of the scan line GL(m) in the second direction Y. The scan line GL(m) is located on one side of the emission control line EML(m) in the second direction Y. The first plate 181 of the storage capacitor of the first pixel circuit in the Mth row and the first plate 381 of the storage capacitor of the inactive pixel circuit can be arranged at intervals along the first direction X and located between the emission control line EML(m) and the scan line GL(m) in the second direction Y. The first plate 181 of the storage capacitor of the first pixel circuit in the M+1th row and the first plate 281 of the storage capacitor of the second pixel circuit can be arranged at intervals along the first direction X and located between the emission control line EML(m+1) and the scan line GL(m+1) in the second direction Y.

[0153] In some examples, the shapes of the first reset control lines RST1(m), RST1(m+1), and RST1(m+2) can be roughly zigzag lines extending along the first direction X. Within the first circuit unit, the area where the first reset control line RST1(m) overlaps with the first active layer of the first transistor 11 of the first pixel circuit of the current row can serve as the gate of the first transistor 11 of the dual-gate structure, and the area where the first reset control line RST1(m) overlaps with the seventh active layer of the seventh transistor of the first pixel circuit of the previous row can serve as the gate of the seventh transistor. Within the invalid circuit unit, the area where the first reset control line RST1(m) overlaps with the first active layer of the first transistor 31 of the invalid pixel circuit of the current row can serve as the gate of the first transistor 31 of the dual-gate structure, and the area where the first reset control line RST1(m) overlaps with the seventh active layer of the seventh transistor of the second pixel circuit of the previous row can serve as the gate of the seventh transistor. In the second circuit unit, the area where the first reset control line RST1(m+1) overlaps with the first active layer of the first transistor 21 of the second pixel circuit of this row can serve as the gate of the first transistor 21 of the dual-gate structure, and the area where the first reset control line RST1(m+1) overlaps with the seventh active layer of the seventh transistor of the invalid pixel circuit of the previous row can serve as the gate of the seventh transistor.

[0154] In some examples, the shape of the scan lines GL(m) and GL(m+1) can be roughly a zigzag shape with the main portion extending along the first direction X. Within the first circuit unit, the area where the scan line GL(m) overlaps with the second active layer of the second transistor 12 of the first pixel circuit in the same row can serve as the first gate of the second transistor 12 of the dual-gate structure, and the area where the scan line GL(m) overlaps with the fourth active layer of the fourth transistor 14 of the first pixel circuit in the same row can serve as the gate of the fourth transistor 14. Within the invalid circuit unit, the area where the scan line GL(m) overlaps with the second active layer of the second transistor 32 of the invalid pixel circuit in the same row can serve as the first gate of the second transistor 32 of the dual-gate structure, and the area where the scan line GL(m) overlaps with the fourth active layer of the fourth transistor 34 of the invalid pixel circuit in the same row can serve as the gate of the fourth transistor 34. Within the second circuit unit, the area where the scan line GL(m+1) overlaps with the second active layer of the second transistor 22 of the second pixel circuit in the same row can serve as the first gate of the second transistor 22 of the dual-gate structure, and the area where the scan line GL(m+1) overlaps with the fourth active layer of the fourth transistor 24 of the second pixel circuit in the same row can serve as the gate of the fourth transistor 24.

[0155] In some examples, within the first circuit unit, a first protrusion 191 may be provided on a side of the scan line GL(m) away from the first reset control line RST1(m). The shape of the first protrusion 191 may be substantially rectangular. The first end of the first protrusion 191 is connected to the scan line GL(m), and the second end of the first protrusion 191 extends toward the first plate 181 of the storage capacitor. The area where the first protrusion 191 overlaps with the second active layer of the second transistor 12 of the first pixel circuit of this row may serve as the second gate of the second transistor 12 of the dual-gate structure. The scan line GL(m) and the first protrusion 191 may be an integral structure connected to each other.

[0156] In some examples, within the second circuit unit, a second protrusion 192 may be provided on the side of the scan line GL(m+1) away from the first reset control line RST1(m+1). The shape of the second protrusion 192 may be approximately rectangular. The first end of the second protrusion 192 is connected to the scan line GL(m+1), and the second end of the second protrusion 192 extends toward the first electrode 281 of the storage capacitor. The area where the second protrusion 192 overlaps with the second active layer of the second transistor 22 of the second pixel circuit of this row can serve as the second gate of the second transistor 22 of the dual-gate structure. The scan line GL(m+1) and the second protrusion 192 may be an integral structure connected to each other. The shape of the second protrusion 192 may be approximately the same as the shape of the first protrusion 191, and the size of the second protrusion 192 may be less than or equal to the size of the first protrusion 191. For example, the length of the second protrusion 192 along the first direction X may be less than or equal to the length of the first protrusion 191 along the first direction X, and the length of the second protrusion 192 along the second direction Y may be greater than or equal to the length of the first protrusion 191 along the second direction Y.

[0157] In some examples, within the invalid circuit unit, a third protrusion 193 may be provided on a side of the scan line GL(m) away from the first reset control line RST1(m). The shape of the third protrusion 193 may be approximately rectangular. The first end of the third protrusion 193 is connected to the scan line GL(m), and the second end of the third protrusion 193 extends toward the first electrode 381 of the storage capacitor. The area where the third protrusion 193 overlaps with the second active layer of the second transistor 32 of the invalid pixel circuit of this row can serve as the second gate of the second transistor 32 of the dual-gate structure. The scan line GL(m) and the third protrusion 193 may be an integral structure connected to each other. The shape and size of the third protrusion 193 may be approximately the same as the shape and size of the second protrusion 192.

[0158] In some examples, within the first circuit unit, the first plate 181 of the storage capacitor of the first pixel circuit can be substantially rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate 181 on the substrate can at least partially overlap with the orthographic projection of the third active layer of the third transistor 13 on the substrate. The first plate 181 can simultaneously serve as the first electrode (i.e., the lower plate) of the storage capacitor of the first pixel circuit and the gate of the third transistor 13.

[0159] In some examples, within the second circuit unit, the shape of the first plate 281 of the storage capacitor of the second pixel circuit can be approximately rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate 281 on the substrate and the orthographic projection of the third active layer of the third transistor 23 on the substrate can at least partially overlap, and the first plate 281 can serve as both the first electrode (i.e., the lower plate) of the storage capacitor of the second pixel circuit and the gate of the third transistor 23. The length L33 of the first plate 281 along the first direction X can be less than the length L31 of the first plate 181 along the first direction X, and the length L34 of the first plate 281 along the second direction Y can be greater than the length L32 of the first plate 181 along the second direction Y.

[0160] In some examples, within the invalid circuit unit, the shape of the first plate 381 of the storage capacitor of the invalid pixel circuit can be roughly rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate 381 on the substrate and the orthographic projection of the third active layer of the third transistor 33 on the substrate can at least partially overlap, and the first plate 381 can simultaneously serve as the first electrode (i.e., the lower plate) of the storage capacitor of the invalid pixel circuit and the gate of the third transistor 33. The length L35 of the first plate 381 along the first direction X can be less than the length L31 of the first plate 181 along the first direction X, for example, it can be equal to the length L33 of the first plate 281 along the first direction X; the length L36 of the first plate 381 along the second direction Y can be less than the length L34 of the first plate 281 along the second direction Y, for example, it can be less than the length L32 of the first plate 181 along the second direction Y.

[0161] In some examples, the emission control lines EML(m) and EML(m+1) can be substantially straight lines extending along the first direction X. Within the first circuit unit, the region where the emission control line EML(m) overlaps with the fifth active layer of the fifth transistor 15 of the first pixel circuit in the same row can serve as the gate of the fifth transistor 15, and the region where the emission control line EML(m) overlaps with the sixth active layer of the sixth transistor 16 of the first pixel circuit in the same row can serve as the gate of the sixth transistor 16. Within the inactive circuit unit, the region where the emission control line EML(m) overlaps with the fifth active layer of the fifth transistor 35 of the inactive pixel circuit in the same row can serve as the gate of the fifth transistor 35, and the region where the emission control line EML(m) overlaps with the sixth active layer of the sixth transistor 36 of the inactive pixel circuit in the same row can serve as the gate of the sixth transistor 36. Within the second circuit unit, the region where the emission control line EML(m+1) overlaps with the fifth active layer of the fifth transistor 25 of the second pixel circuit in the same row can serve as the gate of the fifth transistor 25, and the region where the emission control line EML(m+1) overlaps with the sixth active layer of the sixth transistor 26 of the second pixel circuit in the same row can serve as the gate of the sixth transistor 26.

[0162] In some examples, compared to the routing lines extending along the first direction X within the first circuit unit, the routing lines of the same type extending along the first direction X within the invalid circuit unit can be moved a certain distance (e.g., 2 microns) in the second direction Y to achieve the purpose of compressing the length of the invalid pixel circuit in the second direction Y.

[0163] In some examples, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area blocked by the first conductive layer can form channel regions of the seven transistors of the first pixel circuit, the seven transistors of the second pixel circuit, and the seven transistors of the invalid pixel circuit. The semiconductor layer in the area not blocked by the first conductive layer is conductorized, that is, the first and second areas of the seven transistors of the first pixel circuit, the first and second areas of the seven transistors of the second pixel circuit, and the first and second areas of the seven transistors of the invalid pixel circuit can all be conductorized.

[0164] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second conductive film is patterned through a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer.

[0165] Figure 9A is a planar schematic diagram of the display substrate after the second conductive layer is formed in Figure 6. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A. In some examples, as shown in Figures 9A and 9B, the second conductive layer of the first circuit unit may include at least: a second plate 182 of the storage capacitor of the first pixel circuit, a first initial signal line (e.g., a first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (e.g., a second initial signal line INIT2(m-1) or INIT2(m)). The second conductive layer of the second circuit unit may include at least: a second plate 282 of the storage capacitor of the second pixel circuit, a first initial signal line (e.g., a first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (e.g., a second initial signal line INIT2(m-1) or INIT2(m)). The second conductive layer of the invalid circuit unit may include at least: a second plate 382 of the storage capacitor of the invalid pixel circuit, a first initial signal line (for example, the first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (for example, the second initial signal line INIT2(m-1) or INIT2(m)).

[0166] In some examples, the orthographic projection of the second initial signal line INIT2(m-1) on the substrate is located on one side of the first reset control line RST1(m) in the second direction Y. The first initial signal line INIT1(m) may be located on a side of the second initial signal line INIT2(m-1) in the opposite direction to the second direction Y. The second plate 182 of the storage capacitor of the first pixel circuit and the second plate 382 of the storage capacitor of the inactive pixel circuit of the Mth row may be arranged alternately along the first direction X and located on a side of the first initial signal line INIT1(m) in the opposite direction to the second direction Y.

[0167] In some examples, the orthographic projection of the second initial signal line INIT2(m) on the substrate is located on one side of the first reset control line RST1(m+1) in the second direction Y. The first initial signal line INIT1(m+1) can be located on a side of the second initial signal line INIT2(m) in the opposite direction to the second direction Y. The second plate 182 of the storage capacitor of the first pixel circuit and the second plate 282 of the storage capacitor of the second pixel circuit in the M+1th row can be arranged alternately along the first direction X and located on a side of the first initial signal line INIT1(m+1) in the opposite direction to the second direction Y.

[0168] In some examples, the second initial signal line INIT2(m-1) and the first initial signal line INIT1(m) may be shaped substantially like a zigzag line with a main portion extending along the first direction X. The structures of the second initial signal line INIT2(m+1) and the first initial signal line INIT1(m+2) are as described above and are not further described here.

[0169] In some examples, within the first circuit unit and the invalid circuit unit, a fourth protrusion 194 may be provided on a side of the first initial signal line INIT1(m) close to the second initial signal line INIT2(m-1), and the shape of the fourth protrusion 194 may be substantially rectangular. A first end of the fourth protrusion 194 is connected to the first initial signal line INIT1(m), and a second end of the fourth protrusion 194 extends toward the second initial signal line INIT2(m-1). For example, the fourth protrusion 194 may be located between the first region of the first active layer and the first region of the adjacent seventh active layer. The fourth protrusion 194 and the first initial signal line INIT1(m) may be an integral structure connected to each other. In some examples, the size of the fourth protrusion 194 within the invalid pixel circuit may be smaller than the size of the fourth protrusion 194 within the first circuit unit.

[0170] In some examples, within the first circuit unit and the invalid circuit unit, a fifth protrusion 195 may be provided on a side of the first initial signal line INIT1(m) away from the second initial signal line INIT2(m-1). The fifth protrusion 195 may be substantially rectangular in shape. The fifth protrusion 195 and the fourth protrusion 194 may be spaced apart along the first direction X. The length of the fifth protrusion 195 along the first direction X may be less than the length of the fourth protrusion 194 along the first direction X. The first end of the fifth protrusion 195 is connected to the first initial signal line INIT1(m), and the second end of the fifth protrusion 195 extends toward the second plate 182 or 382 of the storage capacitor. For example, the fifth protrusion 195 may be located between the first region of the second active layer and the first region of the fourth active layer of the first pixel circuit (or invalid pixel circuit). The fifth protrusion 195 and the first initial signal line INIT1(m) may be an integral structure connected to each other. In this example, the provision of the fifth protrusion 195 helps shield the fourth transistor from the effects of other signals. In some examples, the size of the fifth protrusion 195 within the ineffective circuit unit may be smaller than the size of the fifth protrusion 195 within the first circuit unit.

[0171] In some examples, within the second circuit unit, a fourth protrusion 194 may be provided on a side of the first initial signal line INIT1(m+1) close to the second initial signal line INIT2(m). The fourth protrusion 194 may be substantially rectangular in shape. A fifth protrusion 195 may be provided on a side of the first initial signal line INIT1(m+1) away from the second initial signal line INIT2(m). The size of the fifth protrusion in the second circuit unit may be smaller than the size of the fifth protrusion in the first circuit unit, and the size of the fourth protrusion in the second circuit unit may be smaller than the size of the fourth protrusion in the first circuit unit.

[0172] In some examples, within the first circuit unit, the second plate 182 of the storage capacitor of the first pixel circuit may partially overlap with the orthographic projection of the first plate 181 on the substrate. The second plate 182 may have a first opening K1, which may be substantially rectangular. The orthographic projection of the first opening K1 on the substrate may be located within the orthographic projection of the first plate 181 on the substrate. The first plate of the storage capacitor of the first pixel circuit may serve as a first electrode of the storage capacitor, and the second plate of the storage capacitor may serve as a second electrode of the storage capacitor.

[0173] In some examples, within the second circuit unit, the second plate 282 of the storage capacitor of the second pixel circuit may partially overlap with the orthographic projection of the first plate 281 on the substrate. The second plate 282 may have a second opening K2, the second opening K2 may be approximately rectangular, and the orthographic projection of the second opening K2 on the substrate may be located within the orthographic projection of the first plate 281 on the substrate. The first plate of the storage capacitor of the second pixel circuit may serve as the first electrode of the storage capacitor, and the second plate of the storage capacitor may serve as the second electrode of the storage capacitor. In some examples, the size of the second opening K2 may be smaller than the size of the first opening K1, for example, the length of the second opening K2 along the first direction X may be smaller than the length of the first opening K1 along the first direction X, and the length of the second opening K2 along the second direction Y may be greater than or equal to the length of the first opening K1 along the second direction Y.

[0174] In some examples, within the invalid circuit unit, the second plate 382 of the storage capacitor of the invalid pixel circuit may partially overlap with the orthographic projection of the first plate 381 on the substrate. The second plate 382 may have a third opening K3, which may be approximately rectangular, and the orthographic projection of the third opening K3 on the substrate may be located within the orthographic projection of the first plate 381 on the substrate. The first plate of the storage capacitor of the invalid pixel circuit may serve as the first electrode of the storage capacitor, and the second plate of the storage capacitor may serve as the second electrode of the storage capacitor. In some examples, the size of the third opening K3 may be smaller than the size of the first opening K1. For example, the length of the third opening K3 along the first direction X may be smaller than the length of the first opening K1 along the first direction X, and the length of the third opening K3 along the second direction Y may be smaller than the length of the first opening K1 along the second direction Y.

[0175] In some examples, the second plate 182 (or 282 or 382) may be provided with a plate connecting line 183 on one side of the first direction X or on the side opposite to the first direction X. The first end of the plate connecting line 183 may be connected to the second plate of the circuit unit, and the second end may be connected to the second plate of the adjacent circuit unit after extending along the first direction X or the opposite direction of the first direction X, so that the second plates of adjacent circuit units on a unit row can be connected to each other. For example, the second plate 182 of the first pixel circuit in the first circuit unit may be connected to the second plate 382 of the invalid pixel circuit via the plate connecting line 183, or may be connected to the second plate 282 of the second pixel circuit via the plate connecting line 183. In some examples, the plate connecting line 183 and the second plates 182, 282 and 382 may be an integrated structure connected to each other. The second plates (including second plates 182, 282 and 382) of the integrated structure of multiple circuit units in this example can be reused as horizontal lines extending along the first direction X for transmitting the first voltage signal. This not only ensures that the multiple second plates in a unit row have the same potential, but also reduces the voltage drop of the first voltage signal, which is beneficial to improving the uniformity of the display substrate and ensuring the display effect.

[0176] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the third insulating film is patterned by a patterning process to form a third insulating layer. The third insulating layer of each circuit unit is provided with a plurality of vias. In some examples, the third insulating layer may also be referred to as an interlayer insulating layer.

[0177] FIG10 is a schematic plan view of the display substrate after forming the third insulating layer in FIG6 . In some examples, as shown in FIG10 , the plurality of vias of the first circuit unit may include at least first through tenth vias V1 through V10. The plurality of vias of the second circuit unit may include at least eleventh through twentieth vias V11 through V20. The plurality of vias of the inactive circuit unit may include at least twenty-first through thirtieth vias V21 through V30.

[0178] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the first to sixth vias V1 to V6, the eleventh to sixteenth vias V11 to V16, and the twenty-first to twenty-sixth vias V21 to V26 can be removed to expose a portion of the surface of the semiconductor layer. The third insulating layer and the second insulating layer within the seventh to seventh vias V7, the seventeenth to seventh vias V17, and the twenty-seventh to seventh vias V27 can be removed to expose a portion of the surface of the first conductive layer. The third insulating layer within the eighth to tenth vias V8 to V10, the eighteenth to twentieth vias V18 to V20, and the twenty-eighth to thirtieth vias V28 to V30 can be removed to expose a portion of the surface of the second conductive layer.

[0179] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate having the aforementioned pattern, and the third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer. In some examples, the third conductive layer may also be referred to as a first source / drain metal layer.

[0180] Figure 11A is a planar schematic diagram of the display substrate after the third conductive layer is formed in Figure 6. Figure 11B is a schematic diagram of the third conductive layer in Figure 11A. In some examples, as shown in Figures 11A and 11B, the third conductive layer of the first circuit unit may include at least: a plurality of connecting electrodes of the first pixel circuit (for example, including the first connecting electrode 401 to the sixth connecting electrode 406). The third conductive layer of the second circuit unit may include at least: a plurality of connecting electrodes (for example, including the eleventh connecting electrode 411 to the sixteenth connecting electrode 416). The third conductive layer of the invalid circuit unit may include at least: a plurality of connecting electrodes (for example, including the twenty-first connecting electrode 421 to the thirty-sixth connecting electrode 426).

[0181] In some examples, the third conductive layer of the first display area may further include: a first auxiliary trace 45. The first auxiliary trace 45 may be located at the intersection of adjacent circuit unit rows. The first auxiliary trace 45 may be roughly in the shape of a broken line extending along the first direction X. For example, the first auxiliary trace 45 may be configured to transmit a first voltage signal or a second voltage signal line to ensure the uniformity of the first voltage signal or the second voltage signal in the first display area. For another example, the first auxiliary trace 45 may be configured to be electrically connected to the data line and the data fan-out line extending to the peripheral area, so that the data fan-out line of the peripheral area is wound within the first display area, which is conducive to achieving a narrow frame.

[0182] In some examples, the shape of the first connection electrode 401 can be substantially a strip extending along the first direction X. One end of the first connection electrode 401 can be electrically connected to the first region of the first active layer of the first pixel circuit through the first via hole V1, and the other end can be electrically connected to the fourth protrusion 194 through the eighth via hole V8 to achieve electrical connection with the first initial signal line INIT1(m).

[0183] In some examples, the second connection electrode 402 may be shaped substantially like a strip extending along the second direction Y. One end of the second connection electrode 402 may be electrically connected to the first region of the second active layer of the first pixel circuit through the second via V2, and the other end may be electrically connected to the first plate 181 of the storage capacitor of the first pixel circuit through the seventh via V7.

[0184] In some examples, the third connection electrode 403 may be substantially rectangular in shape. The third connection electrode 403 may be electrically connected to the first region of the fourth active layer of the first pixel circuit through a third via hole V3.

[0185] In some examples, the fourth connection electrode 404 can be shaped approximately like a "9." The fourth connection electrode 404 can be electrically connected to the first region of the fifth active layer of the first pixel circuit through a fifth via V5, and can also be electrically connected to the second plate 182 of the storage capacitor of the first pixel circuit through a ninth via V9.

[0186] In some examples, the fifth connection electrode 405 may be substantially rectangular in shape. The fifth connection electrode 405 may be electrically connected to the second region of the sixth active layer of the first pixel circuit through the fourth via hole V4.

[0187] In some examples, the shape of the sixth connection electrode 406 can be substantially a strip extending along the second direction Y. One end of the sixth connection electrode 406 can be electrically connected to the first region of the seventh active layer of the first pixel circuit in the previous row through a sixth via hole V6, and the other end can be electrically connected to the second initial signal line INIT2(m-1) through a tenth via hole V10.

[0188] In some examples, the eleventh connection electrode 411 may be substantially in the shape of a strip extending along the first direction X. One end of the eleventh connection electrode 411 may be electrically connected to the first region of the first active layer of the second pixel circuit through the eleventh via hole V11, and the other end may be electrically connected to the fourth protrusion 194 through the eighteenth via hole V18, thereby achieving electrical connection with the first initial signal line INIT1(m+1).

[0189] In some examples, the twelfth connection electrode 412 may be shaped substantially like a strip extending along the second direction Y. One end of the twelfth connection electrode 412 may be electrically connected to the first region of the second active layer of the second pixel circuit through a twelfth via hole V12, and the other end may be electrically connected to the first plate 281 of the storage capacitor of the second pixel circuit through a seventeenth via hole V17.

[0190] In some examples, the thirteenth connection electrode 413 may be substantially rectangular in shape. The thirteenth connection electrode 413 may be electrically connected to the first region of the fourth active layer of the second pixel circuit through the thirteenth via hole V13.

[0191] In some examples, the shape of the fourteenth connecting electrode 414 can be substantially 9-shaped. The fourteenth connecting electrode 414 can be electrically connected to the first region of the fifth active layer of the second pixel circuit through the fifteenth via hole V15, and can also be electrically connected to the second plate 282 of the storage capacitor of the second pixel circuit through the nineteenth via hole V19.

[0192] In some examples, the shape of the fifteenth connection electrode 415 may be substantially rectangular. The fifteenth connection electrode 415 may be electrically connected to the second region of the sixth active layer of the second pixel circuit through the fourteenth via hole V14.

[0193] In some examples, the shape of the sixteenth connection electrode 416 can be substantially a strip shape extending along the second direction Y. One end of the sixteenth connection electrode 416 can be electrically connected to the first region of the seventh active layer of the invalid pixel circuit in the previous row through the sixteenth via hole V16, and the other end can be electrically connected to the second initial signal line INIT2(m) through the twentieth via hole V20.

[0194] In some examples, the shape of the twenty-first connection electrode 421 can be substantially a strip shape extending along the first direction X. One end of the twenty-first connection electrode 421 can be electrically connected to the first region of the first active layer of the inactive pixel circuit through the twenty-first via hole V21, and the other end can be electrically connected to the other fourth protrusion 194 through the twenty-eighth via hole V28, thereby achieving electrical connection with the first initial signal line INIT1(m).

[0195] In some examples, the shape of the twenty-second connection electrode 422 can be substantially a strip extending along the second direction Y. One end of the twenty-second connection electrode 422 can be electrically connected to the first region of the second active layer of the inactive pixel circuit through the twenty-second via hole V22, and the other end can be electrically connected to the first plate 381 of the storage capacitor of the inactive pixel circuit through the twenty-seventh via hole V27.

[0196] In some examples, the twenty-third connection electrode 423 may be substantially rectangular in shape. The twenty-third connection electrode 423 may be electrically connected to the first region of the fourth active layer of the inactive pixel circuit through the twenty-third via hole V23.

[0197] In some examples, the shape of the twenty-fourth connection electrode 424 can be substantially 9-shaped. The twenty-fourth connection electrode 424 can be electrically connected to the first region of the fifth active layer of the inactive pixel circuit through the twenty-fifth via hole V25, and can also be electrically connected to the second plate 382 of the storage capacitor of the inactive pixel circuit through the twenty-ninth via hole V29.

[0198] In some examples, the twenty-fifth connection electrode 425 may be substantially rectangular in shape. The twenty-fifth connection electrode 425 may be electrically connected to the second region of the sixth active layer of the inactive pixel circuit through the twenty-fourth via hole V24.

[0199] In some examples, the shape of the twenty-sixth connection electrode 426 can be substantially a strip shape extending along the second direction Y. One end of the twenty-sixth connection electrode 426 can be electrically connected to the first region of the seventh active layer of the second pixel circuit in the previous row through the twenty-sixth via hole V26, and the other end can be electrically connected to the second initial signal line INIT2(m-1) through the thirtieth via hole V30.

[0200] (7) Forming a fourth insulating layer and a fifth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a fifth insulating film is coated. The fifth insulating film and the fourth insulating film are patterned in sequence using a patterning process to form the fourth insulating layer and the fifth insulating layer. The fourth insulating layer and the fifth insulating layer of each circuit unit may be provided with a plurality of vias. In some examples, the fourth insulating layer may also be referred to as a passivation layer, and the fifth insulating layer may also be referred to as a first planarization layer.

[0201] FIG12 is a schematic plan view of the display substrate after the fifth insulating layer is formed in FIG6 . In some examples, as shown in FIG12 , the plurality of vias of the first circuit unit may include at least a thirty-first via V31, a thirty-second via V32, and a thirty-third via V33. The plurality of vias of the second circuit unit may include at least a thirty-fourth via V34, a thirty-fifth via V35, and a thirty-sixth via V36. The plurality of vias of the ineffective circuit unit may include at least a thirty-seventh via V37, a thirty-eighth via V38, and a thirty-ninth via V39. The fifth insulating layer and the fourth insulating layer within the thirty-first through thirty-ninth vias V31 to V39 may be removed, exposing a portion of the surface of the third conductive layer.

[0202] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a second source / drain metal layer.

[0203] FIG13 is a schematic diagram of the fourth conductive layer in FIG6 . In some examples, as shown in FIG6 and FIG13 , the fourth conductive layer of the first circuit unit may include at least a first anode connecting electrode 441, a data line 46, and a first power line 47. The fourth conductive layer of the second circuit unit may include at least a second anode connecting electrode 442, a data line 48, and a first power line 49. The fourth conductive layer of the inactive circuit unit may include at least a third anode connecting electrode 443, a data line 48, and a first power line 49.

[0204] In some examples, the shape of the first anode connection electrode 441 can be substantially rectangular, and the corners of the rectangle can be chamfered. The first anode connection electrode 441 can be electrically connected to the fifth connection electrode 405 through the thirty-third via hole V33 to achieve electrical connection with the sixth transistor of the first pixel circuit.

[0205] In some examples, the second anode connection electrode 442 may be substantially rectangular in shape. The second anode connection electrode 442 may be electrically connected to the fifteenth connection electrode 415 through the thirty-sixth via hole V36 to achieve electrical connection to the sixth transistor of the second pixel circuit.

[0206] In some examples, the third anode connection electrode 443 may be substantially rectangular in shape. The third anode connection electrode 443 may be electrically connected to the twenty-fifth connection electrode 425 through the thirty-ninth via hole V39 to achieve electrical connection to the sixth transistor of the deactivated pixel circuit.

[0207] In some examples, the shape of the first power lines 47 and 49 can be roughly a broken line extending along the second direction Y. The first power line 47 can be electrically connected to the fourth connection electrode 404 through the thirty-second via V32 to achieve electrical connection with the fifth transistor of the first pixel circuit and the second plate of the storage capacitor. The positive projection of the first power line 47 on the substrate can cover the positive projection of the second connection electrode 402 on the substrate. Since the second connection electrode 402 is connected to the second area of ​​the first active layer of the first pixel circuit, the first area of ​​the second active layer, the gate of the third transistor and the first plate of the storage capacitor, the second connection electrode 402 can serve as the first node of the first pixel circuit. The first power line 47 can realize the transmission of a constant first voltage signal, can shield the influence of other signals in the first pixel circuit on the first node, avoid other signals (such as data voltage jump) from affecting the voltage of the first node of the first pixel circuit, and can improve the display effect.

[0208] In some examples, the first power line 49 can be electrically connected to the fourteenth connecting electrode 414 through the thirty-fifth via V35 to achieve electrical connection with the fifth transistor of the second pixel circuit and the second plate of the storage capacitor. The positive projection of the first power line 49 on the substrate can cover the positive projection of the twelfth connecting electrode 412 on the substrate. Since the twelfth connecting electrode 412 is connected to the second area of ​​the first active layer of the second pixel circuit, the first area of ​​the second active layer, the gate of the third transistor and the first plate of the storage capacitor, the twelfth connecting electrode 412 can serve as the first node of the second pixel circuit. The first power line 49 can realize the transmission of a constant first voltage signal, can shield the influence of other signals in the second pixel circuit on the first node, avoid other signals (such as data voltage jump) from affecting the voltage of the first node of the second pixel circuit, and can improve the display effect.

[0209] In some examples, the first power line 49 may also be electrically connected to the 24th connection electrode 424 through the 38th via V38. The orthographic projection of the first power line 49 on the substrate may cover the orthographic projection of the 22nd connection electrode 422 on the substrate. The first power line 49 may shield the first node of the inactive pixel circuit from the effects of other signals in the inactive pixel circuit.

[0210] In some examples, the shape of the data lines 46 and 48 can be substantially straight lines extending along the second direction Y. The data line 46 can be electrically connected to the third connection electrode 403 through the thirty-first via hole V31 to achieve electrical connection with the fourth transistor of the first pixel circuit, and is configured to provide a data signal to the first pixel circuit. The data line 48 can be electrically connected to the thirteenth connection electrode 413 through the thirty-fourth via hole V34 to achieve electrical connection with the fourth transistor of the second pixel circuit, and is configured to provide a data signal to the second pixel circuit. The data line 48 can also be electrically connected to the twenty-third connection electrode 423 through the thirty-seventh via hole V37 to achieve electrical connection with the fourth transistor of the inactive pixel circuit.

[0211] At this point, a driving circuit layer can be formed in the first display area of ​​the display substrate. For example, the driving circuit layer may include: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, and a fourth conductive layer disposed on the substrate. In some examples, after forming the fourth conductive layer, the second display area may include the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer stacked on the substrate.

[0212] (11) Forming a conductive connection layer. In some examples, the conductive connection layer may include a first connection layer, a second connection layer, and a third connection layer sequentially arranged in a direction away from the substrate. A sixth insulating layer may be provided on the side of the first connection layer close to the driving circuit layer, a seventh insulating layer may be provided between the first connection layer and the second connection layer, an eighth insulating layer may be provided between the second connection layer and the third connection layer, and a ninth insulating layer may be provided on the side of the third connection layer away from the substrate. In some examples, the sixth insulating layer may also be referred to as a second flat layer, the seventh insulating layer may also be referred to as a third flat layer, the eighth insulating layer may also be referred to as a fourth flat layer, and the ninth insulating layer may also be referred to as a fifth flat layer.

[0213] In some examples, the first connection layer, the second connection layer, and the third connection layer may each include multiple conductive connection lines. The first connection layer may further include: a fourth anode connection electrode located in the first circuit unit and electrically connected to the first anode connection electrode, a fifth anode connection electrode located in the second circuit unit and electrically connected to the second anode connection electrode, and a sixth anode connection electrode located in the inactive circuit unit and electrically connected to the third anode connection electrode. The second connection layer may further include: a seventh anode connection electrode located in the first circuit unit and electrically connected to the fourth anode connection electrode, an eighth anode connection electrode located in the second circuit unit and electrically connected to the fifth anode connection electrode, and a ninth anode connection electrode located in the inactive circuit unit and electrically connected to the sixth anode connection electrode. The third connection layer may further include: a tenth anode connection electrode located in the first circuit unit and electrically connected to the seventh anode connection electrode, an eleventh anode connection electrode located in the second circuit unit and electrically connected to the eighth anode connection electrode, and a twelfth anode connection electrode located in the inactive circuit unit and electrically connected to the ninth anode connection electrode. The first pixel circuit may be electrically connected to the first light-emitting element via the first, fourth, seventh, and tenth anode connection electrodes. The second pixel circuit can be electrically connected to the conductive connection line through the second anode connection electrode, the fifth anode connection electrode, the eighth anode connection electrode and the eleventh anode connection electrode, and electrically connected to the second light-emitting element through the conductive connection line; or it can be electrically connected to the conductive connection line through the second anode connection electrode and the fifth anode connection electrode; or it can be electrically connected to the conductive connection line through the second anode connection electrode, the fifth anode connection electrode and the eighth anode connection electrode. The invalid pixel circuit can be electrically connected to the third anode connection electrode, the sixth anode connection electrode, the ninth anode connection electrode and the twelfth anode connection electrode, but not electrically connected to the light-emitting element. In this example, by setting the third anode connection electrode, the sixth anode connection electrode, the ninth anode connection electrode and the twelfth anode connection electrode, the pattern uniformity of the first connection layer, the second connection layer and the third connection layer can be ensured, which is beneficial to the preparation of the film layer.

[0214] At this point, the conductive connection layer of the display substrate can be formed. In some examples, after forming the tenth insulating layer, the second display area may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a first connection layer, a seventh insulating layer, a second connection layer, an eighth insulating layer, a third connection layer, and a ninth insulating layer stacked on the substrate. However, this embodiment is not limited to this. In other examples, the conductive connection layer of the display substrate may include one or two connection layers.

[0215] (12) Forming a light-emitting structure layer. In some examples, an anode film is deposited on a substrate having the aforementioned pattern, and the anode film is patterned using a patterning process to form an anode layer; subsequently, a pixel definition film is coated on the substrate having the aforementioned pattern, and a pixel definition layer is formed by masking, exposure, and development processes. The pixel definition layer is formed with a plurality of pixel openings exposing the anode layer. Subsequently, an organic light-emitting layer is formed in the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned using a patterning process to form a cathode layer, and the cathode layer is electrically connected to the organic light-emitting layer.

[0216] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The fifth to ninth insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of a reflective material such as metal, and the cathode layer can be made of a transparent conductive material. However, this embodiment is not limited to this.

[0217] The structure of the display substrate and its fabrication process in this embodiment are merely illustrative. In some examples, the structure can be modified and patterning processes can be added or removed based on actual needs. For example, the fourth or fifth insulating layer can be omitted, or the number of conductive connection layers can be reduced. This embodiment is not limited to these.

[0218] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0219] The display substrate of this embodiment increases the occupied space of the second pixel circuit by reducing the occupied space of the invalid pixel circuit. It can reduce the occupied space of the second pixel circuit along the first direction while ensuring the driving effect of the second pixel circuit, thereby facilitating the increase of the arrangement space of the first pixel circuit along the first direction, and facilitating meeting the high PPI requirements of the first display area without increasing the area of ​​the second display area.

[0220] Figure 14 is a schematic diagram of the connection between the second pixel circuit and the second light-emitting element of at least one embodiment of the present disclosure. In some examples, as shown in Figure 14, a second pixel circuit 53 can be configured to drive two second light-emitting elements 54 that emit the same color light. The second display area A2 may include: a plurality of second light-emitting elements that emit red light (R), a plurality of second light-emitting elements that emit blue light (B), and a plurality of second light-emitting elements that emit green light (G). For example, the anodes of the two second light-emitting elements 54 emitting red light in the second display area A2 are electrically connected and electrically connected to a second pixel circuit 53 of the first display area through the same conductive connecting line 61, and the two second light-emitting elements 54 emitting red light can be located in adjacent columns of different rows. The anodes of the two second light-emitting elements 54 emitting blue light in the second display area A2 are electrically connected and then electrically connected to a second pixel circuit 53 in the first display area via the same conductive connecting line 61. The two second light-emitting elements 54 emitting blue light can be located in different rows but adjacent columns. One of the second light-emitting elements 54 emitting blue light and one of the second light-emitting elements 54 emitting red light can be located in the same row and in the same column as the other second light-emitting element 54 emitting red light. Another second light-emitting element 54 emitting blue light and the one of the second light-emitting elements 54 emitting red light can be located in the same column and in the same row as the other second light-emitting element 54 emitting red light. The anodes of the two second light-emitting elements 54 emitting green light in the second display area A2 are electrically connected and then electrically connected to a second pixel circuit 53 in the first display area via the same conductive connecting line 61. The two second light-emitting elements 54 emitting green light are located in the same column and in adjacent rows. Two adjacent second light-emitting elements emitting green light and located in the same column in the second display area A2 can be driven by the same second pixel circuit 53, two second light-emitting elements emitting red light and located in adjacent rows but different columns in the second display area A2 can be driven by the same second pixel circuit 53, and two second light-emitting elements emitting blue light and located in adjacent rows but different columns in the second display area A2 can be driven by the same second pixel circuit 53. However, this embodiment is not limited to this. In other examples, two adjacent second light-emitting elements emitting green light and located in the same column can be driven by the same second pixel circuit.

[0221] In some examples, as shown in FIG14 , the second pixel circuit connected to the second light-emitting element emitting green light can be located on a side of the second pixel circuit connected to the second light-emitting element emitting blue and red light that is closer to the second display area A2, and the second pixel circuit connected to the second light-emitting element emitting red light can be located on a side of the second pixel circuit connected to the second light-emitting element emitting blue light that is closer to the second display area. This connection method can ensure that the second display area A2 is illuminated effectively.

[0222] Regarding the arrangement of the first pixel circuit, the second pixel circuit and the invalid pixel circuit in this example, reference can be made to the description of the aforementioned embodiment, and thus will not be repeated here.

[0223] Figure 15 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 15, a circuit repetition unit in the first display area may include: two rows and five columns of pixel circuits, wherein multiple first pixel circuits 51 can be arranged in two rows and four columns, and one second pixel circuit 53 and an invalid pixel circuit 55 can be arranged in two rows and one column, and the second pixel circuit 53 can be located to one side of the invalid pixel circuit 55 in the second direction Y. The length of the second pixel circuit 53 along the first direction X can be less than the length of the first pixel circuit 51 along the first direction X, the length of the second pixel circuit 53 along the second direction Y can be greater than the length of the first pixel circuit 51 along the second direction Y, and the length of the first pixel circuit 51 along the second direction Y can be greater than the length of the invalid pixel circuit 55 along the second direction Y. The multiple circuit repetition units in the first display area can be arranged in an array along the first direction X and the second direction Y. The remaining description of the display substrate of this example can refer to the description of the previous embodiment, and is not repeated here.

[0224] Figure 16 is another schematic diagram of the connection between the second pixel circuit and the second light-emitting element according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the first display area may include: a plurality of first circuit repeating units as shown in Figure 5 and a plurality of second circuit repeating units as shown in Figure 15. The first circuit repeating units and the second circuit repeating units may be arranged in a spaced arrangement along the first direction X. In the second direction Y, the first circuit repeating units and the second circuit repeating units may be arranged in a spaced arrangement, or a plurality of first circuit repeating units may be arranged in a column, and a plurality of second circuit repeating units may be arranged in a column. This embodiment is not limited to this.

[0225] In some examples, as shown in FIG16 , one second light-emitting element 54 in the second display area A2 is electrically connected to one second pixel circuit 53, and one second pixel circuit 53 can be configured to drive one second light-emitting element 54 to emit light. The second pixel circuit 53 connected to the second light-emitting element 54 that emits green light (G) can be located on a side of the second pixel circuit 53 connected to the second light-emitting element 54 that emits blue light (B) and red light (R) that is closer to the second display area A2, and the second pixel circuit 53 connected to the second light-emitting element 54 that emits red light (R) can be located on a side of the second pixel circuit 53 connected to the second light-emitting element 54 that emits blue light (B) that is closer to the second display area A2. For example, multiple second light-emitting elements in the same row can be electrically connected to multiple second pixel circuits 53 in the same row via multiple conductive connecting lines 61.

[0226] In this example, by arranging the first circuit repeating units and the second circuit repeating units alternately in the first direction, this can facilitate the arrangement of the conductive connecting lines for driving a single second light-emitting element by a single second pixel circuit, and also facilitate display uniformity across the display substrate. However, this embodiment is not limited to this. In other examples, in the first direction, multiple first circuit repeating units can be arranged in a row, and multiple second circuit repeating units can be arranged in another row.

[0227] FIG17 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG17 , a circuit repetition unit in the first display area may include: two rows and five columns of pixel circuits, wherein the second pixel circuit 53 and the invalid pixel circuit 55 may be arranged in a column, and the unit column where the second pixel circuit 53 and the invalid pixel circuit 55 are located is located in the middle of the unit column where the first pixel circuit 51 is located. Two unit columns where the first pixel circuit 51 is located are set on one side of the first direction X of the unit column where the second pixel circuit 53 and the invalid pixel circuit 55 are located, and the other two unit columns where the first pixel circuit 51 is located are set on the other side. The rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0228] FIG18 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG18 , a circuit repetition unit in the first display area may include: two rows and five columns of pixel circuits, wherein the second pixel circuit 53 and the invalid pixel circuit 55 are arranged in a column, and the unit column where the second pixel circuit 53 and the invalid pixel circuit 55 are located can be located between a unit column where the first pixel circuit 51 is located and three unit columns where the first pixel circuit 51 is located. For example, the three unit columns where the first pixel circuit 51 is located are arranged on one side of the first direction X of the unit column where the second pixel circuit 53 and the invalid pixel circuit 55 are located, and the one unit column where the first pixel circuit 51 is located is arranged on the side opposite to the first direction X. The rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0229] FIG19 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG19 , the first display area may include: a first circuit repeating unit as shown in FIG5 and a second circuit repeating unit as shown in FIG15 . In the second direction Y, the first circuit repeating unit and the second circuit repeating unit may be arranged at intervals. In the first direction X, the first circuit repeating unit and the second circuit repeating unit may be arranged at intervals; alternatively, a plurality of first circuit repeating units may be arranged in a row along the first direction X, and a plurality of second circuit repeating units may be arranged in another row along the first direction. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0230] FIG20 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG20 , a circuit repetition unit in the first display area may include: six rows and five columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in six rows and four columns, three second pixel circuits 53 and three invalid pixel circuits 55 may be arranged in six rows and one column, and one invalid pixel circuit 55, three second pixel circuits 53, and two invalid pixel circuits 55 may be arranged sequentially along the second direction Y. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0231] Figure 21 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 21, a circuit repetition unit in the first display area may include: two rows and three columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and second pixel circuits 53 and inactive pixel circuits 55 may be arranged in two rows and one column, and inactive pixel circuits 55 may be located to one side of the second pixel circuit 53 along the second direction Y. Figure 21 illustrates two circuit repetition units arranged along the first direction X. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0232] Figure 22 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 22, the first display area may include a first circuit repeating unit and a second circuit repeating unit. Figure 22 illustrates a first circuit repeating unit and a second circuit repeating unit arranged along a first direction X. The first circuit repeating unit may include two rows and three columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and a second pixel circuit 53 and an inactive pixel circuit 55 may be arranged in two rows and one column, with the inactive pixel circuit 55 being located to one side of the second pixel circuit 53 along a second direction Y. The second circuit repeating unit may include two rows and three columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and a second pixel circuit 53 and an inactive pixel circuit 55 may be arranged in two rows and one column, with the second pixel circuit 53 being located to one side of the inactive pixel circuit 55 along the second direction Y. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and is therefore not repeated here.

[0233] FIG23 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG23 , a plurality of second pixel circuits 53 and a plurality of invalid pixel circuits 55 can be arranged between a plurality of first pixel circuits 51 in the second direction Y. For example, at least one first pixel circuit 51 (e.g., two first pixel circuits 51) can be provided between two adjacent second pixel circuits 53 in the second direction Y, and at least one first pixel circuit 51 (e.g., two first pixel circuits 51) can be provided between two adjacent invalid pixel circuits 55 in the second direction Y. In this example, the second pixel circuits and the invalid pixel circuits can be arranged by performing pixel circuit compression in the second direction Y.

[0234] In some examples, as shown in FIG23 , a circuit repetition unit in the first display area may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and an invalid pixel circuit 55 and a second pixel circuit 53 may be arranged in one row and two columns, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 in the first direction X. FIG23 illustrates two circuit repetition units arranged along the first direction X.

[0235] In some examples, as shown in FIG23 , the length of the first pixel circuit 51 along the first direction X can be denoted as b, and the length along the second direction Y can be denoted as a; the length of the second pixel circuit 53 along the first direction X can be denoted as d2, and the length along the second direction Y can be denoted as c2; the length of the inactive pixel circuit 55 along the first direction X can be denoted as f2, and the length along the second direction Y can be denoted as e2. The length b of the first pixel circuit 51 along the first direction X can be less than the length d2 of the second pixel circuit 53 along the first direction X. For example, the length d2 of the second pixel circuit 53 along the first direction X can be less than 1.5 times the length b of the first pixel circuit 51 along the first direction X, i.e., the ratio of d2 to b can be less than 1.5. The length a of the first pixel circuit 51 along the second direction Y can be greater than the length c2 of the second pixel circuit 53 along the second direction Y. For example, the length a of the first pixel circuit 51 along the second direction Y can be less than 1.5 times the length c2 of the second pixel circuit 53 along the second direction Y, i.e., the ratio of a to c2 can be less than 1.5. The length f2 of the invalid pixel circuit 55 along the first direction X may be smaller than the length b of the first pixel circuit 51 along the first direction X. The length e2 of the invalid pixel circuit 55 along the second direction Y may be substantially the same as the length c2 of the second pixel circuit 53 along the second direction Y.

[0236] In this example, by reducing the space occupied by the inactive pixel circuit 55 along the first direction, the space occupied by the second pixel circuit along the first direction can be increased, and the space occupied by the second pixel circuit along the second direction can be reduced, thereby facilitating the increase in the arrangement space of the first pixel circuit in the second direction. In this way, the arrangement space of the first pixel circuit can be increased without increasing the area of ​​the second display area (i.e., without increasing the number of second pixel circuits), thereby facilitating the high PPI requirement of the first display area.

[0237] Figure 24 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 24, the first display area may include: a first circuit repeating unit and a second circuit repeating unit. Figure 22 illustrates a first circuit repeating unit and a second circuit repeating unit arranged along a first direction X. The first circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the invalid pixel circuit 55 may be located to one side of the second pixel circuit 53 along the first direction X. The second circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the second pixel circuit 53 may be located to one side of the invalid pixel circuit 55 along the first direction X. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is not repeated here.

[0238] Figure 25 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 25, the first display area may include: a first circuit repeating unit and a second circuit repeating unit. Figure 25 illustrates a first circuit repeating unit and a second circuit repeating unit arranged along a first direction X. The first circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the second pixel circuit 53 may be located to one side of the invalid pixel circuit 55 along the first direction X. The second circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, and a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the invalid pixel circuit 55 may be located to one side of the second pixel circuit 53 along the first direction X. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and is not repeated here.

[0239] FIG26 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG26 , this example can arrange the second pixel circuits and invalid pixel circuits by compressing the pixel circuits in both the first direction X and the second direction Y. For example, in the first direction X, four first pixel circuits 51 are arranged alternately with one second pixel circuit 53 a or invalid pixel circuit 55 a, and in the second direction Y, one first pixel circuit 51 is arranged alternately with one second pixel circuit 53 b or invalid pixel circuit 55 b. However, this embodiment is not limited to this.

[0240] In some examples, as shown in FIG26 , the lengths of the second pixel circuit 53 a and the invalid pixel circuit 55 a arranged between the first pixel circuits 51 along the first direction X along the first direction X may be substantially the same and less than the length of the first pixel circuit 51 along the first direction X, the length of the second pixel circuit 53 a along the second direction Y may be greater than the length of the first pixel circuit 51 along the second direction Y, and the length of the invalid pixel circuit 55 a along the second direction Y may be less than the length of the first pixel circuit 51 along the second direction Y. The lengths of the second pixel circuit 53 b and the invalid pixel circuit 55 b arranged between the first pixel circuits 51 along the second direction Y along the second direction Y may be substantially the same and less than the length of the first pixel circuit 51 along the second direction Y, the length of the second pixel circuit 53 b along the first direction X may be greater than the length of the first pixel circuit 51 along the first direction X, and the length of the invalid pixel circuit 55 b along the first direction X may be less than the length of the first pixel circuit 51 along the first direction X.

[0241] In some examples, this example can increase the arrangement space of the second pixel circuit in the first direction or the second direction by reducing the occupied space of the inactive pixel circuit, thereby reducing the arrangement space of the first pixel circuit in the second direction or the first direction. In this way, the arrangement space of the first pixel circuit can be increased without increasing the area of ​​the second display area (i.e., without increasing the number of second pixel circuits), thereby facilitating meeting the high PPI requirements of the first display area. The remaining description of the display substrate of this embodiment can refer to the description of the previous embodiment, and is not repeated here.

[0242] Figure 27 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 27, the first display area A1 of the display substrate may include a transition area A12 and a sub-display area A11. The transition area A12 may surround the second display area A2. For example, the second display area A2 may be circular, and the transition area A12 may be roughly annular. The sub-display area A11 may include a plurality of first pixel circuits and a plurality of first light-emitting elements. The transition area A12 may include a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of inactive pixel circuits, and a plurality of first light-emitting elements. The second display area A2 may include a plurality of second light-emitting elements.

[0243] In some examples, the light transmittance of the first display area A1 can be lower than the light transmittance of the second display area A2. The light transmittance of the sub-display area A11 of the first display area A1 can be lower than the light transmittance of the transition area A12, and the light transmittance of the transition area A12 can be lower than the light transmittance of the second display area A2. However, this embodiment is not limited to this. In other examples, multiple second pixel circuits can be located in the transition area and the sub-display area, and the light transmittance of the sub-display area can be the same as the light transmittance of the transition area.

[0244] This example arranges the second pixel circuit in the transition region to ensure the display effect of the sub-display region, which is conducive to achieving a high PPI in the sub-display region. The arrangement of the first pixel circuit, the second pixel circuit, and the inactive pixel circuit in the transition region of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0245] FIG28 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG28 , the transition region A12 may be located on both sides of the second display region A2 in the first direction X. The remaining description of the display substrate of this example can be found in the description of the previous embodiment and is not repeated here.

[0246] In other examples, the first display area may not be divided into a transition area and a sub-display area, and the plurality of second pixel circuits may be arranged in the entire first display area. This embodiment is not limited to this.

[0247] This embodiment also provides a display substrate, comprising: a substrate, a driving circuit layer, and a light-emitting structure layer. The substrate comprises a first display area and a second display area, wherein the first display area is located on at least one side of the second display area. The driving circuit layer is located in the first display area, and comprises a plurality of first pixel circuits and a plurality of second pixel circuits. The light-emitting structure layer is located on a side of the driving circuit layer away from the substrate, and comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements. The area of ​​at least one first pixel circuit is different from the area of ​​at least one second pixel circuit.

[0248] In some exemplary embodiments, the driving circuit layer further includes: a plurality of invalid pixel circuits; and an area of ​​at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than an area of ​​the at least one first pixel circuit.

[0249] In some exemplary embodiments, the plurality of second pixel circuits are arranged in a first direction with intervals between the plurality of first pixel circuits. A length of at least one first pixel circuit in the first direction is greater than a length of at least one second pixel circuit in the first direction, a length of the at least one first pixel circuit in the second direction is less than a length of the at least one second pixel circuit in the second direction, and the first direction intersects the second direction.

[0250] In some exemplary embodiments, the driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits being arranged alternately between the plurality of first pixel circuits in the first direction, and at least one of the plurality of invalid pixel circuits being adjacent to the at least one second pixel circuit in the second direction. A length of the at least one invalid pixel circuit in the first direction is the same as a length of the at least one second pixel circuit in the first direction, and a length of the at least one invalid pixel circuit in the second direction is less than a length of the at least one first pixel circuit in the second direction.

[0251] The description of the display substrate of this example can be referred to the description of the aforementioned embodiment, so it will not be repeated here.

[0252] FIG29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG29 , this embodiment provides a display device comprising: a display substrate 91. In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be any of the following products: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device for e-government, banks, hospitals, power departments, etc.), a monitor, etc. For another example, the display device may be any of a microdisplay, a VR device or an AR device containing a microdisplay, etc.

[0253] In some examples, the display device may further include: at least one sensor 92 located on a light-emitting side (non-display side) away from the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 overlaps with the second display area A2.

[0254] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; A driving circuit layer, located in the first display area, comprising: a plurality of first pixel circuits and a plurality of second pixel circuits; a light emitting structure layer, located on a side of the driving circuit layer away from the substrate, comprising a plurality of first light emitting elements located in the first display area and a plurality of second light emitting elements located in the second display area; At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light emitting element among the plurality of first light emitting elements, and at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light emitting element among the plurality of second light emitting elements; The size of the at least one first pixel circuit is different from the size of the at least one second pixel circuit.

2. The display substrate according to claim 1, wherein: The sizes of the plurality of first pixel circuits are the same, the sizes of the plurality of second pixel circuits are the same, and the sizes of the plurality of first pixel circuits are different from the sizes of the plurality of second pixel circuits.

3. The display substrate according to claim 1, wherein: The driving circuit layer further includes: a plurality of invalid pixel circuits; a size of at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than a size of the at least one first pixel circuit.

4. The display substrate according to any one of claims 1 to 3, wherein: The plurality of second pixel circuits are arranged between the plurality of first pixel circuits at intervals in the first direction; The length of the at least one first pixel circuit in the first direction is greater than the length of the at least one second pixel circuit in the first direction, the length of the at least one first pixel circuit in the second direction is less than the length of the at least one second pixel circuit in the second direction, and the first direction intersects with the second direction.

5. The display substrate according to claim 4, wherein: The driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits are arranged between the plurality of first pixel circuits at intervals in the first direction, and at least one invalid pixel circuit among the plurality of invalid pixel circuits is adjacent to the at least one second pixel circuit in the second direction; The length of the at least one invalid pixel circuit in the first direction is the same as the length of the at least one second pixel circuit in the first direction, and the length of the at least one invalid pixel circuit in the second direction is less than the length of the at least one first pixel circuit in the second direction.

6. The display substrate according to claim 5, wherein: The sum of the length of the at least one invalid pixel circuit in the second direction and the length of the adjacent second pixel circuit in the second direction is 1.8 times to 2.2 times the length of the at least one first pixel circuit in the second direction.

7. The display substrate according to claim 5 or 6, wherein: The at least one second pixel circuit and the at least one invalid pixel circuit are arranged at intervals in the second direction; Four first pixel circuits and one invalid pixel circuit are arranged at intervals in the first direction, or four first pixel circuits and one second pixel circuit are arranged at intervals in the first direction; or four first pixel circuits, one invalid pixel circuit, four first pixel circuits and one second pixel circuit are arranged at intervals in the first direction.

8. The display substrate according to claim 7, wherein: The sum of four times the length of the at least one first pixel circuit in the first direction and the length of the at least one invalid pixel circuit in the first direction is 1.8 to 2.2 times the length of the at least one first pixel circuit in the second direction.

9. The display substrate according to any one of claims 5 to 8, wherein: The plurality of first pixel circuits, the plurality of second pixel circuits and the plurality of invalid pixel circuits of the driving circuit layer are divided into a plurality of circuit repetition units, each circuit repetition unit comprising: a plurality of first pixel circuits arranged in two rows and four columns, a second pixel circuit and an invalid pixel circuit arranged in two rows and one column; In the circuit repetition unit, the second pixel circuit and the invalid pixel circuit are located on the same side of the multiple first pixel circuits, or, in the circuit repetition unit, the second pixel circuit and the invalid pixel circuit are located in the middle of four columns of first pixel circuits; or, the second pixel circuit and the invalid pixel circuit are located in the middle of one column of first pixel circuits and three columns of first pixel circuits.

10. The display substrate according to claim 9, wherein: The arrangement order of the second pixel circuits and the invalid pixel circuits in the adjacent circuit repetition units in the first direction is different in the second direction.

11. The display substrate according to any one of claims 1 to 10, wherein: A second pixel circuit is electrically connected to a second light-emitting element; or, two second light-emitting elements emitting light of the same color are electrically connected to the same second pixel circuit.

12. The display substrate according to claim 11, wherein: The plurality of second light emitting elements include: a plurality of second light emitting elements emitting red light, a plurality of second light emitting elements emitting blue light, and a plurality of second light emitting elements emitting green light; The second pixel circuit connected to the second light emitting element emitting green light is located on a side of the second pixel circuit connected to the second light emitting element emitting red light and the second light emitting element emitting blue light close to the second display area; The second pixel circuit connected to the emitting red light is located at a side of the second pixel circuit connected to the second light emitting element emitting blue light close to the second display area.

13. The display substrate according to claim 12, wherein: Two adjacent second light emitting elements emitting green light and located in the same column are electrically connected to the same second pixel circuit; two second light emitting elements emitting blue light and located in adjacent rows but different columns are electrically connected to the same second pixel circuit, and two second light emitting elements emitting red light and located in adjacent rows but different columns are electrically connected to the same second pixel circuit; One of the two second light-emitting elements emitting blue light is located in the same row as one of the two second light-emitting elements emitting red light, and is located in the same column as the other second light-emitting element emitting red light; the other second light-emitting element emitting blue light is located in the same column as one of the second light-emitting elements emitting red light, and is located in the same row as the other second light-emitting element emitting red light.

14. The display substrate according to any one of claims 1 to 13, wherein: In a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged on a substrate; The semiconductor layer includes at least: active layers of transistors of the plurality of first pixel circuits and the plurality of second pixel circuits; The first conductive layer at least includes: gates of transistors of the plurality of first pixel circuits and first electrodes of storage capacitors, and gates of transistors of the plurality of second pixel circuits and first electrodes of storage capacitors; The second conductive layer at least includes: second electrodes of storage capacitors of the plurality of first pixel circuits and the plurality of second pixel circuits; The third conductive layer at least includes: a plurality of connecting electrodes; The fourth conductive layer at least includes: a data line and a first power line.

15. The display substrate according to any one of claims 1 to 14, wherein: The first display area includes: a transition area located at at least one side of the second display area and a sub-display area located at at least one side of the transition area, and the plurality of second pixel circuits are located in the transition area; or, The plurality of second pixel circuits are located in the transition area and the sub-display area.

16. The display substrate according to claim 15, wherein: The light transmittance of the first display area is less than the light transmittance of the second display area; or; The light transmittance of the sub-display area of ​​the first display area is less than or equal to the light transmittance of the transition area, and the light transmittance of the transition area is less than the light transmittance of the second display area.

17. The display substrate according to any one of claims 1 to 16, wherein: The pixel density of the first display area is greater than or equal to the pixel density of the second display area.

18. A display device, comprising a display substrate as claimed in any one of claims 1 to 17, and a sensor located on a non-display surface side of the display substrate; the orthographic projection of the sensor on the display substrate overlaps with a second display area of ​​the display substrate.

19. A display substrate, comprising: A substrate, comprising a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; A driving circuit layer, located in the first display area, comprising: a plurality of first pixel circuits and a plurality of second pixel circuits; a light emitting structure layer, located on a side of the driving circuit layer away from the substrate, comprising a plurality of first light emitting elements located in the first display area and a plurality of second light emitting elements located in the second display area; At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light emitting element among the plurality of first light emitting elements, and at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light emitting element among the plurality of second light emitting elements; An area of ​​the at least one first pixel circuit is different from an area of ​​the at least one second pixel circuit.

20. The display substrate according to claim 19, wherein: The driving circuit layer further includes: a plurality of invalid pixel circuits; an area of ​​at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than an area of ​​the at least one first pixel circuit.

21. The display substrate according to claim 19, wherein: The plurality of second pixel circuits are arranged between the plurality of first pixel circuits at intervals in the first direction; The length of the at least one first pixel circuit in the first direction is greater than the length of the at least one second pixel circuit in the first direction, the length of the at least one first pixel circuit in the second direction is less than the length of the at least one second pixel circuit in the second direction, and the first direction intersects with the second direction.

22. The display substrate according to claim 21, wherein: The driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits are arranged between the plurality of first pixel circuits at intervals in the first direction, and at least one invalid pixel circuit among the plurality of invalid pixel circuits is adjacent to the at least one second pixel circuit in the second direction; The length of the at least one invalid pixel circuit in the first direction is the same as the length of the at least one second pixel circuit in the first direction, and the length of the at least one invalid pixel circuit in the second direction is less than the length of the at least one first pixel circuit in the second direction.

Images