System calling method, processing apparatus, chip and electronic device

Abstract

The present application relates to the field of computers. Disclosed in the embodiments of the present application are a system calling method, a processing apparatus, a chip and an electronic device. The present application solves the problems in the prior art that when a processor switches operation states so as to access resources corresponding to different programs, the operation efficiency of the processor is relatively low and the operation cost is relatively high. The specific solution is: providing the system calling method, the method comprising: under a first privilege level, a processor acquiring a first instruction part of a block instruction, the first instruction part being used for indicating a second instruction part of the block instruction and specified registers, the specified registers being registers used when the second instruction part is being executed, the first instruction part comprising an instruction of the first privilege level, the second instruction part comprising an instruction of a second privilege level, the first privilege level being lower than the second privilege level, and the specified registers being some global registers among a plurality of global registers; and executing the second instruction part according to the first instruction part, wherein the specified registers are used when the second instruction part is being executed.

Description

System calling method, processing device, chip and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on July 21, 2023, with application number 202310916332.3 and application name “A system call method, processing device, chip and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of computers, and in particular to a system call method, a processing device, a chip, and an electronic device. Background Art

[0003] Processors perform highly complex computing and control tasks. For example, they need to run multiple applications and an operating system (OS) that manages these applications. The OS is also known as a computer management control program. To limit the range of resources the processor can access when running different programs, protect resources such as memory and input / output (I / O), and avoid security issues such as operating system crashes, processors have multiple operating states (or privilege levels). The operating system assigns a privilege level to each program and allocates corresponding resources. For example, a processor's operating states include kernel state (or operating system privilege level) and user state (or application privilege level). The operating system assigns an operating system privilege level to the operating system kernel and an application privilege level to each application. By switching operating states, the processor can run different programs and access the resources corresponding to each program, without having unlimited access to resources.

[0004] However, in the prior art, when a processor switches its operating state to access resources corresponding to different programs, the operating efficiency of the processor is low and the operating cost is high.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a system call method, processing device, chip and electronic device, which solve the problem in the prior art that the processor has low operating efficiency and high operating cost when switching operating states to access resources corresponding to different programs.

[0007] To achieve the above objectives, the present invention adopts the following technical solutions:

[0008] In a first aspect of an embodiment of the present application, a system call method is provided, which is applied to an electronic device including a processor, the processor being used to execute a block instruction, the processor including multiple global registers, the method comprising: the processor obtaining a first instruction portion of the block instruction at a first privilege level, the first instruction portion being used to indicate a second instruction portion of the block instruction and a designated register, the designated register being a register used when executing the second instruction portion, the first instruction portion including instructions of a first privilege level, the second instruction portion including instructions of a second privilege level, the first privilege level being lower than the second privilege level, and the designated register being a portion of the multiple global registers. The second instruction portion is executed according to the first instruction portion, and the designated register is used when executing the second instruction portion.

[0009] The above-mentioned block instruction refers to an instruction set including a first instruction part and a second instruction part. The first instruction part corresponds to the second instruction part. The first instruction part can also be called a block header, and the second instruction part can also be called a block body. The first instruction part includes instructions of the first privilege level, and the second instruction part includes instructions of the second privilege level.

[0010] Optionally, the first privilege level may include one of a hypervisor privilege level, an operating system privilege level, an application privilege level, etc., and the second privilege level may include one of a security privilege level, a hypervisor privilege level, an operating system privilege level, etc. The embodiments of the present application are not limited to this.

[0011] Optionally, the second instruction part may include one instruction, or may include multiple instructions. The embodiment of the present application does not limit the specific number of instructions included in the second instruction part.

[0012] Optionally, taking the example of a processor including M global registers, the above-mentioned designated register may include 1 global register, or may include N global registers among the M global registers, where M is a positive integer and N is a positive integer greater than 1 and less than M. The embodiments of the present application do not limit the specific values ​​of M and N.

[0013] Optionally, when the designated register includes multiple global registers, some of the multiple global registers can be used to obtain the second instruction part, and other global registers can be used to store the result after the second instruction part is executed. Alternatively, all of the multiple global registers can be used to obtain the second instruction part and store the result after the second instruction part is executed. The embodiments of the present application are not limited to this.

[0014] Based on this solution, the processor first obtains the first instruction part of the block instruction at the first privilege level, and the first instruction part is used to indicate the second instruction part of the block instruction and the designated register used when executing the second instruction part. The first instruction part includes instructions of the first privilege level, the second instruction part includes instructions of the second privilege level, and the designated register is a portion of the multiple global registers included in the processor. Then, the processor executes the second instruction part according to the first instruction part, and uses the designated register when executing the second instruction part. Compared with the prior art, in which the application switches the processor's operating state through system calls, saves the context, and then obtains and executes instructions of the operating system's privilege level through all global registers, the processor, by adopting the system call method provided in the embodiment of the present application, can access the resources corresponding to the second privilege level program through designated registers without switching the operating state or saving the context, execute the second instruction part of the second privilege level, and implement the functions of the second privilege level, thereby improving the operating efficiency of the processor and reducing operating costs.

[0015] In conjunction with the first aspect, in one implementation, the second instruction portion includes at least one instruction, and the method further includes: storing an execution result of the at least one instruction in a designated register. Alternatively, the processor further includes a dedicated register, storing a first execution result of the at least one instruction in the dedicated register, and storing a second execution result in the dedicated register in the designated register, wherein the first execution result includes the second execution result.

[0016] Based on this solution, by storing the first execution result of at least one instruction in a dedicated register and the second execution result in a global register, more instructions can be scheduled for calculation compared to the pipeline technology in the prior art, thereby improving scheduling efficiency and processor performance.

[0017] In conjunction with the first aspect, in one implementation, the first instruction portion is obtained by the processor during execution of a program at a first privilege level, the program at the first privilege level including the first instruction portion, and the second instruction portion is executed by the processor during execution of the program at the first privilege level.

[0018] Based on this solution, while a processor is executing a program at a first privilege level, the processor obtains a first instruction portion, which includes the first instruction portion. During the execution of the program at the first privilege level, the processor executes a second instruction portion based on the first instruction portion, enabling the program at the first privilege level to implement the functionality of the second privilege level. This allows the processor to access resources corresponding to the program at the second privilege level, execute the second instruction portion at the second privilege level, and implement the functionality of the second privilege level without switching operating states or saving context. This improves the processor's operating efficiency and reduces operating costs.

[0019] In combination with the first aspect, in one implementation, the first instruction part includes address information, the address information is used to indicate the address of the second instruction part, and executing the second instruction part according to the first instruction part includes: executing the second instruction part according to the address information.

[0020] Based on this solution, the first instruction part includes address information, which is used to indicate the address of the second instruction part, so that the processor can execute the second instruction part according to the first instruction part. The processor can access the resources corresponding to the program of the second privilege level without switching the running state or saving the context, execute the second instruction part of the second privilege level, and realize the function of the second privilege level, thereby improving the operating efficiency of the processor and reducing the operating cost.

[0021] In combination with the first aspect, in one implementation, the second instruction part includes authentication information. Before executing the second instruction part according to the address information, the method further includes: determining whether the second instruction part is legal according to the authentication information.

[0022] Based on this solution, the second instruction part includes authentication information, and the processor determines that the second instruction part is legal based on the authentication information, thereby avoiding the execution of the second instruction part that affects the security and reliability of the operating system, thereby improving the security and reliability of the system call method provided in the embodiment of this application.

[0023] In combination with the first aspect, in one implementation, the first instruction part includes indication information, there is a correspondence between the indication information and the second instruction part, and the second instruction part is executed according to the first instruction part, including: determining and executing the second instruction part corresponding to the indication information according to the indication information and the correspondence.

[0024] Based on this solution, the first instruction part includes indication information, and there is a correspondence between the indication information and the second instruction part. The processor determines and executes the second instruction part based on the indication information and the correspondence, thereby avoiding obtaining the second instruction part that affects the security and reliability of the operating system based on the first instruction part. Therefore, the security and reliability of the system call method provided in the embodiment of the present application can be improved.

[0025] In combination with the first aspect, in one implementation, the first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

[0026] In a second aspect of an embodiment of the present application, a processing device is provided, which is used to execute block instructions. The processing device includes a global engine, a block engine coupled to the global engine, and multiple global registers. The global engine is used to obtain a first instruction portion of the block instruction when the processing device is operating at a first privilege level. The first instruction portion is used to indicate a second instruction portion of the block instruction and a designated register. The designated register is a register used when executing the second instruction portion. The first instruction portion includes instructions of a first privilege level, and the second instruction portion includes instructions of a second privilege level. The first privilege level is lower than the second privilege level. The designated register is a portion of the multiple global registers. The global engine is also used to schedule the block engine to execute the second instruction portion based on the first instruction portion, and to use the designated register when executing the second instruction portion.

[0027] In conjunction with the second aspect, in one implementation, the second instruction portion includes at least one instruction. The block engine is configured to store an execution result of the at least one instruction in a designated register. Alternatively, the block engine includes a dedicated register, the block engine is configured to store a first execution result of the at least one instruction in the dedicated register, and store a second execution result in the dedicated register in the designated register, wherein the first execution result includes the second execution result.

[0028] In conjunction with the second aspect, in one implementation, the first instruction portion is obtained by the processing device during execution of a program at a first privilege level, the program at the first privilege level including the first instruction portion, and the second instruction portion is executed by the processing device during execution of the program at the first privilege level.

[0029] In combination with the second aspect, in one implementation, the first instruction part includes address information, and the address information is used to indicate the address of the second instruction part. The global engine is specifically used to schedule the block engine to execute the second instruction part according to the address information.

[0030] In combination with the second aspect, in one implementation, the second instruction part includes authentication information. Before the global engine schedules the block engine to execute the second instruction part based on the address information, the global engine is further configured to determine the legitimacy of the second instruction part based on the authentication information.

[0031] In conjunction with the second aspect, in one implementation, the first instruction portion includes instruction information, and there is a correspondence between the instruction information and the second instruction portion. The global engine is specifically configured to determine, based on the instruction information and the correspondence, the second instruction portion corresponding to the instruction information, and schedule the block engine to execute the second instruction portion.

[0032] In conjunction with the second aspect, in one implementation, the first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

[0033] In a third aspect of the embodiments of the present application, a system call device is provided. The system call device is configured to implement the system call method described in the first aspect or any possible implementation of the first aspect. The system call device includes an acquisition module and a processing module. Exemplarily, the acquisition module is configured to support acquisition operations of the system call device, such as acquiring the first instruction portion. The processing module is configured to control and manage the actions of the system call device and to execute the processing operations performed by the system call device in the above embodiments, such as executing the second instruction portion.

[0034] According to a fourth aspect of an embodiment of the present application, a chip is provided, which includes a cache memory and a processing device coupled to the cache memory, wherein the processing device is the processing device described in the second aspect or any possible implementation of the second aspect.

[0035] Optionally, the chip may be a processor, which may be a central processing unit, or a microcontroller, which may also be called a single-chip microcomputer, and the embodiments of the present application are not limited to this.

[0036] According to a fifth aspect of an embodiment of the present application, an electronic device is provided, which includes a memory and a chip coupled to the memory, wherein the chip is the chip described in the fourth aspect or any possible implementation of the fourth aspect.

[0037] Optionally, the above-mentioned storage may be a memory, or may be a hard disk, which is not limited in the embodiment of the present application.

[0038] Optionally, the type of the electronic device may include a computer, a laptop, a smart watch, a smart bracelet, a smart phone, a smart car machine, a drone, etc. The embodiment of the present application does not limit the specific type of the electronic device.

[0039] In a sixth aspect of an embodiment of the present application, a computer-readable storage medium is provided, which stores a computer program. When the computer program runs on a processor, the processor executes the steps in the system call method described in the first aspect or any possible implementation of the first aspect.

[0040] In a seventh aspect of the embodiments of the present application, a computer program product is provided. When the computer program product runs on a processor, the processor executes the steps in the system call method described in the first aspect or any possible implementation of the first aspect.

[0041] The descriptions of the second to seventh aspects of this application can refer to the detailed description of the first aspect; and the beneficial effects described in the second to seventh aspects can refer to the analysis of the beneficial effects of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic diagram of a process of executing instructions by a processor;

[0043] FIG2 is a schematic diagram of a process in which a processor executes instructions using pipeline technology;

[0044] FIG3 is a schematic diagram of a process of executing instructions using a processor using block instruction technology;

[0045] FIG4 is a schematic diagram showing the relationship between a program and a privilege level;

[0046] FIG5 is a flowchart of a system calling method provided in an embodiment of the present application;

[0047] FIG6 is a schematic diagram of a process of executing instructions using a block instruction technology in a processor according to an embodiment of the present application;

[0048] FIG7 is a schematic diagram of the relationship between a program and a privilege level provided in an embodiment of the present application;

[0049] FIG8 is a flowchart of another system call method provided in an embodiment of the present application;

[0050] FIG9 is a schematic structural diagram of a system call device provided in an embodiment of the present application;

[0051] FIG10 is a schematic structural diagram of a chip provided in an embodiment of the present application;

[0052] FIG11 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0054] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0055] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0056] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

[0057] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0058] Before introducing the embodiments of the present application, the technical terms and background technologies involved in the present application are first introduced.

[0059] Operating System Kernel: The operating system kernel is the core component of the operating system, responsible for managing the system's memory, hardware devices, file system, and applications. The kernel provides a set of services that allow applications to interact with the computer's hardware. The kernel and applications are interdependent: the kernel manages computer resources, while applications execute user operations by invoking kernel services.

[0060] Privilege level: A term used in computer operating systems to refer to a specific level of privilege for a user-mode process or thread. Privilege levels are established to ensure system security and stability. By assigning different operations and resources to different privilege levels, the operating system ensures that sensitive operations can only be performed by processes or threads with sufficient privileges, thereby preventing accidental or malicious activity from impacting the system.

[0061] Context: refers to the values ​​of the processor's internal registers and program counter, as well as the address of the program counter, and also includes some other data stored inside the processor.

[0062] As shown in Figure 1, it is a schematic diagram of the process of a processor 110 executing instructions. The processor 110 is coupled to the memory 120. The processor 110 includes a computing unit 111 and an internal memory (also called a register) 112 that are coupled to each other. The memory 120 stores an instruction sequence, which includes at least one instruction arranged in an execution order. When the processor 110 executes an instruction, the processor 110 first obtains an instruction from the instruction sequence in the execution order and stores it in the internal memory 112. Then the computing unit 111 obtains the instruction from the internal memory 112 to complete the calculation and returns the calculation result to the internal memory 112. Finally, the processor 110 stores the calculation result in the internal memory 120 to the memory 120 or the hard disk to complete the calculation of the instruction. The processor 110 continuously obtains instructions from the instruction sequence in the execution order to complete the calculation of the instruction sequence.

[0063] To improve the performance of processor 110, processor 110 can employ pipelining technology. Figure 2 illustrates a schematic diagram of the process by which processor 110 executes instructions using pipelining technology. Processor 110 can begin executing the next instruction before one instruction is completed, thereby improving the performance of processor 110. For example, if processor 110 takes time t to execute each instruction, processor 110 can begin executing the next instruction before the time t has elapsed, thereby improving the efficiency and performance of processor 110.

[0064] However, when dependencies exist between instructions in an instruction sequence, the computational efficiency and performance of the processor 110 may be reduced. For example, if the computation of the third instruction in the instruction sequence requires the execution result of the second instruction to complete, the third instruction cannot be executed until the second instruction completes, which may reduce the efficiency and performance of the processor 110.

[0065] To solve this problem, the processor 110 can use superscalar technology. For example, taking the case where the first instruction and the second instruction in the instruction sequence have a dependency relationship, and the calculation of the second instruction requires the calculation result of the first instruction, the processor 110 can first guess the calculation result of the first instruction in the process of processing the first and second instructions, and calculate the second instruction based on the guessed result. If the guessed result is the same as the calculation result of the first instruction, the calculation result of the second instruction can be used directly. If the guessed result is different from the calculation result of the first instruction, the second instruction is recalculated, thereby improving the computing efficiency and performance of the processor 110. In some instruction execution scenarios where there is less need to guess the results, such as instruction execution scenarios such as conditional judgment, the processor 110 can use this superscalar technology.

[0066] To improve the performance of processor 110, processor 110 may also employ block instruction technology. FIG3 shows a schematic diagram of a process in which processor 110 employs block instruction technology to execute instructions. In this case, processor 110 includes a global engine 113, as well as at least one global register 114 and at least one block engine 115 coupled to global engine 113. Each global register 114 and each block engine 115 may be coupled under the control of global engine 113 to transmit instructions or calculation results. Each block engine 115 includes a dedicated register 1151. Memory 120 stores a first instruction partial sequence and a second instruction partial sequence. Each instruction in the first instruction partial sequence is used to indicate at least one instruction in the second instruction partial sequence, as well as the global register 114 used by processor 110 when executing the at least one instruction. The second instruction partial sequence includes at least one instruction.

[0067] Each instruction in the first instruction sequence can be referred to as a "block header," and at least one instruction in the second instruction sequence indicated by the block header can be referred to as a "block body." Each block header and the block body corresponding to the block header constitute a block instruction. The global engine 113 is used to obtain and schedule the block headers in the first instruction sequence, determine the global register 114 used in the corresponding block body calculation process based on the block header, and allocate the block engine 115 used when calculating the block body. The global register 114 is used to obtain the block body corresponding to the block header and transmit it to the block engine 115. The block engine 115 is used to complete the calculation of the block body. The results of the block body calculation process can be stored in the dedicated register 1151. After the block body calculation is completed, the results are transmitted to the global register 114. The global register 114 transmits the calculation results of the block body to the memory 120 to complete the calculation of the block instruction. The processor 110 executes instructions by adopting block instruction technology. Compared with the above-mentioned pipeline technology, it can schedule more instructions for calculation, thereby improving scheduling efficiency and improving the performance of the processor 110. It can also improve the single-thread execution performance of the processor 110 by setting multiple block engines 115.

[0068] For example, consider an instruction sequence consisting of five instructions with dependencies between them. Processor 110 can construct a block instruction, which includes a block header and a block body. The block header indicates the five instructions and the global registers 114 used to execute the five instructions, while the block body includes the five instructions. When processor 110 executes the block instruction, global engine 113 retrieves the block header, determines the global registers 114 used to calculate the block body of the block instruction, and allocates a block engine 115 to calculate the block body to complete the calculation of the block instruction. The specific process can be found in the description above and will not be repeated here.

[0069] Processor 110 handles increasingly complex computing and control tasks. For example, processor 110 needs to run multiple applications and the operating system that manages these multiple applications. To limit the scope of resources accessible by processor 110 when running different programs, protect resources such as memory and input / output, and avoid security issues such as operating system crashes, processor 110 has multiple operating states. The operating system assigns a privilege level to each program and allocates corresponding resources. For example, the processor's operating states include kernel state and user state. The operating system assigns an operating system privilege level to the operating system kernel and an application privilege level to each application. When the processor runs a program at the application privilege level, it can be said that the processor is in the application privilege level, or that the processor's operating state is user state. When the processor runs a program at the operating system privilege level, it can be said that the processor is in the operating system privilege level, or that the processor's operating state is kernel state. By switching operating states, processor 110 can run different programs and access the resources corresponding to the programs, without having unlimited access to resources.

[0070] For example, FIG4 is a schematic diagram illustrating the relationship between programs and privilege levels. The operating state of processor 110 includes an operating system privilege level (also referred to as a supervisor privilege level) and an application privilege level (also referred to as a user privilege level). The operating system can assign an operating system privilege level to the operating system kernel, assign an application privilege level to each application, and allocate corresponding resources. Each application can be referred to as an "instance" of an application privilege level.

[0071] The operating state of the processor 110 can be switched under the control of the operating system, thereby running at different privilege levels at different times. When the processor 110 is at the operating system privilege level, the processor 110 can run the operating system kernel and access resources managed by the operating system kernel, such as memory, I / O, and other resources. When the processor 110 is at the application privilege level, the processor 110 can run application programs and access resources corresponding to the application programs. When the application program running on the processor 110 requires services or resources provided by the operating system kernel, such as reading files, creating processes, accessing the hardware and software resources of the operating system, etc., the application program can issue a system call (syscall), also known as a system service request, requesting the operating system to switch the operating state of the processor 110 to the operating system privilege level and execute the corresponding instructions to complete the corresponding operation. In this way, the scope of resources accessed by the processor 110 when running a program can be limited, and the processor 110 cannot access all resources at will, which can avoid security issues such as operating system crashes.

[0072] Because the memory resources (e.g., global registers 114) in processor 110 are limited, processor 110 needs to use memory resources when executing instructions from each application. Therefore, processor 110 needs to save context and release memory resources when switching operating states. Specifically, each time the processor 110 switches from the application privilege level to the operating system privilege level, it needs to save the register values ​​used by the application before executing instructions at the operating system privilege level. This process is called "saving user process context," or "saving context."

[0073] For example, as shown in FIG4 , the processor 110 is at the application privilege level and the first application program being run needs to access the resources of the operating system. As shown in (1) in FIG4 , the processor 110 can save the context based on the system call instruction in the first application program, for example, the context can be saved to the memory 120, and the running state of the processor 110 can be switched to the operating system privilege level, the operating system kernel can be restored to control the processor 110, and the instructions specified by the operating system can be executed. As shown in (2) in FIG4 , after the processor 110 has executed the instructions specified by the operating system, the running state can be switched to the application privilege level and, based on the saved context, the execution of the instructions of the first application program can be resumed to continue running the first application program.

[0074] However, when the processor 110 switches the running state and saves the context to access resources corresponding to different programs, the running efficiency of the processor 110 will be low and the running cost will be high.

[0075] For example, consider processor 110, an advanced RISC machine (ARM) V8 architecture processor, including 32 global registers 114. Processor 110 executes a word processing application (Microsoft Word), which requires the operating system kernel to provide file read services. Therefore, the operating state of processor 110 needs to switch from the application privilege level to the operating system privilege level. Before switching the operating state, the 32 global registers 114 store data for the Word program. First, processor 110 needs to store the data in the 32 global registers 114 in memory 120, then store the instructions corresponding to the file read services in the operating system kernel in the 32 global registers 114, and then execute the instructions corresponding to the file read services. However, storing the data in the 32 global registers 114 for the Word program in memory 120 requires storage space in memory 120 and consumes a significant amount of time. Storing the instructions corresponding to the file read services in the operating system kernel in the 32 global registers 114 also consumes a significant amount of time, resulting in reduced operating efficiency and higher operating costs for processor 110.

[0076] In order to solve the problem of low operating efficiency and high operating costs when the processor 110 switches operating states to access resources corresponding to different programs, the embodiments of the present application provide a system call method that can improve the operating efficiency of the processor 110 and reduce operating costs. The system call method provided in the embodiments of the present application can be applied to physical computers, virtual machines, and various types of operating systems, and the embodiments of the present application are not limited to this.

[0077] As shown in Figure 5, a flowchart of a system call method provided in an embodiment of the present application is provided. The method includes steps S501-S502. The system call method is applied to an electronic device including a processor, the processor including multiple global registers, and the processor for executing block instructions. The block instruction refers to an instruction set including a first instruction part and a second instruction part, the first instruction part corresponding to the second instruction part, the first instruction part can also be called a block header, and the second instruction part can also be called a block body, the first instruction part includes instructions of a first privilege level, and the second instruction part includes instructions of a second privilege level.

[0078] For example, the electronic device may be a computer, the processor may be the processor 110 shown in FIG3 , and the global register may be the global register 114. The embodiment of the present application takes the application of the system call method to the processor 110 shown in FIG3 as an example for illustrative explanation, and the description of each component in the above-mentioned processor 110 may be referred to in the following embodiments.

[0079] S501. The processor 110 obtains a first instruction portion of a block instruction at a first privilege level. The first instruction portion is used to indicate a second instruction portion of the block instruction and a designated register. The designated register is a register used when executing the second instruction portion. The first instruction portion includes instructions of a first privilege level, the second instruction portion includes instructions of a second privilege level, the first privilege level is lower than the second privilege level, and the designated register is some global registers 114 among a plurality of global registers 114.

[0080] Optionally, the first privilege level may include one of a hypervisor privilege level, an operating system privilege level, an application privilege level, etc., and the second privilege level may include one of a security privilege level, a hypervisor privilege level, an operating system privilege level, etc. The embodiments of the present application are not limited to this.

[0081] For example, the first privilege level may be an application privilege level, and the second privilege level may be an operating system privilege level. The following embodiments of the present application are described by taking the first privilege level as the application privilege level and the second privilege level as the operating system privilege level as an example.

[0082] In one possible embodiment, the first instruction portion includes instructions at an application privilege level, which may include instructions generated by a compiler based on a program at the application privilege level. The second instruction portion includes instructions at an operating system privilege level, which may include instructions generated by a compiler based on a program at the operating system privilege level. The embodiments of the present application do not limit the specific type of the application privilege level program.

[0083] Optionally, the compiler for compiling the application privileged-level program and the compiler for compiling the operating system privileged-level program may be the same compiler or different compilers, which is not limited in the embodiments of the present application.

[0084] For example, taking the application privilege level program as a Word program, the operating system privilege level program as an operating system kernel, and using different compilers for compilation as an example, the first instruction part may include instructions generated by the application compiler based on the compilation of the Word program, and the second instruction part may include instructions generated by the operating system compiler based on the compilation of the operating system kernel.

[0085] In a possible embodiment, as shown in Figure 6, the processor 110 is coupled to the memory 120. Since the first instruction part includes instructions of the application privilege level, the first instruction part can be stored in the storage area of ​​the application privilege level in the memory 120, and the second instruction part includes instructions of the operating system privilege level, the second instruction part can be stored in the storage area of ​​the operating system privilege level in the memory.

[0086] Optionally, the second instruction part may include one instruction, or may include multiple instructions. The embodiment of the present application does not limit the specific number of instructions included in the second instruction part.

[0087] In a possible embodiment, the processor 110 obtains the first instruction portion of the block instruction at the first privilege level, including: when the processor 110 runs at the application privilege level, the global engine 113 in the processor 110 can control the global register 114 to obtain the first instruction portion of the block instruction from the storage area of ​​the application privilege level in the memory 120.

[0088] Optionally, taking the example of the processor 110 including M global registers 114, the above-mentioned designated register may include one global register 114, or may include N global registers 114 among the M global registers 114, where M is a positive integer and N is a positive integer greater than 1 and less than M. The embodiments of the present application do not limit the specific values ​​of M and N.

[0089] For example, taking the example that the processor 110 includes 32 global registers 114 , the designated registers may include 3 global registers 114 .

[0090] Optionally, when the designated register includes multiple global registers 114, some of the multiple global registers 114 can be used to obtain the second instruction part, and other global registers 114 can be used to store the result after the second instruction part is executed. Alternatively, all of the multiple global registers 114 can be used to obtain the second instruction part and store the result after the second instruction part is executed. This embodiment of the present application is not limited to this.

[0091] For example, if the designated registers include three global registers 114, two of the global registers 114 can be used to obtain the second instruction portion, and the other global register 114 can be used to store the result after the second instruction portion is executed. Alternatively, one of the global registers 114 can be used to obtain the second instruction portion, and the other two global registers 114 can be used to store the result after the second instruction portion is executed. Alternatively, the three global registers 114 can be used to obtain the second instruction portion and also to store the result after the second instruction portion is executed.

[0092] In a possible embodiment, the first instruction portion is obtained by the processor 110 during the process of executing a program of a first privilege level, and the program of the first privilege level includes the first instruction portion.

[0093] For example, when the processor 110 runs a Word program at an application privilege level, it obtains a first instruction portion, and the Word program includes the first instruction portion.

[0094] In a possible embodiment, the processor 110 may be a central processing unit (CPU), which is not limited in the embodiment of the present application.

[0095] S502: The processor 110 executes the second instruction part according to the first instruction part, and uses a designated register when executing the second instruction part.

[0096] In one possible embodiment, the first instruction portion includes address information, where the address information is used to indicate the address of the second instruction portion. For example, the address information may be a pointer. The processor 110 executing the second instruction portion according to the first instruction portion includes: the processor 110 executing the second instruction portion according to the address information.

[0097] In one possible embodiment, the second instruction portion includes at least one instruction, and processor 110 executes the second instruction portion, including storing an execution result of the at least one instruction in a designated register. Alternatively, processor 110 includes a dedicated register 1151, stores a first execution result of the at least one instruction in dedicated register 1151, and stores a second execution result in dedicated register 1151 in a designated register, where the first execution result includes the second execution result.

[0098] Wherein, when the second instruction portion includes one instruction, the first execution result includes the execution result of the instruction, and the execution result of the instruction is the second execution result. When the second instruction portion includes multiple instructions, the first execution result includes the result after each instruction is executed, and the result after the last instruction among the multiple instructions is the second execution result.

[0099] For example, as shown in FIG6 , the processor 110 further includes a block engine 115, which includes the aforementioned dedicated register 1151. For example, in the case where the second instruction portion includes two instructions and the designated register includes one global register 114, the processor 110 executes the second instruction portion, specifically including: first, the block engine 115 retrieves and executes the first of the two instructions from the global register 114, and stores the result of executing the first instruction in the dedicated register 1151. Then, the block engine 115 retrieves the second of the two instructions from the designated register, executes the second instruction based on the execution result of the first instruction, and stores the result of executing the second instruction in the dedicated register 1151. Finally, the execution result of the second instruction portion is stored in the global register 114, completing the execution of the two instructions. It will be understood that the first execution result includes the execution result of the first instruction and the execution result of the second instruction, and the second execution result is the execution result of the second instruction. By storing the first execution result of the two instructions in the dedicated register 1151 and the second execution result in the global register 114, compared with the above-mentioned pipeline technology, more instructions can be scheduled for calculation, thereby improving the scheduling efficiency and the performance of the processor 110. The single-thread execution performance of the processor 110 can also be improved by setting multiple block engines 115.

[0100] In a possible embodiment, the second instruction portion is executed by the processor 110 during the process of running a program at the first privilege level. When the processor 110 executes the second instruction portion, the program at the first privilege level implements the function of the second privilege level.

[0101] Optionally, the functions of the second privilege level include: creating a new process, executing a system call, managing memory, accessing a file system, etc., which is not limited in the embodiments of the present application.

[0102] For example, taking the program of the first privilege level as a Word program and the function of the second privilege level as accessing the file system as an example, when the block engine 115 in the processor 110 executes the second instruction part, the Word program can implement the function of accessing the file system.

[0103] To facilitate understanding of the system call method provided by the present application, the following is an illustration using the processor 110 running a Word program as an example.

[0104] As shown in FIG7 , a schematic diagram of the relationship between a program and a privilege level is provided. For example, the operating state of the processor 110 includes an application privilege level and an operating system privilege level. The operating system assigns an application privilege level to the Word program and other application programs, and an operating system privilege level to the operating system kernel. The instructions compiled by the Word program include a third instruction, a first instruction portion, and a fourth instruction. The instructions compiled by the operating system kernel include a second instruction portion, and the second instruction portion is used to implement the function of accessing system files. When the processor 110 runs at the application privilege level and runs the Word program, the processor 110 can sequentially execute the third instruction generated by the Word program. When a user uses the Word program to input text and the Word program needs to implement the function of accessing system files, as shown in (1) in FIG7 , the processor 110 can obtain the first instruction portion, and according to the first instruction portion, obtain and execute the second instruction portion through a designated register to implement the function of accessing system files. When the processor 110 completes the execution of the second instruction portion, it can continue to execute the fourth instruction. It can be understood that by adopting the system call method provided in the embodiment of the present application, in the process of the Word program implementing the function of accessing the system file, the processor 110 does not need to save the context, and does not need to wait for the data in the global register 114 to be stored in the memory 120 before executing the second instruction part. Therefore, the operating efficiency of the processor 110 can be improved and the operating cost can be reduced.

[0105] In a possible embodiment, when the processor 110 executes a program of the first privilege level to implement the function of the second privilege level, it needs to execute a large number of instructions, and it takes a lot of time to obtain and execute the instructions through the specified register. In this case, the system call method provided in the embodiment of the present application may not be adopted. The compiler may generate a system call instruction based on the compilation of the program of the first privilege level. The processor 110 switches the running state according to the system call instruction, saves the context, and uses all the global registers 114 in the processor 110 to obtain and execute instructions, thereby improving the operating efficiency of the processor.

[0106] In the system call method provided in the embodiments of the present application, the processor 110 first obtains the first instruction portion of a block instruction at the first privilege level. The first instruction portion is used to indicate the second instruction portion of the block instruction and the designated registers to be used when executing the second instruction portion. The first instruction portion includes instructions of the first privilege level, the second instruction portion includes instructions of the second privilege level, and the designated registers are some of the global registers 114 included in the processor 110. The processor 110 then executes the second instruction portion based on the first instruction portion, using the designated registers when executing the second instruction portion. Compared to the prior art, in which an application switches the processor's operating state through a system call, saves the context, and then obtains and executes instructions at the operating system's privilege level through all global registers, the processor 110, through the system call method provided in the embodiments of the present application, can access resources corresponding to a program at the second privilege level through designated registers without switching the operating state or saving the context, execute the second instruction portion of the second privilege level, and implement the functions of the second privilege level. This can improve the operating efficiency of the processor 110 and reduce operating costs.

[0107] In one possible embodiment, to improve the security and reliability of the system call method provided in the embodiments of the present application, the first instruction portion and / or the second instruction portion may be restricted to prevent the processor 110 from obtaining the second instruction portion, which could affect the security and reliability of the operating system, based on the first instruction portion. For example, if the first instruction portion includes address information and the first instruction portion is not restricted, the address information may point to the second instruction portion for accessing the password, resulting in lower security and reliability of the operating system. The following provides examples of various implementations.

[0108] As shown in Figure 8, in a possible embodiment, the above-mentioned second instruction part may include authentication information. The system call method provided in the embodiment of the present application also includes step S503 before the processor 110 executes the second instruction part according to the address information in the above-mentioned step S502.

[0109] S503: The processor 110 determines, based on the authentication information, that the second instruction portion is legal.

[0110] Specifically, after obtaining the second instruction portion and before executing the second instruction portion, the global engine 113 in the processor 110 can determine whether the second instruction portion is legal based on the authentication information in the second instruction portion. If the second instruction portion is determined to be legal, the processor 110 executes the second instruction portion, thereby avoiding the execution of the second instruction portion that may affect the security and reliability of the operating system.

[0111] In a possible embodiment, the authentication information may include at least one special character, and the global engine 113 may determine whether the second instruction part is legal based on the at least one special character.

[0112] In a possible embodiment, the special characters in the above-mentioned authentication information can be generated by the compiler based on the program compiled at the second privilege level. The global engine 113 can determine whether the second instruction part is legal based on whether the authentication information includes special characters and whether the format of the authentication information is correct.

[0113] In the system call method provided in the embodiment of the present application, the second instruction part includes authentication information. The processor 110 determines that the second instruction part is legal based on the authentication information, thereby avoiding the execution of the second instruction part that affects the security and reliability of the operating system. Therefore, the security and reliability of the system call method provided in the embodiment of the present application can be improved.

[0114] In a possible embodiment, the first instruction part may include indication information, and there is a correspondence between the indication information and the second instruction part. The above step S502 includes: the processor 110 determines and executes the second instruction part corresponding to the indication information based on the indication information and the correspondence.

[0115] Specifically, the global engine 113 in the processor 110 can determine the second instruction part corresponding to the indication information based on the indication information and the correspondence between the indication information and the second instruction part, and obtain the second instruction part through the designated register, thereby avoiding obtaining the second instruction part that affects the security and reliability of the operating system based on the first instruction part.

[0116] In a possible embodiment, the correspondence between the above-mentioned indication information and the second instruction part can be stored in a register in the processor 110 in the form of a table, or stored in the memory 120, and the global engine 113 can query the table according to the indication information to determine the second instruction part corresponding to the indication information.

[0117] Exemplarily, the indication information may be a character. In the embodiment of the present application, the character is a number, and different numbers correspond to different second instruction parts as an example for illustrative explanation.

[0118] For example, when the indication information is the number "1", the indication information "1" corresponds to two instructions, and the two instructions are the second instruction part. When the indication information is the number "2", the indication information "2" corresponds to three instructions, and the three instructions are the second instruction part.

[0119] In the system call method provided in the embodiment of the present application, the first instruction part includes indication information, and there is a correspondence between the indication information and the second instruction part. The processor 110 determines the second instruction part based on the indication information and the correspondence, thereby avoiding obtaining the second instruction part that affects the security and reliability of the operating system based on the first instruction part, thereby improving the security and reliability of the system call method provided in the embodiment of the present application.

[0120] Based on this, an embodiment of the present application further provides a processing device for executing a block instruction, wherein the block instruction refers to an instruction set including a first instruction portion and a second instruction portion, wherein the first instruction portion corresponds to the second instruction portion, the first instruction portion may also be referred to as a block header, and the second instruction portion may also be referred to as a block body, wherein the first instruction portion includes instructions of a first privilege level, and the second instruction portion includes instructions of a second privilege level. The processing device may be a processor, and the embodiment of the present application uses the processor 110 shown in FIG6 as an example for illustrative description. The processor 110 includes a global engine 113, a block engine 115 coupled to the global engine 113, and a plurality of global registers 114.

[0121] The global engine 113 is used to obtain the first instruction part of the block instruction when the processor 110 runs at the first privilege level. The first instruction part is used to indicate the second instruction part of the block instruction and the designated register. The designated register is the register used when executing the second instruction part. The first instruction part includes instructions of the first privilege level, and the second instruction part includes instructions of the second privilege level. The first privilege level is lower than the second privilege level. The designated register is some global registers 114 among multiple global registers 114.

[0122] The global engine 113 is further configured to schedule the block engine 115 to execute the second instruction portion according to the first instruction portion, and to use a designated register when executing the second instruction portion.

[0123] Optionally, the first privilege level may include one of a hypervisor privilege level, an operating system privilege level, an application privilege level, and the like, and the second privilege level may include one of a security privilege level, a hypervisor privilege level, an operating system privilege level, and the like, and the embodiments of the present application are not limited thereto. The following embodiments of the present application take the first privilege level as the application privilege level and the second privilege level as the operating system privilege level as an example for illustrative description.

[0124] Optionally, the second instruction part may include one instruction, or may include multiple instructions. The embodiment of the present application does not limit the specific number of instructions included in the second instruction part.

[0125] Optionally, taking the example of the processor 110 including M global registers 114, the above-mentioned designated register may include one global register 114, or may include N global registers 114 among the M global registers 114, where M is a positive integer and N is a positive integer greater than 1 and less than M. The embodiments of the present application do not limit the specific values ​​of M and N.

[0126] Optionally, when the designated register includes multiple global registers 114, some of the multiple global registers 114 can be used to obtain the second instruction part, and other global registers 114 can be used to store the result after the second instruction part is executed. Alternatively, all of the multiple global registers 114 can be used to obtain the second instruction part and store the result after the second instruction part is executed. This embodiment of the present application is not limited to this.

[0127] Optionally, the processor 110 may include at least one block engine 115 , and the at least one block engine 115 and a plurality of global registers 114 are coupled to the global engine 113 . The embodiment of the present application does not limit the specific number of block engines 115 included in the processor 110 .

[0128] As shown in FIG6 , in one possible embodiment, the second instruction portion includes at least one instruction. The block engine 115 is configured to store the execution result of the at least one instruction in a designated register. Alternatively, the block engine 115 includes a dedicated register 1151, and the block engine 115 is configured to store a first execution result of the at least one instruction in the dedicated register and a second execution result in the dedicated register in the designated register, wherein the first execution result includes the second execution result.

[0129] In one possible embodiment, the first instruction portion is obtained by the processor 110 (processing device) while executing a program at a first privilege level, and the program at the first privilege level includes the first instruction portion. The second instruction portion is executed by the processor 110 while executing the program at the first privilege level. When the processor 110 executes the second instruction portion, the program at the first privilege level implements the functionality of the second privilege level.

[0130] In a possible embodiment, the first instruction portion includes address information, and the address information is used to indicate the address of the second instruction portion. The global engine 113 is specifically used to schedule the block engine to execute the second instruction portion according to the address information.

[0131] In a possible embodiment, the second instruction part includes authentication information. Before the global engine 113 schedules the block engine to execute the second instruction part based on the address information, the global engine 113 is further configured to determine whether the second instruction part is legal based on the authentication information.

[0132] In a possible embodiment, the first instruction part includes indication information, and there is a correspondence between the indication information and the second instruction part. The global engine 113 is specifically used to determine the second instruction part corresponding to the indication information based on the indication information and the correspondence, and schedule the block engine to execute the second instruction part.

[0133] The processor 110 (processing device) provided in an embodiment of the present application first obtains the first instruction portion of a block instruction at a first privilege level. The first instruction portion is used to indicate the second instruction portion of the block instruction and the designated registers to be used when executing the second instruction portion. The first instruction portion includes instructions of the first privilege level, the second instruction portion includes instructions of the second privilege level, and the designated registers are some of the multiple global registers included in the processor. Then, based on the first instruction portion, the global engine 113 schedules the block engine 115 to execute the second instruction portion, using the designated registers when executing the second instruction portion. Compared to the prior art, in which an application switches the processor's operating state through a system call, saves the context, and then obtains and executes instructions at the operating system's privilege level through all global registers, the processor 110, by adopting the system call method provided in an embodiment of the present application, can access resources corresponding to a program at the second privilege level through designated registers without switching the operating state or saving the context, execute the second instruction portion of the second privilege level, and implement the functions of the second privilege level. This can improve the operating efficiency of the processor 110 and reduce operating costs.

[0134] As shown in FIG9 , an embodiment of the present application further provides a system call device 900 . The system call device 900 may be the processor 110 in the above embodiment. The system call device 900 may be used to implement the system call method of any of the above embodiments.

[0135] The system call apparatus 900 includes an acquisition module 901 and a processing module 902. Exemplarily, the acquisition module 901 is used to support acquisition operations of the system call apparatus 900, such as acquiring the first instruction portion. The processing module 902 is used to control and manage the actions of the system call apparatus 900 and to execute the processing operations performed by the system call apparatus 900 in the above-described embodiments, such as executing the second instruction portion. Optionally, if the system call apparatus 900 includes a storage unit, the processing module 902 may also execute programs or instructions stored in the storage unit, thereby enabling the system call apparatus 900 to implement the methods and functions involved in any of the above-described embodiments.

[0136] For example, the processing module 902 can be used to execute, for example, step S502 in FIG. 5 , and / or other processes for the technology described herein. The acquisition module 901 can be used to execute, for example, step S501 in FIG. 5 , and / or other processes for the technology described herein. All relevant content of each step involved in the above method embodiment can be referenced to the functional description of the corresponding functional module and will not be repeated here.

[0137] Exemplarily, in hardware implementation, the functions of the acquisition module 901 can be performed by a transceiver (transmitter / receiver) and / or a communication interface, and the functions of the processing module 902 can be performed by an accelerator, wherein the processing module 902 can be embedded in or independent of the processor of the system call device 900 in the form of hardware, or can be stored in the memory of the system call device 900 in the form of software, so that the processor can call and execute the operations corresponding to the above functional units.

[0138] As shown in FIG10 , an embodiment of the present application further provides a chip 1000 , which includes a cache memory 1001 and a processing device 1002 coupled to the cache memory 1001 . The structure of the processing device 1002 is the structure of the processor 110 shown in FIG6 .

[0139] Optionally, the chip 1000 may be a central processing unit, or a microcontroller unit (MCU), or a single-chip microcomputer, which is not limited in the embodiment of the present application.

[0140] As shown in FIG11 , an embodiment of the present application further provides an electronic device 1100 , which includes a memory 1101 and a chip 1000 coupled to the memory 1101 . The structure of the chip 1000 is the same as that of the chip 1000 shown in FIG10 .

[0141] Optionally, the memory 1101 may be a memory, or a hard disk, which is not limited in the embodiment of the present application.

[0142] Optionally, the type of the electronic device 1100 may include a computer, a laptop computer, a smart watch, a smart bracelet, a smart phone, a smart car machine, a drone, etc. The embodiment of the present application does not limit the specific type of the electronic device 1100.

[0143] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the steps in the system call method shown in Figure 5 or Figure 8.

[0144] An embodiment of the present application further provides a computer program product. When at least one processor of the electronic device 1100 runs the computer program product, the processor executes the steps in the system call method shown in FIG. 5 or FIG. 8 .

[0145] The above detailed description of the system call method and the analysis of beneficial effects can all be correspondingly referred to the processor 110, the system call device 900, the chip 1000, the electronic device 1100, the computer-readable storage medium and the computer program product, and the embodiments of the present application will not be repeated here.

[0146] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A system call method, characterized in that: Applied in an electronic device including a processor, the processor is used to execute a block instruction, the processor includes a plurality of global registers, and the method includes: The processor obtains a first instruction part of the block instruction at a first privilege level, the first instruction part is used to indicate a second instruction part and a designated register of the block instruction, the designated register is a register used when executing the second instruction part, the first instruction part includes instructions of the first privilege level, the second instruction part includes instructions of the second privilege level, the first privilege level is lower than the second privilege level, and the designated register is a part of the global registers among the multiple global registers; The second instruction portion is executed according to the first instruction portion, and the designated register is used when executing the second instruction portion.

2. The method according to claim 1, characterized in that The second instruction portion includes at least one instruction, and the method further includes: storing the execution result of the at least one instruction in the designated register; Alternatively, the processor further comprises a dedicated register; A first execution result of the at least one instruction is stored in the dedicated register, and a second execution result in the dedicated register is stored in the designated register, wherein the first execution result includes the second execution result.

3. The method according to claim 1 or 2, characterized in that: The first instruction portion is obtained by the processor during the process of running the program of the first privilege level, and the program of the first privilege level includes the first instruction portion; The second instruction portion is executed by the processor during the process of running the program at the first privilege level.

4. The method according to any one of claims 1 to 3, characterized in that The first instruction part includes address information, and the address information is used to indicate the address of the second instruction part. The executing the second instruction part according to the first instruction part includes: The second instruction portion is executed according to the address information.

5. The method according to any one of claims 1 to 4, characterized in that The second instruction part includes authentication information, and the method further includes: The legality of the second instruction portion is determined according to the authentication information.

6. The method according to any one of claims 1 to 3, characterized in that The first instruction part includes instruction information, and there is a corresponding relationship between the instruction information and the second instruction part. The executing the second instruction part according to the first instruction part includes: According to the indication information and the corresponding relationship, the second instruction part corresponding to the indication information is determined and executed.

7. The method according to any one of claims 1 to 6, characterized in that The first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

8. A processing device, characterized in that: The processing device is used to execute block instructions, and the processing device includes a global engine, a block engine coupled to the global engine, and a plurality of global registers; The global engine is used to obtain a first instruction part of the block instruction when the processing device runs at a first privilege level, the first instruction part is used to indicate a second instruction part of the block instruction and a designated register, the designated register is a register used when executing the second instruction part, the first instruction part includes instructions of a first privilege level, the second instruction part includes instructions of a second privilege level, the first privilege level is lower than the second privilege level, and the designated register is a part of the multiple global registers; The global engine is further configured to schedule the block engine to execute the second instruction part according to the first instruction part, and use the designated register when executing the second instruction part.

9. The processing device according to claim 8, characterized in that The second instruction portion includes at least one instruction; The block engine is configured to store the execution result of the at least one instruction in the designated register; Alternatively, the block engine includes dedicated registers; The block engine is used to store a first execution result of the at least one instruction in the dedicated register, and store a second execution result in the dedicated register in the designated register, wherein the first execution result includes the second execution result.

10. The processing device according to claim 8 or 9, characterized in that: The first instruction portion is obtained by the processing device during the process of running the program of the first privilege level, and the program of the first privilege level includes the first instruction portion; The second instruction portion is executed by the processing device during the process of running the program of the first privilege level.

11. The processing device according to any one of claims 8 to 10, characterized in that: The first instruction part includes address information, and the address information is used to indicate the address of the second instruction part; The global engine is specifically configured to schedule the block engine to execute the second instruction portion according to the address information.

12. The processing device according to any one of claims 8 to 11, characterized in that: The second instruction portion includes authentication information; The global engine is further used to determine whether the second instruction part is legal according to the authentication information.

13. The processing device according to any one of claims 8 to 10, characterized in that: The first instruction part includes instruction information, and there is a corresponding relationship between the instruction information and the second instruction part; The global engine is specifically configured to determine the second instruction portion corresponding to the indication information according to the indication information and the corresponding relationship, and schedule the block engine to execute the second instruction portion.

14. The processing device according to any one of claims 8 to 13, characterized in that: The first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

15. A chip, characterized in that: The chip includes a cache memory and a processing device coupled to the cache memory, wherein the processing device is the processing device according to any one of claims 8 to 14.

16. An electronic device, characterized in that: The electronic device comprises a memory and a chip coupled to the memory, wherein the chip is the chip as claimed in claim 15.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program runs on a processor, the processor is enabled to execute the system call method according to any one of claims 1 to 7.

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