Encoder verification apparatus and verification method, and storage medium

Abstract

An encoder verification deviceapparatus, comprising: a dual-read head chip, arranged on an encoder read head (100), the dual-read head chip comprising a first control module (300) and a second control module (400), the first control module (300) comprising a first chip (310), the second control module (400) comprising a second chip, and optical detection apparatuses being provided on both each of the first chip (310) and the second chip being provided with an optical detection apparatus; a reflective substrate (600), configured to receive and reflect infrared light emitted by an infrared light source; and a controller, configured to perform first configuration on pins of the first chip (310) and the second chip, and perform signal conditioning on a configured first three-channel unit and a configured second three-channel unit, so as to obtain a first control signal and a second control signal, ; and control, , according to signal parameters of the first control signal and the second control signal, controlling the infrared light source to emit the infrared light, so such that the dual-read head chip performs encoder verification according to the infrared light reflected from the reflective substrate (600). Also Further provided are an encoder verification method and a storage medium.

Description

Encoder verification device, verification method and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application number 2023109279226, filed with the Chinese Patent Office on July 26, 2023, entitled “Verification device, verification method and storage medium for encoder,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the field of data verification technology, and in particular to a verification device, a verification method and a storage medium of an encoder. Background Art

[0004] Currently, during the calibration of encoders, in order to address the problem of inaccurate readings from the reader due to contamination of the encoder code disk, which can lead to errors, the problem is usually solved by comparing the read A and B numbers with the set resolution to determine whether the code disk is blocked, and then comparing the read A and B numbers with the known code disk resolution. However, in the prior art, the code disk only records the Z value once per rotation. If multiple A code channels are blocked on the code disk, speed anomalies will occur during speed measurement. Failure to perform calibration in a timely manner will cause the code disk to experience joint jitter, hindering subsequent encoder maintenance. In addition, if the code disk resolution is too high, it will affect the accuracy and efficiency of the encoder calibration.

[0005] Summary of the Invention

[0006] The main purpose of the embodiments of the present disclosure is to provide a verification device, a verification method and a storage medium for an encoder, so as to improve the verification accuracy of the encoder through mutual verification of dual reader chips.

[0007] To achieve the above-mentioned purpose, an embodiment of the present disclosure provides a calibration device for an encoder, wherein the encoder includes a reader and a code disk, wherein the code disk is disposed on the reader, and the calibration device includes:

[0008] A dual-head reader chip is provided in the reader, the dual-head reader chip includes a first control module and a second control module, the first control module includes a first chip, the second control module includes a second chip, and the first chip and the second chip are both provided with a light detection device, wherein the light detection device includes an infrared light source and a light receiver, the infrared light source is configured to generate infrared light, and the light receiver is configured to receive reflected infrared light;

[0009] A reflective substrate is provided on the code disk, and the reflective substrate is configured to reflect the received infrared light;

[0010] a controller connected to the dual-reader chip, the controller being configured to perform a first configuration on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit, and perform signal conditioning on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal;

[0011] The controller is configured to control the infrared light source to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual read head chip verifies the encoder according to the infrared light reflected by the reflective substrate.

[0012] Optionally, the first control module includes a first adjustment unit, the second control module includes a second adjustment unit, the first adjustment unit includes a first resistor module configured to amplify different signal multiples, and the second adjustment unit includes a second resistor module configured to amplify different signal multiples.

[0013] Optionally, a sleeve and a cover plate are further included, wherein the sleeve is arranged between the reflective substrate and the cover plate, and the sleeve is configured to fix the code disk.

[0014] Optionally, the first control module further includes a first filtering unit and a second filtering unit, and the first filtering unit and the second filtering unit are both configured to filter out clutter and AC components.

[0015] Optionally, the second control module further includes a third filtering unit and a fourth filtering unit, and the third filtering unit and the fourth filtering unit are both configured to filter out clutter and AC components.

[0016] Optionally, a positioning hole and a fixing hole are also provided on the reader, and the fixing hole is provided on the upper side of the positioning hole, and the fixing hole and the positioning hole are both provided on the upper side of the dual reader chip; the positioning hole is configured to locate the position of the dual reader chip, and the fixing hole is configured to fix the verification device.

[0017] The present disclosure also provides an encoder calibration method, which is applied to an encoder calibration device, wherein the encoder includes a reader and a code disk, the code disk being disposed on the reader, and the calibration device includes:

[0018] A dual-head reader chip is provided in the reader, the dual-head reader chip includes a first control module and a second control module, the first control module includes a first chip, the second control module includes a second chip, and the first chip and the second chip are both provided with a light detection device, wherein the light detection device includes an infrared light source and a light receiver;

[0019] A reflective substrate, disposed on the code disc;

[0020] The method comprises:

[0021] Performing a first configuration on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit;

[0022] performing signal conditioning on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal;

[0023] The infrared light source is controlled to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual-head chip verifies the encoder according to the infrared light reflected by the reflective substrate.

[0024] Optionally, performing a first configuration on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit includes:

[0025] Numbering the pins of the first chip and the second chip to obtain a first adjustment unit and a second adjustment unit;

[0026] Dividing the first adjustment unit and the second adjustment unit by multiples to obtain a plurality of first subintervals and a plurality of second subintervals, wherein the first subintervals are used to adjust the multiples of the output signal of the first adjustment unit, and the second subintervals are used to adjust the multiples of the output signal of the second adjustment unit;

[0027] The first three-channel unit is generated according to the first adjustment unit, and the second three-channel unit is generated according to the second adjustment unit.

[0028] Optionally, performing signal conditioning on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal includes:

[0029] Adjusting multiple pins of the first three-channel unit to output analog signals;

[0030] performing interval selection on a plurality of second subintervals of the second three-channel unit and outputting a first pulse signal;

[0031] The first control signal is generated according to the analog signal, and the second control signal is generated according to the first pulse signal.

[0032] Optionally, performing signal conditioning on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal includes:

[0033] performing interval selection on a plurality of first subintervals of the first three-channel unit and outputting a second pulse signal;

[0034] performing interval selection on a plurality of second subintervals of the second three-channel unit and outputting a third pulse signal;

[0035] The first control signal is generated according to the second pulse signal, and the second control signal is generated according to the third pulse signal.

[0036] Optionally, controlling the infrared light source to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual-head chip verifies the encoder according to the infrared light reflected by the reflective substrate, includes:

[0037] When the first control signal is an analog signal and the second control signal is a first pulse signal, acquiring an analog value of the analog signal;

[0038] controlling the infrared light source to emit infrared light so that the second chip counts pulses in the first pulse signal according to the infrared light reflected by the reflective substrate to obtain a first pulse value;

[0039] Within a preset time interval, the simulation value and the first pulse value are compared with preset theoretical values ​​to determine target values;

[0040] The encoder is calibrated according to the target value.

[0041] Optionally, controlling the infrared light source to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual-head chip verifies the encoder according to the infrared light reflected by the reflective substrate, includes:

[0042] When the first control signal is a second pulse signal and the second control signal is a third pulse signal, controlling the infrared light source to emit infrared light so that the first chip counts pulses in the second pulse signal to obtain a second pulse value;

[0043] controlling the second chip to count pulses in the third pulse signal according to the infrared light reflected by the reflective substrate to obtain a third pulse value;

[0044] Comparing the second pulse value and the third pulse value within a preset time interval to obtain a target verification value;

[0045] The encoder is verified according to the target verification value.

[0046] The embodiments of the present disclosure further provide a storage medium, which is a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a computer, the computer is configured to execute the encoder verification method as described in any one of the embodiments of the present disclosure.

[0047] The verification device, verification method and storage medium of the encoder proposed in the embodiments of the present disclosure have the following beneficial effects: the dual reader chip of this embodiment is arranged on the reader, including a first control module and a second control module, and the first control module includes a first chip, and the second control module includes a second chip, which is convenient for subsequent mutual verification through the dual reader chips, and a light detection device is provided on the first chip and the second chip, and the light detection device includes an infrared light source and a light receiver, the infrared light source is configured to generate infrared light, and the light receiver is configured to receive reflected infrared light, and the light detection device is integrated on the first chip and the second chip, so there is no need to add a light source and a light receiving module separately, thereby improving the simplicity of the verification device, and the verification device is also provided with a reflective substrate, which is configured to receive the infrared light emitted by the infrared light source and emit the infrared light to the first chip or the second chip. The corresponding optical receiver is convenient for the subsequent controller to verify the encoder. The controller is connected to the dual-head reader chip and is configured to perform a first configuration on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit, so as to adjust the signal parameters output by the first chip and the second chip, and perform signal adjustment on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal, thereby obtaining different types of control signals, and the controller is configured to control the infrared light source to emit infrared light according to the signal parameters of the first control signal and the second control, so that the dual-head reader chip verifies the encoder according to the infrared light reflected by the reflective substrate. Through the mutual verification of the dual-head reader chips, real-time detection of the encoder is achieved, thereby avoiding the problem of joint jitter, improving the verification accuracy of the encoder, and further improving the verification efficiency of the encoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a schematic diagram of a calibration device for an encoder provided in an embodiment of the present disclosure;

[0049] FIG2 is a circuit diagram of a first control module provided in an embodiment of the present disclosure;

[0050] FIG3 is a schematic diagram of a framework of a calibration device for an encoder provided in an embodiment of the present disclosure;

[0051] FIG4 is a flow chart of a verification method for an encoder provided by an embodiment of the present disclosure;

[0052] FIG5 is a flow chart of step S101 in FIG4 ;

[0053] FIG6 is a flow chart of step S102 in FIG4 ;

[0054] FIG7 is a flow chart of step S102 in FIG4 ;

[0055] FIG8 is a flow chart of step S103 in FIG4 ;

[0056] FIG9 is a flow chart of step S103 in FIG4 ;

[0057] FIG10 is a schematic diagram of the hardware structure of a computer device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments described herein are only used to explain the present disclosure and are not intended to limit the present disclosure.

[0059] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and so on, in the specification, claims, and drawings, are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0061] The encoder verification method provided by the embodiment of the present disclosure can be applied to a terminal, a server, or software running on a terminal or a server. Optionally, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, or a smart watch; the server can be configured as an independent physical server, or as a server cluster or distributed system composed of multiple physical servers, or as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms; the software can be an application that implements the above method, but is not limited to the above forms.

[0062] Embodiments of the present disclosure may be applied to numerous general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer computer devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present disclosure may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present disclosure may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communications network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0063] Please refer to Figures 1 and 2. Figure 1 is a schematic diagram of a calibration device for an encoder provided in an embodiment of the present disclosure.

[0064] Optionally, the encoder includes a reader 100 and a code disk 200, the code disk 200 is arranged on one side of the reader 100, and the verification device includes: a dual reader chip, which is arranged on the reader 100, and the dual reader chip includes a first control module 300 and a second control module 400, and the first control module 300 includes a first chip 310, and the second control module 400 includes a second chip, which is convenient for subsequent mutual verification through the dual reader chips, and a light detection device is provided on the first chip 310 and the second chip, and the light detection device includes an infrared light source and a light receiver, the infrared light source is configured to generate infrared light, and the light receiver is configured to receive reflected infrared light, and the light detection device is integrated on the first chip 310 and the second chip, so there is no need to add a light source and a light receiving module separately, thereby improving the simplicity of the verification device, and the verification device is also provided with a reflective substrate 600, which is configured to receive The infrared light emitted by the infrared light source is received, and the infrared light is emitted to the optical receiver in the first chip 310 and the optical receiver in the second chip, so as to facilitate the subsequent verification of the encoder by the controller. The controller is connected to the dual-head reader chip. The controller is configured to perform a first configuration on the pins of the first chip 310 and the second chip to obtain a first three-channel unit and a second three-channel unit, so as to adjust the signal parameters output by the first chip 310 and the second chip, and perform signal adjustment on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal, so as to obtain different types of control signals. The controller is configured to control the infrared light source to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual-head reader chip verifies the encoder according to the infrared light reflected by the reflective substrate 600. The mutual verification of the dual-head reader chips can improve the verification accuracy of the encoder.

[0065] It is worth noting that both the first chip 310 and the second chip are integrated with an infrared light source and a light receiver.

[0066] It should be noted that the reader 100 of the encoder of this embodiment is also provided with a positioning hole 520 and a fixing hole 510. The fixing hole 510 is arranged on the upper side of the positioning hole 520, and the fixing hole 510 and the positioning hole 520 are both arranged on the upper side of the dual reader chip, wherein the positioning hole 520 is configured to locate the position of the dual reader chip, and the fixing hole 510 is configured to fix the encoder to facilitate external physical fixation.

[0067] It is understandable that the number of fixing holes 510 and the number of positioning holes 520 can be set according to user needs. For example, one fixing hole 510 and one positioning hole 520 are respectively set on the left and right sides of the reader, or two fixing holes 510 and one positioning hole 520 are respectively set on the left and right sides of the reader, etc. This embodiment does not impose specific restrictions.

[0068] Please refer to FIG. 2 , which is a circuit diagram of a first control module 300 provided in an embodiment of the present disclosure;

[0069] It should be noted that the circuit schematic diagram of the second control module 400 is consistent with the circuit schematic diagram of the first control module 300 , and will not be described in detail in this embodiment.

[0070] Optionally, the first control module 300 includes a first adjustment unit 320, and the second control module 400 includes a second adjustment unit. The first adjustment unit 320 includes a first resistor module configured to amplify different signal multiples, and the second adjustment unit includes a second resistor module configured to amplify different signal multiples, thereby realizing the selection of the control signal multiple, being able to control the amplification multiple of the control signal, and broadening the application scenarios of the encoder.

[0071] It should be noted that the first control module 300 also includes a first filtering unit 330 and a second filtering unit 340, and the second control module 400 also includes a third filtering unit and a fourth filtering unit, wherein the first resistor module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, so as to be able to amplify different signal multiples, the first filtering unit 330 includes a first capacitor C1 and a second capacitor C2, and the second filtering unit includes a third capacitor C3 and a fourth capacitor C4, so as to be able to filter out the clutter and AC components of the power supply.

[0072] Optionally, the first resistor R1 and the fourth resistor R4 are connected in series to form a first branch, the second resistor R2 and the fifth resistor R5 are connected in series to form a second branch, the third resistor R3 and the sixth resistor R6 are connected in series to form a third branch, and the first branch, the second branch and the third branch are connected in parallel to each other, the connection between the first resistor R1 and the fourth resistor R4 is connected to the first pin of the first chip 310, the connection between the second resistor R2 and the fifth resistor R5 is connected to the second pin of the first chip 310, the connection between the third resistor R3 and the sixth resistor R6 is connected to the third pin of the first chip 310, the first capacitor C1 and the second capacitor C2 are connected in parallel, and the third capacitor C3 and the fourth capacitor C4 are connected in parallel.

[0073] It is worth noting that the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all filter capacitors that can filter out the noise and AC components of the power supply. Among them, the second adjustment unit includes a third filter unit and a fourth filter unit, the structure of the first resistor module is consistent with that of the second resistor module, and the structure of the third filter unit and the fourth filter unit is consistent with that of the first filter unit and the second filter unit. This implementation will not be repeated here.

[0074] It should be noted that the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are all the same. The two capacitors in the first filtering unit, the second filtering unit, the third filtering unit, and the fourth filtering unit select a large capacitance and a small capacitance for filtering, wherein the large capacitor is configured to filter low-frequency waves and the small capacitor is configured to filter high-frequency waves. The large capacitor can be a microfarad (μF) level capacitor and the small capacitor can be a nanofarad (nF) level capacitor.

[0075] Please refer to FIG. 3 , which is a schematic diagram of a framework of a calibration device for an encoder provided in an embodiment of the present disclosure.

[0076] Optionally, the calibration device further includes a sleeve 700 and a cover plate 800 . The sleeve 700 is disposed between the reflective substrate 600 and the cover plate 800 . The sleeve 700 is configured to fix the code disk 200 , thereby preventing the code disk 200 from being skewed and deformed.

[0077] It is understandable that the output signals of the first chip 310 and the second chip can be connected to most signal processing circuits to facilitate integration.

[0078] Please refer to Figure 4, which is a flow chart of the method for verifying an encoder provided by an embodiment of the present disclosure. Optionally, the verification method of this embodiment is applied to, but not limited to, a controller of a verification device for an encoder, and the verification method for the encoder includes but is not limited to steps S101 to S103.

[0079] Step S101, performing a first configuration on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit;

[0080] Step S102, performing signal conditioning on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal;

[0081] Step S103, controlling the infrared light source to emit infrared light according to the signal parameters of the first control signal and the signal parameters of the second control signal, so that the dual-head chip calibrates the encoder according to the infrared light reflected by the reflective substrate.

[0082] Optionally, in steps S101 to S103, in the process of verifying the encoder, first, the pins of the first chip 310 and the second chip are first configured to obtain a first three-channel unit corresponding to the first chip 310 and a second three-channel unit corresponding to the second chip, and then the first three-channel unit and the second three-channel unit are signal adjusted to adjust the signal multiples to output a first control signal and a second control signal, so as to control whether the first chip 310 and the second chip output analog or digital quantities, and finally, the infrared light source is controlled to emit infrared light according to the signal parameters of the first control signal and the signal parameters of the second control signal, so that the dual reader chips verify the encoder according to the infrared light reflected by the reflective substrate, thereby realizing mutual verification of the dual reader chips and improving the verification accuracy of the encoder.

[0083] It should be noted that the first control signal and the second control signal may be original analog signals or processed pulse signals. The correction process of the original analog signal and the pulse signal will be described below.

[0084] Please refer to Figure 5, which is a flow chart of step S101 provided in an embodiment of the present disclosure. Optionally, step S101 includes but is not limited to step S201 and step S203.

[0085] Step S201: Number the pins of the first chip and the second chip to obtain a first adjustment unit and a second adjustment unit;

[0086] Step S202: Divide the first adjustment unit and the second adjustment unit into multiples to obtain a plurality of first sub-intervals and a plurality of second sub-intervals;

[0087] It should be noted that the first subinterval is used to adjust the output signal multiple of the first adjustment unit, and the second subinterval is used to adjust the output signal multiple of the second adjustment unit.

[0088] Step S203 : generating a first three-channel unit according to the first adjustment unit, and generating a second three-channel unit according to the second adjustment unit.

[0089] Optionally, in steps S201 to S203, in the process of performing the first configuration on the pins of the first chip 310 and the second chip, it is necessary to first encode any three pins of the first chip 310 and the second chip to obtain a first adjustment unit and a second adjustment unit, and then divide the first adjustment unit and the second adjustment unit into multiples through resistors to obtain multiple first sub-intervals and multiple second sub-intervals to achieve adjustment of different output signal multiples, and finally generate a first three-channel unit according to the first adjustment unit, and generate a second three-channel unit according to the second adjustment unit to achieve the output of analog signals or digital signals.

[0090] It should be noted that the amplification factors of multiple first sub-intervals are different, and the amplification factors of multiple second sub-intervals are different. The amplification factor of the first sub-interval can be adjusted according to the first resistor module in the first adjustment unit, and the amplification factor of the second sub-interval can be adjusted according to the second resistor module in the second adjustment unit. For example, the first pin in Figure 2 is pulled up, and the second pin and the third pin are pulled down to constitute the first first sub-interval, the first pin and the second pin in Figure 2 are pulled up, and the third pin is pulled down to constitute the second first sub-interval, the first pin, the second pin and the third pin in Figure 2 are all pulled up to constitute the third first interval, and so on. The specific method of pulling up or pulling down is not specifically limited in this embodiment.

[0091] It can be understood that the manner of adjusting the output signal multiple in the second subinterval is the same as that in the first subinterval, and this embodiment will not elaborate on this.

[0092] It is worth noting that, in the process of verifying the encoder in this embodiment, verification can be performed by controlling the first chip 310 and the second chip to output analog signals or pulse signals respectively, which will be explained below.

[0093] Please refer to Figure 6, which is a flow chart of step S102 provided in an embodiment of the present disclosure. Optionally, step S102 includes but is not limited to step S301 and step S303.

[0094] Step S301, adjusting multiple pins of the first three-channel unit to output analog signals;

[0095] Step S302, performing interval selection on a plurality of second subintervals of the second three-channel unit, and outputting a first pulse signal;

[0096] Step S303: generating a first control signal according to the analog signal, and generating a second control signal according to the first pulse signal.

[0097] Optionally, in steps S301 to S303, multiple pins of the first three-channel unit are pulled up or pulled down to output an analog signal, and multiple second sub-intervals of the second three-channel unit are selected to control the pins to connect to different resistors, and the pins are pulled up or pulled down according to the subdivision multiples of the second sub-interval to output a first pulse signal, and then a first control signal is generated according to the analog signal, and a second control signal is generated according to the first pulse signal.

[0098] It should be noted that the first pulse signal output is a three-channel digital differential A, B and I output, so the first pulse signal is the ABI pulse after internal processing of the second chip, and the second chip outputs the ABZ signal.

[0099] It can be understood that, in the embodiment of FIG. 6 , the first chip 310 outputs an analog signal, and the second chip outputs a first pulse signal, which facilitates subsequent verification.

[0100] Please refer to Figure 7, which is a flow chart of step S102 provided in an embodiment of the present disclosure. Optionally, step S102 includes but is not limited to step S401 and step S403.

[0101] Step S401, performing interval selection on a plurality of first sub-intervals of a first three-channel unit, and outputting a second pulse signal;

[0102] Step S402, performing interval selection on a plurality of second subintervals of the second three-channel unit, and outputting a third pulse signal;

[0103] Step S403: Generate a first control signal according to the second pulse signal, and generate a second control signal according to the third pulse signal.

[0104] Optionally, in steps S401 to S403, interval selection is performed on multiple first sub-intervals of the first three-channel unit, so that the control pins are connected to different resistors, pulled up or pulled down according to the subdivision multiples of the first sub-interval, and a second pulse signal is output; and interval selection is performed on multiple second sub-intervals of the second three-channel unit, so that the control pins are connected to different resistors, pulled up or pulled down according to the subdivision multiples of the second sub-interval, and a third pulse signal is output; finally, a first control signal is generated based on the second pulse signal, and a second control signal is generated based on the third pulse signal.

[0105] It can be understood that, in the embodiment of FIG. 7 , the first chip 310 outputs the second pulse signal, and the second chip outputs the third pulse signal, which facilitates subsequent verification.

[0106] Please refer to Figure 8, which is a flow chart of step S103 provided in an embodiment of the present disclosure. Optionally, step S103 includes but is not limited to step S501 and step S504.

[0107] Step S501, when the first control signal is an analog signal and the second control signal is a first pulse signal, obtaining an analog value of the analog signal;

[0108] Step S502, controlling the infrared light source to emit infrared light, so that the second chip counts pulses in the first pulse signal according to the infrared light reflected by the reflective substrate to obtain a first pulse value;

[0109] Step S503: within a preset time interval, the simulation value and the first pulse value are compared with preset theoretical values ​​to determine a target value;

[0110] Step S504: Verify the encoder according to the target value.

[0111] Optionally, in steps S501 to S504, when the first control signal is an analog signal and the second control signal is a first pulse signal, the encoder is verified. First, it is necessary to obtain the analog value of the analog signal, and then control the infrared light source to emit infrared light. The infrared light is emitted to the second chip through the reflective substrate, so that the second chip counts the pulses in the first pulse signal according to the infrared light, that is, the number of A and B scanned is calculated to obtain the first pulse value. Finally, within a preset time interval, the analog value and the first pulse value are compared with the preset theoretical value, and the best one is selected. The data closest to the theoretical data is selected as the target value, and the encoder is verified according to the target value, thereby completing the verification process of the encoder.

[0112] It should be noted that after the infrared light is emitted from the chip, it is irradiated onto the reflective substrate through the code disk and reflected back into the chip. The code disk continues to rotate, and the chip reads the A and B numbers through the transparent and dark lines on the code disk to obtain the pulse value.

[0113] Please refer to Figure 9, which is a flow chart of step S103 provided in an embodiment of the present disclosure. Optionally, step S103 includes but is not limited to step S601 and step S604.

[0114] Step S601, when the first control signal is the second pulse signal and the second control signal is the third pulse signal, controlling the infrared light source to emit infrared light so that the first chip counts pulses in the second pulse signal to obtain a second pulse value;

[0115] Step S602, controlling the second chip to count pulses in the third pulse signal according to the infrared light reflected by the reflective substrate to obtain a third pulse value;

[0116] Step S603, comparing the second pulse value and the third pulse value within a preset time interval to obtain a target verification value;

[0117] Step S604: calibrate the encoder according to the target calibration value.

[0118] Optionally, in steps S601 to S604, when the first control signal is the second pulse signal and the second control signal is the third pulse signal, that is, when both the first chip 310 and the second chip output ABZ signals, the infrared light source is controlled to emit infrared light, and the infrared light is emitted to the second chip through the reflective substrate. The infrared light causes the first chip 310 to count the pulses in the second pulse signal to obtain a second pulse value, and the second chip is controlled to count the pulses in the third pulse signal according to the infrared light reflected by the reflective substrate to obtain a third pulse value. Within a preset time interval, the second pulse value and the third pulse value are compared, and the numbers of A and B counted in the two sets of data at the same time are compared to obtain a target verification value. The encoder is verified according to the target verification value, so that the A and B storage data in the first chip 310 and the second chip can be cleared each time Z is scanned to determine whether the code disk is clean. This ensures that even if the reading of a single chip is abnormal, normal counting can be guaranteed, thereby avoiding joint jitter of the code disk.

[0119] It should be noted that if the readings of the two chips are abnormal, calibration can also be performed within one circle.

[0120] An embodiment of the present disclosure further provides a computer device, including a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor is configured to execute the encoder verification method in the above embodiment of the present disclosure.

[0121] Refer to FIG. 10 , which is a schematic diagram of the hardware structure of a computer device provided in an embodiment of the present disclosure.

[0122] The hardware structure of the computer device is described in detail below with reference to Figure 10. The computer device includes: a processor 910, a memory 920, an input / output interface 930, a communication interface 940, and a bus 950.

[0123] The processor 910 may be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and executes relevant programs to implement the technical solutions provided by the embodiments of the present disclosure.

[0124] The memory 920 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 920 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 920 and is called by the processor 910 to execute the encoder verification method of the embodiment of the present disclosure.

[0125] Input / output interface 930, configured to implement information input and output;

[0126] Communication interface 940, configured to enable communication between the device and other devices, which may be achieved through wired means (e.g., USB, network cable, etc.) or wireless means (e.g., mobile network, WiFi, Bluetooth, etc.); and bus 950, which transmits information between various components of the device (e.g., processor 910, memory 920, input / output interface 930, and communication interface 940);

[0127] The processor 910 , the memory 920 , the input / output interface 930 , and the communication interface 940 are connected to each other in communication within the device via a bus 950 .

[0128] An embodiment of the present disclosure further provides a storage medium, which is a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a computer, the computer is configured to execute the verification method of the encoder in the above embodiment of the present disclosure.

[0129] The memory, as a non-transient computer-readable storage medium, can be configured to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely located relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0130] The embodiments described in the embodiments of the present disclosure are intended to more clearly illustrate the technical solutions of the embodiments of the present disclosure and do not constitute a limitation on the technical solutions provided by the embodiments of the present disclosure. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present disclosure are also applicable to similar technical problems.

[0131] Those skilled in the art will understand that the technical solutions shown in Figures 4 to 8 do not constitute a limitation on the embodiments of the present disclosure, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0132] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0133] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0134] The terms "first," "second," "third," "fourth," and the like (if any) in the specification of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the present disclosure described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0135] It should be understood that in the present disclosure, "at least one (item)" refers to one or more, and "plurality" refers to two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0136] In the embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0137] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0138] In addition, the functional units in the embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0139] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0140] The preferred embodiments of the present disclosure are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present disclosure. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present disclosure should be within the scope of the present disclosure. Industrial Applicability

[0141] The encoder verification device, verification method and storage medium provided by the present disclosure can improve the accuracy of encoder verification through mutual verification of dual reader chips.

Claims

1. A calibration device for an encoder, characterized in that: The encoder includes a reader and a code disc, wherein the code disc is arranged on the reader, and the verification device includes: A dual-head reader chip is provided at the reader, the dual-head reader chip comprises a first control module and a second control module, the first control module comprises a first chip, the second control module comprises a second chip, and a light detection device is provided on the first chip and the second chip, wherein the light detection device comprises an infrared light source and a light receiver, the infrared light source is configured to generate infrared light, and the light receiver is configured to receive reflected infrared light; A reflective substrate, disposed on the code disc, wherein the reflective substrate is configured to reflect the received infrared light; a controller connected to the dual-head chip, the controller being configured to perform a first configuration on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit, and perform signal conditioning on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal; The controller is configured to control the infrared light source to emit infrared light according to signal parameters of the first control signal and the second control signal, so that the dual reader chip verifies the encoder according to the infrared light reflected by the reflective substrate.

2. The encoder verification device according to claim 1, characterized in that: The first control module includes a first regulating unit, and the second control module includes a second regulating unit. The first regulating unit includes a first resistor module configured to amplify different signal multiples, and the second regulating unit includes a second resistor module configured to amplify different signal multiples.

3. The encoder calibration device according to claim 1-2, characterized in that: It also includes a sleeve and a cover plate, wherein the sleeve is arranged between the reflective substrate and the cover plate, and the sleeve is configured to fix the code disc.

4. The encoder verification device according to claim 2-3, characterized in that: The first control module further includes a first filter unit and a second filter unit, and the first filter unit and the second filter unit are both configured to filter out clutter and AC components.

5. The encoder verification device according to claim 2-4, characterized in that: The second control module further includes a third filter unit and a fourth filter unit, and the third filter unit and the fourth filter unit are both configured to filter out clutter and AC components.

6. The encoder calibration device according to claims 1-5, characterized in that: The reader is also provided with a positioning hole and a fixing hole, the fixing hole is arranged on the upper side of the positioning hole, and the fixing hole and the positioning hole are both arranged on the upper side of the dual reader chip; the positioning hole is configured to locate the position of the dual reader chip, and the fixing hole is configured to fix the verification device.

7. A method for checking an encoder, characterized in that: A calibration device applied to an encoder, the encoder comprising a reader and a code disk, the code disk being arranged on the reader, the calibration device comprising: A dual-head reader chip is provided on the reader, and the dual-head reader chip includes a first control module and a second A control module, wherein the first control module includes a first chip, the second control module includes a second chip, and the first chip and the second chip are both provided with a light detection device, wherein the light detection device includes an infrared light source and a light receiver; A reflective substrate, disposed on the code disc; The method comprises: Performing a first configuration on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit; Performing signal conditioning on the first three-channel unit and the second three-channel unit to output a first control signal and a second control signal; The infrared light source is controlled to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual reader chip verifies the encoder according to the infrared light reflected by the reflective substrate.

8. The encoder calibration method according to claim 7, characterized in that: The first configuration is performed on the pins of the first chip and the second chip to obtain a first three-channel unit and a second three-channel unit, including: Numbering the pins of the first chip and the second chip to obtain a first adjustment unit and a second adjustment unit; Dividing the first regulating unit and the second regulating unit by multiples to obtain a plurality of first sub-intervals and a plurality of second sub-intervals, wherein the first sub-interval is used to adjust the multiple of the output signal of the first regulating unit, and the second sub-interval is used to adjust the multiple of the output signal of the second regulating unit; The first three-channel unit is generated according to the first adjustment unit, and the second three-channel unit is generated according to the second adjustment unit.

9. The encoder verification method according to claim 8, characterized in that: The step of performing signal conditioning on the first three-channel unit and the second three-channel unit and outputting a first control signal and a second control signal comprises: Adjusting a plurality of pins of the first three-channel unit to output analog signals; Performing interval selection on a plurality of second sub-intervals of the second three-channel unit, and outputting a first pulse signal; The first control signal is generated according to the analog signal, and the second control signal is generated according to the first pulse signal.

10. The encoder calibration method according to claim 8-9, characterized in that: The step of performing signal conditioning on the first three-channel unit and the second three-channel unit and outputting a first control signal and a second control signal comprises: Performing interval selection on a plurality of first sub-intervals of the first three-channel unit, and outputting a second pulse signal; Performing interval selection on a plurality of second sub-intervals of the second three-channel unit, and outputting a third pulse signal; The first control signal is generated according to the second pulse signal, and the second control signal is generated according to the third pulse signal.

11. The encoder calibration method according to claims 9-10, characterized in that: The step of controlling the infrared light source to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual-head reader chip verifies the encoder according to the infrared light reflected by the reflective substrate, includes: When the first control signal is an analog signal and the second control signal is a first pulse signal, acquiring an analog value of the analog signal; Controlling the infrared light source to emit infrared light, so that the second chip counts pulses in the first pulse signal according to the infrared light reflected by the reflective substrate to obtain a first pulse value; Within a preset time interval, the simulation value and the first pulse value are compared with preset theoretical values ​​to determine a target value; The encoder is calibrated according to the target value.

12. The encoder calibration method according to claim 10-11, characterized in that: The step of controlling the infrared light source to emit infrared light according to the signal parameters of the first control signal and the second control signal, so that the dual-head reader chip verifies the encoder according to the infrared light reflected by the reflective substrate, includes: When the first control signal is a second pulse signal and the second control signal is a third pulse signal, the infrared light source is controlled to emit infrared light, so that the first chip counts the pulses in the second pulse signal to obtain a second pulse value; controlling the second chip to count pulses in the third pulse signal according to the infrared light reflected by the reflective substrate to obtain a third pulse value; Within a preset time interval, comparing the second pulse value and the third pulse value to obtain a target verification value; The encoder is verified according to the target verification value.

13. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, and when the computer program is executed by a computer, the computer is configured to execute the verification method of the encoder as described in any one of claims 7 to 12.

Images