Memory controller, information processing device, and method for processing access to secondary storage device

Abstract

In a standby state of this information processing device 10, a sub CPU 38 stores data downloaded from a server 50 into a flash memory 30 by using a logical address shared with a main CPU 20. The main CPU 20 reads the data which is stored in the flash memory 30 by the sub CPU 38 during a startup process of the information processing device 10, and displays the read data on a display device before completion of the startup process.

Description

MEMORY CONTROLLER, INFORMATION PROCESSING DEVICE, AND METHOD FOR PROCESSING ACCESS TO SECONDARY STORAGE DEVICE - Patent application

[0001] The present invention relates to a memory controller that accesses a secondary storage device, an information processing device, and a method for processing access to a secondary storage device.

[0002] Information processing devices such as personal computers and game devices are now constantly connected to networks, making it possible to send and receive necessary information to and from servers at any time. For example, Cited Document 1 discloses a technology in which, even in a standby state where the main power supply is turned off, a sub-CPU operates to send information in response to a request from the server or download necessary data from the server.

[0003] Japanese Patent Application Laid-Open No. 2013-257717

[0004] Generally, when a user turns on the main power of an information processing device, the BIOS (Basic Input Output System) and OS (Operating System) start up, and various devices are initialized, system services are started, network authentication is performed, and the device becomes ready for use. During this time, the information processing device is dedicated to these startup processes, so even if new data is downloaded in standby mode, it takes time before processing using that data can begin. Furthermore, the wait time until the startup process is complete can be stressful for users.

[0005] The present invention has been made in view of these problems, and its object is to provide a technique for improving the efficiency of the startup and subsequent processing of an information processing device. Another object of the present invention is to reduce the stress on users caused by the waiting time when starting up an information processing device.

[0006] One aspect of the present invention relates to a memory controller that receives access requests to a secondary storage device from a main CPU and a sub-CPU included in an information processing device and executes the corresponding access processing, and is characterized in that the memory controller generates a logical address space for the sub-CPU, maps the logical address space for the sub-CPU onto the logical address space for the main CPU, and executes the access processing to the secondary storage device based on the logical addresses specified in each logical address space in the access request.

[0007] Another aspect of the present invention relates to an information processing device including the memory controller described above, a main CPU, and a sub-CPU, wherein the main CPU displays, on a display device during the startup process of the information processing device, an image stored in the secondary storage device by the sub-CPU while the main CPU is in a standby state, as a startup image.

[0008] Yet another aspect of the present invention relates to a method for processing access to a secondary storage device, the method for processing access to a secondary storage device comprising the steps of: generating a logical address space for the sub-CPU, which is a logical address space that enables a main CPU and a sub-CPU to access the secondary storage device, and mapping the logical address space for the sub-CPU to the logical address space for the main CPU; receiving, from the main CPU and the sub-CPU, access requests for a common storage area, each specifying a logical address in each logical address space; and executing access processing to the secondary storage device based on the specified logical address in the access request.

[0009] Any combination of the above components, and any transformation of the present invention into a method, device, system, computer program, or recording medium on which a computer program is recorded, are also valid aspects of the present invention.

[0010] According to the present invention, it is possible to improve the efficiency of the startup and subsequent processing of the information processing device, and also to reduce the stress of the user caused by the waiting time when the information processing device is started up.

[0011] 5 is a diagram showing the internal configuration of an information processing device in the present embodiment; FIG. 6 is a diagram showing a schematic diagram of the relationship between a logical address space created in the present embodiment and a storage area in a flash memory; FIG. 7 is a flowchart showing the procedure of a startup process of a general information processing device; FIG. 8 is a flowchart showing an example of the procedure of a process performed by the information processing device in the present embodiment in a standby state; FIG. 9 is a flowchart showing an example of the procedure of a startup process of the information processing device in the present embodiment; and FIG. 10 is a flowchart showing the procedure of a process in which the main CPU displays a startup image in S68 of FIG.

[0012] 1 shows the internal configuration of an information processing device according to this embodiment. The information processing device exemplified here may be any of general information devices such as a portable game console, a personal computer, a mobile phone, a tablet terminal, a PDA, etc. While the diagram illustrates the configuration required for this embodiment, it is not intended to limit the configuration of the information processing device to this.

[0013] The information processing device 10 has a main CPU (Central Processing Unit) 20 that operates when the main power supply is on, and a sub-CPU 38 that operates when the main power supply is off. When a user turns on the main power supply, the main CPU 20 starts up and the sub-CPU 38 goes into a standby state. When the main power supply is turned off, the sub-CPU 38 starts up and the main CPU 20 goes into a standby state. Hereinafter, switching the main power supply from off to on may be referred to as "starting up the information processing device," the state in which the main power supply is on may be referred to as "startup state of the information processing device," and the state in which the main power supply is off may be referred to as "standby state of the information processing device."

[0014] In addition to the main CPU 20 and sub-CPU 38, the information processing device 10 includes a NAND flash memory 30 (hereinafter simply referred to as flash memory 30), a flash controller 32, a main memory 12, a memory controller 14 for the main memory 12, a display controller 16, a GPU 22, a flash memory 24 for a boot image, IO controllers 40a and 40b, a sub-memory 34, a memory controller 36 for the sub-memory 34, a network controller 42, a system controller 44, and a wireless module 46. These components send and receive signals to and from each other via a bus 18.

[0015] When the information processing device 10 enters standby mode, power supply to the main CPU 20, the memory controller 14 for the main memory 12, the display controller 16, the GPU 22, and the LSI (Large Scale Integration) including the IO controller 40a are cut off, and the device enters a power-saving mode. When the information processing device 10 starts up, power is supplied to the LSI. The main CPU 20 then loads programs and data stored in the flash memory 30 into the main memory 12 and uses them to process information. If necessary, the main CPU 20 downloads data from the server 50 via the network 52 and stores it in the flash memory 30.

[0016] The flash memory 30 is a secondary storage device configured with a NAND flash memory, and stores various programs and data. This data may include data read from a recording medium driven by a recording medium drive unit (not shown) or data downloaded from the server 50. The flash controller 32 receives access requests to the flash memory 30 from the main CPU 20 or the sub-CPU 38, and writes or reads data accordingly.

[0017] For example, the main CPU 20 generates an access request specifying a logical address (LBA: Logical Block Address) of the access destination in the flash memory 30 and stores it in the main memory 12. The flash controller 32 reads the access request stored in the main memory 12 and converts the specified logical address into a physical address in the flash memory 30. For this reason, the flash controller 32 holds at least a portion of an address conversion table that converts logical addresses into physical addresses in its internal memory. The flash controller 32 reads or writes data requested by the main CPU 20 by accessing the corresponding area in the flash memory 30 based on the physical address obtained from the address conversion table.

[0018] The flash controller 32 also creates a logical address space for the sub-CPU 38 in response to a request from the main CPU 20. This allows the sub-CPU 38 to share a predetermined area in the flash memory 30 with the main CPU 20 without using the file system of the main CPU 20. Details will be explained later. The flash controller 32, together with the flash memory 30, may be a device independent of the information processing device 10.

[0019] The main memory 12 is a primary storage device such as a RAM (Random Access Memory) into which data is expanded in order for the main CPU 20 to perform various processes. The memory controller 14 receives access requests to the main memory 12 from the main CPU 20 and executes the access processing accordingly. The GPU 22 draws display images under the control of the main CPU 20 and stores the data in a frame buffer provided in the main memory 12.

[0020] The display controller 16 reads display image data from the frame buffer and outputs it to the display device sequentially at appropriate timing to display still images and moving images. The IO controllers 40a and 40b control I / O devices and their interfaces. The boot image flash memory 24 is an external flash memory that stores a boot loader and a BIOS image required to start the information processing device 10.

[0021] The wireless module 46 wirelessly communicates with an input device 54 such as a game controller and a Wi-Fi router (not shown) using a communication protocol such as Bluetooth (registered trademark) or IEEE802.11. This allows the information processing device 10 to establish communication with the server 50 via a network 52 such as the Internet. However, the connection between the information processing device 10 and the input device 54 or the network 52 is not limited to wireless communication. The network controller 42 controls communication with the input device 54 and the server 50 in response to requests from the main CPU 20 or the sub-CPU 38.

[0022] The system controller 44 controls basic system operations such as power management, interrupt requests, and the system clock. For example, the system controller 44 detects the user's operation to turn the main power supply on or off. In the example shown, the means for the on / off operation is assigned to the input device 54, and the system controller 44 acquires the operation details via the wireless module 46. However, the path of the operation information is not limited to this, and the system controller 44 may also detect, for example, an operation on a power button (not shown).

[0023] When the system controller 44 detects that the main power supply is turned on, it puts the operating sub-CPU 38 into a standby state and starts up the main CPU 20. On the other hand, when it detects that the main power supply is turned off, it puts the operating main CPU 20 into a standby state and starts up the sub-CPU 38.

[0024] At this time, as described above, the system controller 44 cuts off the power supply to the LSI including the main CPU 20. The flash controller 32 is also basically in a standby state. Just before this, the main CPU 20 saves the data in the main memory 12 to the flash memory 30. This makes it possible to read the saved data into the main memory 12 and resume processing the next time the main CPU 20 is started. The main CPU 20 also stores session information between it and the server 50 in the flash memory 30.

[0025] When the information processing device 10 is in standby mode, the sub-CPU 38 loads programs and data stored in the flash memory 30 into the sub-memory 34 and uses them to process information. The sub-memory 34 is a primary storage device, such as a random access memory (RAM), into which the sub-CPU 38 expands data for various processes. The memory controller 36 receives access requests for the sub-memory 34 from the sub-CPU 38 and executes the corresponding access processing. The sub-CPU 38 reads session information stored in the flash memory 30 by the main CPU 20 into the sub-memory 34 and takes over the connection, thereby periodically accessing the server 50.

[0026] As a result of the sub-CPU 38 accessing the server 50, it may detect the presence of data that should be presented to the user. Examples of such data include update information for previously purchased application programs, messages from other users who have registered as friends, still image and video data shared with other users, and information on new arrivals and campaigns from companies. In recent years, such information has been transmitted regardless of time or place, and the volume of such information is steadily increasing.

[0027] The information processing device 10, even in standby mode, downloads this data as needed to streamline processing in the active mode. Hereinafter, this information that is generated and provided over time will be referred to as "dynamic content," while pre-created, unchanging information such as images will be referred to as "static content." When the server 50 detects the presence of dynamic content, the sub-CPU 38 downloads the data and stores it in the flash memory 30. At this time, the sub-CPU 38 cancels the standby mode of the flash controller 32 and requests that the data be written to the flash memory 30.

[0028] This data is basically processed by the main CPU 20 when the information processing device 10 is started up or in an active state. Meanwhile, the main CPU 20 manages the data stored in the flash memory 30 using its own file system. Therefore, a complicated procedure is required for the sub-CPU 38 to be able to share a storage area with the main CPU 20. If easy sharing were permitted, security problems such as data tampering through impersonation could arise.

[0029] Therefore, the flash controller 32 of this embodiment creates a logical address space for the sub-CPU 38, allowing the sub-CPU 38 to access the same storage area as the main CPU 20 in a unique format. Figure 2 schematically shows the relationship between the logical address space created in this embodiment and the storage areas in the flash memory 30. From the left end of the figure, there are shown a logical address space 100 for the main CPU 20, a logical address space 102 for the sub-CPU 38, an address conversion table 104, and a storage area in the flash memory 30.

[0030] As described above, the flash controller 32 converts logical addresses specified by the main CPU 20 into physical addresses based on the address conversion table 104. In this embodiment, a range of logical addresses that can be specified by the sub CPU 38 is provided, so that logical addresses within that range can also be converted into physical addresses. This logical address range corresponds to the logical address space 102 for the sub CPU 38. The address conversion table 104 includes a data area 110 that converts logical addresses for the sub CPU 38 into physical addresses.

[0031] This allows the sub-CPU 38 to access the flash memory 30 using a logical address within the range of the logical address space 102. For example, the sub-CPU 38 issues a data write request by specifying logical address 112 within the logical address space 102, and stores this together with the data to be written in the sub-memory 34. The flash controller 32 reads this, converts the logical address into a physical address by referring to the address conversion table 104, and writes the data to the corresponding area in the flash memory 30 (arrows a1 and a2).

[0032] In the figure, the flash memory 30 has four channels, "ch0" to "ch3," and data is stored in a distributed manner. However, the number of channels of the flash memory 30 is not limited. Similarly, the main CPU 20 also realizes access to the flash memory 30 using logical addresses within the range of the logical address space 100 for the main CPU 20.

[0033] For example, the main CPU 20 issues a data write request by specifying logical address 114 in the logical address space 100, and stores it together with the data to be written in the main memory 12. The flash controller 32 reads it, converts the logical address into a physical address by referring to the address conversion table 104, and writes the data to the corresponding area in the flash memory 30 (arrows b1 and b2).

[0034] Here, the logical address space 100 for the main CPU 20 includes a logical address area 106 that can only be used by the main CPU 20, as well as a logical address area 108 that can be used by the sub CPU 38. The logical address area 108 is a mapping of the logical address space 102 for the sub CPU 38. This allows the main CPU 20 to access the flash memory 30 by specifying a logical address that can be specified by the sub CPU 112 (for example, logical address 112).

[0035] The main CPU 20 writes information to be handed over to the sub-CPU 38, such as session information with the server 50, to the flash memory 30 using the logical address in area 108. This allows the sub-CPU 38 to read the information using the same logical address. The sub-CPU 38 also writes data downloaded from the server 50 to the flash memory 30 using the logical address in its own logical address space 102. This allows the main CPU 20 to read the data using the same logical address.

[0036] In this way, the sub-CPU 38 can access the flash memory 30 in its own format without having to construct a file system for a given logical address space. For example, the sub-CPU 38 can store data downloaded from the server 50 in sequential logical addresses. Meanwhile, the main CPU 20 can reconstruct the file system through the startup process of the information processing device 10, and then access the data stored in the flash memory 30 by the sub-CPU 38.

[0037] When the information processing device 10 is started up, the main CPU 20 requests the flash controller 32 to create a logical address space 102 for the sub-CPU 38. At that time, the flash controller 32 invalidates the original logical addresses in the logical address area 106 that can only be used by the main CPU 20, by the amount of the logical address frame to be assigned to the sub-CPU 38. In other words, a portion of the logical address area 116 is invalidated so that the storage capacity indicated by the logical addresses does not change before and after the addition of the logical address area 108 that the sub-CPU 38 can use.

[0038] This prevents the use of logical addresses exceeding the capacity of the flash memory 30. Note that invalidating a logical address may be achieved by writing dummy data to the target logical address area to reserve it. The address space configuration shown in the figure allows easy and safe data transfer between the main CPU 20 and the sub-CPU 38. Furthermore, the logical address area 108 available to the sub-CPU 38 does not need to go through a file system, so it can be accessed directly without waiting for the system module to start up. Therefore, data stored in the flash memory 30 in the standby state can be read and processed at an early stage during the startup process of the information processing device 10.

[0039] For example, the main CPU 20 can display still images or videos showing dynamic content downloaded in standby mode or generated by the sub-CPU 38 in parallel with the startup process of the information processing device 10. This aspect will be described below. First, to clarify the effects of this embodiment, the startup process of a general information processing device will be outlined.

[0040] 3 is a flowchart showing the startup procedure of a typical information processing device. First, when a user turns on the main power supply, the system controller 44 detects this and power is supplied to the LSI including the main CPU 20 (S10). The main CPU 20 then reads the boot loader and BIOS image from the external flash memory 24 (S12) and starts the BIOS (S14).

[0041] When the BIOS is started, the main CPU 20 initializes the IO controllers 40a, 40b, the display controller 16, the memory controller 14, and the flash controller 32 (S16), and then displays an image for BIOS startup on the display device via the display controller 16 (S18). In this state, the main CPU 22 reads a kernel image, which is part of the OS, from the flash memory 30, expands it into the main memory 12 (S20), and starts the kernel, transferring control to the OS (S22).

[0042] Here, the main CPU 20 reinitializes the devices using the kernel to restore the operating speed to its original state (S24). Next, the main CPU 20 reads images for startup, such as the OS logotype, from the flash memory 30, writes them to the main memory 12 (S26), and displays them on the display device via the display controller 16 (S28). Next, the main CPU 22 reads various system modules from the flash memory 30, loads them into the main memory 12, and starts them up (S30).

[0043] If the status information of the information processing device 10 was saved from the main memory 12 to the flash memory 30 when the device previously entered the standby state, the main CPU 20 reads the saved data from the flash memory 30 and restores it to the main memory 12. When the initialization of the system module is complete, the main CPU 20 displays a login screen for the system via the display controller 16 (S32). When the user enters information on the login screen, the main CPU 20 performs login processing by transmitting login information to the server 50 via the network controller 42 and the network 52 (S34).

[0044] If dynamic content intended for the logged-in user exists on the server 50, the main CPU 20 downloads the data of that content via the network 52 and the network controller 42 and writes it to the main memory 12 (S36). The main CPU 20 then creates an initial menu screen using the data written to the main memory 12 (S38) and displays it on the display device via the display controller 16 (S40). This completes the startup process, allowing the user to perform desired operations such as checking the dynamic content.

[0045] Generally, the startup process shown in the figure takes several seconds or more. Until the initialization of the system module is completed in S30, the images that can be displayed are limited to static content, such as logotypes that were originally stored in flash memory 30. In the illustrated processing procedure, after the system module is started and login to server 50 is performed, dynamic content is downloaded. Therefore, the content will be displayed after that, and static content will continue to be displayed during that time.

[0046] 4 is a flowchart showing an example of the procedure of processing performed by the information processing device 10 of this embodiment in the standby state. First, when the user turns off the main power, the system controller 44 detects this and the sub-CPU 38 starts operating (S50). At this time, as described above, the power supply to the LSI including the main CPU 20 is cut off, and the entire information processing device 10 enters the power saving mode.

[0047] The sub-CPU 38 first reads the boot loader, BIOS image, and kernel image from the flash memories 24 and 30 and stores them in the sub-memory 34 (S52). This eliminates the need for the main CPU to access the flash memories 24 and 30 to read this data when the information processing device 10 is started. The sub-CPU 38 also reads information necessary for communication with the server 50, such as session information stored in the flash memory 30 by the main CPU 20, stores this information in the sub-memory 34, and uses this information to periodically access the server 50. This allows the sub-CPU 38 to repeatedly check whether dynamic content intended for the user exists on the server 50 (Y in S54, S56).

[0048] If dynamic content is detected (Y in S56), the sub-CPU 38 downloads the data of the content via the network 52 and the network controller 42 and writes it to the flash memory 30 (S58). The sub-CPU 38 further generates a startup image that indicates the presence of the dynamic content or the dynamic content itself and writes it to the flash memory 30 (S59). At this time, the GPU 22 is not operating, but because it is in a standby state, there are few time constraints and the sub-CPU 38 can take its own time to generate the startup image.

[0049] The startup image may be generated by the sub-CPU 38 itself, or may be data generated and downloaded by the server 50 or the like. In this case, the process of S59 can be omitted. If no dynamic content is present on the server 50 in S56 (N in S56), or after the dynamic content is downloaded and a startup image is generated as appropriate (Y in S56, S58, S59), the sub-CPU 38 will appropriately repeat the processes of S56, S58, and S59 during the period in which the system controller 44 does not detect that the main power has been turned on (Y in S54).

[0050] When the system controller 44 detects that the user has turned on the main power, the information processing device 10 ends the standby state processing (N in S54). Note that the timing for ending the standby state processing is not limited to that shown in the figure. For example, the information processing device 10 may interrupt the illustrated processing at any time when the main power is turned on, even if it is in the middle of a processing step such as S58 or S59, and proceed to the startup processing shown in FIG. 5.

[0051] The data downloaded from the server 50 in S58 may include sensitive data such as the user's personal information. In this case, the sub-CPU 38 performs signature encryption on the data, such as the startup image created by reconstructing the downloaded image, as necessary, and stores it in the flash memory 30. This allows data to be securely exchanged with the main CPU 20 via the flash memory 30.

[0052] 5 is a flowchart showing an example of the startup process of information processing device 10 according to this embodiment. First, when the user turns on the main power supply, system controller 44 detects this and supplies power to the LSI including main CPU 20 (S60). Next, main CPU 20 reads the boot loader and BIOS image that were loaded into sub-memory 34 in S52 of FIG. 4 (S62) and starts the BIOS (S64). This enables high-speed startup without accessing external flash memory 24.

[0053] Upon booting the BIOS, the main CPU 20 initializes the IO controllers 40a and 40b, the display controller 16, the memory controller 14, and the flash controller 32 (S66). The main CPU 20 then loads the generated and downloaded boot image from the flash memory 30 into the main memory 12, and displays it on the display device via the display controller 16 (S68). By using the address conversion mechanism described above, the sub-CPU 38 stores the boot image data in the flash memory 30, allowing the main CPU 20 to treat the data in the same way as a BIOS boot image, and thus enabling images related to dynamic content to be displayed without waiting for the OS to boot.

[0054] In parallel with the display process of the startup image, the main CPU 22 reads the kernel image expanded in the sub-memory 34 in S52 of Fig. 4 and starts it, thereby transferring control to the OS (S70). The main CPU 20 then re-initializes the devices using the kernel (S71). Next, the main CPU 22 reads the system module, which is part of the kernel, from the sub-memory 34 and starts it (S72).

[0055] In this embodiment as well, if the status information and the like of the information processing device 10 was saved to the flash memory 30 when the device previously transitioned to the standby state, the main CPU 20 may read the saved data from the flash memory 30 and restore it to the main memory 12. The main CPU 20 then uses the session information and the like stored in the sub-memory 34 to perform a login process with the server 50 via the network controller 42 or the network 52 (S74). The main CPU 20 then creates an initial menu screen using the data and the like written to the main memory 12 (S76).

[0056] Next, the main CPU 20 ends the startup image display process of S68 and begins displaying the menu screen (S78). This completes the startup process, allowing the user to perform desired operations. According to the illustrated processing procedure, startup images related to dynamic content can be displayed during the period in which the BIOS startup image and the OS startup image are displayed in the typical startup process shown in FIG. 3. This allows the user to view and enjoy various content even during startup. Therefore, when the menu screen is displayed in S78, at least a portion of the dynamic content has already been viewed, improving subsequent work efficiency.

[0057] The startup image may be an advertising video targeted at users of the information processing device 10. As described above, it takes several seconds to several tens of seconds for the startup process of the entire information processing device 10 to be completed after the BIOS has started, so a short advertising video can be displayed during that time. Since the amount of time for which the startup image can be displayed varies depending on the information processing device 10, the server 50 or the sub-CPU 38 selects advertising video with an optimal playback time for the information processing device 10 and makes it the subject of download.

[0058] For example, the sub-CPU 38 selects and downloads one advertising video whose playback time is closest to the time required for the startup process in which the startup image can be displayed. Alternatively, the sub-CPU 38 may select and download multiple advertising videos whose total playback time falls within the time required for the startup image to be displayed. By displaying advertising videos in areas of interest to the user during the startup process, the user can reduce the stress they feel while waiting. This naturally increases attention, thereby improving the effectiveness of the advertising. However, the content selected to match the time required for the startup image to be displayed is not limited to advertising videos, and may also include videos shared by other users.

[0059] 6 is a flowchart showing the procedure for the main CPU 20 to display the startup image in S68 of Fig. 5. First, the main CPU 20 reads out the startup image data from the flash memory 30 (S100). As described above, this data is downloaded by the sub-CPU 38 from the server 50 while the information processing device 10 is in standby mode, or is generated by the sub-CPU 38 itself by reconstructing a downloaded image.

[0060] If the read is successful (Y in S102), the main CPU 20 decodes and expands the data if it is moving image data and stores it in the main memory 12 (Y in S104, S106). If the read data is a still image (N in S104), the process of S106 is skipped. In either case, the main CPU 20 writes the read startup image data to the frame buffer of the main memory 12 and displays it on the display device via the display controller 16 (S108).

[0061] 5, the main CPU 20 continues to display the startup image until the creation of the menu screen is complete (Y at S110). At this time, the main CPU 20 accepts a user operation to display a different startup image, such as turning the page. For example, the initial startup image could indicate that dynamic content is being downloaded, such as "You've received a message from your friend Tanaka," and when the user selects that image, an image showing the specific content could be displayed.

[0062] Alternatively, when multiple types of dynamic content are acquired, the user may select one of the displayed content images to transition to the next content image. If such a user operation is performed (Y at S112), the main CPU 20 reads data for another startup image determined by the user operation from the flash memory 30 (S100) and repeats the processes of S102 to S108. If no user operation is performed (N at S112), the main CPU 20 continues decoding and decompressing the currently displayed moving image as necessary, and continues displaying it (S104 to S108).

[0063] If the data read in S100 is unsuccessful (N in S102), for example, because the data for the startup image to be displayed does not exist in flash memory 30 or because the undisplayed startup images have been exhausted, the main CPU 20 reads the startup image data for the BIOS (or OS) from flash memory 30 and displays it (S114). In this case, too, the main CPU 20 continues to display the startup image for the BIOS, etc., until the startup process up to the creation of the menu screen shown in S76 of Fig. 5 is completed (N in S116, S114).

[0064] When the startup process is complete, the main CPU 20 ends the display of the startup image displayed in S108 or the startup image of the BIOS or the like displayed in S114 (N in S110, Y in S116), thereby switching the display from the startup image to the menu screen, as shown in S78 of FIG.

[0065] 4 to 6, the main CPU 20 immediately displays the startup image downloaded or generated by the sub-CPU 38 after the BIOS starts, thereby making effective use of the user's waiting time. Meanwhile, the data supplied from the sub-CPU 38 to the main CPU 20 using the address conversion mechanism shown in Fig. 2 is not limited to images. For example, this mechanism is also effective when the main CPU 20 uses application patch files downloaded by the sub-CPU 38 or additional content data.

[0066] In a typical information processing device, when downloading from the server 50 becomes necessary while the device is in standby mode, the system controller 44 activates the main CPU 20. In response, the main CPU 20 activates a kernel, accesses the server 50, and executes the download. Once the download is complete, the sub-CPU 38 activates, and the main CPU 20 transitions to standby mode. According to this embodiment, the sub-CPU 38 completes the download without going through these complicated procedures. Furthermore, when the information processing device 10 is started, the main CPU 20 can read the downloaded data from the flash memory 30 immediately after starting the BIOS, and perform any available processing or prepare for any processing that will become available thereafter.

[0067] If the user turns on the main power of the information processing device 10 while the sub-CPU 38 is downloading data, the sub-CPU 38 may store various information necessary for resuming the download in the flash memory 30 along with the data being downloaded. The information necessary for resuming the download may include, for example, at least one of the IP address of the server, a session number specified by a communication protocol such as TCP (Transmission Control Protocol), a sequence number, and a session key obtained during authentication with the server. This allows the main CPU 20 to resume the download interrupted by the sub-CPU 38 from where it left off after starting the kernel.

[0068] According to the present embodiment described above, the flash controller provides a logical address space for each of the main CPU and the sub-CPU, which allows access to the flash memory. Here, the address space of the main CPU includes a logical address area that can only be used by the main CPU and a logical address area that can be used by the sub-CPU. By providing a common address space for both CPUs in this way, the sub-CPU can share the limited storage area of ​​the flash memory with the main CPU without having the same file system as the main CPU.

[0069] By utilizing this logical address space, when the information processing device is in standby mode, the sub-CPU stores dynamic content downloaded from the server in flash memory. This allows the main CPU to read the data and perform any available processing before starting the OS when the information processing device starts up. As a result, it is possible to prevent the accumulation of processing that needs to be performed after the main CPU completes startup processing, which can lead to prolonged user waiting times and reduced processing speeds.

[0070] The main CPU can also display images downloaded or generated by the sub-CPU, such as application update information, user notifications, still images and videos shared by other users, and advertisements, in parallel with the OS startup process. This allows users who have started up the information processing device to enjoy images and obtain necessary information while waiting for the information processing device to become ready for use. Displaying advertisements during this waiting time can also increase attention and improve advertising effectiveness.

[0071] The present invention has been described above based on the embodiments. The above embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and treatment processes, and that such modifications are also within the scope of the present invention.

[0072] As described above, the present invention can be used in memory controllers and information processing devices such as personal computers and game devices that incorporate such memory controllers.

[0073] REFERENCE SIGNS LIST 10 information processing device, 12 main memory, 20 main CPU, 30 flash memory, 32 flash controller, 34 sub-memory, 36 memory controller, 38 sub-CPU, 42 network controller, 44 system controller, 50 server, 52 network, 54 input device.

Claims

1. A memory controller that receives access requests to a secondary storage device from a main CPU and a sub-CPU equipped in an information processing device and executes the corresponding access processing, wherein the memory controller generates a logical address space for the sub-CPU and maps the logical address space for the sub-CPU to the logical address space for the main CPU, and executes the access processing to the secondary storage device based on the logical addresses specified in each logical address space in the access request.

2. An information processing device comprising the memory controller of claim 1, the main CPU and a sub-CPU, wherein the main CPU causes an image stored in the secondary storage device by the sub-CPU when the main CPU is in a standby state to be displayed on a display device during the startup process of the information processing device as a startup image.

3. The information processing device according to claim 2, characterized in that, when the main CPU is in standby mode, the sub-CPU reads the session information stored in the secondary storage device by the main CPU, uses it to access a server, downloads data, and stores it in the secondary storage device.

4. The information processing device according to claim 3, characterized in that, when the main CPU is in standby mode, the sub-CPU generates image data to be displayed on a display device by the main CPU based on data downloaded from the server, and stores the image data in the secondary storage device.

5. The information processing apparatus according to claim 2, wherein said main CPU, while displaying said startup image, switches the display to another startup image in response to a user operation.

6. The information processing apparatus according to claim 2, wherein said main CPU displays an advertising video downloaded by said sub-CPU as said startup image.

7. The information processing apparatus according to claim 6, wherein said sub-CPU selects and downloads said advertising video having a corresponding playback time based on the time during which said start-up image can be displayed.

8. The information processing device according to claim 3, characterized in that when it becomes necessary to start up the main CPU in the middle of data downloading, the sub-CPU stores information necessary for resuming the download in the secondary storage device and then transitions to a standby state, and the main CPU resumes the download using the information necessary for resuming the download that it has read from the secondary storage device.

9. The information processing device according to claim 2, characterized in that when the main CPU is in a standby state, the sub-CPU stores in a primary storage device program data for the startup processing of the information processing device, which is stored in the secondary storage device, and the main CPU performs the startup processing using the program data stored in the primary storage device.

10. A method for processing access to a secondary storage device, comprising the steps of: generating a logical address space for the sub-CPU, which is a logical address space that enables a main CPU and a sub-CPU to access a secondary storage device, and mapping the logical address space for the sub-CPU to the logical address space for the main CPU; obtaining from the main CPU and the sub-CPU an access request to a common storage area, the access request specifying a logical address in each logical address space; and executing access processing for the secondary storage device based on the logical address specified in the access request.

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