Display substrate and display device

Abstract

Provided are a display substrate and a display device. The display substrate comprises: multiple pixel units disposed on a base substrate, at least one pixel unit comprising multiple light-emitting elements stacked in a third direction, wherein the multiple light-emitting elements stacked in the third direction each comprise: a charge generation layer disposed on the base substrate, a first light-emitting layer arranged on the side of the charge generation layer close to the base substrate, and a second light-emitting layer arranged on the side of the charge generation layer away from the base substrate; and at least one testing component disposed on the base substrate and located in a testing component region, wherein the at least one testing component comprises multiple testing elements, and the multiple testing elements are arranged in an array in the testing component region along a first direction and a second direction. The multiple testing elements include first testing elements and second testing elements, the first testing elements and the first light-emitting layer contain the same material, the second testing elements and the second light-emitting layer contain the same material, and the first testing elements and the second testing elements are located in two rows.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) devices have attracted considerable attention due to their self-luminescence, rich colors, fast response time, wide viewing angle, light weight, thinness, low power consumption, and flexible display capabilities. The core component of OLED products is the OLED light-emitting device, whose luminous efficiency and lifespan directly determine the product's core competitiveness.

[0003] With the development of OLED display technology, OLED light-emitting devices with a tandem structure (i.e., a series or stacked structure) have begun to attract the attention of researchers. In tandem OLED light-emitting devices, multiple electroluminescent elements are stacked, which can improve the luminous efficiency and lifespan of OLED light-emitting devices. How to design and manufacture OLED display products with a tandem structure is one of the important research topics for researchers.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display substrate is provided, comprising: a base substrate, the base substrate comprising a display area and a test component area; a plurality of pixel units provided on the base substrate, the plurality of pixel units being arranged in an array in the display area along a first direction and a second direction, at least one of the pixel units comprising a plurality of light-emitting elements stacked along a third direction, the plurality of light-emitting elements stacked along the third direction comprising: a charge generation layer provided on the base substrate; a first light-emitting layer provided on a side of the charge generation layer close to the base substrate; and a second light-emitting layer provided on a side of the charge generation layer away from the base substrate, wherein the first direction and the second direction intersect, the third direction is perpendicular to the first direction and the second direction; and a plurality of pixel units provided on the base substrate. At least one test component on the base substrate, the at least one test component is located in the test component area, the at least one test component includes a plurality of test elements, the plurality of test elements are arranged in an array along a first direction and a second direction in the test component area, wherein the plurality of test elements include a first test element and a second test element, the first test element and the first light-emitting layer include the same material, the second test element and the second light-emitting layer include the same material, and the first test element and the second test element are located in two rows; and the display substrate also includes a first calibration mark provided on the base substrate, the first calibration mark is located in the test component area, and the first calibration mark is located between two adjacent rows of test elements.

[0006] According to some exemplary embodiments, the first light-emitting layer includes a first sub-light-emitting layer of multiple colors, the at least one test component includes a first test element of multiple colors, and the first test element of multiple colors and the first sub-light-emitting layer of multiple colors include the same material; the second light-emitting layer includes a second sub-light-emitting layer of multiple colors, the at least one test component includes a second test element of multiple colors, and the second test element of multiple colors and the second sub-light-emitting layer of multiple colors include the same material; and the test component area has a rectangular shape, the test component area has a first dimension along the first direction and a second dimension along the second direction, the first dimension is smaller than the second dimension, and in the same test component, the first test elements and the second test elements of the same color are located in two columns arranged along the first direction, and the first test elements and the second test elements of the same color are located in a row extending along the first direction.

[0007] According to some exemplary embodiments, in the same test assembly, the first test elements of different colors are located in the same column extending along the second direction; and / or, in the same test assembly, the second test elements of different colors are located in the same column extending along the second direction.

[0008] According to some exemplary embodiments, the plurality of light-emitting elements stacked along the third direction further include: a first compensation layer disposed on a side of the first light-emitting layer close to the base substrate; and a second compensation layer disposed on a side of the second light-emitting layer close to the base substrate; and the plurality of test elements further include a third test element and a fourth test element, the third test element and the first compensation layer include the same material, the fourth test element and the second compensation layer include the same material, and the third test element and the fourth test element are located in two rows.

[0009] According to some exemplary embodiments, the first compensation layer and the second compensation layer are of the same color, and the third test element and the fourth test element are located in the same row extending along the first direction.

[0010] According to some exemplary embodiments, in the same test assembly, the first test element and the third test element of different colors are located in the same column extending along the second direction; and / or, in the same test assembly, the second test element and the fourth test element of different colors are located in the same column extending along the second direction.

[0011] According to some exemplary embodiments, the display substrate further includes a reference mark disposed on the base substrate, the reference mark being located in the test component area, and the reference mark being located between two adjacent columns of test elements in the first direction.

[0012] According to some exemplary embodiments, the reference mark is located between two adjacent rows of test elements in the second direction.

[0013] According to some exemplary embodiments, the display substrate further includes a second calibration mark disposed on the base substrate, the second calibration mark being located in the test component area, extending along a second direction, and being located between two adjacent rows of test elements in the second direction.

[0014] According to some exemplary embodiments, at least one of the test components includes q columns of test elements arranged along the first direction and n rows of test elements arranged along the second direction, wherein q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4.

[0015] According to some exemplary embodiments, in the same test component, a first spacing distance between two adjacent columns of test elements arranged along the first direction is greater than or equal to 150 microns; and / or, in the same test component, a first spacing distance between two adjacent columns of test elements arranged along the first direction is less than or equal to 390 microns.

[0016] According to some exemplary embodiments, the reference mark includes a first reference mark portion extending along a first direction and a second reference mark portion extending along a second direction, the first reference mark portion and the second reference mark portion intersect at a reference point; and a first imaginary straight line extends along the second direction and passes through the reference point, a second imaginary straight line extends along the second direction and passes through the centers of at least two test elements in a column of test elements, and a third imaginary straight line extends along the second direction and passes through the centers of at least two test elements in another column of test elements, and a ratio of a first distance in the first direction between the second imaginary straight line and the first imaginary straight line to a second distance in the first direction between the third imaginary straight line and the first imaginary straight line is between 0.8 and 1.2.

[0017] According to some exemplary embodiments, a fourth imaginary straight line extends along the first direction and passes through the reference point, a fifth imaginary straight line extends along the first direction and passes through the center of a row of test elements adjacent to the reference mark, a sixth imaginary straight line extends along the first direction and passes through the center of another row of test elements adjacent to the reference mark, and a ratio of a third distance in the second direction between the fifth imaginary straight line and the fourth imaginary straight line to a fourth distance in the second direction between the sixth imaginary straight line and the fourth imaginary straight line is between 0.8 and 1.2.

[0018] According to some exemplary embodiments, the display substrate includes n first calibration marks, and in the first direction, the i-th first calibration mark is located between the first test element and the second test element in the i-th row of test elements, where 1≤i≤n and i is a positive integer.

[0019] According to some exemplary embodiments, the display substrate includes q second calibration marks, and one of the q second calibration marks is located between two first test elements in the first column in the second direction.

[0020] According to some exemplary embodiments, the n rows of test elements include the kth row of test elements and the k+1th row of test elements adjacent to the reference mark, the kth row of test elements and the k+1th row of test elements having a second spacing distance in the second direction, wherein 1≤k≤n-1 and k is a positive integer; the pth row of test elements and the p+1th row of test elements have a third spacing distance in the second direction, wherein 1≤p≤n-1 and p is a positive integer, and p is not equal to k; and the second spacing distance is greater than the third spacing distance.

[0021] According to some exemplary embodiments, the second spacing distance is more than twice the third spacing distance.

[0022] According to some exemplary embodiments, the display area of ​​the display substrate includes a first side, a second side, a third side, a fourth side, a first corner, a second corner, a third corner and a fourth corner, and the first corner, the second corner, the third corner and the fourth corner are respectively located at the connection of two adjacent sides among the first side, the second side, the third side and the fourth side; and the display substrate includes a plurality of the test components, and the plurality of the test components are respectively arranged adjacent to the first side, the second side, the third side, the fourth side, the first corner, the second corner, the third corner and the fourth corner.

[0023] According to some exemplary embodiments, the display substrate includes a driving chip disposed adjacent to the first side, and the at least one test component disposed adjacent to the first side is located between the driving chip and the first side of the display area.

[0024] According to some exemplary embodiments, the display substrate includes a driving chip disposed adjacent to the first side, and the at least one test component disposed adjacent to the first side is located on a side of the driving chip away from the first side of the display area.

[0025] According to some exemplary embodiments, the display substrate includes two adjacent test component areas, and the test components in the two test component areas are arranged side by side along a first direction; and / or, the display substrate includes two adjacent test component areas, and the test components in the two test component areas are arranged side by side along a second direction.

[0026] Another aspect of the present disclosure provides a display device, comprising the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] FIG1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0029] FIG2 is a schematic cross-sectional view of a display substrate taken along line AA′ in FIG1 according to some exemplary embodiments of the present disclosure;

[0030] FIG3 is a partial enlarged view of a test component area in a display substrate according to some exemplary embodiments of the present disclosure;

[0031] FIG4 schematically shows a structural diagram of a mask used in an evaporation process according to some exemplary embodiments of the present disclosure;

[0032] FIG5 is a schematic plan view of a display substrate according to some other exemplary embodiments of the present disclosure;

[0033] FIG6 is a schematic cross-sectional view of a display substrate taken along line BB′ in FIG5 according to some other exemplary embodiments of the present disclosure;

[0034] FIG7 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure;

[0035] FIG8 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure;

[0036] FIG9 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure;

[0037] 10A and 10B are respectively partial enlarged views of a test component area in a display substrate according to further exemplary embodiments of the present disclosure;

[0038] FIG11 is a schematic plan view of a display substrate according to further exemplary embodiments of the present disclosure; and

[0039] FIG. 12 is a schematic structural diagram of a testing device for detecting pixel position accuracy of a display substrate according to some exemplary embodiments of the present disclosure.

[0040] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0041] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0043] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "include," "comprising," and similar words mean that the element or object preceding the word encompasses the elements or objects listed after the word, and their equivalents, without excluding other elements or objects.

[0044] Unless otherwise specified, directional terms such as "upper," "lower," "left," "right," "inner," and "outer" are used herein to indicate positions or relationships based on the figures shown. These terms are intended solely to facilitate the description of the present disclosure and are not intended to indicate or imply that the devices, components, or parts referred to must have, be constructed, or operate in a specific orientation. It should be understood that when the absolute positions of the objects being described change, the relative positions they represent may also change accordingly. Therefore, these directional terms should not be construed as limiting the present disclosure.

[0045] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0046] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0047] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel unit, such as the longitudinal and transverse directions of a pixel unit, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0048] In the preparation process of OLED display devices, vacuum thermal evaporation can be used to form OLED light-emitting devices. The vacuum thermal evaporation method has moderate process complexity and the lifespan of the OLED light-emitting devices produced is long, so it has been widely used. In this preparation method, the FMM (Fine Metal Mask, i.e., a high-precision metal mask) is a key structure to ensure that the organic light-emitting material is accurately evaporated to the designed position. The FMM includes an evaporation opening corresponding to the display area. During the evaporation process, the heated and evaporated organic material molecules will pass through the openings in the FMM and be deposited on the openings of the pixel definition layer (PDL) of the backplane, thereby forming a predetermined pattern.

[0049] The FMM structure is delicate, with openings only tens of microns in size. Therefore, a TEG (Test Element Group) is required to accurately test and align the vapor-deposited pattern to prevent poor color mixing caused by poor alignment and ensure the final display quality. Each layer of the vapor-deposited pattern typically corresponds to a mask plate, which is equipped with a pixel position alignment test element group (PPA TEG). The PPA TEG can monitor and improve the pixel position accuracy of the display screen, thereby improving the yield of the display product and ensuring a good display effect.

[0050] Figure 1 is a planar schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, Figure 2 is a cross-sectional schematic diagram of the display substrate according to some exemplary embodiments of the present disclosure taken along line AA' in Figure 1, and Figure 3 is a partially enlarged view of a test component area in the display substrate according to some exemplary embodiments of the present disclosure.

[0051] 1 to 3 , the display substrate 100 ′ includes: a base substrate 1 ′, the base substrate including a display area AA and a test assembly area TGA; a plurality of pixel units P disposed on the base substrate 1 ′, the plurality of pixel units P being arranged in an array in the display area AA along a first direction D1 and a second direction D2; and at least one test assembly 2 ′ disposed on the base substrate 1 ′, the at least one test assembly 2 ′ being located in the test assembly area TGA, the at least one test assembly 2 ′ including a plurality of test elements 3 ′, the plurality of test elements 3 ′ being arranged in the test assembly area TGA along the first direction D1 or the second direction D2.

[0052] As shown in FIG2 , in the display area AA, the display substrate 100′ includes: a first electrode 4′, a second electrode 6′, and a light-emitting functional layer 5′ disposed on a base substrate 1. For example, the light-emitting functional layer 5′ may include a hole injection layer 51′, a hole transport layer 52′, a light-emitting layer 53′, an electron transport layer 54′, and an electron injection layer 55′.

[0053] The light emitting layer 53' may include multiple sub-light emitting layers, for example, a first sub-light emitting layer 53'R, a second sub-light emitting layer 53'G, and a third sub-light emitting layer 53'B. The first sub-light emitting layer 53'R, the second sub-light emitting layer 53'G, and the third sub-light emitting layer 53'B may emit red light, green light, and blue light, respectively.

[0054] In this embodiment, a pixel unit P may include at least three sub-pixels SP1, SP2, and SP3, where the sub-pixels SP1, SP2, and SP3 are red, green, and blue sub-pixels, respectively, and the sub-pixels SP1, SP2, and SP3 include a first sub-light-emitting layer 53'R, a second sub-light-emitting layer 53'G, and a third sub-light-emitting layer 53'B, respectively.

[0055] It should be noted that the embodiments of the present disclosure do not impose any special restrictions on the design of the pixel unit P. For example, although the accompanying drawings schematically show that the pixel unit P includes 3 sub-pixels, in other embodiments, a pixel unit P may also include a smaller or larger number of sub-pixels. In addition, the arrangement of the sub-pixels within a pixel unit P may adopt various arrangement methods known in the art, and the embodiments of the present disclosure do not impose any special restrictions.

[0056] Continuing with FIG2 , the hole injection layer 51 ', the hole transport layer 52 ', the light-emitting layer 53 ', the electron transport layer 54 ', and the electron injection layer 55 ' are sequentially disposed on the side of the first electrode 4 ' away from the substrate 1 '. In this embodiment, the first electrode 4 ' may be an anode, and the second electrode 6 ' may be a cathode. The holes provided by the first electrode 4 ' are assisted by the hole injection layer 51 ' and the hole transport layer 52 ' in transporting them to the light-emitting layer 53 '. The electrons provided by the second electrode 6 ' are assisted by the electron injection layer 55 ' and the electron transport layer 54 ' in transporting them to the light-emitting layer 53 '. The holes and electrons recombine in the light-emitting layer 53 ' to excite the light-emitting layer 53 ' to emit light of the corresponding color.

[0057] Optionally, the light-emitting functional layer 5 ′ may further include an electron blocking layer disposed between the first electrode 4 ′ and the light-emitting layer 53 ′, and a hole blocking layer disposed between the second electrode 6 ′ and the light-emitting layer 53 ′.

[0058] Because red, green, and blue light have different wavelengths, they experience different losses when passing through the structure above the light-emitting layer. Longer wavelengths result in greater losses. To ensure that each pixel unit P has the same display effect under the same conditions, in some embodiments of the present disclosure, the luminous intensity of the red and / or green sub-pixels can be increased to offset the losses during transmission. In other words, a compensation layer can be added below the sub-light-emitting layers of the red and green sub-pixels.

[0059] 2 , the light emitting functional layer 5 ′ may further include a compensation layer 56 ′. For example, the compensation layer 56 ′ may include a sub-compensation layer 56 ′R located in the first sub-pixel SP1 and / or a sub-compensation layer 56 ′G located in the second sub-pixel SP2 .

[0060] The sub-compensation layer 56'R is located below the first sub-luminescent layer 53'R. In other words, the sub-compensation layer 56'R is located between the first sub-luminescent layer 53'R and the first electrode 4'. For example, the thickness of the sub-compensation layer 56'R is greater than that of the first sub-luminescent layer 53'R. When holes transferred by the first electrode 4' and electrons transferred by the second electrode 6' recombine in the sub-compensation layer 56'R, the sub-compensation layer 56'R is excited to emit red light, thereby enhancing the intensity of the red light emitted by the first sub-pixel SP1.

[0061] The sub-compensation layer 56'G is located below the second sub-light-emitting layer 53'G. In other words, the sub-compensation layer 56'G is located between the second sub-light-emitting layer 53'G and the first electrode 4'. For example, the thickness of the sub-compensation layer 56'G is greater than that of the second sub-light-emitting layer 53'G. When holes transferred by the first electrode 4' and electrons transferred by the second electrode 6' recombine in the sub-compensation layer 56'G, the sub-compensation layer 56'G is excited to emit green light, thereby enhancing the intensity of the green light emitted by the second sub-pixel SP2.

[0062] 1 to 3 , the display area AA of the display substrate 100 ′ includes a first side AA1, a second side AA2, a third side AA3, a fourth side AA4, a first corner AC1, a second corner AC2, a third corner AC3, and a fourth corner AC4. The first corner AC1, the second corner AC2, the third corner AC3, and the fourth corner AC4 are respectively located at the connection between two adjacent sides among the first side AA1, the second side AA2, the third side AA3, and the fourth side AA4.

[0063] In some embodiments, the display substrate 100' may include a plurality of the test components 2', which are respectively arranged adjacent to the first side AA1, the second side AA2, the third side AA3, the fourth side AA4, the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4.

[0064] FIG3 schematically illustrates a partial enlarged view of a test assembly area. As shown in FIG3 , a test assembly 2' is disposed in at least one test assembly area TGA. The test assembly 2' may include multiple test elements 3'. For example, the multiple test elements 3' may be test elements of multiple colors. For ease of description, the test elements of multiple colors are labeled as test elements 3'R, 3'G, 3'B, 3"R, and 3"G, respectively.

[0065] The test elements 3'R, 3'G, 3'B, 3"R, and 3"G of multiple colors respectively correspond to the first sub-light-emitting layer 53'R, the second sub-light-emitting layer 53'G, the third sub-light-emitting layer 53'B, the sub-compensation layer 56'R, and the sub-compensation layer 56'G formed by the evaporation process. Specifically, during the preparation of the display substrate 100', the first sub-light-emitting layer 53'R, the second sub-light-emitting layer 53'G, the third sub-light-emitting layer 53'B, the sub-compensation layer 56'R, and the sub-compensation layer 56'G are respectively formed by multiple evaporation processes. It should be noted that the "multiple evaporation processes" here mean that in the multiple evaporation processes, different FMMs are used to form each evaporated film layer, or, although the same FMM is used, different evaporation process parameters are used to form each evaporated film layer.

[0066] In this embodiment, the test element 3'R and the first sub-light-emitting layer 53'R are formed by the same evaporation process, the test element 3'G and the second sub-light-emitting layer 53'G are formed by the same evaporation process, the test element 3'B and the third sub-light-emitting layer 53'B are formed by the same evaporation process, the test element 3"R and the sub-compensation layer 56'R are formed by the same evaporation process, and the test element 3"G and the sub-compensation layer 56'G are formed by the same evaporation process. In this way, by detecting the positional accuracy of the test element 3'R, the pixel positional accuracy of the first sub-light-emitting layer 53'R can be correspondingly determined. By detecting the positional accuracy of the test element 3'G, the pixel positional accuracy of the second sub-light-emitting layer 53'G can be correspondingly determined. By detecting the positional accuracy of the test element 3'B, the pixel positional accuracy of the third sub-light-emitting layer 53'B can be correspondingly determined. By detecting the positional accuracy of the test element 3"R, the pixel positional accuracy of the sub-compensation layer 56'R can be correspondingly determined. By detecting the positional accuracy of the test element 3"G, the pixel positional accuracy of the sub-compensation layer 56'G can be correspondingly determined.

[0067] As shown in Figure 3, a test assembly area TGA has a first dimension X1 in a first direction D1 and a second dimension Y1 in a second direction D2. Multiple test components are arranged in a row along the second direction D2 within the test assembly area TGA. For example, test components 3'R, 3'G, 3'B, 3"R, and 3"G are arranged in a row along the second direction D2.

[0068] It should be noted that, in FIG3 , the shape of the orthographic projection of each test element on the substrate 1 ' is schematically shown, and its shape is schematically shown as a square. However, the embodiments of the present disclosure are not limited to this. The shape of the orthographic projection of each test element on the substrate 1 ' may include, but is not limited to, a rectangle, a circle, an ellipse, an approximately circular shape, a triangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and the like.

[0069] 3 , the display substrate 100 ′ may further include a fiducial mark 7 ′, a first calibration mark 8 ′, and a second calibration mark 9 ′ disposed on the base substrate 1 ′. The fiducial mark 7 ′, the first calibration mark 8 ′, and the second calibration mark 9 ′ are all located in the test assembly area TGA.

[0070] The reference mark 7' may include a first reference mark portion 71' extending along the first direction D1 and a second reference mark portion 72' extending along the second direction D2. The first reference mark portion 71' and the second reference mark portion 72' intersect at a reference point. The first calibration mark 8' extends along the first direction D1. The second calibration mark 9' extends along the second direction D2.

[0071] For example, the reference mark 7 ′ may have a cross shape, and the first calibration mark 8 ′ and the second calibration mark 9 ′ may each have a straight shape.

[0072] In the embodiment of the present disclosure, only one reference mark 7 ′ is provided in one test assembly area TGA, and the reference mark 7 ′ is used to mark the position of the test assembly area TGA.

[0073] In some embodiments, m' evaporated film layers are provided in the display area AA, where m' is a positive integer greater than or equal to 1. For example, in the illustrated embodiment, m' is 5. The five evaporated film layers are the first sub-light-emitting layer 53'R, the second sub-light-emitting layer 53'G, the third sub-light-emitting layer 53'B, the sub-compensation layer 56'R, and the sub-compensation layer 56'G. Accordingly, in the test assembly area TGA, a test assembly includes m' test elements, each corresponding to one of the m' evaporated film layers and used to detect the pixel position accuracy of each of the m' evaporated film layers.

[0074] In the test assembly area TGA, m' first calibration marks 8' are provided. The m' first calibration marks 8' correspond to the m' test elements respectively and are used to detect the position accuracy of the m' test elements in the second direction D2.

[0075] The number of second calibration marks 9' provided in the test assembly area TGA corresponds to the number of columns of m' test elements. For example, in this embodiment, m' test elements are arranged in a column, and accordingly, one second calibration mark 9' is provided in the test assembly area TGA. This second calibration mark 9' is used to detect the positional accuracy of the m' test elements arranged in a column in the first direction D1.

[0076] It should be noted that the purpose of calibration or positioning using the reference mark 7 ′, the first calibration mark 8 ′ and the second calibration mark 9 ′ will be further explained in detail below in conjunction with the detection process.

[0077] Referring back to FIG. 2 , in some embodiments, the first sub-light emitting layer 53 ′R, the second sub-light emitting layer 53 ′G, and the third sub-light emitting layer 53 ′B may be formed by an evaporation process using different FMMs, respectively.

[0078] In display area AA, sub-compensation layer 56'R is located below first sub-light-emitting layer 53'R. The sub-compensation layer 56'R and the first sub-light-emitting layer 53'R are aligned in the first direction D1 and the second direction D2. Therefore, the same FMM can be used to form both sub-compensation layer 56'R and the first sub-light-emitting layer 53'R. It should be noted that the evaporation process parameters used during the formation of sub-compensation layer 56'R and the first sub-light-emitting layer 53'R are different, so the evaporation processes used to form sub-compensation layer 56'R and the first sub-light-emitting layer 53'R are different. Similarly, sub-compensation layer 56'G is located below second sub-light-emitting layer 53'G. The sub-compensation layer 56'G and the second sub-light-emitting layer 53'G are aligned in the first direction D1 and the second direction D2. Therefore, the same FMM can be used to form both sub-compensation layer 56'G and the second sub-light-emitting layer 53'G. It should be noted that, during the formation of the compensation sub-layer 56'G and the second light-emitting sub-layer 53'G, the evaporation process parameters are different, so the evaporation processes for forming the compensation sub-layer 56'G and the second light-emitting sub-layer 53'G are different evaporation processes.

[0079] FIG. 4 schematically illustrates a structural diagram of a mask used in an evaporation process according to some exemplary embodiments of the present disclosure.

[0080] As shown in Figure 4, the mask 20 includes an evaporation area 21 and a test area 22 located around the evaporation area 21. The evaporation area 21 includes an evaporation opening 211 for target material to pass through and reach the backplane's graphic area, thereby forming a pattern of the light-emitting layer or compensation layer in the display area AA. The test area 22 includes a test hole 221 for target material to pass through and reach the backplane's test assembly area, thereby forming a pattern of test elements in the test assembly area TGA.

[0081] In actual applications, the mask plate 20 is fixed in a chamber, with a target material disposed below the mask plate 20, and the backplane to be evaporated is disposed above the mask plate 20. Appropriate process conditions within the chamber are set to ensure that the target material is evaporated to the predetermined position on the backplane through the evaporation openings and test holes in the mask plate 20. For example, the mask plate 20 may be a fiber-optic membrane (FMM). During evaporation, the heated and evaporated organic material molecules pass through the evaporation openings 211 on the FMM and are deposited at the openings of the pixel definition layer of the backplane, thereby forming a pattern of the light-emitting layer or compensation layer in the display area AA. Simultaneously, the organic material molecules pass through the test holes 221 on the FMM and are deposited into the test component area of ​​the backplane, thereby forming a pattern of test elements in the test component area TGA. Multiple test elements disposed in the test component area TGA form position test marks for precise test alignment of the evaporation pattern formed by FMM evaporation. Each evaporation pattern corresponds to a test element to ensure the correctness and accuracy of the evaporation pattern.

[0082] Figure 5 is a planar schematic diagram of a display substrate according to some other exemplary embodiments of the present disclosure, Figure 6 is a cross-sectional schematic diagram of the display substrate according to some other exemplary embodiments of the present disclosure taken along line BB' in Figure 5, and Figure 7 is a partial enlarged diagram of a test component area in the display substrate according to some other exemplary embodiments of the present disclosure.

[0083] 5 to 7 , the display substrate 100 includes: a base substrate 1 including a display area AA and a test assembly area TGA; a plurality of pixel units P disposed on the base substrate 1, the plurality of pixel units P being arranged in an array in the display area AA along a first direction D1 and a second direction D2; and at least one test assembly 2 disposed on the base substrate 1, the at least one test assembly 2 being located in the test assembly area TGA, the at least one test assembly 2 including a plurality of test elements 3, the plurality of test elements 3 being arranged in an array in the test assembly area TGA along the first direction D1 and the second direction D2.

[0084] In this embodiment, at least one of the pixel units P includes a plurality of light-emitting elements stacked along a third direction D3, and the plurality of light-emitting elements stacked along the third direction D3 include: a charge generation layer CGL arranged on the base substrate 1; a first light-emitting layer arranged on the side of the charge generation layer CGL close to the base substrate 1; and a second light-emitting layer arranged on the side of the charge generation layer CGL away from the base substrate 1, wherein the first direction D1 and the second direction D2 intersect, and the third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0085] As shown in FIG5 , in display area AA, display substrate 100 includes: a first electrode 4 and a second electrode 6 disposed on base substrate 1; and a first light-emitting layer, a charge generation layer CGL, and a second light-emitting layer sandwiched between first electrode 4 and second electrode 6. In third direction D3, the first light-emitting layer is located between first electrode 4 and charge generation layer CGL, and the second light-emitting layer is located between charge generation layer CGL and second electrode 6.

[0086] That is, in at least one pixel unit P, the OLED light-emitting device includes two light-emitting elements connected in series, forming the OLED light-emitting device as a tandem device. For example, the upper light-emitting element 32 includes: a second electrode 6, an electron injection layer EIL, an electron transport layer ETL, a hole blocking layer HBL2, a second light-emitting layer EML2, a hole transport layer HTL2, and a charge generation layer CGL. The lower light-emitting element 31 includes: a charge generation layer CGL, a hole blocking layer HBL1, a first light-emitting layer EML1, a hole transport layer HTL1, a hole injection layer HIL, and a first electrode 4.

[0087] For example, the charge generation layer CGL may include an N-type charge generation layer CGL1 and a P-type charge generation layer CGL2. The N-type charge generation layer CGL1 is located on the side of the P-type charge generation layer CGL2 close to the first electrode 4. That is, the N-type charge generation layer CGL1 is paired with the first electrode 4 to excite the light-emitting element located below to emit light; the P-type charge generation layer CGL2 is paired with the second electrode 6 to excite the light-emitting element located above to emit light.

[0088] For example, the N-type charge generation layer CGL1 may be composed of an organic electron transport material doped with a metal material at a doping concentration of ≤1%. The P-type charge generation layer CGL2 may be composed of an organic hole transport material doped with a PD (p-dopant) at a doping concentration of approximately 10%.

[0089] That is, as shown in FIG6 , the display substrate 100 includes: a first electrode 4 disposed on a base substrate 1; a hole injection layer HIL disposed on a side of the first electrode 4 away from the base substrate; a first hole transport layer HTL1 disposed on a side of the hole injection layer HIL away from the base substrate; a first light-emitting layer EML1 disposed on a side of the first hole transport layer HTL1 away from the base substrate; a first hole blocking layer HBL1 disposed on a side of the first light-emitting layer EML1 away from the base substrate; an N-type charge generation layer CGL1 disposed on a side of the first hole blocking layer HBL1 away from the base substrate; and a first hole transport layer HTL1 disposed on a side of the first hole transport layer HTL1 away from the base substrate. 1 a P-type charge generation layer CGL2 located on a side away from the base substrate; a second hole transport layer HTL2 located on a side away from the base substrate; a second light-emitting layer EML2 located on a side away from the base substrate; a second hole blocking layer HBL2 located on a side away from the base substrate; an electron transport layer ETL located on a side away from the base substrate; an electron injection layer EIL located on a side away from the base substrate; and a second electrode 6 located on a side away from the base substrate.

[0090] In some embodiments of the present disclosure, the first light-emitting layer EML1 includes a plurality of first sub-light-emitting layers of various colors, for example, the plurality of first sub-light-emitting layers may include sub-light-emitting layers 51R, 51G, and 51B. The second light-emitting layer EML2 includes a plurality of second sub-light-emitting layers of various colors, for example, the plurality of second sub-light-emitting layers may include sub-light-emitting layers 52R, 52G, and 52B.

[0091] In this embodiment, the OLED light-emitting device is formed as a tandem device, where two or more light-emitting elements are connected in series via a charge generation layer to form a stacked device. Due to the increased number of light-emitting layers, the charge generation layer reduces the driving voltage and generates new carriers. Stacking multiple light-emitting elements can exponentially increase the device's luminous efficiency, significantly improving it. At the same brightness, the tandem device's current density is reduced, significantly extending the device's lifespan.

[0092] For example, the sub-light emitting layers 51R, 51G, and 51B can emit red light, green light, and blue light, respectively. The sub-light emitting layers 52R, 52G, and 52B can emit red light, green light, and blue light, respectively.

[0093] In this embodiment, a pixel unit P may include at least three sub-pixels SP1, SP2, and SP3, where sub-pixels SP1, SP2, and SP3 are red, green, and blue sub-pixels, respectively. Sub-pixel SP1 includes a stacked sub-light-emitting layer 51R and a sub-light-emitting layer 52R, sub-pixel SP2 includes a stacked sub-light-emitting layer 51G and a sub-light-emitting layer 52G, and sub-pixel SP3 includes a stacked sub-light-emitting layer 51B and a sub-light-emitting layer 52B.

[0094] It should be noted that the embodiments of the present disclosure do not impose any special restrictions on the design of the pixel unit P. For example, although the accompanying drawings schematically show that the pixel unit P includes 3 sub-pixels, in other embodiments, a pixel unit P may also include a smaller or larger number of sub-pixels. In addition, the arrangement of the sub-pixels within a pixel unit P may adopt various arrangement methods known in the art, and the embodiments of the present disclosure do not impose any special restrictions.

[0095] In some exemplary embodiments of the present disclosure, at least one light-emitting element stacked along the third direction may further include: a first compensation layer arranged on a side of the first light-emitting layer EML1 close to the base substrate; and a second compensation layer arranged on a side of the second light-emitting layer EML2 close to the base substrate.

[0096] Because red, green, and blue light have different wavelengths, they experience different losses when passing through the structure above the light-emitting layer. Longer wavelengths result in greater losses. To ensure that each pixel unit P has the same display effect under the same conditions, in some embodiments of the present disclosure, the luminous intensity of the red and / or green sub-pixels can be increased to offset the losses during transmission. In other words, a compensation layer can be added below the sub-light-emitting layer of the red and / or green sub-pixels.

[0097] For example, in the embodiment shown in Figure 6, at least one light-emitting element located in the first sub-pixel SP1 may include a compensation layer, that is, including: a first sub-compensation layer 561R arranged on the side of the first light-emitting layer EML1 close to the base substrate; and a second sub-compensation layer 562R arranged on the side of the second light-emitting layer EML2 close to the base substrate.

[0098] The first sub-compensation layer 561R is located below the sub-luminescent layer 51R, or in other words, between the sub-luminescent layer 51R and the first electrode 4. For example, the thickness of the first sub-compensation layer 561R is greater than that of the sub-luminescent layer 51R. When holes transferred by the first electrode 4 and electrons transferred by the N-type charge generation layer CGL1 recombine in the first sub-compensation layer 561R, the first sub-compensation layer 561R is stimulated to emit red light, thereby enhancing the intensity of the red light emitted by the first sub-pixel SP1.

[0099] 5 to 7 , the display area AA of the display substrate 100 includes a first side AA1, a second side AA2, a third side AA3, a fourth side AA4, a first corner AC1, a second corner AC2, a third corner AC3, and a fourth corner AC4. The first corner AC1, the second corner AC2, the third corner AC3, and the fourth corner AC4 are respectively located at the connection between two adjacent sides of the first side AA1, the second side AA2, the third side AA3, and the fourth side AA4.

[0100] In some embodiments, the display substrate 100 may include a plurality of the test components 2, which are respectively arranged adjacent to the first side AA1, the second side AA2, the third side AA3, the fourth side AA4, the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4.

[0101] FIG7 schematically illustrates a partial enlarged view of a test assembly area. As shown in FIG7 , in at least one test assembly area TGA, a test assembly 2 is provided. The test assembly 2 may include multiple test elements 3. For example, the multiple test elements 3 may be test elements of multiple colors. For ease of description, the test elements of multiple colors are labeled as test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R, respectively.

[0102] The test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R of multiple colors correspond to the sub-luminescent layer 51R, sub-luminescent layer 52R, sub-luminescent layer 51G, sub-luminescent layer 52G, sub-luminescent layer 51B, sub-luminescent layer 52B, first sub-compensation layer 561R, and second sub-compensation layer 562R formed by the evaporation process, respectively. Specifically, during the preparation of the display substrate 100, the sub-luminescent layer 51R, sub-luminescent layer 52R, sub-luminescent layer 51G, sub-luminescent layer 52G, sub-luminescent layer 51B, sub-luminescent layer 52B, first sub-compensation layer 561R, and second sub-compensation layer 562R are formed by multiple evaporation processes. It should be noted that the term "multiple evaporation processes" herein means that different FMMs are used to form each evaporated film layer in the multiple evaporation processes, or that the same FMM is used but different evaporation process parameters are used to form each evaporated film layer.

[0103] In this embodiment, the test element 31R and the sub-light-emitting layer 51R are formed by the same evaporation process, the test element 32R and the sub-light-emitting layer 52R are formed by the same evaporation process, the test element 31G and the sub-light-emitting layer 51G are formed by the same evaporation process, the test element 32G and the sub-light-emitting layer 52G are formed by the same evaporation process, the test element 31B and the sub-light-emitting layer 51B are formed by the same evaporation process, the test element 32B and the sub-light-emitting layer 52B are formed by the same evaporation process, the test element 33R and the first sub-compensation layer 561R are formed by the same evaporation process, and the test element 34R and the second sub-compensation layer 562R are formed by the same evaporation process. In this way, by detecting the position accuracy of the test element 31R, the pixel position accuracy of the sub-light-emitting layer 51R can be determined accordingly; by detecting the position accuracy of the test element 32R, the pixel position accuracy of the sub-light-emitting layer 52R can be determined accordingly; by detecting the position accuracy of the test element 31G, the pixel position accuracy of the sub-light-emitting layer 51G can be determined accordingly; by detecting the position accuracy of the test element 32G, the pixel position accuracy of the sub-light-emitting layer 52G can be determined accordingly; by detecting the position accuracy of the test element 31B, the pixel position accuracy of the sub-light-emitting layer 51B can be determined accordingly; by detecting the position accuracy of the test element 32B, the pixel position accuracy of the sub-light-emitting layer 52B can be determined accordingly; by detecting the position accuracy of the test element 33R, the pixel position accuracy of the first sub-compensation layer 561R can be determined accordingly; by detecting the position accuracy of the test element 34R, the pixel position accuracy of the second sub-compensation layer 562R can be determined accordingly.

[0104] In the embodiments of the present disclosure, the test element located in the test assembly area and the light-emitting layer or sub-light-emitting layer located in the display area are formed by the same evaporation process. Thus, the test element and the light-emitting layer or sub-light-emitting layer formed by the same evaporation process include the same material and have substantially the same thickness. It should be noted that the "substantially the same thickness" herein can be understood as: the test element and the light-emitting layer or sub-light-emitting layer formed by the same evaporation process have substantially the same thickness in their respective middle portions, and the thickness at their respective edge portions may vary slightly due to differences in the diffusion regions.

[0105] As shown in FIG. 7 , a test assembly area TGA has a first size X1 in the first direction D1 and a second size Y1 in the second direction D2 .

[0106] It should be noted that, in the embodiments of the present disclosure, the expression "test component area" refers to the area where the test component is placed, and its size is limited by the field of view of the image acquisition sensor (such as CCD) of the test equipment.

[0107] For example, the first size and the second size of the single test component area TGA in the embodiments shown in FIG5-7 are respectively equal to the first size and the second size of the single test component area TGA in the embodiments shown in FIG1-3.

[0108] It should also be noted that, in the embodiment of the present disclosure, the test assembly area TGA is illustratively rectangular, and the first dimension X1 of the test assembly area TGA is smaller than the second dimension Y1. The embodiment of the present disclosure is not limited thereto, and the test assembly area TGA may also have other shapes, such as polygonal, circular, etc.

[0109] As shown in FIG. 7 , in one test assembly area TGA, test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R are arranged in an array along a first direction D1 and a second direction D2 in the test assembly area TGA.

[0110] Exemplarily, test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R are respectively located in two columns arranged along the first direction. For example, referring to FIG7 , the column of test elements on the left is referred to as the first column, and the column of test elements on the right is referred to as the second column. Test elements corresponding to the light-emitting layer and / or compensation layer of light-emitting element 31 below the tandem structure can be located in the first column, while test elements corresponding to the light-emitting layer and / or compensation layer of light-emitting element 32 above the tandem structure can be located in the second column. Specifically, test elements 31R, 31G, 31B, and 33R are located in the first column, and test elements 32R, 32G, 32B, and 34R are located in the second column.

[0111] In the embodiments of the present disclosure, the number of film layers formed by the evaporation process in the tandem display substrate increases, and accordingly, the number of test elements required to be provided in the test assembly area also increases. For example, in the embodiments shown in Figures 5-7, the number of film layers formed by the evaporation process in the display area increases to 8, and the number of test elements provided in the test assembly area also increases to 8. When the number of test elements increases, the arrangement of the test elements is changed from a single-column arrangement to a multi-column arrangement, thereby achieving pixel position accuracy detection of the tandem display substrate without changing the size of a single test assembly area.

[0112] It should be noted that, in Figure 7, the shape of the positive projection of each test element on the substrate 1 is schematically shown, and its shape is schematically shown as a square. However, the embodiments of the present disclosure are not limited to this. The shape of the positive projection of each test element on the substrate 1 may include but is not limited to a rectangle, a circle, an ellipse, an approximate circle, a triangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon and the like.

[0113] It should be noted that, in this article, for the convenience of description, the test elements 31R, 31G, and 31B corresponding to the light-emitting layer of the light-emitting element 31 below the Tandem structure are referred to as first test elements, the test elements 32R, 32G, and 32B corresponding to the light-emitting layer of the light-emitting element 32 above the Tandem structure are referred to as second test elements, the test element 33R corresponding to the compensation layer of the light-emitting element 31 below the Tandem structure is referred to as the third test element, and the test element 34R corresponding to the compensation layer of the light-emitting element 32 above the Tandem structure is referred to as the fourth test element.

[0114] 7 , in the same test assembly, first test elements and second test elements of the same color are located in two columns arranged along the first direction D1, and are located in a row extending along the first direction D1. Specifically, first test elements 31R and second test elements 32R of the same color are located in two columns arranged along the first direction D1, and are located in a row extending along the first direction D1. First test elements 31G and second test elements 32G of the same color are located in two columns arranged along the first direction D1, and are located in a row extending along the first direction D1. First test elements 31B and second test elements 32B of the same color are located in two columns arranged along the first direction D1, and are located in a row extending along the first direction D1.

[0115] In the same test assembly, first test elements of different colors are located in the same column extending along the second direction. For example, first test elements 31R, 31G, and 31B of different colors are located in the same column extending along the second direction D2. Additionally or alternatively, in the same test assembly, second test elements of different colors are located in the same column extending along the second direction. For example, second test elements 32R, 32G, and 32B of different colors are located in the same column extending along the second direction D2.

[0116] The third test elements 33R and the fourth test elements 34R of the same color are located in two columns arranged along the first direction D1 , and the third test elements 33R and the fourth test elements 34R of the same color are located in a row extending along the first direction D1 .

[0117] 7 , the display substrate 100 may further include a fiducial mark 7, a first calibration mark 8, and a second calibration mark 9 disposed on the base substrate 1. The fiducial mark 7, the first calibration mark 8, and the second calibration mark 9 are all located in the test assembly area TGA.

[0118] The reference mark 7 may include a first reference mark portion 71 extending along the first direction D1 and a second reference mark portion 72 extending along the second direction D2 . The first reference mark portion 71 and the second reference mark portion 72 intersect at a reference point 70.

[0119] The first alignment mark 8 extends along the first direction D1 , and the second alignment mark 9 extends along the second direction D2 .

[0120] For example, the reference mark 7 may have a cross shape, and the first alignment mark 8 and the second alignment mark 9 may each have a straight shape.

[0121] In some embodiments, m evaporated film layers are provided in the display area AA, where m is a positive integer greater than or equal to 1. For example, in the embodiments shown in Figures 5-7, m is 8. The eight evaporated film layers are sub-luminescent layer 51R, sub-luminescent layer 52R, sub-luminescent layer 51G, sub-luminescent layer 52G, sub-luminescent layer 51B, sub-luminescent layer 52B, first sub-compensation layer 561R, and second sub-compensation layer 562R. Accordingly, in the test assembly area TGA, a test assembly includes m test elements, each corresponding to one of the m evaporated film layers and used to detect the pixel position accuracy of each of the m evaporated film layers.

[0122] In an embodiment of the present disclosure, at least one test assembly includes q columns of test elements arranged along a first direction D1 and n rows of test elements arranged along a second direction, where q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4. In the embodiment shown in FIG7 , q = 2, and n = 4. It should be understood that m = q × n.

[0123] In the embodiment of the present disclosure, only one reference mark 7 is provided in one test component area TGA, and the reference mark 7 is used to calibrate the position of the test component area TGA.

[0124] At least one test assembly area TGA is provided with n first calibration marks 8. That is, the number of first calibration marks 8 matches the number of test element rows. The n first calibration marks 8 correspond to n rows of test elements, respectively, and are used to detect the positional accuracy of the n rows of test elements in the second direction D2.

[0125] In at least one test assembly area TGA, q second calibration marks 9 are provided. That is, the number of second calibration marks 9 matches the number of test element columns. The q second calibration marks 9 correspond to q columns of test elements and are used to detect the positional accuracy of the q columns of test elements in the first direction D1.

[0126] Exemplarily, the reference mark 7 is located approximately in the center of the test assembly area TGA. In the first direction D1, the reference mark 7 is located between two adjacent columns of test elements; in the second direction D2, the reference mark 7 is located between two adjacent rows of test elements.

[0127] The n first calibration marks 8 correspond one-to-one with the n rows of test elements. Specifically, the n first calibration marks 8 are located between two adjacent columns of test elements in the first direction D1. That is, in the first direction D1, the i-th first calibration mark 8 is located between the first and second test elements in the i-th row of test elements, where 1 ≤ i ≤ n and i is a positive integer. This arrangement allows the positional accuracy of multiple test elements in a row to be detected using a single first calibration mark, while also achieving a compact arrangement of multiple test elements and first calibration marks.

[0128] As shown in FIG7 , four first calibration marks 8 are provided in a test assembly area TGA, wherein two first calibration marks 8 are located above the reference mark 7 in the second direction, and the other two first calibration marks 8 are located below the reference mark 7 in the second direction.

[0129] The q second calibration marks 9 correspond one-to-one with the q columns of test elements. Specifically, in the first direction D1, the jth second calibration mark 9 is aligned with the jth column of test elements; in the second direction D2, the jth second calibration mark 9 is located between two adjacent test elements in the jth column of test elements. Where 1 ≤ j ≤ q, and j is a positive integer. This arrangement allows the positional accuracy of multiple test elements in a column to be detected using a single second calibration mark, while also achieving a compact arrangement of multiple test elements and second calibration marks.

[0130] As shown in Figure 7, two second calibration marks 9 are set in a test component area TGA, wherein, in the second direction D2, the two second calibration marks 9 are located between the second row of test elements and the third row of test elements; in the first direction D1, one second calibration mark 9 is located on the left side of the reference mark 7, and the other second calibration mark 9 is located on the right side of the reference mark 7.

[0131] In an embodiment of the present disclosure, multiple test elements are prepared by utilizing the evaporation process of FMM, and the test elements need to be within the field of view of the CCD of the test equipment when in use. Based on this, while the size of a single test component area TGA remains unchanged, the arrangement, size, and spacing distance of the multiple test elements in the test component area TGA need to be designed.

[0132] As shown in Figure 7, a test component area TGA has a first size X1 in the first direction D1 and a second size Y1 in the second direction D2. The first size X1 and the second size Y1 are designed to meet the following requirements: when the CCD of the test equipment takes a picture of the test component area TGA, the image of the entire test component area TGA can be captured by one picture.

[0133] Due to the limitations of the FMM evaporation process, each test element must be designed to maintain a certain distance from each side edge of the test element TGA, i.e., a certain margin. For example, as shown in Figure 7, test elements 31R and 32R in the top row must be a certain distance from the top edge of the test element TGA, which is referred to as the top margin. Test elements 33R and 34R in the bottom row must be a certain distance from the bottom edge of the test element TGA, which is referred to as the top margin. Test elements in the leftmost column must be a certain distance from the left edge of the test element TGA, which is referred to as the left margin. Test elements in the rightmost column must be a certain distance from the right edge of the test element TGA, which is referred to as the right margin. For example, any two of the top margin, bottom margin, left margin, and right margin can be substantially equal, or the ratio of any two of the top margin, bottom margin, left margin, and right margin can be between 0.8 and 1.2. For example, any one of the top margin, the bottom margin, the left margin, and the right margin is greater than 20 micrometers.

[0134] Continuing with reference to Figure 7, in the same test assembly, that is, in a single test assembly area TGA, the first spacing distance W1 of the two columns of test elements arranged along the first direction D1 along the first direction D1 needs to meet certain design requirements. Specifically, when forming each test element by utilizing the evaporation process of FMM, due to factors such as processing accuracy, a single test element has a certain processing accuracy error, and a single margin deviation needs to be reserved for each test element on each side. Based on this, the first spacing distance W1 can be greater than or equal to 150 microns, so that it can be ensured that the adjacent two-side test elements do not overlap. Furthermore, the first spacing distance W1 can be less than or equal to 390 microns, so that it can be ensured that the two columns of test elements can be arranged within the range of a single test assembly area TGA.

[0135] Continuing with FIG7 , the n rows of test elements include the kth row of test elements and the k+1th row of test elements adjacent to the reference mark 7, or, in other words, the kth row of test elements and the k+1th row of test elements adjacent to the second calibration mark 9. The kth row of test elements and the k+1th row of test elements are spaced a second distance H2 apart in the second direction D2, where 1 ≤ k ≤ n-1 and k is a positive integer. For example, in the embodiment of FIG7 , k = 2, meaning that the second row of test elements and the third row of test elements are spaced a second distance H2 apart in the second direction D2.

[0136] The test elements in the p-th row and the test elements in the p+1-th row are spaced apart by a third distance H3 in the second direction D2, where 1≤p≤n-1, p is a positive integer, and p is not equal to k. For example, in the embodiment of FIG7 , p may be equal to 1, i.e., the test elements in the 1st row and the test elements in the 2nd row are spaced apart by the third distance H3 in the second direction D2; p may be equal to 3, i.e., the test elements in the 3rd row and the test elements in the 4th row are spaced apart by the third distance H3 in the second direction D2.

[0137] In the embodiment of the present disclosure, the second spacing distance H2 is greater than the third spacing distance H3. Specifically, the second spacing distance H2 is more than twice the third spacing distance H3. This design, on the one hand, provides a relatively large space for arranging a row of second calibration marks 9, and on the other hand, allows each row of test elements to be arranged relatively compactly in the second direction, facilitating the arrangement of multiple rows of test elements in the test assembly area TGA.

[0138] Continuing with reference to FIG7 , the first imaginary straight line L1 extends along the second direction D2 and passes through the reference point 7O, the second imaginary straight line L2 extends along the second direction D2 and passes through the centers of at least two test elements in a column of test elements (for example, the first column of test elements on the left), and the third imaginary straight line L3 extends along the second direction D2 and passes through the centers of at least two test elements in another column of test elements (for example, the second column of test elements on the right).

[0139] In an embodiment of the present disclosure, the first distance WD1 between the second imaginary straight line L2 and the first imaginary straight line L1 in the first direction D1 is basically equal to the second distance WD2 between the third imaginary straight line L3 and the first imaginary straight line L1 in the first direction D1, or in other words, the ratio of the first distance WD1 to the second distance WD2 is between 0.8 and 1.2.

[0140] Continuing with reference to Figure 7, the fourth imaginary straight line L4 extends along the first direction D1 and passes through the reference point 7O, the fifth imaginary straight line L5 extends along the first direction D1 and passes through the center of a row of test elements adjacent to the reference mark 7 (for example, the second row of test elements), and the sixth imaginary straight line L6 extends along the first direction D1 and passes through the center of another row of test elements adjacent to the reference mark 7 (for example, the third row of test elements).

[0141] In an embodiment of the present disclosure, the third distance WD3 between the fifth imaginary straight line L5 and the fourth imaginary straight line L4 in the second direction D2 is basically equal to the fourth distance WD4 between the sixth imaginary straight line L6 and the fourth imaginary straight line L4 in the second direction D2, or in other words, the ratio of the third distance WD3 to the fourth distance WD4 is between 0.8 and 1.2.

[0142] FIG. 8 is a partially enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure.

[0143] As shown in FIG8 , at least one test assembly includes q columns of test elements arranged along a first direction D1 and n rows of test elements arranged along a second direction, where q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4. For example, q=2, n=5.

[0144] For example, in some embodiments, a first sub-compensation layer disposed on the side of the first light-emitting layer EML1 close to the base substrate can be located in the first sub-pixel SP1 and the second sub-pixel SP2. A second sub-compensation layer disposed on the side of the second light-emitting layer EML2 close to the base substrate can be located in the first sub-pixel SP1 and the second sub-pixel SP2. In other words, the luminous intensity of the red and green sub-pixels can be increased to offset the loss during transmission.

[0145] In the embodiment shown in FIG8 , the plurality of test elements 3 may be test elements of multiple colors. For ease of description, the test elements of multiple colors are labeled as test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, 34R, 33G, and 34G. Test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, 34R, 33G, and 34G correspond to the sub-luminescent layer 51R, 52R, 51G, 52G, 51B, and 52B formed by the evaporation process, respectively; the first sub-compensation layer portion located in the first sub-pixel; the second sub-compensation layer portion located in the first sub-pixel; the first sub-compensation layer portion located in the second sub-pixel; and the second sub-compensation layer portion located in the second sub-pixel.

[0146] 7 and 8 , the size of the test assembly area TGA, the size of the test elements themselves, and the spacing distances between the test elements may remain unchanged.

[0147] The reference mark 7 is located approximately in the center of the test assembly area TGA. In the first direction D1, the reference mark 7 is located between two adjacent columns of test elements; in the second direction D2, the reference mark 7 is located between two adjacent rows of test elements.

[0148] The five first calibration marks 8 correspond one-to-one with the five rows of test elements. Specifically, the five first calibration marks 8 are located between two adjacent columns of test elements in the first direction D1. That is, in the first direction D1, the i-th first calibration mark 8 is located between the first and second test elements in the i-th row of test elements, where 1 ≤ i ≤ 5 and i is a positive integer. This arrangement allows the positional accuracy of multiple test elements in a row to be detected using a single first calibration mark, while also achieving a compact arrangement of multiple test elements and the first calibration marks.

[0149] As shown in FIG8 , five first calibration marks 8 are provided in a test assembly area TGA, wherein three first calibration marks 8 are located above the reference mark 7 in the second direction, and the other two first calibration marks 8 are located below the reference mark 7 in the second direction.

[0150] The two second calibration marks 9 correspond one-to-one with the two columns of test elements. Specifically, in the first direction D1, the jth second calibration mark 9 is aligned with the jth column of test elements; in the second direction D2, the jth second calibration mark 9 is located between two adjacent test elements in the jth column of test elements. Where 1 ≤ j ≤ 2, and j is a positive integer. This arrangement allows the positional accuracy of multiple test elements in a column to be detected using a single second calibration mark, while also achieving a compact arrangement of multiple test elements and second calibration marks.

[0151] As shown in Figure 8, two second calibration marks 9 are set in a test component area TGA, wherein, in the second direction D2, the two second calibration marks 9 are located between the third row of test elements and the fourth row of test elements; in the first direction D1, one second calibration mark 9 is located on the left side of the reference mark 7, and the other second calibration mark 9 is located on the right side of the reference mark 7.

[0152] In an embodiment of the present disclosure, multiple test elements are prepared by utilizing the evaporation process of FMM, and the test elements need to be within the field of view of the CCD of the test equipment when in use. Based on this, while the size of a single test component area TGA remains unchanged, the arrangement, size, and spacing distance of the multiple test elements in the test component area TGA need to be designed.

[0153] FIG. 9 is a partially enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure.

[0154] As shown in FIG9 , at least one test assembly includes q columns of test elements arranged along a first direction D1 and n rows of test elements arranged along a second direction D2 , where q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4. For example, q=2, n=6.

[0155] 7 , 8 and 9 , compared to FIG7 and FIG8 , the size of the test component area TGA in FIG9 remains unchanged, and the size of the test elements themselves and at least a portion of the spacing distance between the test elements can be reduced so that multiple elements arranged in 6 rows and 2 columns can be arranged in a single test component area TGA of unchanged size.

[0156] The reference mark 7 is located approximately in the center of the test assembly area TGA. In the first direction D1, the reference mark 7 is located between two adjacent columns of test elements; in the second direction D2, the reference mark 7 is located between two adjacent rows of test elements.

[0157] The six first calibration marks 8 correspond one-to-one with the six rows of test elements. Specifically, the six first calibration marks 8 are located between two adjacent columns of test elements in the first direction D1. That is, in the first direction D1, the i-th first calibration mark 8 is located between the first and second test elements in the i-th row of test elements, where 1 ≤ i ≤ 6 and i is a positive integer. This arrangement allows the positional accuracy of multiple test elements in a row to be detected using a single first calibration mark, while also achieving a compact arrangement of multiple test elements and the first calibration marks.

[0158] As shown in FIG9 , six first calibration marks 8 are provided in a test assembly area TGA, wherein three first calibration marks 8 are located above the reference mark 7 in the second direction, and the other three first calibration marks 8 are located below the reference mark 7 in the second direction.

[0159] The two second calibration marks 9 correspond one-to-one with the two columns of test elements. Specifically, in the first direction D1, the jth second calibration mark 9 is aligned with the jth column of test elements; in the second direction D2, the jth second calibration mark 9 is located between two adjacent test elements in the jth column of test elements. Where 1 ≤ j ≤ 2, and j is a positive integer. This arrangement allows the positional accuracy of multiple test elements in a column to be detected using a single second calibration mark, while also achieving a compact arrangement of multiple test elements and second calibration marks.

[0160] As shown in Figure 9, two second calibration marks 9 are set in a test component area TGA, wherein, in the second direction D2, the two second calibration marks 9 are located between the third row of test elements and the fourth row of test elements; in the first direction D1, one second calibration mark 9 is located on the left side of the reference mark 7, and the other second calibration mark 9 is located on the right side of the reference mark 7.

[0161] In an embodiment of the present disclosure, multiple test elements are prepared by utilizing the evaporation process of FMM, and the test elements need to be within the field of view of the CCD of the test equipment when in use. Based on this, while the size of a single test component area TGA remains unchanged, the arrangement, size, and spacing distance of the multiple test elements in the test component area TGA need to be designed.

[0162] 10A and 10B are respectively partial enlarged views of a test component area in a display substrate according to further exemplary embodiments of the present disclosure.

[0163] In the case that a single test assembly includes a large number of test elements, a plurality of test assembly areas may be provided for arranging the large number of test elements.

[0164] As shown in FIG10A , the display substrate 100 includes two adjacent test assembly areas TGA, with the test assemblies in the two test assembly areas TGA arranged side by side along a first direction D1. For example, the arrangement of the multiple test elements in each test assembly area TGA can refer to the description of FIG7 , FIG8 , and FIG9 above, and will not be repeated here.

[0165] As shown in FIG10B , the display substrate 100 includes two adjacent test assembly areas TGA, with the test assemblies in the two test assembly areas TGA arranged side by side along a second direction D1. For example, the arrangement of the multiple test elements in each test assembly area TGA can refer to the description of FIG7 , FIG8 , and FIG9 above, and will not be repeated here.

[0166] FIG. 11 is a schematic plan view of a display substrate according to further exemplary embodiments of the present disclosure.

[0167] In an embodiment of the present disclosure, a plurality of test assemblies 2 are respectively disposed adjacent to the first side AA1, the second side AA2, the third side AA3, the fourth side AA4, the first corner AC1, the second corner AC2, the third corner AC3, and the fourth corner AC4. For example, referring to FIG5 and FIG11 , eight test assemblies 2 are schematically illustrated. One test assembly 2 is disposed adjacent to the first side AA1, and one test assembly 2 is disposed adjacent to each of the first side AA1, the second side AA2, the third side AA3, the fourth side AA4, the first corner AC1, the second corner AC2, the third corner AC3, and the fourth corner AC4.

[0168] As shown in Figure 5 , the display substrate 100 includes a driver chip IC positioned adjacent to the first side AA1. At least one test component 2 positioned adjacent to the first side AA1 is located between the driver chip IC and the first side AA1 of the display area. The inventors have discovered that the closer the test component is to the display area, the closer the vapor deposition conditions of the test component closely resemble those of the various film layers within the display area. In this embodiment, the closer the test components 2 are to the display area AA, enabling more accurate detection of pixel position accuracy within the display area.

[0169] Optionally, as shown in FIG11 , at least one of the test components 2 disposed adjacent to the first side AA1 is located on a side of the driver chip IC away from the first side AA1 of the display area AA.

[0170] FIG. 12 is a schematic structural diagram of a testing device for detecting pixel position accuracy of a display substrate according to some exemplary embodiments of the present disclosure.

[0171] As shown in Figure 12, the testing device 200 may include a white light source 210 and an ultraviolet light source 220. Exemplarily, the testing method may be performed according to the following steps.

[0172] In step S110 , the testing device 200 is moved above the testing component area TGA of the display substrate 100 , and the white light source 210 is turned on to illuminate the testing component area TGA to obtain a first image of the testing component area TGA under white light illumination.

[0173] Specifically, when the test device 200 is moved above the test component area TGA, the test device 200 may be aligned with the reference mark 7 in the test component area TGA, so that the position of the test device 200 is calibrated by the reference mark 7 .

[0174] In this step, grayscale processing may be performed on the first image to obtain the outline of each test element.

[0175] In step S120 , the white light source 210 of the testing device 200 is turned off.

[0176] In step S130, the test component area TGA is illuminated. For example, the ultraviolet light source 220 on the test device 200 is turned on to activate the test element to emit light under the irradiation of ultraviolet light, and a second image of the test component area under the irradiation of ultraviolet light is obtained. The contour pattern of the test element can be obtained in the second image.

[0177] In step S140 , the pixel position accuracy of the display substrate 100 is detected according to the first image and the second image.

[0178] With reference to Figures 7 to 10B , specifically, an image processing algorithm can be used to obtain the outlines of the first calibration mark 7, the second calibration mark 8, and the test element 3. For example, consider test element 31R in Figure 7 . Imaginary lines 7L and 8L extending toward test element 31R are obtained for the outlines of the first calibration mark 7 and the second calibration mark 8, respectively. The intersection O1 of these imaginary lines 7L and 8L is the theoretical center of test element 31R. Next, the two symmetry axes AX1 and AX2 of the outline of test element 31R are obtained. The intersection O2 of these two symmetry axes AX1 and AX2 is the actual center of test element 31R. Since test device 200 is aligned with reference mark 7, a Cartesian coordinate system can be established, selecting reference mark 7 as the origin. The coordinates of intersection points O1 and O2 can be obtained. Based on this, the horizontal and vertical offsets ΔX and ΔY of intersection point O2 relative to intersection point O1 can be determined, i.e., the offset of the test element. A larger offset of the test element indicates a lower pixel position accuracy; a smaller offset of the test element indicates a higher pixel position accuracy.

[0179] The present disclosure also provides a display device, which may include the display substrate described in any of the above embodiments. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0180] It should be understood that the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, and the beneficial effects of the display device are the same as the beneficial effects of the above-mentioned display substrate, which will not be repeated here.

[0181] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A display substrate, characterized in that: include: A base substrate, the base substrate comprising a display area and a test component area; A plurality of pixel units are provided on the substrate, the plurality of pixel units are arranged in an array in the display area along a first direction and a second direction, at least one of the pixel units comprises a plurality of light emitting elements stacked along a third direction, the plurality of light emitting elements stacked along the third direction comprises: a charge generation layer provided on the substrate; a first light emitting layer provided on a side of the charge generation layer close to the substrate; and a second light emitting layer provided on a side of the charge generation layer away from the substrate, wherein the first direction intersects with the second direction, and the third direction is perpendicular to the first direction and the second direction; and At least one test component is disposed on the substrate, the at least one test component is located in the test component area, the at least one test component includes a plurality of test elements, and the plurality of test elements are arranged in an array in the test component area along a first direction and a second direction, wherein the plurality of test elements include a first test element and a second test element, the first test element and the first light-emitting layer include the same material, the second test element and the second light-emitting layer include the same material, and the first test element and the second test element are located in two rows; and The display substrate further includes a first calibration mark disposed on the base substrate, the first calibration mark is located in the test component area, and the first calibration mark is located between two adjacent rows of test elements.

2. The display substrate according to claim 1, wherein: The first light-emitting layer includes a first sub-light-emitting layer of multiple colors, the at least one test component includes a first test element of multiple colors, and the first test element of multiple colors and the first sub-light-emitting layer of multiple colors include the same material; The second light-emitting layer includes a second sub-light-emitting layer of a plurality of colors, the at least one test component includes a second test element of a plurality of colors, and the second test element of the plurality of colors and the second sub-light-emitting layer of the plurality of colors include the same material; and The test component area has a rectangular shape, and has a first dimension along a first direction and a second dimension along a second direction, the first dimension is smaller than the second dimension, and in the same test component, the first test element and the second test element of the same color are located in two columns arranged along the first direction, and the first test element and the second test element of the same color are located in a row extending along the first direction.

3. The display substrate according to claim 2, wherein: In the same test assembly, the first test elements of different colors are located in the same column extending along the second direction; and / or, In the same test assembly, the second test elements of different colors are located in the same column extending along the second direction.

4. The display substrate according to any one of claims 1 to 3, characterized in that: The plurality of light emitting elements stacked along the third direction further include: a first compensation layer disposed on a side of the first light emitting layer close to the base substrate; and a second compensation layer disposed on a side of the second light emitting layer close to the base substrate; and The plurality of test elements further include a third test element and a fourth test element, the third test element and the first compensation layer include the same material, the fourth test element and the second compensation layer include the same material, and the third test element and the fourth test element are located in two rows.

5. The display substrate according to claim 4, wherein: The first compensation layer and the second compensation layer are of the same color, and the third test element and the fourth test element are located in the same row extending along the first direction.

6. The display substrate according to any one of claims 2 to 5, characterized in that: In the same test assembly, the first test element and the third test element of different colors are located in the same column extending along the second direction; and / or, In the same test assembly, the second test elements and the fourth test elements of different colors are located in the same column extending along the second direction.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The display substrate further comprises a reference mark disposed on the base substrate, wherein the reference mark is located in the test component area, and the reference mark is located between two adjacent columns of test elements in a first direction.

8. The display substrate according to claim 7, wherein: The reference mark is located between two adjacent rows of test elements in the second direction.

9. The display substrate according to claim 7, wherein: The display substrate further includes a second calibration mark disposed on the base substrate, the second calibration mark is located in the test component area, the second calibration mark extends along a second direction, and the second calibration mark is located between two adjacent rows of test elements in the second direction.

10. The display substrate according to claim 1, wherein: At least one of the test components includes q columns of test elements arranged along the first direction and n rows of test elements arranged along the second direction, wherein q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4.

11. The display substrate according to claim 10, wherein: In the same test assembly, a first spacing distance between two adjacent columns of test elements arranged along the first direction is greater than or equal to 150 micrometers; and / or, In the same test assembly, a first spacing distance between two adjacent columns of test elements arranged along the first direction is less than or equal to 390 micrometers.

12. The display substrate according to claim 10 or 11, characterized in that: The reference mark includes a first reference mark portion extending along a first direction and a second reference mark portion extending along a second direction, wherein the first reference mark portion and the second reference mark portion intersect at a reference point; as well as A first imaginary straight line extends along the second direction and passes through the reference point, a second imaginary straight line extends along the second direction and passes through the centers of at least two test elements in a column of test elements, a third imaginary straight line extends along the second direction and passes through the centers of at least two test elements in another column of test elements, and a ratio of a first distance in the first direction between the second imaginary straight line and the first imaginary straight line to a second distance in the first direction between the third imaginary straight line and the first imaginary straight line is between 0.8 and 1.

2.

13. The display substrate according to claim 12, wherein: A fourth imaginary straight line extends along the first direction and passes through the reference point, a fifth imaginary straight line extends along the first direction and passes through the center of a row of test elements adjacent to the reference mark, a sixth imaginary straight line extends along the first direction and passes through the center of another row of test elements adjacent to the reference mark, and a ratio of a third distance between the fifth imaginary straight line and the fourth imaginary straight line in the second direction to a fourth distance between the sixth imaginary straight line and the fourth imaginary straight line in the second direction is between 0.8 and 1.

2.

14. The display substrate according to any one of claims 10 to 13, characterized in that: The display substrate includes n first calibration marks, and in a first direction, the i-th first calibration mark is located between the first test element and the second test element in the i-th row of test elements, wherein 1≤i≤n and i is a positive integer.

15. The display substrate according to claim 14, wherein: The display substrate includes q second calibration marks, and one of the q second calibration marks in the second direction is located between two first test elements in the first column.

16. The display substrate according to claim 14, wherein: The n rows of test elements include a kth row of test elements and a k+1th row of test elements adjacent to the reference mark, and the kth row of test elements and the k+1th row of test elements have a second spacing distance in the second direction, wherein 1≤k≤n-1 and k is a positive integer; The test elements in the pth row and the test elements in the p+1th row have a third spacing distance in the second direction, wherein 1≤p≤n-1 and p is a positive integer, and p is not equal to k; and The second spacing distance is greater than the third spacing distance.

17. The display substrate according to claim 16, wherein: The second spacing distance is more than twice the third spacing distance.

18. The display substrate according to any one of claims 1 to 17, characterized in that: The display area of ​​the display substrate includes a first side, a second side, a third side, a fourth side, a first corner, a second corner, a third corner and a fourth corner, wherein the first corner, the second corner, the third corner and the fourth corner are respectively located at the connection of two adjacent sides among the first side, the second side, the third side and the fourth side; as well as The display substrate includes a plurality of the test components, and the plurality of the test components are respectively disposed adjacent to the first side, the second side, the third side, the fourth side, the first corner, the second corner, the third corner, and the fourth corner.

19. The display substrate according to claim 18, wherein: The display substrate includes a driving chip disposed adjacent to the first side edge, and at least one of the testing components disposed adjacent to the first side edge is located between the driving chip and the first side edge of the display area.

20. The display substrate according to claim 18, wherein: The display substrate includes a driving chip disposed adjacent to the first side, and at least one of the testing components disposed adjacent to the first side is located on a side of the driving chip away from the first side of the display area.

21. The display substrate according to any one of claims 1 to 20, characterized in that: The display substrate comprises two adjacent test component areas, and the test components in the two test component areas are arranged side by side along a first direction; and / or, The display substrate includes two adjacently arranged test component areas, and the test components in the two test component areas are arranged side by side along the second direction.

22. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 21.

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