Pixel drive circuit and driving method therefor, and array substrate and display panel

Abstract

Disclosed is a pixel drive circuit. The pixel drive circuit comprises a drive sub-circuit, a light-emission control sub-circuit, a writing sub-circuit, a compensation sub-circuit and a storage sub-circuit, wherein the drive sub-circuit is coupled to a first node, a second node and a third node; the light-emission control sub-circuit comprises a first branch, and the first branch is coupled to a first power supply signal line, a first enable signal line and the second node; the compensation sub-circuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node and a second power supply signal line; the writing sub-circuit is coupled to a third scanning signal line, a data writing signal line and the fourth node; and the storage sub-circuit is coupled to the first node and the fourth node.

Description

Pixel driving circuit and driving method thereof, array substrate and display panel

[0001] This application claims priority to Chinese patent application No. 202310945825.X filed on July 28, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, an array substrate, and a display panel. Background Art

[0003] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display.

[0004] Summary of the Invention

[0005] In one aspect, a pixel driving circuit is provided. The pixel driving circuit includes a driving subcircuit, a light-emission control subcircuit, a writing subcircuit, a compensation subcircuit, and a storage subcircuit. The driving subcircuit is coupled to a first node, a second node, and a third node, and is configured to, under the control of the voltage at the first node, transmit the voltage from the second node to the third node. The light-emission control subcircuit includes a first branch, the first branch coupled to a first power signal line, a first enable signal line, and a second node. The first branch is configured to, during a compensation phase, cooperate with the driving subcircuit under the control of a first enable signal from the first enable signal line to transmit a first power signal received at the first power signal line to the third node. The compensation subcircuit is coupled to a first scan signal line, a second scan signal line, the first node, the third node, a fourth node, and a second power signal line. The compensation sub-circuit is configured to, during a compensation phase, transfer the voltage of the third node to the first node under control of a first scan signal received from the first scan signal line, and to transfer the second power signal received from the second power signal line to the fourth node under control of a second scan signal received from the second scan signal line. The write sub-circuit is coupled to the third scan signal line, a data write signal line, and the fourth node. The write sub-circuit is configured to, during a write phase, transfer the data write signal received from the data write signal line to the fourth node under control of a third scan signal received from the third scan signal line. The storage sub-circuit is coupled to the first node and the fourth node. During the write phase, the storage sub-circuit is configured to couple the voltage of the fourth node to the first node.

[0006] In some embodiments, the driving subcircuit includes a driving transistor, a control electrode of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

[0007] In some embodiments, the compensation sub-circuit includes a second transistor and a ninth transistor. The control electrode of the second transistor is coupled to the first scan signal line, the first electrode of the second transistor is coupled to the third node, and the second electrode of the second transistor is coupled to the first node. The control electrode of the ninth transistor is coupled to the third scan signal line, the first electrode of the ninth transistor is coupled to the second power signal line, and the second electrode of the ninth transistor is coupled to the fourth node.

[0008] In some embodiments, the write sub-circuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the third scan signal line, a first electrode of the fourth transistor is coupled to the data write signal line, and a second electrode of the fourth transistor is coupled to the fourth node.

[0009] In some embodiments, the storage sub-circuit includes a storage capacitor, a first plate of the storage capacitor is coupled to the fourth node, and a second plate of the storage capacitor is coupled to the first node.

[0010] In some embodiments, the light-emission control subcircuit further includes a second branch coupled to the third node, the second enable signal line, and the light-emitting device. During a light-emission phase, the light-emission control subcircuit is configured to, under the control of a first enable signal from the first enable signal line and a second enable signal from the second enable signal line, cooperate with the driver subcircuit to transmit the first power signal received from the first power signal line to the light-emitting device.

[0011] In some embodiments, the first branch includes a fifth transistor, a control electrode of the fifth transistor is coupled to the first enable signal line, a first electrode of the fifth transistor is coupled to the first power signal line, and a second electrode of the fifth transistor is coupled to the second node. The second branch includes a sixth transistor, a control electrode of the sixth transistor is coupled to the second enable signal line, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the light-emitting device.

[0012] In some embodiments, the pixel driving circuit further includes a first reset subcircuit. The first reset subcircuit is coupled to the first node, a first reset signal line, and a first initialization signal line. The first reset subcircuit is configured to, under control of a first reset signal received from the first reset signal line, transmit the first initialization signal received from the first initialization signal line to the first node, thereby resetting the first node.

[0013] In some embodiments, the first reset sub-circuit includes a first transistor, a control electrode of the first transistor is coupled to the first reset signal line, a first electrode of the first transistor is coupled to the first initialization signal line, and a second electrode of the first transistor is coupled to the first node.

[0014] In some embodiments, the pixel driving circuit further includes a second reset subcircuit. The second reset subcircuit is coupled to the light-emitting device, a second reset signal line, and a second initialization signal line. The second reset subcircuit is configured to, under control of a second reset signal received from the second reset signal line, transmit the second initialization signal received from the second initialization signal line to the light-emitting device, thereby resetting the light-emitting device.

[0015] In some embodiments, the second reset subcircuit includes a seventh transistor, a control electrode of the seventh transistor is coupled to the second reset signal line, a first electrode of the seventh transistor is coupled to the second initialization signal line, and a seventh electrode of the eighth transistor is coupled to the light emitting device.

[0016] In some embodiments, the pixel driving circuit further includes a third reset subcircuit. The third reset subcircuit is coupled to the second node, a third reset signal line, and a first reference voltage signal line. The third reset subcircuit is configured to, under control of a third reset signal received from the third reset signal line, transmit the first reference voltage signal received from the first reference voltage signal line to the second node, thereby resetting the second node.

[0017] In some embodiments, the third reset sub-circuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the third reset signal line, a first electrode of the eighth transistor is coupled to the first reference voltage signal line, and a second electrode of the eighth transistor is coupled to the second node.

[0018] In some embodiments, the voltage value of the first power signal is equal to the voltage value of the second power signal.

[0019] In some embodiments, the first power signal line is multiplexed as the second power signal line.

[0020] In some embodiments, when the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is a dual-gate transistor.

[0021] In some embodiments, when the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is an N-type transistor.

[0022] On the other hand, a driving method for a pixel driving circuit is provided. The pixel driving circuit includes: a driving subcircuit, a light-emitting control subcircuit, a writing subcircuit, a compensation subcircuit, and a storage subcircuit. The driving subcircuit is coupled to a first node, a second node, and a third node. The light-emitting control subcircuit includes a first branch, and the first branch is coupled to a first power signal line, a first enable signal line, and a second node. The compensation subcircuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node, a first power signal line, and a second power signal line. The voltage value of the first power signal is equal to the voltage value of the second power signal. The writing subcircuit is coupled to a third scanning signal line, a data writing signal line, and the fourth node. The storage subcircuit is coupled to the first node and the fourth node.

[0023] The driving method includes a compensation phase and a write phase. During the compensation phase, the first branch, under the control of a first enable signal from the first enable signal line, cooperates with the driving sub-circuit to transmit the first power signal received at the first power signal line to the third node. The compensation sub-circuit, under the control of a first scan signal received from the first scan signal line, transmits the voltage of the third node to the first node; and, under the control of a second scan signal received from the second scan signal line, transmits the second power signal received from the second power signal line to the fourth node. Furthermore, the storage sub-circuit receives the voltage of the first node and the voltage of the fourth node. During the write phase, the write sub-circuit, under the control of a third scan signal received from the third scan signal line, transmits the data write signal received from the data write signal line to the fourth node. Furthermore, the storage sub-circuit couples the voltage of the fourth node to the first node.

[0024] In some embodiments, the pixel driving circuit further includes a third reset subcircuit coupled to the second node, a third reset signal line, and a first reference voltage signal line. The driving method further includes a first reset phase. During the first reset phase, the third reset subcircuit, under control of a third reset signal received from the third reset signal line, transmits the first reference voltage signal received from the first reference voltage signal line to the second node, thereby resetting the second node.

[0025] In some embodiments, the pixel driving circuit further includes a first reset subcircuit coupled to the first node, a first reset signal line, and a first initialization signal line. The driving method further includes a first initialization phase. During the first initialization phase, the first reset subcircuit, under control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node, thereby initializing the first node.

[0026] In some embodiments, the driving method further includes a second initialization phase. During the second initialization phase, the first reset sub-circuit, under control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node. The compensation sub-circuit, under control of a first scan signal received from the first scan signal line, transmits the voltage of the first node to the third node. Furthermore, the driving sub-circuit, under control of the voltage of the first node, transmits the voltage from the second node to the third node, thereby initializing the first, second, and third nodes.

[0027] In another aspect, an array substrate is provided, comprising a substrate and a plurality of pixel driving circuits as described in any one of the above embodiments located on the substrate.

[0028] In some embodiments, the plurality of pixel driving circuits are arranged in multiple rows and columns. The array substrate further includes: a plurality of first scanning signal lines, a plurality of second scanning signal lines, and a plurality of first reset signal lines. The plurality of first scanning signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The second direction intersects with the first direction. The plurality of second scanning signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The plurality of first reset signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. Among them, the second scanning signal line coupled to the pixel driving circuit in the nth row, the first scanning signal line coupled to the pixel driving circuit in the n+3th row, and the first reset signal line coupled to the pixel driving circuit in the n+6th row respond to the control of the same control signal, and n is a positive integer.

[0029] In another aspect, a display panel is provided, comprising a light-emitting device layer and the array substrate according to any one of the above embodiments, wherein the light-emitting device layer comprises a plurality of light-emitting devices, and the pixel driving circuit is coupled to the light-emitting devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0031] FIG1 is a structural diagram of a display device according to some embodiments;

[0032] FIG2 is a structural diagram of a display panel according to some embodiments;

[0033] FIG3 is a cross-sectional view of a display panel according to some embodiments;

[0034] FIG4 is a structural diagram of an array substrate according to some embodiments;

[0035] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to some possible implementation schemes;

[0036] FIG6 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0037] FIG7 is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments;

[0038] FIG8 is an equivalent circuit diagram of a pixel driving circuit according to yet other embodiments;

[0039] FIG9 is an equivalent circuit diagram of a pixel driving circuit according to yet other embodiments;

[0040] FIG10 is an equivalent circuit diagram of a pixel driving circuit according to yet other embodiments;

[0041] FIG11 is a timing diagram of a pixel driving circuit according to some embodiments;

[0042] FIG12 is a timing diagram of a pixel driving circuit according to some other embodiments;

[0043] FIG13 is a structural diagram of an array substrate according to some other embodiments;

[0044] FIG14 is a timing diagram of a pixel driving circuit according to yet other embodiments;

[0045] FIG15 is a timing diagram of a pixel driving circuit according to yet other embodiments. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0053] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "perpendicular" includes the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable range of deviation, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes both absolute perpendicularity and approximately perpendicularity, where the acceptable range of deviation for approximately perpendicularity can be, for example, within 5°.

[0057] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0059] In the circuit structure provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0060] In the circuit structure provided in the embodiments of the present disclosure, the first electrode of each transistor is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be structurally symmetrical, the source and drain can be structurally identical. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally identical.

[0061] FIG1 is a structural diagram of a display device according to some embodiments. Referring to FIG1 , some embodiments of the present disclosure provide a display device 300 , which includes a display panel 200 .

[0062] Exemplarily, the display device 300 further includes a frame and other electronic accessories.

[0063] Exemplarily, the display device 300 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0064] Exemplarily, the display device 300 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0065] FIG. 2 is a structural diagram of a display panel according to some embodiments, and FIG. 3 is a cross-sectional diagram of a display panel according to some embodiments.

[0066] Some embodiments of the present disclosure provide a display panel 200. As shown in Figures 2 and 3 , the display panel 200 includes an active area (AA), also known as an effective display area. The active area AA includes multiple sub-pixel regions P, which can be arranged in an array. A sub-pixel region P is the smallest unit used by the display panel 200 for displaying images.

[0067] In some examples, a sub-pixel region P includes a pixel driver circuit Q and a light-emitting device O electrically connected to the pixel driver circuit Q. The pixel driver circuit Q can be adjusted based on a variety of different signal lines to generate a drive signal, and each light-emitting device O can emit light under the drive signal generated by the corresponding pixel driver circuit Q. Based on this, the pixel driver circuits Q in multiple sub-pixel regions can drive the corresponding light-emitting devices O to emit light, so that the display panel 200 can display a predetermined image in the display area AA. Specifically, the multiple sub-pixel regions P can include multiple sub-pixel regions P with different luminescent colors.

[0068] For example, the plurality of sub-pixel regions P may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first sub-pixel region, the second sub-pixel region, and the third sub-pixel region each emit three primary colors of light. For example, the first sub-pixel region may emit red light, the second sub-pixel region may emit green light, and the third sub-pixel region may emit blue light. Based on this, by adjusting the brightness (grayscale) of the sub-pixel regions P of different colors, a multi-color display can be achieved through color combination and superposition, thereby achieving full-color display of the display panel 200.

[0069] Continuing with Figures 2 and 3 , the display panel 200 further includes an array substrate 100 and a light-emitting device layer 210. The array substrate 100 may include a plurality of pixel driving circuits Q. The light-emitting device layer 210 is located on one side of the array substrate 100 and includes a plurality of light-emitting devices O, which are electrically connected to the pixel driving circuits Q in the array substrate 100.

[0070] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer stacked in sequence. In some examples, an electron transport layer is further provided between the cathode layer and the light-emitting layer, and a hole transport layer is further provided between the anode layer and the light-emitting layer. Exemplarily, the light-emitting device O may be an OLED light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device, that is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light by discharge), as long as they can emit light so that the display panel 200 can display a picture.

[0071] In some examples, the plurality of pixel driving circuits Q and the plurality of light-emitting devices O may be coupled in a one-to-one correspondence. In other examples, one pixel driving circuit Q may be coupled to multiple light-emitting devices O, or multiple pixel driving circuits Q may be coupled to one light-emitting device O.

[0072] Below, the present disclosure takes the coupling of one pixel driving circuit Q and one light-emitting device O as an example to schematically illustrate the structure of the display panel 200 .

[0073] FIG. 4 is a structural diagram of an array substrate according to some embodiments.

[0074] 4 , some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 located on one side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q.

[0075] In some examples, substrate 01 may be a flexible substrate. Exemplarily, the material of substrate 01 may be an organic material. For example, the material of substrate 01 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0076] In other examples, the substrate 01 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0077] In some examples, the pixel circuit layer 02 includes multiple metal layers stacked on a substrate 01. The multiple metal layers include pixel driving circuits Q and multiple different types of signal lines. The different types of signal lines include, but are not limited to, multiple first scanning signal lines G1. The different types of signal lines may also include other types of signal lines, as described in detail below.

[0078] The plurality of pixel driving circuits Q are located on one side of the substrate 01 and are arranged in multiple rows and columns. For ease of description, the plurality of pixel driving circuits Q are described in this disclosure as being arranged in a matrix.

[0079] At this time, returning to FIG. 2 , the pixel driving circuits Q arranged in a row along the first direction X are called a row of pixel driving circuits Q, and the pixel driving circuits Q arranged in a row along the second direction Y are called a column of pixel driving circuits Q.

[0080] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit according to some possible implementation schemes.

[0081] 5 , the pixel driving circuit Q may be a first type of pixel driving circuit. The first type of pixel driving circuit includes a first reset transistor M1, a compensation transistor M2, a driving transistor M3, a data writing transistor M4, a first emission control transistor M5, a second emission control transistor M6, a second reset transistor M7, and a capacitor Cst.

[0082] Because the first pixel driving circuit needs to be electrically connected to multiple different types of signal lines, multiple different types of signal lines are also shown in Figure 5. The multiple different types of signal lines may include: a first scanning signal line G1, a second scanning signal line G2, a data write signal line Data, an enable signal line EM, a first power signal line Vdd, a first reset signal line R1, a second reset signal line R2, a first initialization signal line Vinit1, and a second initialization signal line Vinit2.

[0083] The control electrode of the first reset transistor M1 is coupled to the first reset signal line R1 , the first electrode of the first reset transistor M1 is coupled to the first initialization signal line Vinit1 , and the second electrode of the first reset transistor M1 is coupled to the first node N1 .

[0084] A control electrode of the compensation transistor M2 is coupled to the first scan signal line Gate1 , a first electrode of the compensation transistor M2 is coupled to the first node N1 , and a second electrode of the compensation transistor M2 is coupled to the third node N3 .

[0085] A control electrode of the driving transistor M3 is coupled to the first node N1 , a first electrode of the driving transistor M3 is coupled to the second node N2 , and a second electrode of the driving transistor M3 is coupled to the third node N3 .

[0086] A control electrode of the data writing transistor M4 is coupled to the second scanning signal line Gate2 , a first electrode of the data writing transistor M4 is coupled to the data writing signal line Data, and a second electrode of the data writing transistor M4 is coupled to the second node N2 .

[0087] A control electrode of the first emission control transistor M5 is coupled to the enable signal line EM, a first electrode of the first emission control transistor M5 is coupled to the first power signal line VDD, and a second electrode of the first emission control transistor M5 is coupled to the second node N2.

[0088] A control electrode of the second light-emitting control transistor M6 is coupled to the enable signal line EM, a first electrode of the second light-emitting control transistor M6 is coupled to a third node N3, and a second electrode of the second light-emitting control transistor M6 is coupled to one end of the light-emitting device O. The other end of the light-emitting device O is coupled to a third power signal line VSS. The voltage value of the third power signal provided by the third power signal line VSS is lower than the voltage value of the first power signal provided by the first power signal line VDD.

[0089] Exemplarily, one end of the light emitting device O coupled to the first pixel driving circuit is the anode of the light emitting device O, and one end of the light emitting device O coupled to the third power signal point VSS is the cathode of the light emitting device O.

[0090] A control electrode of the second reset transistor M7 is coupled to the second reset signal line R2 , a first electrode of the second reset transistor M7 is coupled to the second initialization signal line Vinit2 , and a second electrode of the second reset transistor M7 is coupled to the light emitting device O.

[0091] It should be noted that each sub-pixel in the display panel 200 is driven by multiple thin-film transistors (TFTs) to emit light. Using TFT driving technology can improve display speed, contrast, brightness, and resolution. However, TFTs exhibit a hysteresis effect. The hysteresis effect of a TFT is an uncertainty in the electrical characteristics of a TFT under a certain bias voltage. That is, the current flowing through the TFT is not only related to the current bias voltage, but also to the state of the TFT at the previous moment. The hysteresis effect of a TFT is related to the TFT's gate dielectric, semiconductor material, and the interface state traps between the two. During the light-emitting phase, the hysteresis effect of the TFT will cause the current to decrease within a frame, which the human eye perceives as flicker, thereby affecting the display quality of the display panel 200.

[0092] To improve the hysteresis effect of the driving transistor M3, the threshold voltage of the pixel circuit is usually compensated to improve the brightness uniformity of the entire display screen. Specifically, the threshold voltage of the pixel circuit can be compensated when data is written.

[0093] In some embodiments, the driving process of the first pixel driving circuit shown in FIG5 is as follows: one frame period includes an initialization phase, a writing phase, and a light emitting phase.

[0094] Initialization stage: the first reset signal transmitted by the first reset signal line R1 is a valid signal. At this time, the first reset transistor M1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the third node N3, and the third node N3 is reset, so as to improve the stability of the driving transistor M3 included in the first pixel driving circuit.

[0095] Writing phase: The first scanning signal transmitted by the first scanning signal line G1 is a valid signal, and the compensation transistor M2 is turned on. Also, the second scanning signal transmitted by the second scanning signal line G2 is a valid signal, and the data writing transistor M4 is turned on. The data writing signal transmitted by the data writing signal line Data can be sequentially transmitted through the data writing transistor M4, the driving transistor M3, and the compensation transistor M2 to the first node N1, compensating the first node N1. The potential of the first node N1 gradually rises to Vdata + Vth.

[0096] Wherein, Vdata is the voltage value of the data write signal provided by the data write signal line Data, and Vth is the threshold voltage of the driving transistor M3 in the first pixel driving circuit. When the potential of the first node N1 reaches Vdata + Vth, the charging process is completed. Subsequently, the storage capacitor Cst is discharged to keep the driving transistor M3 included in the first pixel driving circuit continuously turned on, ensuring that the light-emitting device O emits light.

[0097] Light-emitting stage: The enable signal transmitted by the enable signal line EM is a valid signal, and the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned on. At this time, the storage capacitor Cst is discharged to keep the driving transistor M3 included in the first pixel driving circuit continuously turned on.

[0098] Based on this, the constant voltage power signal provided by the first power signal line Vdd can flow through the first light emission control transistor M5, the driving transistor M3, and the second light emission control transistor M6 in sequence to the anode of the light emitting device O, and the cathode of the light emitting device O can be electrically connected to the second power signal line Vss, thereby driving the light emitting device O to emit light. The first power signal line Vdd can be a high power signal line, and the third power signal line Vss can be a low power signal line.

[0099] It should be noted that a "valid signal" refers to a signal that can turn on the transistor to which it is electrically connected. For example, if the first scanning signal line G1 is electrically connected to a P-type transistor, the valid signal is a low voltage signal. Alternatively, if the first scanning signal line G1 is electrically connected to an N-type transistor, the valid signal is a high voltage signal. The same applies to other signal lines.

[0100] The inventors have found that, during the operation of the first pixel driving circuit, since the threshold compensation and data voltage writing occur in the same phase (writing phase), the threshold compensation time cannot be separated from the row cycle.

[0101] When the display panel 200 has a high resolution or is driven at a high refresh rate, the row period of the display panel 200 becomes shorter, that is, the row period of each first-type pixel driving circuit becomes shorter, which shortens the writing phase of the first-type pixel driving circuit, resulting in a shorter threshold compensation time of the first-type pixel driving circuit, poor threshold compensation effect of the pixel driving circuit, and poor display uniformity of the display panel 200.

[0102] Furthermore, when the display panel 200 is in a low grayscale image or black state, the voltage value Vdata of the data write signal provided by the data write signal line Data required by the driving transistor M3 is larger, which will result in a longer time required for data writing, thereby also causing the threshold compensation time of the first pixel driving circuit to be shorter, and the threshold compensation effect of the pixel driving circuit to be poor, which will result in poor display uniformity of the display panel 200.

[0103] FIG. 6 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.

[0104] Based on the above problems, as shown in FIG6 , some embodiments of the present disclosure provide a pixel driving circuit Q. The pixel driving circuit Q may be a second type of pixel driving circuit. The pixel driving circuit Q hereinafter all refers to the second type of pixel driving circuit.

[0105] The pixel driving circuit Q (the second type of pixel driving circuit) includes a driving sub-circuit 10 , a light emitting control sub-circuit 20 , a writing sub-circuit 30 , a compensation sub-circuit 40 and a storage sub-circuit 50 .

[0106] The driver sub-circuit 10 is coupled to the first node N1, the second node N2, and the third node N3. The driver sub-circuit 10 is configured to transmit the voltage from the second node N2 to the third node N3 under the control of the voltage of the first node N1. The driver sub-circuit 10 includes a driver transistor.

[0107] The light-emission control sub-circuit 20 includes a first branch 21 coupled to the first power signal line VDD, the first enable signal line EM1, and the second node N2. During the compensation phase, the first branch 21 is configured to cooperate with the driver sub-circuit 10 under the control of a first enable signal from the first enable signal line EM1 to transmit the first power signal received at the first power signal line VDD to the third node N3.

[0108] The compensation sub-circuit 40 is coupled to the first scan signal line Gate1, the second scan signal line Gate2, the first node N1, the third node N3, the fourth node N4, and the second power signal line VGH. During a compensation phase, the compensation sub-circuit 40 is configured to transfer the voltage of the third node N3 to the first node N1 under the control of a first scan signal received from the first scan signal line Gate1, and to transfer the second power signal received from the second power signal line VGH to the fourth node N4 under the control of a second scan signal received from the second scan signal line Gate2.

[0109] The write sub-circuit 30 is coupled to the third scan signal line Gate3, the data write signal line Date, and the fourth node N4. During a write phase, the write sub-circuit 30 is configured to transmit a data write signal received at the data write signal line Date to the fourth node N4 under the control of the third scan signal received at the third scan signal line Gate3.

[0110] The storage sub-circuit 50 is coupled to the first node N1 and the fourth node N4. In the write phase, the storage sub-circuit 50 is configured to couple the voltage of the fourth node N4 to the first node N1.

[0111] Using the above-mentioned setting method, in the compensation stage, the first enable signal of the first enable signal line EM1 is a valid signal, which controls the first branch 21 in the light-emitting control sub-circuit 20 to be turned on, the first scanning signal received at the first scanning signal line Gate1 is a valid signal, and the second scanning signal received at the second scanning signal line Gate2 is also a valid signal, which controls the compensation sub-circuit 40 to be turned on.

[0112] Based on this, the compensation sub-circuit 40 is controlled to be turned on, and the second power signal received at the second power signal line VGH can be transmitted to the fourth node N4. At this time, the voltage of the fourth node N4 is the voltage V2 of the second power signal.

[0113] Furthermore, based on controlling the compensation sub-circuit 40 to be turned on, the first branch 21 is turned on, and then cooperating with the driving sub-circuit 10 (at this time, the driving sub-circuit 10 is in the on state), the first power signal received at the first power signal line VDD can be transmitted to the first node N1 via the second node N2 and the third node N3, and the first node N1 is compensated, and the potential of the first node N1 gradually rises to V1+Vth.

[0114] Wherein, V1 is the voltage value of the first power signal provided by the first power signal line VDD, and Vth is the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the second pixel driving circuit. When the potential of the first node N1 is V1+Vth, the driving sub-circuit 10 (driving transistor T3) is turned off, completing the threshold compensation.

[0115] At the same time, since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, one end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4, and the other end of the storage sub-circuit 50 receives the voltage V1+Vth from the first node N1. The storage sub-circuit 50 determines the voltage difference between its two ends.

[0116] Subsequently, the storage capacitor Cst is discharged to keep the driving sub-circuit 10 (driving transistor T3 ) included in the second pixel driving circuit continuously turned on, so as to ensure that the light-emitting device O emits light.

[0117] After the compensation phase, when the write phase begins, the third scan signal received at the third scan signal line Gate3 becomes valid, turning on the write sub-circuit 30 and transmitting the data write signal received at the data write signal line Date to the fourth node N4. At this point, the voltage at the fourth node N4 changes from V2 to Vdata. That is, the voltage change at the fourth node N4 is Δ=Vdata-V2. Vdata is the voltage value of the data write signal provided by the data write signal line Data.

[0118] Due to the coupling effect of the storage sub-circuit 50, the voltage of the first node N1 follows the change in the voltage of the fourth node N4, and the voltage change of the first node N1 is also approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can change from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0119] During the light-emitting phase, the first enable signal on the first enable signal line EM1 is active, turning on the first branch 21 in the light-emitting control sub-circuit 20. This allows the first power signal received from the first power signal line VDD to be transmitted to the second node N2. At this point, the voltage at the second node N2 is V1. In conjunction with the driver sub-circuit 10, the voltage at the second node N2 is transmitted to the third node N3 and, ultimately, to the light-emitting device O. Furthermore, the voltage at the first node N1 remains at Vdata + Vth.

[0120] The light emitting current of the light emitting device O electrically connected to the pixel driving circuit Q is equal to the current flowing through the driving sub-circuit 10, which is expressed as follows:

[0121] Wherein, μ is the electron mobility of the driving sub-circuit 10 (driving transistor), Cox is the insulation capacitance per unit area, is the width-to-length ratio of the driving subcircuit 10 (driving transistor), Vth is the threshold voltage of the driving subcircuit 10 (driving transistor), and Vgs is the gate-source voltage of the driving subcircuit 10 (driving transistor). That is, Vgs is the difference between the voltage of the first node N1 and the voltage of the second node N2, and its expression is as follows: Vgs=V1+Vth+Vdata-V2-V1=Vth+Vdata-V2; (2);

[0122] Based on this, substituting expression (2) into expression (1), we get the following expression:

[0123] It can be seen from this that the current I flowing through the driving sub-circuit 10 (driving transistor) DThe current I flowing through the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH. D It is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, thereby improving the uniformity of the luminance of the light-emitting device O.

[0124] In summary, the pixel drive circuit Q provided in the embodiment of the present disclosure can utilize the cooperation of the drive sub-circuit 10, the light-emitting control sub-circuit 20, the write sub-circuit 30, the compensation sub-circuit 40, and the storage sub-circuit 50 to implement the writing of the data voltage Vdata and the compensation threshold voltage through two separate paths, respectively, separating the threshold compensation phase from the write phase to prevent the duration of the write phase from limiting the duration of the threshold compensation phase. In other words, the duration of the threshold compensation phase can be made unaffected by the data write time (row time), ensuring that the threshold compensation phase has sufficient duration to fully write the required voltage, thereby compensating for threshold voltage fluctuations within a large range and ensuring that the threshold voltage is fully compensated.

[0125] Based on this, the problem of poor display uniformity on a display panel 200 with a high resolution or a display panel 200 driven with a high refresh rate, caused by insufficient threshold compensation duration when driving the pixel driving circuit Q, can be effectively improved. Furthermore, the problem of poor display uniformity on a low grayscale image or in a black state, caused by insufficient threshold compensation duration when driving the pixel driving circuit, can be effectively improved.

[0126] That is, the pixel driving circuit Q provided in the embodiment of the present disclosure can fully compensate the threshold voltage of the driving sub-circuit 10 (driving transistor T3) within the pixel driving circuit Q even at a high refresh rate, or in a low grayscale image or black state, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0127] In some embodiments, as shown in FIG6 , the voltage value V1 of the first power signal is equal to the voltage value V2 of the second power signal, which is expressed as follows: V2=V1; (4);

[0128] Based on this, after the compensation stage and during the light emitting stage, the voltage of the first node N1 may be V1+Vth+Vdata-V2=Vth+Vdata.

[0129] Furthermore, the gate-source voltage of the driving sub-circuit 10 (driving transistor) is Vgs=Vth+Vdata-V1; (5);

[0130] Substituting expression (5) into the above expression (1), we get the following expression:

[0131] It can be seen from this that the current I flowing through the driving sub-circuit 10 (driving transistor) D The current I of the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V1 of the first power supply signal provided by the first power supply signal line VDD. D It is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, thereby improving the uniformity of the luminance of the light-emitting device O.

[0132] In some embodiments, referring to FIG. 6 , the first power signal line VDD is multiplexed as the second power signal line VGH.

[0133] With this arrangement, on the one hand, the first power signal line VDD is reused as the second power signal line VGH, that is, there is no need to set up the second power signal line VGH separately, which can help simplify the structure of the pixel driving circuit Q and reduce the layout difficulty in the display panel 200.

[0134] On the other hand, the first power signal line VDD is reused as the second power signal line VGH, so that the voltage value V1 of the first power signal is equal to the voltage value V2 of the second power signal, thereby reducing the current I flowing through the driving sub-circuit 10 (driving transistor) D The current I of the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V1 of the first power supply signal provided by the first power supply signal line VDD. D It is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, thereby improving the uniformity of the luminance of the light-emitting device O.

[0135] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments.

[0136] In some embodiments, as shown in FIG7 , the driving sub-circuit 10 includes a driving transistor T3 , a control electrode of the driving transistor T3 coupled to the first node N1 , a first electrode of the driving transistor T3 coupled to the second node N2 , and a second electrode of the driving transistor T3 coupled to the third node N3 .

[0137] When the voltage of the first node N1 is a valid signal, the driving transistor T3 may be turned on under the control of the voltage of the first node N1 to transmit the electrical signal (eg, data signal) from the second node N2 to the third node N3 .

[0138] It should be noted that the "effective signal" in this disclosure refers to a signal that can turn on a transistor. If the transistor is an N-type transistor, the "effective signal" is a high voltage signal; if the transistor is a P-type transistor, the "effective signal" is a low voltage signal. The following embodiments are similar to this and will not be further described.

[0139] Exemplarily, when the driving transistor T3 is a P-type transistor, the driving transistor T3 is controlled to be turned on when the voltage of the first node N1 is a low voltage signal, and the electrical signal (eg, data signal) from the second node N2 can be transmitted to the third node N3.

[0140] Exemplarily, when the driving transistor T3 is an N-type transistor, the driving transistor T3 is controlled to be turned on when the voltage of the first node N1 is a high voltage signal, and the electrical signal (eg, data signal) from the second node N2 can be transmitted to the third node N3.

[0141] It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the condition for turning on an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage, and the threshold voltage of the N-type transistor is a positive value. In this case, the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The condition for turning on a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage, and the threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage, and the gate voltage signal that turns on the P-type transistor is called a low voltage signal. Among them, the voltage of the "high voltage signal" is greater than the voltage of the "low voltage signal".

[0142] In some embodiments, as shown in FIG. 7 , the compensation sub-circuit 40 includes a second transistor T2 and a ninth transistor T9. The control electrode of the second transistor T2 is coupled to the first scan signal line Gate1, the first electrode of the second transistor T2 is coupled to the third node N3, and the second electrode of the second transistor T2 is coupled to the first node N1. The control electrode of the ninth transistor T9 is coupled to the third scan signal line Gate3, the first electrode of the ninth transistor T9 is coupled to the second power supply signal line VGH, and the second electrode of the ninth transistor T9 is coupled to the fourth node N4.

[0143] Based on this, in the compensation phase, the second scan signal received at the second scan signal line Gate2 is also a valid signal, which controls the ninth transistor T9 to be turned on, and can transmit the second power signal received at the second power signal line VGH to the fourth node N4.

[0144] In addition, in the compensation stage, the first scanning signal received at the first scanning signal line Gate1 is a valid signal, which controls the second transistor T2 to turn on, and can transmit the voltage of the third node N3 to the first node N1 to compensate the first node N1. The potential of the first node N1 gradually rises to V1+Vth, and the driving sub-circuit 10 (driving transistor T3) is turned off to complete the threshold compensation, and the charging process of the storage sub-circuit 50 is completed.

[0145] In some embodiments, referring to FIG. 7 , the write sub-circuit 30 includes a fourth transistor T4, a control electrode of the fourth transistor T4 coupled to the third scan signal line Gate3, a first electrode of the fourth transistor T4 coupled to the data write signal line Date, and a second electrode of the fourth transistor T4 coupled to the fourth node N4.

[0146] Based on this, during the write phase, the third scan signal received at the third scan signal line Gate3 is a valid signal, controlling the fourth transistor T4 to turn on, transmitting the data write signal received at the data write signal line Date to the fourth node N4. At this point, the voltage at the fourth node N4 changes from V2 to Vdata. That is, the voltage change at the fourth node N4 is Δ=Vdata-V2. Vdata is the voltage value of the data write signal provided by the data write signal line Data.

[0147] Due to the coupling effect of the storage sub-circuit 50, the voltage of the first node N1 follows the change in the voltage of the fourth node N4, and the voltage change of the first node N1 is also approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can change from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0148] Then, the current I flowing through the driving sub-circuit 10 (driving transistor) is calculated. D Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, and the uniformity of the luminance of the light-emitting device O is improved.

[0149] In some embodiments, referring to FIG. 7 , the storage sub-circuit 50 includes a storage capacitor Cst, a first plate of the storage capacitor Cst is coupled to the fourth node N4 , and a second plate of the storage capacitor Cst is coupled to the first node N1 .

[0150] In the compensation stage, since the first plate of the storage capacitor Cst is coupled to the fourth node N4, the voltage of the first plate of the storage capacitor Cst is the voltage V2 of the second power signal received at the second power signal line VGH; and since the second plate of the storage capacitor Cst is coupled to the first node N1, the voltage of the second plate of the storage capacitor Cst is the voltage V1+Vth of the first node N.

[0151] During the write phase, the third scan signal received at the third scan signal line Gate3 is a valid signal, controlling the fourth transistor T4 to turn on and transmit the data write signal received at the data write signal line Date to the fourth node N4. At this point, the voltage at the fourth node N4 changes from V2 to Vdata, and the voltage change at the fourth node N4 is Δ=Vdata-V2.

[0152] Due to the coupling effect of the storage capacitor Cst, the voltage of the first node N1 can follow the change of the voltage of the fourth node N4.

[0153] Based on this, the voltage change of the first node N1 is also approximately Δ=Vdata-V2. Furthermore, the voltage of the first node N1 can change from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0154] Then, the current I flowing through the driving sub-circuit 10 (driving transistor) is calculated. D Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, and the uniformity of the luminance of the light-emitting device O is improved.

[0155] FIG8 is an equivalent circuit diagram of a pixel driving circuit according to yet other embodiments.

[0156] 8 , the light emitting control subcircuit 20 in the pixel driving circuit Q further includes a second branch 22. The second branch 22 is coupled to the third node N3, the second enable signal line EM2, and the light emitting device O.

[0157] In the light emitting stage, under the control of the second enable signal from the second enable signal line EM2, the second branch 22 is turned on, and the voltage of the third node N3 can be transmitted to the light emitting device O to drive the light emitting device O to emit light.

[0158] As for the light-emitting control sub-circuit 20, during the light-emitting phase, the light-emitting control sub-circuit 20 is configured to turn on the first branch 21 under the control of a first enable signal from the first enable signal line EM1, and to turn on the second branch 22 under the control of a second enable signal from the second enable signal line EM2. Furthermore, the light-emitting control sub-circuit 20 can cooperate with the driving sub-circuit 10 to transmit the first power signal received at the first power signal line VDD to the light-emitting device O. That is, during the light-emitting phase, the light-emitting control sub-circuit 20 is configured to transmit the first power signal received at the first power signal line VDD to the anode of the light-emitting device O, while the cathode of the light-emitting device O can be electrically connected to the second power signal line Vss, thereby driving the light-emitting device O to emit light.

[0159] In some embodiments, please continue to refer to Figure 8, the first branch 21 includes a fifth transistor T5, the control electrode of the fifth transistor T5 is coupled to the first enable signal line EM1, the first electrode of the fifth transistor T5 is coupled to the first power signal line VDD, and the second electrode of the fifth transistor T5 is coupled to the second node N2.

[0160] In the compensation stage, the first enable signal provided by the first enable signal line EM1 is a valid signal, which controls the fifth transistor T5 to turn on, and the first power signal provided by the first power signal line VDD is transmitted to the second node N2; then cooperates with the driving sub-circuit 10 to transmit the voltage of the second node N2 (the voltage V1 of the first power signal) to the third node N3; finally, cooperates with the compensation sub-circuit 40, and the voltage of the third node N3 (the voltage V1 of the first power signal) is transmitted to the first node N1 until the voltage of the first node N1 is V1+Vth, and controls the driving sub-circuit 10 (driving transistor T3) to turn off, completing the threshold compensation.

[0161] In some embodiments, please continue to refer to Figure 8, the second branch 22 includes a sixth transistor T6, the control electrode of the sixth transistor T6 is coupled to the second enable signal line EM2, the first electrode of the sixth transistor T6 is coupled to the third node N3, and the second electrode of the sixth transistor T6 is coupled to the light-emitting device O.

[0162] In the light-emitting stage, the first enable signal provided by the first enable signal line EM1 is a valid signal, which controls the fifth transistor T5 to turn on, and the second enable signal provided by the second enable signal line EM2 is also a valid signal, which controls the sixth transistor T6 to turn on, and then cooperates with the driving sub-circuit 10 to transmit the first power signal provided by the first power signal line VDD to the light-emitting device O to drive the light-emitting device O to emit light.

[0163] In some embodiments, referring to FIG. 8 , the pixel driving circuit Q further includes a first reset sub-circuit 60. The first reset sub-circuit 60 is coupled to the first node N1, the first reset signal line R1, and the first initialization signal line Vinit1. The first reset sub-circuit 60 is configured to, under the control of the first reset signal received from the first reset signal line R1, transmit the first initialization signal received from the first initialization signal line Vinit1 to the first node N1, thereby initializing the first node N1.

[0164] Before the compensation phase begins, the first node N1 of the pixel driving circuit Q can be initialized. At this point, the first reset signal provided by the first reset signal line R1 is a valid signal, which controls the first reset sub-circuit 60 to conduct, transmitting the first initialization signal received from the first initialization signal line Vinit1 to the first node N1, thereby initializing the first node N1. In other words, the first initialization signal provided by the first initialization signal line Vinit1 is used to initialize the control electrode of the driving transistor T3, thereby improving the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0165] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low voltage signal. Therefore, before the compensation phase, the low voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3, thereby improving the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0166] For example, the low voltage signal may be a signal having a voltage Vdata lower than the voltage of the data write signal when the display panel 200 displays any gray scale, so as to eliminate the residual signal when displaying the previous frame of image.

[0167] In some embodiments, please continue to refer to Figure 8, the first reset sub-circuit 60 includes a first transistor T1, the control electrode of the first transistor T1 is coupled to the first reset signal line R1, the first electrode of the first transistor T1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the first node N1.

[0168] Before the compensation stage, the first reset signal provided by the first reset signal line R1 can be controlled to be a valid signal, the first transistor T1 can be controlled to turn on, and the first initialization signal received on the first initialization signal line Vinit1 is transmitted to the first node N1, the first node N1 is reset, and the control electrode of the driving transistor T3 is reset, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0169] Furthermore, when the first node N1 is initialized using the first initialization signal provided by the first initialization signal line Vinit1, the first initialization signal provided by the first initialization signal line Vinit1 is simultaneously transmitted to the storage capacitor Cst in the storage sub-circuit 50. Subsequently, during the compensation phase, the storage capacitor Cst in the storage sub-circuit 50 can be discharged, keeping the driving sub-circuit 10 (driving transistor T3) continuously turned on, thereby ensuring that the first power signal provided by the first power signal terminal VDD can be transmitted to the first node N1.

[0170] In some embodiments, referring to FIG. 8 , the pixel driving circuit Q further includes a second reset sub-circuit 70. The second reset sub-circuit 70 is coupled to the light-emitting device O, the second reset signal line R2, and the second initialization signal line Vinit2. The second reset sub-circuit 70 is configured to, under the control of the second reset signal received from the second reset signal line R2, transmit the second initialization signal received from the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the light-emitting device O.

[0171] Before the light-emitting stage begins, the light-emitting device O electrically connected to the pixel driving circuit Q may be reset. At this time, the second reset signal provided by the second reset signal line R2 is a valid signal, which controls the second reset sub-circuit 70 to be turned on, thereby transmitting the second initialization signal received on the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the anode of the light-emitting device O, and facilitating improved stability of the light-emitting device O.

[0172] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low voltage signal. Therefore, before the light-emitting phase begins, the low voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O from emitting light, thereby reducing the effect of the charge remaining on the anode of the light-emitting device O on the light-emitting brightness, and improving the brightness uniformity of the light-emitting device O.

[0173] Exemplarily, the low voltage signal may be a signal less than 0V, so as to control the light emitting device O not to emit light, thereby improving the influence of the charge remaining in the anode of the light emitting device O on the light emitting brightness.

[0174] In some embodiments, please continue to refer to Figure 8, the second reset sub-circuit 70 includes a seventh transistor T7, the control electrode of the seventh transistor T7 is coupled to the second reset signal line R2, the first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, and the seventh electrode of the eighth transistor T8 is coupled to the light-emitting device O.

[0175] Before the light-emitting stage, the second reset signal provided by the second reset signal line R2 can be controlled to be a valid signal, and the seventh transistor T7 can be controlled to turn on to transmit the second initialization signal received on the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the anode of the light-emitting device O, which is beneficial to improving the stability of the light-emitting device O.

[0176] In some embodiments, referring to FIG. 8 , the pixel driving circuit Q further includes a third reset sub-circuit 80. The third reset sub-circuit 80 is coupled to the second node N2, the third reset signal line R3, and the first reference voltage signal line Vref. The third reset sub-circuit 80 is configured to, under control of a third reset signal received from the third reset signal line R3, transmit the first reference voltage signal received from the first reference voltage signal line Vref to the second node N2, thereby resetting the second node N2.

[0177] Before the compensation phase begins, the third reset signal provided by the third reset signal line R3 can be controlled to be a valid signal, thereby turning on the third reset sub-circuit 80 and transmitting the first reference voltage signal received by the first reference voltage signal line Vref to the second node N2, thereby resetting the second node N2. This allows the initial state of the driving transistor T3 to be fixed before the write phase, facilitating a stable state of the driving transistor T3 during the write phase and significantly reducing the hysteresis effect of the driving transistor T3.

[0178] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref can be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in an on-bias state. That is, before data is written, the driving transistor is in an on-bias state, ensuring that the driving transistor in each pixel driving circuit is charged and compensated from the on-bias state without being affected by the data voltage of the previous frame. This can eliminate the influence of hysteresis of the driving transistor T3 and improve afterimage and response time.

[0179] In some embodiments, please continue to refer to Figure 8, the third reset sub-circuit 80 includes an eighth transistor T8, the control electrode of the eighth transistor T8 is coupled to the third reset signal line R3, the first electrode of the eighth transistor T8 is coupled to the first reference voltage signal line Vref, and the second electrode of the eighth transistor T8 is coupled to the second node N2.

[0180] Before the compensation phase, the third reset signal provided by the third reset signal line R3 can be controlled to be an active signal to control the eighth transistor T8 to turn on, transmitting the first reference voltage signal received from the first reference voltage signal line Vref to the second node N2, thereby resetting the second node N2. Based on this, the initial state of the driving transistor T3 before the writing phase can be fixed, facilitating the driving transistor T3 to be in a stable state during the writing phase, thereby significantly improving the hysteresis effect of the driving transistor T3.

[0181] In some embodiments, please continue to refer to FIG. 8 , the third reset signal line R3 is multiplexed as the second reset signal line R2 .

[0182] With this arrangement, on the one hand, the third reset signal line R3 is multiplexed as the second reset signal line R2 , and there is no need to set up a separate second reset signal line R2 , which can help simplify the structure of the pixel driving circuit Q and reduce the layout difficulty within the display panel 200 .

[0183] On the other hand, the third reset signal line R3 is multiplexed as the second reset signal line R2, and the third reset signal can be used to control the second reset sub-circuit 70 (seventh transistor T7) to be turned on multiple times (once in the reset phase, and again after the writing phase and before the light-emitting phase), and the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, and the anode of the light-emitting device O is reset multiple times, which can help improve the stability of the light-emitting device O.

[0184] In some embodiments, referring to FIG. 8 , the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9:

[0185] The nine transistors may all be P-type transistors, that is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 may all be P-type transistors.

[0186] In the case where all the nine transistors are P-type transistors, the “valid signal” can be understood as a low voltage signal, that is, all the nine transistors can be turned on under the control of the low level signal.

[0187] In some examples, the nine transistors can all be low-temperature polysilicon (LTPS) transistors. That is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can all be LTPS transistors. Because LTPS transistors have higher carrier mobility, the above transistors can have a faster response speed.

[0188] FIG. 9 is an equivalent circuit diagram of a pixel driving circuit according to yet other embodiments.

[0189] In some embodiments, as shown in FIG9 , the first transistor T1 in the first reset sub-circuit 60 of the pixel driving circuit Q can be an N-type transistor. When the first transistor T1 is an N-type transistor, the "valid signal" can be understood as a high voltage signal. That is, the first transistor T1 can be turned on under the control of the high voltage signal.

[0190] Setting the first transistor T1 as an N-type transistor can help reduce the risk of leakage of the first transistor T1 and help ensure the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0191] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the first node N1 through the first transistor T1 during the light emitting phase.

[0192] In some embodiments, as shown in FIG9 , the second transistor T2 in the compensation sub-circuit 40 of the pixel driving circuit Q can be an N-type transistor. When the second transistor T2 is an N-type transistor, the "valid signal" can be understood as a high voltage signal. That is, the second transistor T2 can be turned on under the control of the high voltage signal.

[0193] Setting the second transistor T2 as an N-type transistor can help reduce the risk of leakage of the second transistor T2 and help ensure the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0194] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the first node N1 through the second transistor T2 during the light emitting phase.

[0195] In some embodiments, please refer to Figure 9. Since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0196] Based on this, the fourth transistor T4 in the data writing sub-circuit 30 of the pixel driving circuit Q can be an N-type transistor. In the case where the fourth transistor T4 is an N-type transistor, the above-mentioned "valid signal" can be understood as a high voltage signal. That is, the fourth transistor T4 can be turned on under the control of the high voltage signal.

[0197] Setting the fourth transistor T4 as an N-type transistor can help reduce the risk of leakage of the fourth transistor T4 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1, so as to improve the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0198] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the fourth node N4 through the fourth transistor T4 during the light emitting phase.

[0199] In some embodiments, please refer to Figure 9. Since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0200] Based on this, the ninth transistor T9 in the compensation sub-circuit 40 of the pixel driving circuit Q can be an N-type transistor. In the case where the ninth transistor T9 is an N-type transistor, the above-mentioned "valid signal" can be understood as a high voltage signal. In other words, the ninth transistor T9 can be turned on under the control of the high voltage signal.

[0201] Setting the ninth transistor T9 as an N-type transistor can help reduce the risk of leakage of the ninth transistor T9 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1, so as to improve the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0202] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the fourth node N4 through the ninth transistor T9 during the light emitting phase.

[0203] In some embodiments, referring to FIG. 9 , when the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a ninth transistor T9, at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 is an N-type transistor.

[0204] Such a configuration can improve the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0205] Among them, “at least one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is an N-type transistor” may include the following situations:

[0206] The first type: any one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be an N-type transistor.

[0207] The second type: any two of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be N-type transistors.

[0208] The third type: any three of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be N-type transistors.

[0209] Fourth type: the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all N-type transistors. FIG9 illustrates an example in which the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all N-type transistors. However, the present disclosure is not limited thereto.

[0210] Regardless of whether any of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are N-type transistors, the stability of the driving transistor T3 and the brightness maintenance rate of the light-emitting device O within a frame can be improved.

[0211] FIG. 10 is an equivalent circuit diagram of a pixel driving circuit according to yet other embodiments.

[0212] In some embodiments, referring to FIG. 10 , the first transistor T1 in the first reset sub-circuit 60 in the pixel driving circuit Q may be a dual-gate transistor.

[0213] In the case where the first transistor T1 is a dual-gate transistor, the first transistor T1 may be a P-type transistor, or the first transistor T1 may be an N-type transistor.

[0214] When the first transistor T1 is a P-type dual-gate transistor, the “valid signal” can be understood as a low voltage signal, that is, the first transistor T1 can be turned on under the control of the low voltage signal.

[0215] When the first transistor T1 is an N-type dual-gate transistor, the “valid signal” can be understood as a high voltage signal, that is, the first transistor T1 can be turned on under the control of the high voltage signal.

[0216] Setting the first transistor T1 as a dual-gate transistor can improve the stability of the first transistor, thereby reducing the risk of leakage of the first transistor T1. Based on this, it can help ensure the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, thereby improving the brightness maintenance rate of the light-emitting device O within a frame.

[0217] In some embodiments, referring to FIG. 10 , the second transistor T2 in the compensation sub-circuit 40 in the pixel driving circuit Q may be a dual-gate transistor.

[0218] In the case where the second transistor T2 is a dual-gate transistor, the second transistor T2 may be a P-type transistor, or the second transistor T2 may be an N-type transistor.

[0219] When the second transistor T2 is a P-type dual-gate transistor, the “valid signal” can be understood as a low voltage signal, that is, the second transistor T2 can be turned on under the control of the low voltage signal.

[0220] When the second transistor T2 is an N-type dual-gate transistor, the “valid signal” can be understood as a high voltage signal, that is, the second transistor T2 can be turned on under the control of the high voltage signal.

[0221] Setting the second transistor T2 as a dual-gate transistor can improve the stability of the second transistor T2, thereby reducing the risk of leakage of the second transistor T2. Based on this, it can help ensure the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, thereby improving the brightness maintenance rate of the light-emitting device O within a frame.

[0222] In some embodiments, please refer to Figure 10. Since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0223] Based on this, the fourth transistor T4 in the data writing sub-circuit 30 in the pixel driving circuit Q can be a dual-gate transistor.

[0224] In the case where the fourth transistor T4 is a dual-gate transistor, the fourth transistor T4 may be a P-type transistor, or the fourth transistor T4 may be an N-type transistor.

[0225] When the fourth transistor T4 is a P-type dual-gate transistor, the “valid signal” can be understood as a low voltage signal, that is, the fourth transistor T4 can be turned on under the control of the low voltage signal.

[0226] When the fourth transistor T4 is an N-type dual-gate transistor, the “valid signal” can be understood as a high voltage signal, that is, the fourth transistor T4 can be turned on under the control of the high voltage signal.

[0227] Setting the fourth transistor T4 as a dual-gate transistor can improve the stability of the fourth transistor T4, thereby reducing the risk of leakage of the fourth transistor T4 and ensuring the stability of the voltage of the fourth node N4. Therefore, the fourth node N4 can be prevented from affecting the voltage of the first node N1, thereby improving the stability of the voltage of the first node N1, that is, ensuring the stability of the driving transistor T3, and improving the brightness maintenance rate of the light-emitting device O within a frame.

[0228] In some embodiments, please refer to Figure 10. Since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0229] Based on this, the ninth transistor T9 in the compensation sub-circuit 40 in the pixel driving circuit Q can be set to be a dual-gate transistor.

[0230] In the case where the ninth transistor T9 is a dual-gate transistor, the ninth transistor T9 may be a P-type transistor, or the ninth transistor T9 may be an N-type transistor.

[0231] When the ninth transistor T9 is a P-type dual-gate transistor, the “valid signal” can be understood as a low voltage signal, that is, the ninth transistor T9 can be turned on under the control of the low voltage signal.

[0232] When the ninth transistor T9 is an N-type dual-gate transistor, the “valid signal” can be understood as a high voltage signal, that is, the ninth transistor T9 can be turned on under the control of the high voltage signal.

[0233] Setting the ninth transistor T9 as a dual-gate transistor can improve the stability of the ninth transistor T9, thereby reducing the risk of leakage of the ninth transistor T9 and ensuring the stability of the voltage of the fourth node N4. Therefore, the fourth node N4 can be prevented from affecting the voltage of the first node N1, thereby improving the stability of the voltage of the first node N1, that is, ensuring the stability of the driving transistor T3, and improving the brightness maintenance rate of the light-emitting device O within a frame.

[0234] In some embodiments, referring to FIG. 10 , when the pixel driving circuit Q includes a first transistor T1 , a second transistor T2 , a fourth transistor T4 , and a ninth transistor T9 , at least one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 , and the ninth transistor T9 is a dual-gate transistor.

[0235] Such a configuration can improve the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0236] Among them, “at least one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is a dual-gate transistor” may include the following situations:

[0237] The first type: any one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be a dual-gate transistor.

[0238] The second type: any two of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be dual-gate transistors.

[0239] The third type: any three of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be dual-gate transistors.

[0240] Fourth type: The first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all dual-gate transistors. FIG10 illustrates an example in which the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all dual-gate transistors. However, the present disclosure is not limited thereto.

[0241] Regardless of whether any of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are dual-gate transistors, the stability of the driving transistor T3 and the brightness maintenance rate of the light-emitting device O within a frame can be improved.

[0242] FIG. 11 is a timing diagram of a pixel driving circuit according to some embodiments.

[0243] Some embodiments of the present disclosure further provide a driving method for a pixel driving circuit, which is applied to the pixel driving circuit Q in any of the above embodiments.

[0244] As shown in Figures 8 to 10 , the pixel driving circuit Q includes a driving sub-circuit 10, a light-emission control sub-circuit 20, a write sub-circuit 30, a compensation sub-circuit 40, and a storage sub-circuit 50. The driving sub-circuit 10 is coupled to a first node N1, a second node N2, and a third node N3. The light-emission control sub-circuit 20 includes a first branch 21, which is coupled to a first power signal line VDD, a first enable signal line EM1, and a second node N2. The compensation sub-circuit 40 is coupled to a first scan signal line Gate1, a second scan signal line Gate2, a first node N1, a third node N3, and a fourth node N4, namely, the first power signal line VDD and the second power signal line VGH; the voltage value of the first power signal is equal to the voltage value of the second power signal. The write sub-circuit 30 is coupled to a third scan signal line Gate3, a data write signal line Date, and a fourth node N4. The storage sub-circuit 50 is coupled to the first node N1 and the fourth node N4.

[0245] First, the pixel driving circuit Q shown in FIG8 is used as an example for description. That is, the nine transistors in the pixel driving circuit Q are all P-type transistors. The following method is also applicable to the pixel driving circuit Q including P-type dual-gate transistors, that is, the following method is also applicable to the pixel driving circuit shown in FIG10.

[0246] The driving method includes: a plurality of light-emitting cycles F. One light-emitting cycle F (one frame) includes one refresh frame and at least one hold frame. One light-emitting cycle (one frame) is one display frame, that is, one display screen.

[0247] The refresh frame includes a compensation phase t2 and a writing phase t3.

[0248] During compensation phase t2, the second scan signal provided by the second scan signal line Gate2 is a low-level signal, which controls the compensation sub-circuit 40 (ninth transistor T9) to be conductive, transmitting the second power signal received at the second power signal line VGH to the fourth node N4. At this time, the voltage value of the fourth node N4 is the voltage value V2 of the second power signal.

[0249] The first enable signal provided by the first enable signal line EM1 is a low voltage signal, which controls the first branch 21 to be turned on, and can transmit the first power signal received at the first power signal line VDD to the second node N2; and then cooperates with the driving sub-circuit to transmit the voltage of the second node N2 to the third node N3.

[0250] The first scanning signal provided by the first scanning signal line Gate1 is a low voltage signal, which controls the compensation sub-circuit 40 (second transistor T2) to be turned on, transmits the voltage of the third node N3 to the first node N1, compensates the first node N1, and the potential of the first node N1 gradually rises to V1+Vth.

[0251] Wherein, V1 is the voltage value of the first power signal provided by the first power signal line VDD, and Vth is the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the second pixel driving circuit. When the potential of the first node N1 is V1+Vth, the driving sub-circuit 10 (driving transistor T3) is turned off, completing the threshold compensation.

[0252] Since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, when one end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4 and the other end of the storage sub-circuit 50 receives the voltage V1+Vth from the first node N1, the charging process of the storage sub-circuit 50 is completed.

[0253] Based on this, the first power signal provided by the first power signal line VDD can be used to perform threshold compensation on the driving transistor T3 included in the driving sub-circuit 10 .

[0254] During write phase t3, the third scan signal provided by the third scan signal line Gate3 is a low voltage signal, turning on the data write sub-circuit 30 (fourth transistor T4). The data write signal received at the data write signal line Date is transmitted to the fourth node N4. At this point, the voltage at the fourth node N4 changes from V2 to Vdata. That is, the voltage change at the fourth node N4 is Δ=Vdata-V2. Vdata is the voltage value of the data write signal provided by the data write signal line Data.

[0255] The storage sub-circuit 50 couples the voltage of the fourth node N4 to the first node N1. That is, the voltage of the first node N1 follows the voltage of the fourth node N4, and the voltage of the first node N1 changes by approximately Δ=Vdata-V2. Therefore, the voltage of the first node N1 can change from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0256] In some examples, the refresh frame may further include a light emitting phase t5 after the writing phase t3.

[0257] During light-emitting phase t5, the first enable signal on the first enable signal line EM1 is a low voltage signal, turning on the first branch 21 (fifth transistor T5), thereby transmitting the first power signal received at the first power signal line VDD to the second node N2. At this point, the voltage at the second node N2 is V1. In conjunction with the driver sub-circuit 10, the voltage at the second node N2 is transmitted to the third node N3, and ultimately to the light-emitting device O.

[0258] The light emitting current of the light emitting device O electrically connected to the pixel driving circuit Q is equal to the current flowing through the driving sub-circuit 10, which is expressed as follows:

[0259] Wherein, μ is the electron mobility of the driving sub-circuit 10 (driving transistor), Cox is the insulation capacitance per unit area, is the width-to-length ratio of the driving subcircuit 10 (driving transistor), Vth is the threshold voltage of the driving subcircuit 10 (driving transistor), and Vgs is the gate-source voltage of the driving subcircuit 10 (driving transistor). That is, Vgs is the difference between the voltage of the first node N1 and the voltage of the second node N2, and its expression is as follows: Vgs=V1+Vth+Vdata-V2-V1=Vth+Vdata-V2; (2);

[0260] Based on this, substituting expression (2) into expression (1), we get the following expression:

[0261] It can be seen from this that the current I flowing through the driving sub-circuit 10 (driving transistor T3) D The current I flowing through the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH. D It is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, thereby improving the uniformity of the luminance of the light-emitting device O.

[0262] In summary, the pixel drive circuit Q driving method provided by the embodiments of the present disclosure includes a separate compensation phase t2 and a write phase t3. That is, the writing of the data voltage Vdata and the compensation threshold voltage are implemented through two separate paths, separating the threshold compensation phase from the write phase to prevent the duration of the write phase from limiting the duration of the threshold compensation phase. This ensures that the duration of the threshold compensation phase is not affected by the data write time (row time), ensuring that the threshold compensation phase has sufficient duration to fully write the required voltage, thereby compensating for threshold voltage fluctuations within a large range and ensuring that the threshold voltage is fully compensated.

[0263] Based on this, the problem of poor display uniformity on a display panel 200 with a high resolution or a display panel 200 driven with a high refresh rate, caused by insufficient threshold compensation duration when driving the pixel driving circuit Q, can be effectively improved. Furthermore, the problem of poor display uniformity on a low grayscale image or in a black state, caused by insufficient threshold compensation duration when driving the pixel driving circuit, can be effectively improved.

[0264] That is, the pixel driving circuit Q provided in the embodiment of the present disclosure can fully compensate the threshold voltage of the driving sub-circuit 10 (driving transistor T3) within the pixel driving circuit Q even at a high refresh rate, or in a low grayscale image or black state, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0265] 8 and 11 , the pixel driving circuit Q further includes a third reset subcircuit 80. The third reset subcircuit 80 is coupled to the second node N2, the third reset signal line R3, and the first reference voltage signal line Vref.

[0266] The refresh frame further includes a reset phase t1 , and the reset phase t1 may include a first reset phase t11 .

[0267] In the first reset stage t11, the third reset signal provided by the third reset signal line R3 is a low voltage signal, which controls the third reset sub-circuit (eighth transistor T8) 80 to be turned on, and transmits the first reference voltage signal received on the first reference voltage signal line Vref to the second node N2, thereby resetting the second node N2.

[0268] Based on this, it is equivalent to resetting the second node N2 of the pixel driving circuit Q before the compensation phase t2. Therefore, the initial state of the driving transistor T3 before the writing phase can be fixed, so that the driving transistor T3 is in a stable state during the writing phase, and the hysteresis effect of the driving transistor T3 is greatly improved.

[0269] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref can be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in an on-bias state. That is, before data is written, the driving transistor is in an on-bias state, ensuring that the driving transistor in each pixel driving circuit is charged and compensated from the on-bias state without being affected by the data voltage of the previous frame. This can eliminate the influence of hysteresis of the driving transistor T3 and improve afterimage and response time.

[0270] 8 and 11 , the pixel driving circuit Q further includes a second reset subcircuit 70. The second reset subcircuit 70 is coupled to the light emitting device O, the second reset signal line R2, and the second initialization signal line Vinit2.

[0271] In the first reset stage t11, the second reset signal provided by the second reset signal line R2 can be a low voltage signal, which controls the second reset sub-circuit (seventh transistor T7) 70 to be turned on, and transmits the second initialization signal received on the second initialization signal line Vinit2 to the light-emitting device O to reset the light-emitting device O.

[0272] This is equivalent to resetting the light-emitting device O electrically connected to the pixel driving circuit Q before the light-emitting stage t5 is performed, which is beneficial to improving the stability of the light-emitting device O.

[0273] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low voltage signal. Therefore, before the light-emitting phase begins, the low voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O from emitting light, thereby reducing the effect of the charge remaining on the anode of the light-emitting device O on the light-emitting brightness, and improving the brightness uniformity of the light-emitting device O.

[0274] Exemplarily, the low voltage signal may be a signal less than 0V, so as to control the light emitting device O not to emit light, thereby improving the influence of the charge remaining in the anode of the light emitting device O on the light emitting brightness.

[0275] In some embodiments, referring to FIG. 8 and FIG. 11 , the third reset signal line R3 is multiplexed as the second reset signal line R2 .

[0276] As described above, in the first reset phase t11, the second reset sub-circuit 70 and the third reset sub-circuit 80 are simultaneously turned on in response to the low voltage signal provided by the third reset signal line R3, transmitting the first reference voltage signal received on the first reference voltage signal line Vref to the second node N2 to reset the second node N2, thereby alleviating the effects of hysteresis on the driving transistor T3. Furthermore, the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O to reset the light-emitting device O, thereby improving the stability of the light-emitting device O.

[0277] 8 and 11 , the pixel driving circuit Q further includes a first reset subcircuit 60. The first reset subcircuit 60 is coupled to the first node N1, the first reset signal line R1, and the first initialization signal line Vinit1.

[0278] The refresh frame further includes a reset phase t1 , and the reset phase t1 may further include a first initialization phase t12 .

[0279] In the first initialization stage t12, the first reset signal provided by the first reset signal line R1 is a low voltage signal, which controls the first reset sub-circuit (first transistor T1) 60 to be turned on, and transmits the first initialization signal received on the first initialization signal line Vinit1 to the first node N1 to initialize the first node N1.

[0280] Based on this, it is equivalent to initializing the first node N1 in the pixel driving circuit Q before the compensation phase t2 , so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10 .

[0281] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low voltage signal. Therefore, before the compensation phase, the low voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3, thereby improving the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0282] For example, the low voltage signal may be a signal having a voltage Vdata lower than the voltage of the data write signal when the display panel 200 displays any gray scale, so as to eliminate the residual signal when displaying the previous frame of image.

[0283] In some embodiments, referring to FIG. 8 and FIG. 11 , the reset phase t1 further includes a second initialization phase t13 .

[0284] During the second initialization phase t13, the first reset signal provided by the first reset signal line R1 remains at a low voltage, turning on the first reset sub-circuit (first transistor T1) 60 and transmitting the first initialization signal received on the first initialization signal line Vinit1 to the first node N1. At this point, the voltage at the first node N1 is the first initialization signal. Furthermore, the first scan signal provided by the first scan signal line Gate1 is at a low voltage, turning on the second transistor T2 in the compensation sub-circuit 40 and transmitting the voltage at the first node N1 to the third node N3.

[0285] In addition, the driving sub-circuit (driving transistor T3 ) 10 is turned on under the control of the voltage of the first node N1 , so that the voltage of the third node N3 can be transmitted to the second node N2 .

[0286] Based on this, the first reset signal line R1, the first scan signal line Gate1 and the first initialization signal line Vinit1 can be used to synchronously initialize the first node N1, the second node N2 and the third node N3, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0287] In some embodiments, referring to Figures 8 and 11 , the refresh frame further includes a second reset phase t4 . The second reset phase t4 is after the writing phase t3 and before the light emitting phase t5 .

[0288] In the second reset stage t4, the low voltage signal provided by the second reset signal line R2 is used to control the second reset sub-circuit (seventh transistor T7) 70 to be turned on, and the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, so that the light-emitting device O is reset again, which is beneficial to improving the stability of the light-emitting device O.

[0289] Furthermore, since the three reset signal lines R3 are multiplexed into the second reset signal line R2, in the second reset phase t4, the low voltage signal provided by the third reset signal line R3 can be used to control the third reset sub-circuit (eighth transistor T8) 80 to be turned on, thereby transmitting the first reference voltage signal received on the first reference voltage signal line Vref to the second node N2, thereby resetting the second node N2, which is beneficial to improving the stability of the driving transistor T3.

[0290] Furthermore, after the refresh frame within each light-emitting period F is completed, the hold frame phase begins. At this point, the third reset signal line R3 can provide a low voltage signal to control the conduction of the second reset sub-circuit 70 and the third reset sub-circuit 80. The first reference voltage signal received on the first reference voltage signal line Vref is transmitted to the second node N2, resetting the second node N2 and thus improving the stability of the driving transistor T3. Furthermore, the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting devices O, resetting them. This ensures that the anode voltages of all light-emitting devices O are consistent at the start of the next frame refresh, thereby improving the brightness uniformity of the light-emitting devices O.

[0291] In addition, in the hold frame, the first enable signal line EM1 and the second enable signal line EM2 can also be used to provide low voltage signals to turn on the light emitting control subcircuit 20 and cooperate with the driving subcircuit 10 to drive the light emitting device O to emit light.

[0292] FIG12 is a timing diagram of a pixel driving circuit according to some other embodiments.

[0293] The following description is made using the pixel driving circuit Q shown in FIG9 as an example, that is, taking the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 in the pixel driving circuit Q as an example in which the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all N-type transistors. The following method is also applicable to the pixel driving circuit Q including N-type dual-gate transistors.

[0294] The difference from the driving method shown in FIG11 is that the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 in the pixel driving circuit Q corresponding to FIG11 are all P-type transistors.

[0295] In the pixel driving circuit Q corresponding to FIG12 , the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 are all N-type transistors.

[0296] Based on this, the effective signals for the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 in the pixel driving circuit Q driven by the timing diagram shown in FIG12 are high voltage signals. That is, the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all turned on under high voltage control. The driving method is consistent with the driving method shown in FIG11, the only difference being the "effective signal" for controlling the turning on of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9. How to drive the pixel driving circuit in other stages can be combined with FIG11 and the above-mentioned driving method, and will not be further described here.

[0297] Figure 13 is a structural diagram of an array substrate according to some other embodiments. To clearly illustrate how to configure various signal lines to respond to the same signal terminal, Figure 13 only illustrates the second scan signal line Gate2 coupled to the first row of pixel drive circuits, the first scan signal line Gate1 coupled to the fourth row of pixel drive circuits, and the first reset signal line R1 coupled to the seventh row of pixel drive circuits Q.

[0298] Referring to FIG. 13 , some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a display area AA and a peripheral area SA. The peripheral area SA can be located on at least one side of the display area AA (e.g., one side; or, for example, all four sides, i.e., including the upper and lower sides and the left and right sides).

[0299] The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 located on one side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q, and the plurality of pixel driving circuits Q are arranged in multiple rows and columns.

[0300] For the convenience of explanation, the above-mentioned multiple pixel driving circuits Q are described in the present disclosure by taking a matrix arrangement as an example.

[0301] At this time, the pixel driving circuits Q arranged in a row along the first direction X are called a row of pixel driving circuits Q, and the pixel driving circuits Q arranged in a row along the second direction Y are called a column of pixel driving circuits Q.

[0302] The array substrate 100 further includes a plurality of different types of signal lines to drive the pixel driving circuit Q. The plurality of different types of signal lines include a plurality of first scanning signal lines Gate1 , a plurality of second scanning signal lines Gate2 , and a plurality of first reset signal lines R1 .

[0303] The plurality of first scanning signal lines Gate1 are located on one side of the substrate and extend along a first direction X and are arranged along a second direction Y, which intersects the first direction X. One first scanning signal line Gate1 is coupled to a row of pixel driving circuits Q.

[0304] A plurality of second scan signal lines Gate2 are located on one side of the substrate, and the plurality of second scan signal lines Gate2 extend along the first direction X and are arranged along the second direction Y. One second scan signal line Gate2 is coupled to a row of pixel driving circuits Q.

[0305] A plurality of first reset signal lines R1 are located on one side of the substrate, and the plurality of first reset signal lines R1 extend along a first direction X and are arranged along a second direction Y. One first reset signal line R1 is coupled to a row of pixel driving circuits Q.

[0306] The multiple first scan signal lines Gate1, the multiple second scan signal lines Gate2, and the multiple first reset signal lines R1 can each be controlled using different signal terminals. However, research has found that because the signal terminals are located in the peripheral area SA, if the multiple first scan signal lines Gate1, the multiple second scan signal lines Gate2, and the multiple first reset signal lines R1 can each be controlled using different signal terminals, an excessive number of signal terminals will be required within the array substrate 100, occupying excessive space within the array substrate 100. This will increase the area of ​​the peripheral area SA, thereby affecting the subsequent achievement of a narrow bezel on the display panel 200.

[0307] In some examples, the first direction X and the second direction Y may be approximately perpendicular, and in this case, the angle between the first direction X and the second direction Y is approximately 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0308] Based on the above problems, the array substrate 100 provided in some embodiments of the present disclosure, as shown in Figure 13, can be provided with a second scanning signal line Gate2 coupled to the nth row of pixel driving circuits and a first scanning signal line Gate1 coupled to the n+3th row of pixel driving circuits, in response to the control of the same control signal.

[0309] That is, the second scanning signal line Gate2 coupled to the nth row of pixel driving circuits and the first scanning signal line Gate1 coupled to the n+3th row of pixel driving circuits can be coupled to the same signal terminal, where n is a positive integer.

[0310] Because, the first scanning signal provided by the first scanning signal line Gate1 can be used to control the second transistor T2 in the compensation sub-circuit 40 to turn on, and cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to initialize the first node N1, the second node N2 and the third node N2 at the same time; then the second scanning signal provided by the second scanning signal line Gate2 can be used to control the ninth transistor T9 in the compensation sub-circuit 40 to turn on, and cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light-emitting control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0311] Based on this, the second scanning signal line Gate2 coupled to the pixel driving circuit in the nth row and the first scanning signal line Gate1 coupled to the pixel driving circuit in the n+3th row can be coupled to the same signal terminal. That is, when the gate signal is sent to the second scanning signal line Gate2 coupled to the pixel driving circuit in the nth row to control the ninth transistor T9 in the compensation sub-circuit 40 in the pixel driving circuit in the nth row to turn on, the gate signal can be synchronously sent to the first scanning signal line Gata1 coupled to the pixel driving circuit in the n+3th row to control the second transistor T2 in the compensation sub-circuit 40 in the pixel driving circuit in the n+3th row to turn on, so that the first node N1, the second node N2, and the third node N2 can be initialized before the pixel driving circuit in the n+3th row performs threshold compensation.

[0312] Such a setting can not only ensure the conductivity of the sub-circuit electrically connected to the first scanning signal line Gate1 and the second scanning signal line Gate2 in the pixel driving circuit Q; but also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0313] In some embodiments, as shown in FIG13 , a second scanning signal line Gate2 coupled to the nth row of pixel driving circuits and a first reset signal line R1 coupled to the n+6th row of pixel driving circuits may be set to respond to the control of the same control signal.

[0314] That is, the second scanning signal line Gate2 coupled to the nth row of pixel driving circuits and the first reset signal line R1 coupled to the n+6th row of pixel driving circuits can be coupled to the same signal terminal, where n is a positive integer.

[0315] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first transistor T1 in the first reset sub-circuit to turn on and initialize the first node N1; then use the second scan signal provided by the second scan signal line Gate2 to control the ninth transistor T9 in the compensation sub-circuit 40 to turn on, and cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light-emitting control sub-circuit 20, and the storage sub-circuit 50 to perform threshold compensation.

[0316] Based on this, the second scanning signal line Gate2 coupled to the pixel driving circuit in the nth row and the first reset signal line R1 coupled to the pixel driving circuit in the (n+6th) row may be coupled to the same signal terminal.

[0317] That is, when the signal end is used to send a gate signal to the second scanning signal line Gate2 coupled to the n-th row pixel driving circuit to control the ninth transistor T9 in the compensation sub-circuit 40 in the n-th row pixel driving circuit to turn on, the signal end can be used to synchronously send a gate signal to the first reset signal line R1 coupled to the n+6-th row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit in the n+6-th row pixel driving circuit to turn on, so that the n+6-th row pixel driving circuit can initialize the first node N1 before performing threshold compensation.

[0318] Such a setting can not only ensure the conductivity of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the second scanning signal line Gate2; it can also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0319] In some embodiments, as shown in FIG13 , a first scan signal line Gate1 coupled to the nth row of pixel driving circuits and a first reset signal line R1 coupled to the n+3th row of pixel driving circuits can be configured to respond to the same control signal, where n is a positive integer.

[0320] That is, the first scanning signal line Gate1 coupled to the pixel driving circuit in the nth row and the first reset signal line R1 coupled to the pixel driving circuit in the (n+3)th row may be coupled to the same signal terminal.

[0321] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first reset sub-circuit to turn on and initialize the first node N1; then use the first scan signal provided by the first scan signal line Gate1 to control the second transistor T2 in the compensation sub-circuit 40 to turn on, and cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to initialize the first node N1, the second node N2 and the third node N3 at the same time.

[0322] Based on this, the first scanning signal line Gate1 coupled to the pixel driving circuit in the nth row and the first reset signal line R1 coupled to the pixel driving circuit in the (n+3)th row may be coupled to the same signal terminal.

[0323] That is, when the signal end is used to send a gate signal to a scanning signal line Gate1 coupled to the n-th row pixel driving circuit to control the second transistor T2 in the compensation sub-circuit 40 in the n-th row pixel driving circuit to turn on, the signal end can be used to synchronously send a gate signal to the first reset signal line R1 coupled to the n+3-th row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit in the n+3-th row pixel driving circuit to turn on, so that the n+3-th row pixel driving circuit can initialize the first node N1, the second node N2 and the third node N2 before performing threshold compensation.

[0324] Such a setting can not only ensure the conductivity of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the first scanning signal line Gate1; it can also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0325] In some embodiments, as shown in FIG. 13 , a second scan signal line Gate2 coupled to the pixel driving circuit in the nth row, a first scan signal line Gate1 coupled to the pixel driving circuit in the n+3th row, and a first reset signal line R1 coupled to the pixel driving circuit in the n+6th row can be configured to respond to the same control signal, where n is a positive integer.

[0326] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first reset sub-circuit to be turned on and initialize the first node N1; then use the first scanning signal provided by the first scanning signal line Gate1 to control the second transistor T2 in the compensation sub-circuit 40 to be turned on, and cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to simultaneously initialize the first node N1, the second node N2 and the third node N2; finally, use the second scanning signal provided by the second scanning signal line Gate2 to control the ninth transistor T9 in the compensation sub-circuit 40 to be turned on, and cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light-emitting control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0327] Based on this, a second scanning signal line Gate2 coupled to the nth row pixel driving circuit, a first scanning signal line Gate1 coupled to the n+3th row pixel driving circuit, and a first reset signal line R1 coupled to the n+6th row pixel driving circuit can be set to respond to the same control signal.

[0328] That is, when the signal terminal is used to send a gate signal to the second scanning signal line Gate2 coupled to the pixel driving circuit of the nth row to control the ninth transistor T9 in the compensation sub-circuit 40 in the pixel driving circuit of the nth row to turn on; the signal terminal can be used to send a gate signal to a scanning signal line Gate1 coupled to the pixel driving circuit of the n+3th row to control the second transistor T2 in the compensation sub-circuit 40 in the pixel driving circuit of the n+3th row to turn on, so that the pixel driving circuit of the n+3th row can initialize the first node N1 before performing threshold compensation; and the signal terminal can be used to synchronously send a gate signal to the first reset signal line R1 coupled to the pixel driving circuit of the n+6th row to control the first transistor T1 in the first reset sub-circuit in the pixel driving circuit of the n+6th row to turn on, so that the pixel driving circuit of the n+6th row can initialize each node before performing threshold compensation.

[0329] Such a setting can not only ensure the conductivity of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1; it can also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0330] In some examples, as shown in FIG13 , the plurality of first scan signal lines Gate1 , the plurality of second scan signal lines Gate2 , and the plurality of first reset signal lines R1 can be coupled to the same signal terminal, which can be a gate driver circuit 101 (Gate Driver on Array, GOA).

[0331] The gate drive circuit 101 is used to provide gate signals for the first scan signal line Gate1, the second scan signal line Gate2 and the first reset signal line R1. The first scan signal line Gate1, the second scan signal line Gate2 and the first reset signal line R1 transmit the gate signals to the corresponding coupled sub-circuit to control the opening and closing of the transistors included in the sub-circuit.

[0332] In some examples, the gate driver circuit 101 may include multiple shift register units arranged in cascade. One shift register unit may be coupled to the second scan signal line Gate2 coupled to the pixel driver circuit in the nth row, the first scan signal line Gate1 coupled to the pixel driver circuit in the n+3th row, and the first reset signal line R1 coupled to the pixel driver circuit in the n+6th row, so that the same shift register unit can be used to drive the second scan signal line Gate2 coupled to the pixel driver circuit in the nth row, the first scan signal line Gate1 coupled to the pixel driver circuit in the n+3th row, and the first reset signal line R1 coupled to the pixel driver circuit in the n+6th row.

[0333] For example, a shift register 102 can be coupled to the second scan signal line Gate2 coupled to the 1st row of pixel driving circuits, the first scan signal line Gate1 coupled to the 4th row of pixel driving circuits, and the first reset signal line R1 coupled to the 7th row of pixel driving circuits.

[0334] Based on this, when the pixel driving circuit Q in the 1st row receives the second scanning signal provided by the second scanning signal line Gate2, the pixel driving circuit Q in the 4th row can simultaneously receive the first scanning signal provided by the first scanning signal line Gate1, and the pixel driving circuit Q in the 7th row receives the first reset signal provided by the first reset signal R1.

[0335] Therefore, the pixel driving circuit Q in the 7th row and the pixel driving circuit Q in the 4th row are initialized on each node before threshold compensation is performed.

[0336] Such a setting can not only ensure the conductivity of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1; it can also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0337] FIG. 14 is a timing diagram of a pixel driving circuit according to some further embodiments, and FIG. 15 is a timing diagram of a pixel driving circuit according to some further embodiments.

[0338] It should be noted that when the second scanning signal line Gate2 coupled to the nth row pixel driving circuit, the first scanning signal line Gate1 coupled to the n+3th row pixel driving circuit, and the first reset signal line R1 coupled to the n+6th row pixel driving circuit are set to respond to the same control signal, when driving the corresponding pixel driving circuits, in the corresponding timing diagram, as shown in combination with Figures 14 and 15, the pulse widths of the signals transmitted by the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1 are equal.

[0339] The timing diagram shown in FIG14 is similar to the timing diagram shown in FIG11 , and the timing diagram shown in FIG15 is similar to the timing diagram shown in FIG12 . That is, the timing diagram shown in FIG14 can be used to drive the pixel driving circuits shown in FIG8 and FIG11 , and FIG15 can be used to drive the pixel driving circuit shown in FIG9 . For specific driving methods, reference can be made to the above embodiments and will not be repeated here.

[0340] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel driving circuit, comprising: A driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a compensation subcircuit and a storage subcircuit; The driving subcircuit is coupled to the first node, the second node and the third node, and the driving subcircuit is configured to transmit the voltage from the second node to the third node under the control of the voltage of the first node; The light-emitting control subcircuit includes a first branch, the first branch is coupled to a first power signal line, a first enable signal line, and a second node; the first branch is configured to cooperate with the driving subcircuit under the control of a first enable signal from the first enable signal line in a compensation phase to transmit a first power signal received at the first power signal line to the third node; The compensation subcircuit is coupled to the first scan signal line, the second scan signal line, the first node, the third node, the fourth node and the second power signal line; the compensation subcircuit is configured to, in a compensation phase, under the control of a first scan signal received at the first scan signal line, transmit the voltage of the third node to the first node, and under the control of a second scan signal received at the second scan signal line, transmit the second power signal received at the second power signal line to the fourth node; The write subcircuit is coupled to the third scan signal line, the data write signal line and the fourth node; the write subcircuit is configured to, in a write phase, under the control of a third scan signal received at the third scan signal line, transmit the data write signal received at the data write signal line to the fourth node; The storage sub-circuit is coupled to the first node and the fourth node; in the writing phase, the storage sub-circuit is configured to couple the voltage of the fourth node to the first node.

2. The pixel driving circuit according to claim 1, wherein: The driving sub-circuit includes a driving transistor, a control electrode of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

3. The pixel driving circuit according to claim 1 or 2, wherein: The compensation sub-circuit includes a second transistor and a ninth transistor; The control electrode of the second transistor is coupled to the first scan signal line, the first electrode of the second transistor is coupled to the third node, and the second electrode of the second transistor is coupled to the first node; The control electrode of the ninth transistor is coupled to the third scan signal line, the first electrode of the ninth transistor is coupled to the second power signal line, and the second electrode of the ninth transistor is coupled to the fourth node.

4. The pixel driving circuit according to any one of claims 1 to 3, wherein: The write subcircuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the third scan signal line, a first electrode of the fourth transistor is coupled to the data write signal line, and a second electrode of the fourth transistor is coupled to the fourth node.

5. The pixel driving circuit according to any one of claims 1 to 4, wherein: The storage subcircuit includes a storage capacitor, a first plate of the storage capacitor is coupled to the fourth node, and a second plate of the storage capacitor is coupled to the first node.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein: The light-emitting control subcircuit also includes a second branch, which is coupled to the third node, the second enable signal line and the light-emitting device; in the light-emitting stage, the light-emitting control subcircuit is configured to cooperate with the driving subcircuit under the control of the first enable signal from the first enable signal line and the second enable signal from the second enable signal line to transmit the first power signal received at the first power signal line to the light-emitting device.

7. The pixel driving circuit according to claim 6, wherein: The first branch includes a fifth transistor, a control electrode of the fifth transistor is coupled to the first enable signal line, a first electrode of the fifth transistor is coupled to the first power signal line, and a second electrode of the fifth transistor is coupled to the second node; The second branch includes a sixth transistor, a control electrode of the sixth transistor is coupled to the second enable signal line, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the light emitting device.

8. The pixel driving circuit according to any one of claims 1 to 7, further comprising a first reset subcircuit; The first reset sub-circuit is coupled to the first node, the first reset signal line and the first initialization signal line; the first reset sub-circuit is configured to, under the control of the first reset signal received from the first reset signal line, transmit the first initialization signal received on the first initialization signal line to the first node to reset the first node.

9. The pixel driving circuit according to claim 8, wherein: The first reset subcircuit includes a first transistor, a control electrode of the first transistor is coupled to the first reset signal line, a first electrode of the first transistor is coupled to the first initialization signal line, and a second electrode of the first transistor is coupled to the first node.

10. The pixel driving circuit according to any one of claims 1 to 9, further comprising a second reset subcircuit; The second reset sub-circuit is coupled to the light-emitting device, the second reset signal line and the second initialization signal line; the second reset sub-circuit is configured to, under the control of the second reset signal received from the second reset signal line, transmit the second initialization signal received on the second initialization signal line to the light-emitting device to reset the light-emitting device.

11. The pixel driving circuit according to claim 10, wherein: The second reset subcircuit includes a seventh transistor, a control electrode of the seventh transistor is coupled to the second reset signal line, a first electrode of the seventh transistor is coupled to the second initialization signal line, and a seventh electrode of the eighth transistor is coupled to the light emitting device.

12. The pixel driving circuit according to any one of claims 1 to 11, further comprising a third reset subcircuit; The third reset subcircuit is coupled to the second node, the third reset signal line and the first reference voltage signal line; the third reset subcircuit is configured to, under the control of a third reset signal received from the third reset signal line, transmit the first reference voltage signal received from the first reference voltage signal line to the second node, The second node is reset.

13. The pixel driving circuit according to claim 12, wherein: The third reset subcircuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the third reset signal line, a first electrode of the eighth transistor is coupled to the first reference voltage signal line, and a second electrode of the eighth transistor is coupled to the second node.

14. The pixel driving circuit according to any one of claims 1 to 13, wherein: The voltage value of the first power signal is equal to the voltage value of the second power signal.

15. The pixel driving circuit according to any one of claims 1 to 14, wherein: The first power signal line is multiplexed as the second power signal line.

16. The pixel driving circuit according to any one of claims 1 to 15, wherein: In the case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: At least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is a dual-gate transistor.

17. The pixel driving circuit according to any one of claims 1 to 16, wherein: In the case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: At least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is an N-type transistor.

18. A driving method for a pixel driving circuit, wherein: The pixel driving circuit comprises: a driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a compensation subcircuit and a storage subcircuit; The driving subcircuit is coupled to the first node, the second node and the third node; The light emitting control subcircuit comprises a first branch, the first branch is coupled to a first power signal line, a first enable signal line and a second node; The compensation subcircuit is coupled to the first scan signal line, the second scan signal line, the first node, the third node, the fourth node, the first power signal line and the second power signal line; wherein the voltage value of the first power signal is equal to the voltage value of the second power signal; The writing sub-circuit is coupled to the third scanning signal line, the data writing signal line and the fourth node; The storage sub-circuit is coupled to the first node and the fourth node; The driving method comprises: a compensation phase and a writing phase; In the compensation stage, the first branch, under the control of the first enable signal from the first enable signal line, cooperates with the driving sub-circuit to transmit the first power signal received at the first power signal line to the third node; the compensation sub-circuit, under the control of the first scan signal received at the first scan signal line, transmits the voltage of the third node to the first node; under the control of the second scan signal received at the second scan signal line, transmits the second power signal received at the second power signal line to the fourth node; and the storage sub-circuit receives the voltage of the first node and the voltage of the fourth node; In the write phase, the write subcircuit, under the control of the third scan signal received at the third scan signal line, transmits the data write signal received at the data write signal line to the fourth node; and the storage subcircuit couples the voltage of the fourth node to the first node.

19. The driving method according to claim 18, wherein: The pixel driving circuit further includes a third reset subcircuit, wherein the third reset subcircuit is coupled to the second node, the third reset signal line and the first reference voltage signal line; The driving method also includes a first reset stage. In the first reset stage, the third reset sub-circuit, under the control of a third reset signal received from the third reset signal line, transmits the first reference voltage signal received on the first reference voltage signal line to the second node to reset the second node.

20. The driving method according to claim 19, wherein: The pixel driving circuit further includes a first reset subcircuit, wherein the first reset subcircuit is coupled to the first node, the first reset signal line and the first initialization signal line; The driving method also includes a first initialization stage. In the first initialization stage, the first reset sub-circuit, under the control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node to initialize the first node.

21. The driving method according to claim 20, wherein: The driving method further comprises a second initialization phase; In the second initialization stage, the first reset subcircuit transmits the first initialization signal received from the first initialization signal line to the first node under the control of the first reset signal received from the first reset signal line; The compensation sub-circuit transmits the voltage of the first node to the third node under the control of the first scan signal received from the first scan signal line; The driving sub-circuit transmits the voltage from the second node to the third node under the control of the voltage of the first node, so as to initialize the first node, the second node and the third node.

22. An array substrate, comprising: A substrate, and a plurality of pixel driving circuits as claimed in any one of claims 1 to 21 located on the substrate.

23. The array substrate according to claim 22, wherein: The plurality of pixel driving circuits are arranged in multiple rows and columns; the array substrate further comprises: A plurality of first scanning signal lines are located on one side of the substrate, extending along a first direction and arranged along a second direction, wherein the second direction intersects the first direction; a plurality of second scanning signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; a plurality of first reset signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; The second scanning signal line coupled to the pixel driving circuit of the nth row is coupled to the pixel driving circuit of the n+3th row. The first scanning signal line coupled to the n+6th row of pixel driving circuits responds to the control of the same control signal, where n is a positive integer.

24. A display panel comprising: a light emitting device layer, comprising a plurality of light emitting devices; as well as, An array substrate as described in claim 22 or 23 above; wherein the pixel driving circuit is coupled to the light emitting device.

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