Array substrate and display device

Abstract

The present application provides an array substrate and a display device. The array substrate comprises a display area and a non-display area; the non-display area comprises at least one binding sub-area; the binding sub-area is adapted to be electrically connected to a circuit board; the array substrate further comprises a driving module arranged in the non-display area; the circuit board provides a driving control signal for the driving module by means of the binding sub-area; the at least one binding sub-area comprises at least three signal providing areas; the bonding sub-area comprises a plurality of pad terminals arranged in the at least three signal providing areas; the pad terminals provide driving control signals for the driving module by means of signal wires. According to the present application, the temperature of the signal wires is reduced by increasing the number of signal access points.

Description

Array substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310942940.1 filed in China on July 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0004] In the related borderless screen display products, the driving module includes a plurality of cascaded driving circuits, and the plurality of cascaded driving circuits are arranged along the first direction. In the related art, the non-display area includes at least one binding sub-area, and the at least one binding sub-area can be arranged along the first direction; the at least one binding sub-area includes two signal supply areas, the first signal supply area can be set at the left end of the leftmost binding sub-area, and the second signal supply area can be set at the right end of the rightmost binding sub-area. Therefore, the length of the signal line for receiving the driving control signal of the driving circuit located in the middle is longer, so the temperature of the signal line is high, which can cause abnormality of the driving circuit or generate high-temperature gravity yellow spot in the display screen, affecting the display effect.

[0005] Summary of the Invention

[0006] In one aspect, at least one embodiment of the present disclosure provides an array substrate, comprising a display area and a non-display area, wherein the non-display area includes at least one binding sub-area, the binding sub-area being electrically connected to a circuit board, the array substrate further comprising a driving module disposed in the non-display area, the circuit board providing a driving control signal to the driving module via the binding sub-area;

[0007] The at least one binding sub-region includes at least three signal providing regions;

[0008] The at least one binding sub-region includes a plurality of pad terminals arranged in the at least three signal providing regions, and the pad terminals provide driving control signals to the driving module through signal wiring.

[0009] Optionally, the non-display area includes a plurality of binding sub-areas; the plurality of pad terminals are arranged along a first direction;

[0010] The binding sub-area includes a first signal providing area and a second signal providing area;

[0011] The plurality of pad terminals include a plurality of first pad terminals and a plurality of second pad terminals;

[0012] The first pad terminal corresponds to the first signal supply area, and the second pad terminal corresponds to the second signal supply area;

[0013] The first pad terminal and the second pad terminal are disposed on two opposite sides of the binding sub-region.

[0014] Optionally, the array substrate according to at least one embodiment of the present disclosure further includes a data line at least partially disposed in the display area;

[0015] The plurality of pad terminals further include a plurality of third pad terminals;

[0016] The third pad terminal is provided between the first pad terminal and the second pad terminal;

[0017] The third pad terminal is electrically connected to the data line and is used to provide a data voltage to the data line.

[0018] Optionally, the driving control signal includes at least one of a clock signal, a common electrode voltage signal, a DC voltage signal, and a frame start signal.

[0019] Optionally, the signal line is used to provide a clock signal for the driving module; the non-display area includes a first binding sub-area and a second binding sub-area;

[0020] The array substrate further includes at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region;

[0021] The clock signal line includes a first end and a second end that are oppositely arranged;

[0022] The first signal providing region of the first binding sub-region is provided at a first end of the first binding sub-region, and the second signal providing region of the first binding sub-region is provided at a second end of the first binding sub-region;

[0023] The first signal providing region of the second binding sub-region is provided at a first end portion of the second binding sub-region, and the second signal providing region of the second binding sub-region is provided at a second end portion of the first binding sub-region;

[0024] A first end of the first binding sub-region is close to a first end of the clock signal line, and a second end of the second binding sub-region is close to a second end of the clock signal line.

[0025] Optionally, the clock signal line is provided in a first metal layer; the first binding sub-region is electrically connected to the clock signal line via a signal trace formed in the second metal layer and provided in its second signal providing region;

[0026] The second binding sub-region is electrically connected to the clock signal line via a signal trace formed on the second metal layer and provided in the first signal providing region thereof;

[0027] The first metal layer and the second metal layer are different metal layers.

[0028] Optionally, the first binding sub-region is electrically connected to the clock signal line via a signal trace formed on the first metal layer and provided in the first signal providing region thereof;

[0029] The second binding sub-region is electrically connected to the clock signal line via a signal trace formed on the first metal layer and arranged in the second signal providing region of the second binding sub-region.

[0030] Optionally, the non-display area includes M binding sub-areas arranged along a first direction; M is an integer greater than or equal to 3; and the plurality of pad terminals are arranged along the first direction;

[0031] The signal providing area included in the binding sub-area is arranged at the first end or the second end of the binding sub-area.

[0032] Optionally, the signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0033] The clock signal line includes a first end and a second end;

[0034] The signal providing region of the first binding sub-region is set at a first end of the first binding sub-region, and the signal providing region of the Mth binding sub-region is set at a second end of the Mth binding sub-region;

[0035] The signal providing area of ​​the mth binding sub-area is provided at the first end or the second end of the mth binding sub-area, where m is an integer greater than 1 and less than M;

[0036] The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the Mth binding sub-region is close to the second end of the clock signal line.

[0037] Optionally, the non-display area includes a binding sub-area; the plurality of pad terminals are arranged along a first direction;

[0038] The binding sub-area includes N signal providing areas; N is an integer greater than or equal to 3

[0039] Two of the N signal supply areas are arranged at opposite sides of the binding sub-area, and the signal supply areas other than the two signal supply areas are arranged in the middle of the binding sub-area.

[0040] Optionally, the signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0041] The clock signal line includes a first end and a second end;

[0042] The first signal providing area of ​​the binding sub-area is set at the first end of the binding sub-area, the Nth signal providing area of ​​the binding sub-area is set at the second end of the binding sub-area, and the nth signal providing area of ​​the binding sub-area is set in the middle of the binding sub-area; n is an integer greater than 1 and less than N.

[0043] Optionally, the non-display area includes a first non-display region provided on a first side of the display area;

[0044] The clock signal line, the driving module and the binding sub-area are all arranged in the first non-display area.

[0045] Optionally, the signal trace includes at least two electrically connected signal line portions;

[0046] The at least two signal line portions are respectively formed in different metal layers.

[0047] Optionally, the array substrate includes a first metal layer and a second metal layer;

[0048] The signal trace includes a first signal line portion and a second signal line portion;

[0049] The first signal line portion is formed in a first metal layer, and the second signal line portion is formed in a second metal layer.

[0050] Optionally, the array substrate further includes a base, a conductive layer, a first insulating layer disposed between the first metal layer and the second metal layer, and a second insulating layer disposed between the second metal layer and the conductive layer;

[0051] The first signal line portion is electrically connected to the second signal line portion through a conductive pattern formed on the conductive layer and a via hole penetrating the second insulating layer;

[0052] The first metal layer, the second metal layer and the conductive layer are arranged in sequence along a direction away from the substrate.

[0053] Optionally, the array substrate further includes a base;

[0054] An orthographic projection of the first signal line portion on the substrate at least partially overlaps with an orthographic projection of the second signal line portion on the substrate.

[0055] Optionally, the plurality of pad terminals include a first pad terminal for providing a clock signal and a third pad terminal for providing a data voltage;

[0056] The first pad terminal includes at least one first sub-pad and at least one second sub-pad; the third pad terminal includes at least one third sub-pad;

[0057] The first sub-pad includes a first sub-pad portion formed on the first metal layer and a second sub-pad portion formed on the second metal layer;

[0058] The second sub-pad includes a third sub-pad portion formed on the first metal layer;

[0059] The third sub-pad includes a fourth sub-pad portion formed in the first metal layer.

[0060] Optionally, the driving module includes a multi-stage driving circuit;

[0061] The driving circuit includes an output transistor;

[0062] The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0063] A channel width-to-length ratio of the output transistor is smaller than a first width-to-length ratio threshold.

[0064] Optionally, the driving circuit further includes an output reset transistor;

[0065] The gate of the output reset transistor is electrically connected to the reset terminal, the first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal;

[0066] A channel width-to-length ratio of the output reset transistor is greater than a second width-to-length ratio threshold.

[0067] Optionally, the signal trace is used to transmit a clock signal;

[0068] The rising edge of the clock signal includes at least two steps.

[0069] In a second aspect, an embodiment of the present disclosure provides a display device, comprising a circuit board and the above-mentioned array substrate;

[0070] The circuit board is electrically connected to the binding sub-region in the array substrate, and is used to provide a driving control signal to the driving module in the array substrate through the binding sub-region. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] FIG1A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0072] FIG1B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0073] FIG1C is an enlarged schematic diagram of the first binding sub-region Q1 in FIG1A ;

[0074] FIG1D is an enlarged schematic diagram of the second binding sub-region Q2 in FIG1A ;

[0075] FIG2A is a waveform diagram of a current I0 on a clock signal line when at least one embodiment of the array substrate shown in FIG1A is in operation;

[0076] FIG2B is a waveform diagram of the current I1 on the clock signal line when the relevant array substrate is working;

[0077] FIG3A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0078] FIG3B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0079] FIG3C is an enlarged schematic diagram of the first binding sub-region Q1 and the second binding sub-region Q2 in FIG3A ;

[0080] FIG3D is an enlarged schematic diagram of the third binding sub-region Q3 and the fourth binding sub-region Q4 in FIG3A ;

[0081] FIG4A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0082] FIG4B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0083] FIG4C is an enlarged schematic diagram of the first binding sub-region Q1 in FIG4A ;

[0084] FIG5 is a layout diagram of six signal traces in an array substrate according to at least one embodiment of the present disclosure;

[0085] FIG6 is a layout diagram of the gate metal layer in FIG5 ;

[0086] FIG7 is a layout diagram of the source and drain metal layers in FIG5 ;

[0087] FIG8 is a layout diagram of the conductive layer in FIG5;

[0088] FIG9 is a cross-sectional view of AA′ in FIG5 ;

[0089] FIG10 is a schematic diagram showing the actual connection relationship between the pad terminal and the signal trace;

[0090] FIG11 is a layout diagram of the gate metal layer in FIG10 ;

[0091] FIG12 is a layout diagram of the source / drain metal layer in FIG10 ;

[0092] FIG. 13 is a layout diagram of the conductive layer in FIG. 10

[0093] FIG14 is a schematic diagram showing the connection relationship between the actual signal traces and the GOA module;

[0094] FIG15 is a circuit diagram of at least one embodiment of the driving circuit;

[0095] FIG16 is a waveform diagram of the current on the clock signal line before and after the channel width-to-length ratio of the output transistor M3 decreases;

[0096] FIG17 is a comparison diagram of the channel width W of M3 and the current I on the clock signal line;

[0097] FIG18 is a comparison diagram of the channel width of M3 and the falling time Tf of the driving signal;

[0098] FIG19 is a waveform diagram of a clock signal CLK in at least one embodiment of the present disclosure;

[0099] FIG20 is a waveform diagram of the current I on the clock signal line when the rising edge of the clock signal includes two steps;

[0100] FIG. 21 is a waveform diagram of a current I on a clock signal line when a rising edge of a clock signal includes only one step in the related art. DETAILED DESCRIPTION

[0101] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0102] The array substrate according to the embodiment of the present disclosure includes a display area and a non-display area, wherein the non-display area includes at least one binding sub-area, wherein the binding sub-area is electrically connected to a circuit board, and the array substrate further includes a driving module disposed in the non-display area, wherein the circuit board provides a driving control signal to the driving module via the binding sub-area.

[0103] The at least one binding sub-region includes at least three signal providing regions;

[0104] The at least one binding sub-region includes a plurality of pad terminals arranged in the at least three signal providing regions, and the pad terminals provide driving control signals to the driving module through signal wiring.

[0105] In the related borderless screen display product, the driving module includes a plurality of cascaded driving circuits, and the plurality of cascaded driving circuits are arranged along the first direction. In the related art, the non-display area includes at least one binding sub-area, and the at least one binding sub-area can be arranged along the first direction; the at least one binding sub-area includes two signal supply areas, the first signal supply area can be set at the left end of the leftmost binding sub-area, and the second signal supply area can be set at the right end of the rightmost binding sub-area. Therefore, the length of the signal trace for receiving the driving control signal of the driving circuit located in the middle is longer, so the temperature of the signal trace is high, which can cause abnormality of the driving circuit or generate high-temperature gravity yellow spots in the display screen, affecting the display effect. Based on this, in the array substrate described in the embodiment of the present disclosure, the non-display area includes at least one binding sub-area, and the circuit board provides the driving control signal to the driving module through the binding sub-area. The at least one binding sub-area is set to include at least three signal supply areas, and the pad terminals set in the at least three signal supply areas provide the driving control signal to the driving module through the signal trace, so as to reduce the temperature of the signal trace by increasing the signal access points.

[0106] In at least one embodiment of the present disclosure, the first direction may be a row direction, that is, a horizontal direction, but is not limited thereto.

[0107] In the borderless screen display product, gate lines extending along the row direction and gate lines extending along the column direction are provided, and the gate lines in the row direction and the gate lines in the column direction are electrically connected. Referring to Figure 1, the gate lines GLH extending along the row direction and the gate lines GLV extending along the column direction are electrically connected through the connection point D, as well as the data lines extending along the column direction. The gate lines extending along the column direction are electrically connected to the driving module for receiving the driving signals generated by the driving module. The driving module includes multiple cascaded driving circuits (the driving circuits can be gate driving circuits).

[0108] Optionally, the driving control signal includes at least one of a clock signal, a common electrode voltage signal, a DC voltage signal, and a frame start signal.

[0109] In at least one embodiment of the present disclosure, the drive control signal includes, but is not limited to, a ground signal, a power supply voltage signal, a common electrode voltage signal, a common electrode feedback voltage signal, a clock signal, a high voltage signal, a first low voltage signal, a second low voltage signal, a frame start signal, an ADD test signal, and the like. The principle of heat generation by these signals on signal traces is the same, except that, compared to other signals, the clock signal is a high-frequency square wave signal, and the heat generated by the signal trace used to transmit the clock signal has the greatest impact on the temperature of the signal trace. In at least one embodiment of the present disclosure, the drive control signal is described as a clock signal.

[0110] In related high-resolution, high-refresh-rate display products, due to limitations such as the border and charging rate, the current of the signal lines that transmit the drive control signals is large, resulting in high signal line temperatures, which can easily lead to defects such as multiple outputs of the drive circuit and high-temperature black spots on the display.

[0111] In at least one embodiment of the present disclosure, the non-display area includes a plurality of binding sub-areas; the plurality of pad terminals are arranged along a first direction;

[0112] The binding sub-area includes a first signal providing area and a second signal providing area;

[0113] The plurality of pad terminals include a plurality of first pad terminals and a plurality of second pad terminals;

[0114] The first pad terminal corresponds to the first signal supply area, and the second pad terminal corresponds to the second signal supply area;

[0115] The first pad terminal and the second pad terminal are disposed on two opposite sides of the binding sub-region.

[0116] In a specific implementation, the non-display area may include multiple binding sub-areas, each binding sub-area may include two signal supply areas, the multiple pad terminals include a first pad terminal arranged in the first signal supply area and a second pad terminal arranged in the second signal supply area, and the first pad terminal and the second pad terminal are arranged on opposite sides of the binding sub-area.

[0117] The array substrate according to at least one embodiment of the present disclosure further includes a data line at least partially disposed in the display area;

[0118] The plurality of pad terminals further include a plurality of third pad terminals;

[0119] The third pad terminal is provided between the first pad terminal and the second pad terminal;

[0120] The third pad terminal is electrically connected to the data line and is used to provide a data voltage to the data line.

[0121] In a specific implementation, the array substrate may further include a data line extending along a vertical direction, and a third pad terminal disposed between the first pad terminal and the second pad terminal provides a data voltage for the data line.

[0122] In at least one embodiment of the present disclosure, the signal line is used to provide a clock signal to the driving module; the non-display area includes a first binding sub-area and a second binding sub-area;

[0123] The array substrate further includes at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region;

[0124] The clock signal line includes a first end and a second end;

[0125] The first signal providing region of the first binding sub-region is provided at a first end of the first binding sub-region, and the second signal providing region of the first binding sub-region is provided at a second end of the first binding sub-region;

[0126] The first signal providing region of the second binding sub-region is provided at a first end portion of the second binding sub-region, and the second signal providing region of the second binding sub-region is provided at a second end portion of the first binding sub-region;

[0127] A first end of the first binding sub-region is close to a first end of the clock signal line, and a second end of the second binding sub-region is close to a second end of the clock signal line.

[0128] In a specific implementation, the non-display area may include two binding sub-areas, at least one clock signal line extending along the first direction is arranged between the driving module and the binding sub-area, the first signal supply area of ​​the first binding sub-area is arranged at the first end of the first binding sub-area, and the second signal supply area of ​​the first binding sub-area is arranged at the second end of the first binding sub-area; the first signal supply area of ​​the second binding sub-area is arranged at the first end of the second binding sub-area, and the second signal supply area of ​​the second binding sub-area is arranged at the second end of the first binding sub-area; the first end of the first binding sub-area is close to the first end of the clock signal line, and the second end of the second binding sub-area is close to the second end of the clock signal line.

[0129] Optionally, when the first direction is a horizontal direction, the first end may be a left end, and the second end may be a right end, but the present invention is not limited thereto.

[0130] In at least one embodiment of the present disclosure, the clock signal line is provided in the first metal layer; the first binding sub-region is electrically connected to the clock signal line via a signal trace formed in the second metal layer and provided in the second signal providing region thereof;

[0131] The second binding sub-region is electrically connected to the clock signal line via a signal trace formed on the second metal layer and provided in the first signal providing region thereof;

[0132] The first metal layer and the second metal layer are different metal layers.

[0133] In a specific implementation, the first binding sub-region is electrically connected to the clock signal line through a signal route located in a second signal providing region and located on a different layer from the clock signal line; the second binding sub-region is electrically connected to the clock signal line through a signal route located in a first signal providing region and located on a different layer from the clock signal line, so as to avoid a short circuit between the signal route and the clock signal line at the interaction point.

[0134] In at least one embodiment of the present disclosure, the first binding sub-region is electrically connected to the clock signal line via a signal trace formed on the first metal layer and provided in the first signal providing region thereof;

[0135] The second binding sub-region is electrically connected to the clock signal line via a signal trace formed on the first metal layer and arranged in the second signal providing region of the second binding sub-region.

[0136] In a specific implementation, at the edge, the first binding sub-area is electrically connected to the clock signal line through a signal trace set in the same layer as the clock signal line in its first signal supply area, and the second binding sub-area is electrically connected to the clock signal line through a signal trace set in the same layer as the clock signal line in its second signal supply area, so as to facilitate electrical connection between the signal trace and the clock signal line.

[0137] Optionally, the first metal layer may be a gate metal layer, and the second metal layer may be a source / drain metal layer, but is not limited thereto.

[0138] As shown in FIG1A , an array substrate according to at least one embodiment of the present disclosure includes a display area A0 and a non-display area; the non-display area includes a first non-display region F1 disposed on a first side of the display area A0 ;

[0139] The array substrate according to at least one embodiment of the present disclosure includes a driving module, a first binding sub-region Q1 and a second binding sub-region Q2;

[0140] The driving module includes multiple driving circuits arranged along a first direction;

[0141] The first signal providing area included in the first binding sub-area Q1 is marked as S11, the second signal providing area included in the first binding sub-area Q1 is marked as S12, and the third signal providing area included in the first binding sub-area Q1 is marked as S13;

[0142] The first signal providing area included in the second binding sub-area Q2 is marked as S21, the second signal providing area included in the second binding sub-area Q2 is marked as S22, and the third signal providing area included in the second binding sub-area Q2 is marked as S23;

[0143] S11 is provided at the left end of Q1, S12 is provided at the right end of Q1, and S13 is provided between S11 and S12, that is, S11 and S12 are provided on opposite sides of S13;

[0144] S21 is provided at the left end of Q2, S22 is provided at the right end of Q2, and S23 is provided between S21 and S22, that is, S21 and S22 are provided on opposite sides of S23;

[0145] At least one embodiment of the array substrate includes a first first pad terminal H11, a second first pad terminal H21, a third first pad terminal H31, and a fourth first pad terminal H41 provided at S11;

[0146] At least one embodiment of the array substrate further includes a fifth first pad terminal H51, a sixth first pad terminal H61, and a seventh first pad terminal H71 provided at S21;

[0147] At least one embodiment of the array substrate further includes a first second pad terminal H12, a second second pad terminal H22, and a third second pad terminal H32 provided at S12;

[0148] At least one embodiment of the array substrate further includes a fourth second pad terminal H42, a fifth second pad terminal H52, a sixth second pad terminal H62, and a seventh second pad terminal H72 provided at S22;

[0149] At least one embodiment of the array substrate further includes a first third pad terminal H13, a second third pad terminal H23, a third third pad terminal H33, a fourth third pad terminal H43, a fifth third pad terminal H53, and a sixth third pad terminal H63 provided at S13;

[0150] At least one embodiment of the array substrate further includes a seventh third pad terminal H73, an eighth third pad terminal H83, a ninth third pad terminal H93, a tenth third pad terminal H103, an eleventh third pad terminal H113, and a twelfth third pad terminal H123 provided at S23;

[0151] In FIG1A , GA1 is a first-stage driving circuit included in the driving module, GA2 is a second-stage driving circuit included in the driving module, GA3 is a third-stage driving circuit included in the driving module, GAp is a p-th stage driving circuit included in the driving module, GAp+1 is a p+1-th stage driving circuit included in the driving module, GAp+2 is a p+2-th stage driving circuit included in the driving module, GAp+3 is a p+3-th stage driving circuit included in the driving module, GAp+4 is a p+4-th stage driving circuit included in the driving module, GAp+5 is a p+5-th stage driving circuit included in the driving module, GAb-2 is a b-2-th stage driving module included in the driving module, GAb-1 is a b-1-th stage driving module included in the driving module, and GAb is a b-th stage driving module included in the driving module.

[0152] Wherein, p and b are positive integers.

[0153] In at least one embodiment shown in FIG1A , the first clock signal line is labeled CK1 , the second clock signal line is labeled CK2 , and the third clock signal line is labeled CK3 ; each clock signal line is disposed in the gate metal layer;

[0154] CK1, CK2, and CK3 all extend in the horizontal direction;

[0155] The pad terminals are arranged in a horizontal direction;

[0156] The data line labeled DL1 is the first data line, the data line labeled DL2 is the second data line, the data line labeled DL3 is the third data line, the data line labeled DL4 is the fourth data line, the data line labeled DL5 is the fifth data line, the data line labeled DL6 is the sixth data line, the data line labeled DL7 is the seventh data line, the data line labeled DL8 is the eighth data line, the data line labeled DL9 is the ninth data line, the data line labeled DL10 is the tenth data line, the data line labeled DL11 is the eleventh data line, and the data line labeled DL12 is the twelfth data line; each data line is set in the source and drain metal layer.

[0157] In at least one embodiment shown in FIG1A , H11 is directly electrically connected to GA1 via a first signal trace L1 provided on the gate metal layer, or H11 is electrically connected to both GA1 and GA2 via the first signal trace provided on the gate metal layer, for providing an initial trigger signal (STV signal) for the driving circuit, H21 is electrically connected to the left end of CK1 via a second signal trace L2 provided on the gate metal layer, H31 is electrically connected to the left end of CK2 via a third signal trace L3 provided on the gate metal layer, and H41 is electrically connected to the left end of CK3 via a fourth signal trace L4 provided on the gate metal layer, for providing a clock signal;

[0158] H12 is electrically connected to CK3 via a fifth signal trace L5 provided on the source / drain metal layer, H22 is electrically connected to CK2 via a sixth signal trace L6 provided on the source / drain metal layer, and H32 is electrically connected to CK1 via a seventh signal trace L7 provided on the source / drain metal layer;

[0159] H51 is electrically connected to CK3 via an eighth signal trace L8 provided on the source / drain metal layer, H61 is electrically connected to CK2 via a ninth signal trace L9 provided on the source / drain metal layer, and H71 is electrically connected to CK1 via a tenth signal trace L10 provided on the source / drain metal layer;

[0160] H42 is electrically connected to the right end of CK3 via an eleventh signal trace L11 provided on the gate metal layer, H52 is electrically connected to the right end of CK2 via a twelfth signal trace L12 provided on the gate metal layer, and H62 is electrically connected to the right end of CK1 via a thirteenth signal trace L13 provided on the gate metal layer, for providing a clock signal; H72 is directly electrically connected to Gab via a fourteenth signal trace L14 provided on the gate metal layer, or H72 is simultaneously connected to GAb-1 and Gab via the fourteenth signal trace L14 provided on the gate metal layer, for providing an initial trigger signal. Optionally, in this case, the driving circuits included at both ends of the driving module can be electrically connected to the initial trigger signal, so that the driving module can achieve a bidirectional scanning mode, or the driving circuit included at only one of the two ends of the driving module can be electrically connected to the initial trigger signal to achieve unidirectional scanning, which is not limited here;

[0161] H13 is electrically connected to DL1, H23 is electrically connected to DL2, H33 is electrically connected to DL3, H43 is electrically connected to DL4, H53 is electrically connected to DL5, H63 is electrically connected to DL6, H73 is electrically connected to DL7, H83 is electrically connected to DL8, H93 is electrically connected to DL9, H103 is electrically connected to DL10, H113 is electrically connected to DL11, and H123 is electrically connected to DL12.

[0162] In at least one embodiment of the array substrate shown in FIG. 1A , the driving module, CK1 , CK2 , CK3 , and each binding sub-region are all disposed in the first non-display region F1 , which can achieve a full-screen display effect.

[0163] As shown in FIG1B , based on FIG1A , the first end and the second end of each clock signal line are marked, wherein the first end is the left end and the second end is the right end;

[0164] In Figure 1B, the first end of CK1 is labeled D11, the second end of CK1 is labeled D12, the first end of CK2 is labeled D21, the second end of CK2 is labeled D22, the first end of CK3 is labeled D31, and the second end of CK3 is labeled D32.

[0165] FIG1C is an enlarged schematic diagram of the first binding sub-region Q1 in FIG1A , and FIG1D is an enlarged schematic diagram of the second binding sub-region Q2 in FIG1A .

[0166] 2A is a waveform diagram of a current I0 on a clock signal line when at least one embodiment of the array substrate shown in FIG. 1A is in operation, and FIG. 2B is a waveform diagram of a current I1 on a clock signal line when the related array substrate is in operation.

[0167] By comparison, when at least one embodiment of the array substrate shown in FIG. 1A is in operation, the current value of the current I0 on the clock signal line is smaller than the current value of the current I1 on the clock signal line of the related array substrate when in operation.

[0168] In at least one embodiment of the present disclosure, the non-display area includes M binding sub-areas arranged along a first direction; M is an integer greater than or equal to 3; the array substrate includes a plurality of pad terminals disposed in the binding sub-areas, and the plurality of pad terminals are arranged along the first direction;

[0169] The signal providing area included in the binding sub-area is arranged at the first end or the second end of the binding sub-area.

[0170] In a specific implementation, the non-display area may include at least three binding sub-areas arranged along the first direction, and the signal providing area included in each binding sub-area may be set at the first end or the second end of the binding sub-area.

[0171] In at least one embodiment of the present disclosure, the signal line is used to provide a clock signal for the driving module; the array substrate further includes at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0172] The clock signal line includes a first end and a second end that are oppositely arranged;

[0173] The signal providing region of the first binding sub-region is set at a first end of the first binding sub-region, and the signal providing region of the Mth binding sub-region is set at a second end of the Mth binding sub-region;

[0174] The signal providing area of ​​the mth binding sub-area is provided at the first end or the second end of the mth binding sub-area, where m is an integer greater than 1 and less than M;

[0175] The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the Mth binding sub-region is close to the second end of the clock signal line.

[0176] Optionally, the first end portion may be a left end portion, and the second end portion may be a right end portion.

[0177] In a specific implementation, when the non-display area includes at least three binding sub-areas arranged along a first direction (the first direction can be a horizontal direction), the signal supply area of ​​the first binding sub-area located on the leftmost side can be set at the left end of the first binding sub-area, the signal supply area of ​​the Mth binding sub-area located on the rightmost side can be set at the right end of the Mth binding sub-area, the mth binding sub-area is set between the first binding sub-area and the Mth binding sub-area, and the signal supply areas of the mth binding sub-area are set at the left end or right end of the mth binding sub-area, the left end of the first binding sub-area is close to the left end of the clock signal line, and the right end of the Mth binding sub-area is close to the right end of the clock signal line.

[0178] As shown in FIG3A , the array substrate according to at least one embodiment of the present disclosure includes a display area A0 and a non-display area; the non-display area includes a first non-display region F1 disposed on a first side of the display area A0;

[0179] The array substrate according to at least one embodiment of the present disclosure includes a driving module, a first binding sub-region Q1, a second binding sub-region Q2, a third binding sub-region Q3, and a fourth binding sub-region Q4; each binding sub-region includes a signal providing region;

[0180] The driving module includes multiple driving circuits arranged along a first direction;

[0181] The signal providing area included in the first binding sub-area Q1 is marked as S1; the signal providing area included in the second binding sub-area Q2 is marked as S2; the signal providing area included in the third binding sub-area Q3 is marked as S3; the signal providing area included in the fourth binding sub-area Q4 is marked as S4;

[0182] S1 is set at the left end of Q1; S2 is set at the left end of Q2; S3 is set at the right end of Q3; S4 is set at the right end of Q4;

[0183] In FIG3A , GA1 is a first-stage driving circuit included in the driving module, GA2 is a second-stage driving circuit included in the driving module, GA3 is a third-stage driving circuit included in the driving module, GAp is a p-th stage driving circuit included in the driving module, GAp+1 is a p+1-th stage driving circuit included in the driving module, GAp+2 is a p+2-th stage driving circuit included in the driving module, GAp+3 is a p+3-th stage driving circuit included in the driving module, GAp+4 is a p+4-th stage driving circuit included in the driving module, GAp+5 is a p+5-th stage driving circuit included in the driving module, GAb-2 is a b-2-th stage driving module included in the driving module, GAb-1 is a b-1-th stage driving module included in the driving module, and GAb is a b-th stage driving module included in the driving module.

[0184] Wherein, p and b are positive integers.

[0185] In at least one embodiment shown in FIG3A , the line labeled CK1 is a first clock signal line, the line labeled CK2 is a second clock signal line, and the line labeled CK3 is a third clock signal line; each clock signal line is disposed in the gate metal layer;

[0186] CK1, CK2, and CK3 all extend in the horizontal direction;

[0187] The pad terminals are arranged in a horizontal direction;

[0188] In FIG3A , H11 is the first first pad terminal, H21 is the second first pad terminal; H31 is the third first pad terminal, H41 is the fourth first pad terminal; H51 is the fifth first pad terminal, H61 is the sixth first pad terminal; H71 is the seventh first pad terminal, H81 is the eighth first pad terminal; H91 is the ninth first pad terminal, H101 is the tenth first pad terminal; H111 is the eleventh first pad terminal, H121 is the twelfth first pad terminal; H131 is the thirteenth first pad terminal, H141 is the fourteenth first pad terminal;

[0189] H11, H21, H31 and H41 are set in S1, H51, H61 and H71 are set in S2, H81, H91 and H101 are set in S3, H111, H121, H131 and H141 are set in S4; H11 is directly electrically connected to GA1 and GA2 for providing a clock signal;

[0190] H21 is electrically connected to the left end of CK1, H31 is electrically connected to the left end of CK2, and H41 is electrically connected to the left end of CK3;

[0191] H51 is electrically connected to the middle of CK3, H61 is electrically connected to the middle of CK2, and H71 is electrically connected to the middle of CK3;

[0192] H81 is electrically connected to the middle of CK3, H91 is electrically connected to the middle of CK2, and H101 is electrically connected to the middle of CK3;

[0193] H111 is electrically connected to the right end of CK3, H121 is electrically connected to the right end of CK2, H131 is electrically connected to the right end of CK1, and H141 is directly electrically connected to GAb-1 and Gab for providing clock signals.

[0194] In at least one embodiment of the array substrate shown in FIG. 3A , the driving module, CK1 , CK2 , CK3 , and each binding sub-region are all disposed in the first non-display region F1 .

[0195] As shown in FIG3B , based on FIG3A , the first end and the second end of each clock signal line are marked, wherein the first end is the left end and the second end is the right end;

[0196] In Figure 3B, the first end of CK1 is labeled D11, the second end of CK1 is labeled D12, the first end of CK2 is labeled D21, the second end of CK2 is labeled D22, the first end of CK3 is labeled D31, and the second end of CK3 is labeled D32.

[0197] FIG3C is an enlarged schematic diagram of the first binding sub-region Q1 and the second binding sub-region Q2 in FIG3A , and FIG3D is an enlarged schematic diagram of the third binding sub-region Q3 and the fourth binding sub-region Q4 in FIG3A .

[0198] In at least one embodiment shown in FIG3A , the number of binding sub-areas is an even number, the pad terminal for providing the clock signal of the binding sub-area located at the leftmost end is led out from the left end of the binding sub-area, and the pad terminal for providing the clock signal of the binding sub-area located at the rightmost end is led out from the right end of the binding sub-area, and the binding sub-area located in the middle can be divided into two groups, the pad terminal for providing the clock signal of the binding sub-area close to the left end is led out from the left end of the binding sub-area, and the pad terminal for providing the clock signal of the binding sub-area close to the right end is led out from the right end of the binding sub-area, that is, the overall design is symmetrical with respect to the center line of the array substrate.

[0199] In at least one embodiment of the present disclosure, the number of the binding sub-regions may be an even number or an odd number;

[0200] The pad terminal for providing the clock signal of the leftmost binding sub-area is led out from the left end of the binding sub-area, and the pad terminal for providing the clock signal of the rightmost binding sub-area is led out from the right end of the binding sub-area. The pad terminal for providing the clock signal of the binding sub-area located in the middle can be partially led out from the left end of the binding sub-area and the other part can be led out from the right end of the binding sub-area; or, the pad terminal for providing the clock signal of the binding sub-area located in the middle can be led out entirely from the left end or the right end.

[0201] In at least one embodiment of the present disclosure, the number of the binding sub-regions may be an even number or an odd number;

[0202] The pad terminal for providing the clock signal of the leftmost binding sub-area is led out from the left end of the binding sub-area, the pad terminal for providing the clock signal of the rightmost binding sub-area is led out from the right end of the binding sub-area, and the pad terminal for providing the clock signal of the binding sub-area located in the middle can be led out from both the left and right ends of the binding sub-area.

[0203] In at least one embodiment of the present disclosure, the number of the binding sub-regions may be an even number or an odd number;

[0204] The pad terminal for providing the clock signal of the leftmost binding sub-area is led out from the left end of the binding sub-area, the pad terminal for providing the clock signal of the rightmost binding sub-area is led out from the right end of the binding sub-area, the pad terminals for providing the clock signal of the middle part of the binding sub-area are led out from both the left and right ends of the binding sub-area, and the pad terminals for providing the clock signal of another middle part of the binding sub-area are led out from the left or right end of the binding sub-area.

[0205] In at least one embodiment of the present disclosure, the non-display area includes a binding sub-area; the array substrate includes a plurality of pad terminals disposed in the binding sub-area, and the plurality of pad terminals are arranged along a first direction;

[0206] The binding sub-area includes N signal providing areas; N is an integer greater than or equal to 3

[0207] Two of the N signal supply areas are arranged at opposite sides of the binding sub-area, and the signal supply areas other than the two signal supply areas are arranged in the middle of the binding sub-area.

[0208] In a specific implementation, the non-display area may include a binding sub-area, the binding sub-area includes at least three signal supply areas, and the N signal supply areas are arranged along the first direction.

[0209] In at least one embodiment of the present disclosure, the signal line is used to provide a clock signal for the driving module; the array substrate further includes at least one clock signal line extending along the first direction and arranged between the driving module and the binding sub-region;

[0210] The clock signal line includes a first end and a second end;

[0211] The first signal providing area of ​​the binding sub-area is set at the first end of the binding sub-area, the Nth signal providing area of ​​the binding sub-area is set at the second end of the binding sub-area, and the nth signal providing area of ​​the binding sub-area is set in the middle of the binding sub-area; n is an integer greater than 1 and less than N.

[0212] As shown in FIG4A , the array substrate according to at least one embodiment of the present disclosure includes a display area A0 and a non-display area; the non-display area includes a first non-display region F1 disposed on a first side of the display area A0 ;

[0213] The array substrate according to at least one embodiment of the present disclosure includes a driving module and a first binding sub-region Q1; the first binding sub-region includes four signal providing regions;

[0214] The driving module includes multiple driving circuits arranged along a first direction;

[0215] The first signal providing area included in the first binding sub-area Q1 is marked as S1; the second signal providing area included in the first binding sub-area Q1 is marked as S2; the third signal providing area included in the first binding sub-area Q1 is marked as S3; and the fourth signal providing area included in the first binding sub-area Q1 is marked as S4;

[0216] S1 is set at the left end of Q1; S2 and S3 are set between S1 and S4; S4 is set at the right end of Q1;

[0217] In FIG4A , GA1 is a first-stage driving circuit included in the driving module, GA2 is a second-stage driving circuit included in the driving module, GA3 is a third-stage driving circuit included in the driving module, GAp is a p-th stage driving circuit included in the driving module, GAp+1 is a p+1-th stage driving circuit included in the driving module, GAp+2 is a p+2-th stage driving circuit included in the driving module, GAp+3 is a p+3-th stage driving circuit included in the driving module, GAp+4 is a p+4-th stage driving circuit included in the driving module, GAp+5 is a p+5-th stage driving circuit included in the driving module, GAb-2 is a b-2-th stage driving module included in the driving module, GAb-1 is a b-1-th stage driving module included in the driving module, and GAb is a b-th stage driving module included in the driving module.

[0218] Wherein, p and b are positive integers.

[0219] In at least one embodiment shown in FIG. 4A , the line labeled CK1 is a first clock signal line, the line labeled CK2 is a second clock signal line, and the line labeled CK3 is a third clock signal line; each clock signal line is disposed in a gate metal layer;

[0220] CK1, CK2, and CK3 all extend in the horizontal direction;

[0221] The pad terminals are arranged in a horizontal direction;

[0222] In FIG4A , H11 is the first first pad terminal, H21 is the second first pad terminal; H31 is the third first pad terminal, H41 is the fourth first pad terminal; H51 is the fifth first pad terminal, H61 is the sixth first pad terminal; H71 is the seventh first pad terminal, H81 is the eighth first pad terminal; H91 is the ninth first pad terminal, H101 is the tenth first pad terminal; H111 is the eleventh first pad terminal, H121 is the twelfth first pad terminal; H131 is the thirteenth first pad terminal, H141 is the fourteenth first pad terminal;

[0223] H11, H21, H31 and H41 are set in S1, H51, H61 and H71 are set in S2, H81, H91 and H101 are set in S3, H111, H121, H131 and H141 are set in S4; H11 is directly electrically connected to GA1 and GA2 for providing a clock signal;

[0224] H21 is electrically connected to the left end of CK1, H31 is electrically connected to the left end of CK2, and H41 is electrically connected to the left end of CK3;

[0225] H51 is electrically connected to the middle of CK3, H61 is electrically connected to the middle of CK2, and H71 is electrically connected to the middle of CK3;

[0226] H81 is electrically connected to the middle of CK3, H91 is electrically connected to the middle of CK2, and H101 is electrically connected to the middle of CK3;

[0227] H111 is electrically connected to the right end of CK3, H121 is electrically connected to the right end of CK2, H131 is electrically connected to the right end of CK1, and H141 is directly electrically connected to GAb-1 and Gab for providing clock signals.

[0228] In at least one embodiment of the array substrate shown in FIG. 4A , the driving module, CK1 , CK2 , CK3 , and each binding sub-region are all disposed in the first non-display region F1 .

[0229] As shown in FIG4B , based on FIG4A , the first end and the second end of each clock signal line are marked, wherein the first end is the left end and the second end is the right end;

[0230] In Figure 4B, the first end of CK1 is labeled D11, the second end of CK1 is labeled D12, the first end of CK2 is labeled D21, the second end of CK2 is labeled D22, the first end of CK3 is labeled D31, and the second end of CK3 is labeled D32.

[0231] FIG. 4C is an enlarged schematic diagram of the first binding sub-region Q1 in FIG. 4A .

[0232] In at least one embodiment of the present disclosure, the non-display area includes a first non-display region disposed on a first side of the display area;

[0233] The clock signal line, the driving module and the binding sub-area are all arranged in the first non-display area.

[0234] In at least one embodiment of the present disclosure, the signal trace includes at least two electrically connected signal line portions;

[0235] The at least two signal line portions are respectively formed in different metal layers.

[0236] In specific implementation, the heat source power of the signal routing mainly comes from the current flowing through the signal routing and the square resistance per unit length. In related technologies, the signal routing adopts a single-layer routing. In at least one embodiment of the present disclosure, the signal routing is configured to include at least two electrically connected signal line portions, and the at least two signal line portions are respectively formed in different metal layers, thereby reducing the resistance of the signal routing and achieving the purpose of reducing the heat source power and thus reducing the temperature of the signal routing.

[0237] Optionally, the array substrate includes a first metal layer and a second metal layer;

[0238] The signal trace includes a first signal line portion and a second signal line portion;

[0239] The first signal line portion is formed in a first metal layer, and the second signal line portion is formed in a second metal layer.

[0240] In at least one embodiment of the present disclosure, the array substrate further includes a base, a conductive layer, a first insulating layer disposed between the first metal layer and the second metal layer, and a second insulating layer disposed between the second metal layer and the conductive layer;

[0241] The first signal line portion is electrically connected to the second signal line portion through a conductive pattern formed on the conductive layer and a via hole penetrating the second insulating layer;

[0242] The first metal layer, the second metal layer and the conductive layer are arranged in sequence along a direction away from the substrate.

[0243] The array substrate according to at least one embodiment of the present disclosure further includes a base;

[0244] An orthographic projection of the first signal line portion on the substrate at least partially overlaps with an orthographic projection of the second signal line portion on the substrate.

[0245] FIG5 is a layout diagram of six signal lines (six signal lines are used as an example, and the number of signal lines is not limited) in the array substrate according to at least one embodiment of the present disclosure.

[0246] In FIG5 , L1 is the first signal line, L2 is the second signal line, L3 is the third signal line, L4 is the fourth signal line, L5 is the fifth signal line, and L6 is the sixth signal line.

[0247] FIG6 is a layout diagram of the gate metal layer in FIG5 , FIG7 is a layout diagram of the source / drain metal layer in FIG5 , and FIG8 is a layout diagram of the conductive layer in FIG5 .

[0248] In Figure 6, the first signal line portion labeled L11 is included in the first signal routing, the first signal line portion labeled L21 is included in the second signal routing, the first signal line portion labeled L31 is included in the third signal routing, the first signal line portion labeled L41 is included in the fourth signal routing, the first signal line portion labeled L51 is included in the fifth signal routing, and the first signal line portion labeled L61 is included in the sixth signal routing.

[0249] As shown in Figure 7, the second signal line portion labeled L12 is included in the first signal routing, the second signal line portion labeled L22 is included in the second signal routing, the second signal line portion labeled L32 is included in the third signal routing, the second signal line portion labeled L42 is included in the fourth signal routing, the second signal line portion labeled L52 is included in the fifth signal routing, and the second signal line portion labeled L62 is included in the sixth signal routing.

[0250] FIG. 9 is a cross-sectional view taken along line AA′ in FIG. 5 .

[0251] In Figure 9, labeled 90 is the substrate, labeled 91 is the gate metal layer, labeled 92 is the first insulating layer (the first insulating layer can be, for example, a gate insulating layer), labeled 93 is the source-drain metal layer, labeled 94 is the second insulating layer (the second insulating layer can be, for example, a PVX passivation layer), and labeled 95 is the conductive layer (optionally, the conductive layer can be an ITO (indium tin oxide) layer on the same layer as the pixel electrode or the common electrode).

[0252] As shown in Figures 5 to 9, the orthographic projection of L11 on the substrate at least partially overlaps with the orthographic projection of L12 on the substrate, the orthographic projection of L21 on the substrate at least partially overlaps with the orthographic projection of L22 on the substrate, the orthographic projection of L31 on the substrate at least partially overlaps with the orthographic projection of L32 on the substrate, the orthographic projection of L41 on the substrate at least partially overlaps with the orthographic projection of L42 on the substrate, the orthographic projection of L51 on the substrate at least partially overlaps with the orthographic projection of L52 on the substrate, and the orthographic projection of L61 on the substrate at least partially overlaps with the orthographic projection of L62 on the substrate. Optionally, they may also completely overlap.

[0253] In specific implementation, when each signal line adopts double-layer wiring, the resistance value of each signal line can be reduced from 0.85 ohms in single-layer wiring to 0.43 ohms. The double-layer wiring has no effect on the current of each signal line. The temperature of the signal line is reduced from 53.3 degrees Celsius to 42.2 degrees Celsius, and the temperature of the signal line is directly and effectively reduced.

[0254] Optionally, the plurality of pad terminals include a first pad terminal for providing a clock signal and a third pad terminal for providing a data voltage;

[0255] The first pad terminal includes at least one first sub-pad and at least one second sub-pad; the third pad terminal includes at least one third sub-pad;

[0256] The first sub-pad includes a first sub-pad portion formed on the first metal layer and a second sub-pad portion formed on the second metal layer;

[0257] The second sub-pad includes a third sub-pad portion formed on the first metal layer;

[0258] The third sub-pad includes a fourth sub-pad portion formed in the first metal layer.

[0259] FIG10 is a schematic diagram showing the actual connection relationship between the pad terminals and the signal traces.

[0260] FIG11 is a layout diagram of the gate metal layer in FIG10 , FIG12 is a layout diagram of the source / drain metal layer in FIG10 , and FIG13 is a layout diagram of the conductive layer in FIG10 .

[0261] As shown in FIG10 , the first pad terminal for transmitting the clock signal includes a first sub-pad H01 and a second sub-pad H02 ; the third sub-pad H03 labeled H03 is used to transmit the data voltage;

[0262] As shown in FIG11 , the first sub-pad H01 includes a first sub-pad portion HB1 , the second sub-pad H02 includes a third sub-pad portion HB3 , and the third sub-pad H03 includes a fourth sub-pad portion HB4 ;

[0263] As shown in FIG12 , the first sub-pad H01 includes a second sub-pad portion HB2 ;

[0264] In FIG10 , the pads labeled HD are dummy pads.

[0265] In a specific implementation, each pad terminal also includes a conductive layer (the conductive layer can be made of ITO (indium tin oxide) for example). Referring to Figures 11 and 12, the first sub-pad portion HB1 is arranged in the gate metal layer and includes two branch structures. The second sub-pad portion HB2 is arranged in the source and drain metal layer and includes two branches, wherein the two branches included in HB1 and the two branches included in HB2 are arranged opposite to each other (the two branches included in HB1 are designed on the right side, and the two branches included in HB2 are designed on the left side, and do not overlap in the direction perpendicular to the substrate). HB1 and HB2 are electrically connected through a conductive layer and a via. The conductive layer is exposed to be bound to an FPC (flexible printed circuit board), and the conductive pattern located on the conductive layer is used to electrically connect the sub-pad portion formed in the gate metal layer and the sub-pad portion formed in the source and drain metal layer included in the same pad terminal.

[0266] FIG14 is a schematic diagram showing the connection relationship between actual signal traces and the GOA module. In FIG14 , the portion labeled GA is a driving circuit included in the driving module.

[0267] In at least one embodiment of the present disclosure, the driving module includes a multi-stage driving circuit;

[0268] The driving circuit includes an output transistor;

[0269] The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0270] A channel width-to-length ratio of the output transistor is smaller than a first width-to-length ratio threshold.

[0271] In a specific implementation, the drive circuit includes an output transistor configured to control the connection or disconnection between the clock signal line and the drive signal output terminal under the control of the potential of the first node. In related art, the channel width-to-length ratio of the output transistor is large, significantly impacting the load on the clock signal line and thereby increasing the temperature of the signal line. By reducing the channel width-to-length ratio of the output transistor, the current on the clock signal line is reduced, thereby reducing the temperature of the signal line. Furthermore, reducing the channel width-to-length ratio of the output transistor increases the fall time Tf of the drive signal, which can be compensated by increasing the channel width-to-length ratio of the output reset transistor.

[0272] Optionally, the first aspect ratio threshold may be greater than or equal to 6000 / 4.3 and less than or equal to 20000 / 4.3. Optionally, the first aspect ratio threshold may be greater than or equal to 9000 / 4.3 and less than or equal to 12000 / 4.3. For example, the first aspect ratio threshold may be 11000 / 4.3, 10500 / 4.3, 12000 / 5.3, etc., but is not limited thereto.

[0273] In at least one embodiment of the present disclosure, the driving circuit further includes an output reset transistor;

[0274] The gate of the output reset transistor is electrically connected to the reset terminal, the first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal;

[0275] A channel width-to-length ratio of the output reset transistor is greater than a second width-to-length ratio threshold.

[0276] Optionally, the second aspect ratio threshold may be greater than or equal to 10000 / 4.3 and less than or equal to 25000 / 4.3. Optionally, the second aspect ratio threshold may be greater than or equal to 13000 / 4.3 and less than or equal to 19000 / 4.3. For example, the second aspect ratio threshold may be 14000 / 4.3, 15000 / 4.3, 16000 / 4.3, etc., but is not limited thereto.

[0277] Optionally, the channel width-to-length ratio of the output transistor of the driving circuit can be smaller than the channel width-to-length ratio of the output reset transistor. For example, the channel width-to-length ratio of the output transistor of the driving circuit / the channel width-to-length ratio of the output reset transistor is between 1.1 and 1.4, including the endpoint values. Such a design improves the temperature on the peripheral signal lines without affecting the normal operation of the driving circuit.

[0278] As shown in FIG15 , at least one embodiment of the driving circuit may include a first transistor M1, a second transistor M2, an output transistor M3, an output reset transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, and a storage capacitor C0.

[0279] In Figure 15, labeled I1 is the input terminal, labeled R1 is the reset signal terminal, labeled STV0 is the frame reset terminal, labeled LVGL is the first low voltage terminal, labeled VGL is the second low voltage terminal, labeled PU is the first node, labeled PD1 is the first second node, labeled PD2 is the second first node, labeled OC is the carry output terminal, labeled GU is the drive signal output terminal, labeled RST is the reset terminal, labeled CLK is the clock signal terminal, labeled VDDO is the first control voltage terminal, and labeled VDDE is the second control voltage terminal.

[0280] FIG. 15 only shows one embodiment of the driving circuit and does not limit the structure of the driving circuit.

[0281] Taking the channel length of the driving transistor in the driving circuit as 4.3μm as an example, in the relevant technology, the channel width-to-length ratio of M3 can be 17500 / 4.3, and the channel width-to-length ratio of M4 can be 16000 / 4.3. While ensuring the frame, the channel width of M3 is simulated and adjusted with a step value of 1000μm. When the channel width-to-length ratio of M3 is reduced to 10500 / 4.3, the RMS (root mean square) value of the current of the corresponding clock signal line decreases from 35.33mA to 30.16mA, and the fall time of the driving signal increases from 1.88μs to 2.06μs. The temperature of the clock signal line drops significantly, directly from 53.3 degrees Celsius to 47.7 degrees Celsius. At the same time, it has little impact on the fall time of the driving signal, and the image quality loss is small.

[0282] In FIG16 , B1 is a waveform diagram of the current I on the clock signal line before the channel width-to-length ratio of M3 decreases, and B2 is a waveform diagram of the current I on the clock signal line after the channel width-to-length ratio of M3 decreases.

[0283] In FIG16 , the vertical axis represents the current I on the clock signal line, with a unit of A, and the horizontal axis represents the time t, with a unit of μs.

[0284] FIG17 is a comparison diagram of the channel width W of M3 and the current I on the clock signal line, and FIG18 is a comparison diagram of the channel width of M3 and the falling time Tf of the driving signal.

[0285] In at least one embodiment of the present disclosure, the signal trace is used to transmit a clock signal;

[0286] The rising edge of the clock signal includes at least two steps. Specifically, the rising edge of the clock signal can be implemented by adding a clock signal charge sharing (CLK Charge Sharing) circuit at the circuit driving end.

[0287] In a specific implementation, the rising edge of the clock signal is controlled to have multiple stages, that is, when the potential of the clock signal is controlled to suddenly change from a low voltage Vgl to a high voltage Vgh, the intermediate voltage GPM is increased to split the large single peak of the current on the rising edge of the clock signal into two smaller peaks, thereby achieving the purpose of reducing the current on the clock signal line.

[0288] In at least one embodiment of the present disclosure, the waveform of the clock signal CLK is shown in FIG. 19 .

[0289] In at least one embodiment shown in FIG19 , the voltage value of the intermediate voltage GPM is (Vgl+Vgh) / 2, the potential of the clock signal CLK is the duration of GPM is 0.5H, 1H is a line scan time, and after simulation, the RMS value of the current on the clock signal line drops from 35.33mA to 30.82mA.

[0290] FIG20 is a waveform diagram of the current I on the clock signal line when the rising edge of the clock signal includes two steps, and FIG21 is a waveform diagram of the current I on the clock signal line when the rising edge of the clock signal includes only one step in the related art.

[0291] The display device according to the embodiment of the present disclosure includes a circuit board and the above-mentioned array substrate;

[0292] The circuit board is electrically connected to the binding sub-region of the array substrate and is used to provide drive control signals to the drive module in the array substrate through the binding sub-region. The number of circuit boards can correspond to the number of binding sub-regions included in the array substrate. For example, if there are two binding sub-regions, two circuit boards can be provided.

[0293] In at least one embodiment of the present disclosure, a display device may include at least one circuit board, the circuit board includes a binding area, and at least one binding area of ​​at least one circuit board includes at least three signal providing areas; the binding area includes a plurality of gold finger structures for achieving electrical connection with the pad terminals of the array substrate (electrical connection can be achieved by welding or ACF (anisotropic conductive adhesive), etc.), transmitting data lines of the display area to provide data signals and control signals of the driving circuit.

[0294] The circuit board may be a flexible circuit board, and the circuit board may further include a data driving chip.

[0295] In at least one embodiment of the present disclosure, the display device may include two circuit boards, each circuit board is respectively bound to a corresponding binding sub-region, and the circuit board includes a plurality of first gold fingers, a plurality of second gold fingers, and a plurality of third gold fingers;

[0296] The first gold finger and the second gold finger are arranged on opposite sides of the circuit board, and the third gold finger is arranged between the first gold finger and the second gold finger;

[0297] The first gold finger is electrically connected to the first pad terminal for transmitting a driving control signal; the second gold finger is electrically connected to the second pad terminal for transmitting a driving control signal; the third gold finger is electrically connected to the third pad terminal for transmitting a data voltage.

[0298] In at least one embodiment of the present disclosure, the display device may include at least three circuit boards, each circuit board is respectively bound to a corresponding binding sub-region, and the circuit board includes a plurality of first gold fingers; the first gold fingers are electrically connected to the first pad terminal for transmitting a drive control signal;

[0299] The first gold finger included in the circuit board located on the far left is arranged at the left end of the circuit board, and the first gold finger included in the circuit board located on the far right can be arranged at the right end of the circuit board;

[0300] The first gold finger included in the circuit board located in the middle can be arranged at the left end and / or the right end of the circuit board.

[0301] In at least one embodiment of the present disclosure, the display device may include a circuit board, the circuit board being bound to a corresponding binding sub-region, the circuit board including a plurality of first gold fingers; the first gold fingers being electrically connected to the first pad terminal for transmitting a driving control signal;

[0302] The first gold fingers can be arranged at the left end, the right end and the middle of the circuit board.

[0303] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. An array substrate, comprising a display area and a non-display area, wherein the non-display area comprises at least one binding sub-area, wherein the binding sub-area is used to be electrically connected to a circuit board, and the array substrate further comprises a driving module disposed in the non-display area, wherein the circuit board provides a driving control signal to the driving module through the binding sub-area; The at least one binding sub-region includes at least three signal providing regions; The at least one binding sub-region includes a plurality of pad terminals arranged in the at least three signal providing regions, and the pad terminals provide driving control signals to the driving module through signal routings.

2. The array substrate according to claim 1, wherein: The non-display area includes a plurality of binding sub-areas; the plurality of pad terminals are arranged along a first direction; The binding sub-region includes a first signal providing region and a second signal providing region; The plurality of pad terminals include a plurality of first pad terminals and a plurality of second pad terminals; The first pad terminal corresponds to the first signal providing area, and the second pad terminal corresponds to the second signal providing area; The first pad terminal and the second pad terminal are disposed on two opposite sides of the binding sub-region.

3. The array substrate according to claim 2, wherein: Also included is a data line at least partially disposed in the display area; The plurality of pad terminals further include a plurality of third pad terminals; The third pad terminal is arranged between the first pad terminal and the second pad terminal; The third pad terminal is electrically connected to the data line and is used to provide data power to the data line. pressure.

4. The array substrate according to claim 1, wherein: The driving control signal includes at least one of a clock signal, a common electrode voltage signal, a direct current voltage signal, and a frame start signal.

5. The array substrate according to claim 2, wherein: The signal wiring is used to provide a clock signal for the driving module; the non-display area includes a first binding sub-area and a second binding sub-area; The array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region; The clock signal line includes a first end and a second end that are arranged opposite to each other; The first signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the second signal providing region of the first binding sub-region is arranged at a second end of the first binding sub-region; The first signal providing region of the second binding sub-region is arranged at a first end of the second binding sub-region, and the second signal providing region of the second binding sub-region is arranged at a second end of the first binding sub-region; The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the second binding sub-region is close to the second end of the clock signal line.

6. The array substrate according to claim 5, wherein: The clock signal line is arranged on the first metal layer; the first binding sub-region is electrically connected to the clock signal line via a signal routing line formed on the second metal layer and arranged in its second signal providing region; The second binding sub-region is electrically connected to the clock signal line through a signal trace formed on the second metal layer and arranged in the first signal providing region thereof; The first metal layer and the second metal layer are different metal layers.

7. The array substrate according to claim 6, wherein: The first binding sub-region is electrically connected to the clock signal line through a signal trace formed on the first metal layer and arranged in the first signal providing region thereof; The second binding sub-region is electrically connected to the clock signal line through a signal routing line formed on the first metal layer and arranged in the second signal providing region thereof.

8. The array substrate according to claim 1, wherein: The non-display area includes M binding sub-areas arranged along a first direction; M is an integer greater than or equal to 3; the plurality of pad terminals are arranged along the first direction; The signal providing area included in the binding sub-area is arranged at the first end or the second end of the binding sub-area.

9. The array substrate according to claim 8, wherein: The signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region; The clock signal line includes a first end and a second end; The signal providing region of the first binding sub-region is arranged at a first end of the first binding sub-region, and the signal providing region of the Mth binding sub-region is arranged at a second end of the Mth binding sub-region; The signal providing area of ​​the mth binding sub-area is provided at the first end or the second end of the mth binding sub-area, where m is an integer greater than 1 and less than M; The first end of the first binding sub-region is close to the first end of the clock signal line, and the second end of the Mth binding sub-region is close to the second end of the clock signal line.

10. The array substrate according to claim 1, wherein: The non-display area includes a binding sub-area; the plurality of pad terminals are arranged along a first direction; The binding sub-area includes N signal providing areas; N is an integer greater than or equal to 3 Two of the N signal providing areas are disposed at opposite sides of the binding sub-area, and signal providing areas other than the two signal providing areas of the N signal providing areas are disposed in the middle of the binding sub-area.

11. The array substrate according to claim 10, wherein: The signal line is used to provide a clock signal for the driving module; the array substrate further comprises at least one clock signal line extending along a first direction and arranged between the driving module and the binding sub-region; The clock signal line includes a first end and a second end; The first signal providing area of ​​the binding sub-area is set at the first end of the binding sub-area, the Nth signal providing area of ​​the binding sub-area is set at the second end of the binding sub-area, and the nth signal providing area of ​​the binding sub-area is set in the middle of the binding sub-area; n is an integer greater than 1 and less than N.

12. The array substrate according to claim 5, 6, 7, 9 or 11, wherein: The non-display area includes a first non-display region disposed on a first side of the display area; The clock signal line, the driving module and the binding sub-area are all arranged in the first non-display area.

13. The array substrate according to any one of claims 1 to 11, wherein: The signal routing includes at least two electrically connected signal line portions; The at least two signal line portions are respectively formed in different metal layers.

14. The array substrate according to claim 13, wherein: The array substrate comprises a first metal layer and a second metal layer; The signal routing line includes a first signal line portion and a second signal line portion; The first signal line portion is formed in a first metal layer, and the second signal line portion is formed in a second metal layer.

15. The array substrate according to claim 14, wherein: The array substrate further includes a base, a conductive layer, a first insulating layer disposed between the first metal layer and the second metal layer, and a second insulating layer disposed between the second metal layer and the conductive layer; The first signal line portion is electrically connected to the second signal line portion through a conductive pattern formed on the conductive layer and a via hole penetrating the second insulating layer; The first metal layer, the second metal layer and the conductive layer are arranged in sequence along a direction away from the substrate.

16. The array substrate according to claim 14, wherein: The array substrate further comprises a base; An orthographic projection of the first signal line portion on the substrate at least partially overlaps with an orthographic projection of the second signal line portion on the substrate.

17. The array substrate according to claim 14, wherein: The plurality of pad terminals include a first pad terminal for providing a clock signal and a third pad terminal for providing a data voltage; The first pad terminal includes at least one first sub-pad and at least one second sub-pad; the third pad terminal includes at least one third sub-pad; The first sub-pad includes a first sub-pad portion formed on the first metal layer and a second sub-pad portion formed on the second metal layer; The second sub-pad includes a third sub-pad portion formed on the first metal layer; The third sub pad includes a fourth sub pad portion formed in the first metal layer.

18. The array substrate according to any one of claims 1 to 11, wherein: The driving module includes a multi-stage driving circuit; The driving circuit includes an output transistor; The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal; The channel width-to-length ratio of the output transistor is less than a first width-to-length ratio threshold.

19. The array substrate according to claim 18, wherein: The driving circuit also includes an output reset transistor; The gate of the output reset transistor is electrically connected to the reset terminal, and the first stage of the output reset transistor is electrically connected to the drive terminal. The first reset transistor is electrically connected to the first voltage terminal; The channel width-to-length ratio of the output reset transistor is greater than a second width-to-length ratio threshold.

20. The array substrate according to any one of claims 1 to 11, wherein: The signal trace is used to transmit the clock signal; The rising edge of the clock signal includes at least two steps.

21. A display device comprising a circuit board and an array substrate according to any one of claims 1 to 20; The circuit board is electrically connected to the binding sub-region in the array substrate, and is used to provide a driving control signal to the driving module in the array substrate through the binding sub-region.

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