Pixel circuit, drive method and display apparatus

Abstract

The present disclosure provides a pixel circuit, a drive method and a display apparatus. The pixel circuit comprises a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit and a light-emitting control voltage control circuit. Under the control of an input signal, a reset signal and a light-emitting control signal, the light-emitting control voltage control circuit controls a light-emitting control voltage provided by a light-emitting control voltage end according to a light-emitting control data voltage provided by a light-emitting control data voltage end, an on-off data voltage provided by an on-off data voltage end and a control data voltage provided by a control data end. The pixel circuit in the embodiments of the present disclosure can implement full-grayscale PWM (pulse width modulation) driving, so as to thoroughly replace PAM (pulse amplitude modulation), thus greatly reducing power consumption and heat generation.

Description

Pixel circuit, driving method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310954438.2 filed in China on July 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, and a display device. Background Art

[0004] The related pixel circuit cannot realize full grayscale PWM (pulse width modulation) driving, cannot completely replace PAM (pulse amplitude modulation), and has high power consumption and high heat generation.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a pixel circuit, comprising a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, and a light-emitting control voltage control circuit;

[0007] The first light-emitting control circuit is electrically connected to the light-emitting control voltage terminal, the power supply voltage terminal and the first node respectively, and is used to control the connection between the power supply voltage terminal and the first node under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal;

[0008] The second light emitting control circuit is electrically connected to the light emitting control terminal, the first node, and the first electrode of the light emitting element, respectively, and is configured to control the connection between the first node and the first electrode of the light emitting element under the control of a light emitting control signal provided by the light emitting control terminal; and the second electrode of the light emitting element is electrically connected to the first voltage terminal;

[0009] The light-emitting control voltage control circuit is electrically connected to the light-emitting control voltage terminal, the light-emitting control input terminal, the light-emitting control reset terminal, the light-emitting control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the light-emitting control voltage provided by the light-emitting control voltage terminal according to the light-emitting control data voltage provided by the light-emitting control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal and the control data voltage provided by the control data terminal, under the control of the input signal provided by the light-emitting control input terminal, the reset signal provided by the light-emitting control reset terminal and the light-emitting control signal provided by the light-emitting control terminal.

[0010] Optionally, the light emitting control voltage control circuit includes an input circuit, a reset circuit, an on-off control circuit, a first control circuit, a second control circuit and a first control node control circuit;

[0011] The input circuit is electrically connected to the light-emitting control input terminal, the second voltage terminal and the light-emitting control voltage terminal respectively, and is used to control the connection between the light-emitting control voltage terminal and the second voltage terminal under the control of the input signal provided by the light-emitting control input terminal;

[0012] The reset circuit is electrically connected to the light emitting control reset terminal and the on-off control node respectively, and is used to control the potential of the on-off control node under the control of the reset signal provided by the light emitting control reset terminal;

[0013] The on-off control circuit is electrically connected to the on-off control node, the third voltage terminal and the light-emitting control voltage terminal respectively, and is used to control the connection between the light-emitting control voltage terminal and the third voltage terminal under the control of the potential of the on-off control node;

[0014] The first control circuit is electrically connected to the light emitting control reset terminal, the on-off control node and the first intermediate node respectively, and is used to control the connection between the on-off control node and the first intermediate node under the control of the reset signal;

[0015] The second control circuit is electrically connected to the first control node, the first intermediate node and the fourth voltage terminal respectively, and is used to control the connection between the first intermediate node and the fourth voltage terminal under the control of the potential of the first control node;

[0016] The first control node control circuit is electrically connected to the first control node, the light-emitting control end, the light-emitting control data voltage end, the on-off data voltage end and the control data end, respectively, and is used to control the potential of the first control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control end.

[0017] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first intermediate node control circuit;

[0018] The first intermediate node control circuit is electrically connected to the light-emitting control voltage terminal, the first intermediate node and the fourth voltage terminal respectively, and is used to control the connection between the first intermediate node and the fourth voltage terminal under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal.

[0019] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0020] The first energy storage circuit is electrically connected to the light-emitting control voltage terminal, and is used to maintain the potential of the light-emitting control voltage terminal;

[0021] The second energy storage circuit is electrically connected to the on-off control node and is configured to maintain the potential of the on-off control node.

[0022] Optionally, the first control node control circuit includes a third control circuit, a fourth control circuit and a second control node control circuit;

[0023] The third control circuit is electrically connected to the second control node, the fifth voltage terminal and the first control node respectively, and is used to control the connection between the first control node and the fifth voltage terminal under the control of the potential of the second control node;

[0024] The fourth control circuit is electrically connected to the sixth voltage terminal and the first control node respectively, and is used to control the potential of the first control node;

[0025] The second control node control circuit is electrically connected to the second control node, the light-emitting control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0026] Optionally, the second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit;

[0027] The first data writing circuit is electrically connected to the light emitting control terminal, the light emitting control data voltage terminal and the second control node respectively, and is used to write the light emitting control data voltage into the second control node under the control of the light emitting control signal;

[0028] The second data writing circuit is respectively connected to the light emitting control terminal, the on-off data voltage terminal and the third control node, and is used to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under the control of the light emitting control signal;

[0029] The fifth control circuit is electrically connected to the third control node, the control data terminal and the fourth control node respectively, and is used to write the control data voltage into the fourth control node under the control of the potential of the third control node;

[0030] The sixth control circuit is respectively connected to the third control node, the sixth voltage terminal, the fourth control node and the sixth voltage terminal;

[0031] The seventh control circuit is electrically connected to the fourth control node, the fifth voltage terminal and the second control node respectively, and is used to control the connection between the second control node and the fifth voltage terminal under the control of the potential of the fourth control node.

[0032] Optionally, the first control node control circuit includes an eighth control circuit and a second control node control circuit;

[0033] The eighth control circuit is electrically connected to the light-emitting control terminal, the second control node, and the first control node, respectively, and is configured to control the communication between the first control node and the second control node under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0034] The second control node control circuit is electrically connected to the light-emitting control terminal, the driving control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal and the driving control signal provided by the driving control terminal.

[0035] Optionally, the second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit;

[0036] The first data writing circuit is electrically connected to the driving control terminal, the light emitting control data voltage terminal and the second control node respectively, and is used to write the light emitting control data voltage into the second control node under the control of the driving control signal;

[0037] The second data writing circuit is respectively connected to the light emitting control terminal, the on-off data voltage terminal and the third control node, and is used to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under the control of the light emitting control signal;

[0038] The fifth control circuit is electrically connected to the third control node, the control data terminal and the fourth control node respectively, and is used to write the control data voltage into the fourth control node under the control of the potential of the third control node;

[0039] The sixth control circuit is electrically connected to the third control node, the sixth voltage terminal, and the fourth control node, respectively, and is configured to control the connection between the fourth control node and the sixth voltage terminal under the control of the potential of the third control node;

[0040] The seventh control circuit is electrically connected to the fourth control node, the sixth voltage terminal and the second control node respectively, and is used to control the connection between the second control node and the sixth voltage terminal under the control of the potential of the fourth control node.

[0041] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a third energy storage circuit and a fourth energy storage circuit;

[0042] The third energy storage circuit is electrically connected to the second control node, and is used to maintain the potential of the second control node;

[0043] The fourth energy storage circuit is electrically connected to the third control node and is configured to maintain the potential of the third control node.

[0044] Optionally, the input circuit includes a first transistor, the reset circuit includes a second transistor, the on-off control circuit includes a third transistor, the first control circuit includes a fourth transistor, and the second control circuit includes a fifth transistor;

[0045] The gate of the first transistor is electrically connected to the light emission control input terminal, the first electrode of the first transistor is electrically connected to the second voltage terminal, and the second electrode of the first transistor is electrically connected to the light emission control voltage terminal;

[0046] The gate of the second transistor and the first electrode of the second transistor are both electrically connected to the light emission control reset terminal, and the second electrode of the second transistor is electrically connected to the on-off control node;

[0047] The gate of the third transistor is electrically connected to the on-off control node, the first electrode of the third transistor is electrically connected to the third voltage terminal, and the second electrode of the third transistor is electrically connected to the light emitting control voltage terminal;

[0048] The gate of the fourth transistor is electrically connected to the light emission control reset terminal, the first electrode of the fourth transistor is electrically connected to the on-off control node, and the second electrode of the fourth transistor is electrically connected to the first intermediate node;

[0049] A gate of the fifth transistor is electrically connected to the first control node, a first electrode of the fifth transistor is electrically connected to the first intermediate node, and a second electrode of the fifth transistor is electrically connected to the fourth voltage terminal.

[0050] Optionally, the first intermediate node control circuit includes a sixth transistor;

[0051] The gate of the sixth transistor is electrically connected to the light emitting control voltage terminal, the first electrode of the sixth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first intermediate node.

[0052] Optionally, the third control circuit includes a seventh transistor, and the fourth control circuit includes an eighth transistor;

[0053] The gate of the seventh transistor is electrically connected to the second control node, the first electrode of the seventh transistor is electrically connected to the fifth voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;

[0054] The gate electrode of the eighth transistor and the first electrode of the eighth transistor are both electrically connected to the sixth voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first control node.

[0055] Optionally, the first data writing circuit includes a ninth transistor, the second data writing circuit includes a tenth transistor, the fifth control circuit includes an eleventh transistor, the sixth control circuit includes a twelfth transistor, and the seventh control circuit includes a thirteenth transistor;

[0056] The gate of the ninth transistor is electrically connected to the light emitting control terminal, the first electrode of the ninth transistor is electrically connected to the light emitting control data voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second control node;

[0057] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the on-off data voltage terminal, and the second electrode of the tenth transistor is electrically connected to the third control node;

[0058] The gate of the eleventh transistor is electrically connected to the third control node, the first electrode of the eleventh transistor is electrically connected to the control data terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth control node;

[0059] The gate of the twelfth transistor is electrically connected to the third control node, the first electrode of the twelfth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fourth control node;

[0060] A gate of the thirteenth transistor is electrically connected to the fourth control node, a first electrode of the thirteenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second control node.

[0061] Optionally, the eighth control circuit includes a fourteenth transistor;

[0062] The gate of the fourteenth transistor is electrically connected to the light emitting control terminal, the first electrode of the fourteenth transistor is electrically connected to the second control node, and the second electrode of the fourteenth transistor is electrically connected to the first control node.

[0063] Optionally, the first data writing circuit includes a ninth transistor, the second data writing circuit includes a tenth transistor, the fifth control circuit includes an eleventh transistor, the sixth control circuit includes a twelfth transistor, and the seventh control circuit includes a thirteenth transistor;

[0064] The gate of the ninth transistor is electrically connected to the driving control terminal, the first electrode of the ninth transistor is electrically connected to the light emitting control data voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second control node;

[0065] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the on-off data voltage terminal, and the second electrode of the tenth transistor is electrically connected to the third control node;

[0066] The gate of the eleventh transistor is electrically connected to the third control node, the first electrode of the eleventh transistor is electrically connected to the control data terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth control node;

[0067] The gate of the twelfth transistor is electrically connected to the third control node, the first electrode of the twelfth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fourth control node;

[0068] A gate of the thirteenth transistor is electrically connected to the fourth control node, a first electrode of the thirteenth transistor is electrically connected to the sixth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second control node.

[0069] Optionally, the first light emitting control circuit includes a fifteenth transistor, and the second light emitting control circuit includes a sixteenth transistor;

[0070] The gate of the fifteenth transistor is electrically connected to the light emission control voltage terminal, the first electrode of the fifteenth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the first node;

[0071] A gate of the sixteenth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixteenth transistor is electrically connected to the first node, and a second electrode of the sixteenth transistor is electrically connected to the first electrode of the light emitting element.

[0072] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit. The driving method includes:

[0073] The first light emitting control circuit controls the power supply voltage terminal to be connected to the first node under the control of the light emitting control voltage;

[0074] The second light emitting control circuit controls the connection between the first node and the first electrode of the light emitting element under the control of the light emitting control signal;

[0075] The light-emitting control voltage control circuit controls the light-emitting control voltage provided by the light-emitting control input terminal, the reset signal provided by the light-emitting control reset terminal, and the light-emitting control signal provided by the light-emitting control terminal, according to the light-emitting control data voltage provided by the light-emitting control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal, and the control data voltage provided by the control data terminal.

[0076] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] FIG8A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] FIG8B is a simulation timing diagram of at least one embodiment of the pixel circuit shown in FIG8A during operation, performing high grayscale display;

[0086] 8C and 8D are simulated operation timing diagrams of at least one embodiment of the pixel circuit shown in FIG. 8A during operation when performing low grayscale display;

[0087] FIG9A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] FIG9B is a timing diagram of a simulation of at least one embodiment of the pixel circuit shown in FIG9A during operation when performing high grayscale display;

[0089] FIG9C is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG8A during operation when performing low grayscale display;

[0090] FIG10A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0091] FIG10B is a timing diagram of a simulation of at least one embodiment of the pixel circuit shown in FIG10A during operation when performing high grayscale display;

[0092] 10C and 10D are simulated operation timing diagrams of at least one embodiment of the pixel circuit shown in FIG. 10A during operation when performing low grayscale display;

[0093] FIG11A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0094] FIG11B is a timing diagram of a simulation of at least one embodiment of the pixel circuit shown in FIG11A during operation, when performing high grayscale display;

[0095] FIG11C is a simulated operation timing diagram of at least one embodiment of the pixel circuit shown in FIG11A during operation when performing low grayscale display;

[0096] FIG12A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0097] FIG12B is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG12A when in operation and displaying a high grayscale;

[0098] FIG12C is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG12A when in operation and displaying a low grayscale;

[0099] FIG13A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0100] FIG13B is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG13A when in operation and displaying a high grayscale;

[0101] FIG13C is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG13A when in operation and displaying a low grayscale;

[0102] FIG14A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0103] FIG14B is a timing diagram of a simulated operation of at least one embodiment of the pixel circuit shown in FIG14A when displaying a high grayscale;

[0104] FIG14C is a timing diagram of a simulated operation of at least one embodiment of the pixel circuit shown in FIG14A when displaying a low grayscale;

[0105] FIG15A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0106] FIG15B is a timing diagram of a simulated operation of at least one embodiment of the pixel circuit shown in FIG15A when displaying a high grayscale;

[0107] FIG. 15C is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 15A when displaying a low grayscale. DETAILED DESCRIPTION

[0108] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0109] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0110] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0111] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1 , a first light-emitting control circuit 11 , a second light-emitting control circuit 12 , and a light-emitting control voltage control circuit 13 ;

[0112] The first light emitting control circuit 11 is electrically connected to the light emitting control voltage terminal HFO, the power supply voltage terminal ELVDD and the first node N1 respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the first node N1 under the control of the light emitting control voltage provided by the light emitting control voltage terminal HFO;

[0113] The second light emitting control circuit 12 is electrically connected to the light emitting control terminal EM, the first node N1, and the first electrode of the light emitting element E1, respectively, and is configured to control the first node N1 to be connected to the first electrode of the light emitting element E1 under the control of a light emitting control signal provided by the light emitting control terminal EM; the second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0114] The light-emitting control voltage control circuit 13 is electrically connected to the light-emitting control voltage terminal HFO, the light-emitting control input terminal HFI, the light-emitting control reset terminal HFR, the light-emitting control terminal EM, the light-emitting control data voltage terminal DE, the on-off data voltage terminal DS and the control data terminal DC, respectively, and is used to control the light-emitting control voltage provided by the light-emitting control voltage terminal HFO according to the light-emitting control data voltage provided by the light-emitting control data voltage terminal DE, the on-off data voltage provided by the on-off data voltage terminal DS and the control data voltage provided by the control data terminal DC under the control of the input signal provided by the light-emitting control input terminal HFI, the reset signal provided by the light-emitting control reset terminal HFR and the light-emitting control signal provided by the light-emitting control terminal EM.

[0115] During operation, the pixel circuit of the disclosed embodiment can control the duty cycle of the light control voltage according to the light control data voltage, the on / off data voltage, and the control data voltage, through the light control voltage control circuit under the control of an input signal, a reset signal, and a light control signal. This can then control the second light control circuit 12 to control the duration of the connection between the first node N1 and the first electrode of the light-emitting element E1, thereby controlling the brightness of the light-emitting element E1. The pixel circuit of the disclosed embodiment can implement full-grayscale PWM (pulse width modulation) drive, completely replacing PAM (pulse amplitude modulation), significantly reducing power consumption and heat generation.

[0116] Optionally, the first voltage end may be a low level end, but is not limited thereto.

[0117] As shown in FIG2 , based on the embodiment of the pixel circuit shown in FIG1 , in the pixel circuit according to at least one embodiment of the present disclosure, the light emission control voltage control circuit includes an input circuit 21, a reset circuit 22, an on / off control circuit 23, a first control circuit 24, a second control circuit 25, and a first control node control circuit 26;

[0118] The input circuit 21 is electrically connected to the light control input terminal HFI, the second voltage terminal V2 and the light control voltage terminal HFO, respectively, and is used to control the connection between the light control voltage terminal HFO and the second voltage terminal V2 under the control of the input signal provided by the light control input terminal HFI;

[0119] The reset circuit 22 is electrically connected to the light emitting control reset terminal HFR and the on-off control node Q, respectively, and is used to control the potential of the on-off control node Q under the control of the reset signal provided by the light emitting control reset terminal HFR;

[0120] The on-off control circuit 23 is electrically connected to the on-off control node Q, the third voltage terminal V3, and the light-emission control voltage terminal HFO, respectively, and is configured to control the connection between the light-emission control voltage terminal HFO and the third voltage terminal V3 under the control of the potential of the on-off control node Q;

[0121] The first control circuit 24 is electrically connected to the light emitting control reset terminal HFR, the on-off control node Q and the first intermediate node NZ1 respectively, and is used to control the connection between the on-off control node Q and the first intermediate node NZ1 under the control of the reset signal;

[0122] The second control circuit 25 is electrically connected to the first control node S, the first intermediate node NZ1 and the fourth voltage terminal V4 respectively, and is used to control the connection between the first intermediate node NZ1 and the fourth voltage terminal V4 under the control of the potential of the first control node S;

[0123] The first control node control circuit 26 is electrically connected to the first control node S, the light-emitting control terminal EM, the light-emitting control data voltage terminal DE, the on-off data voltage terminal DS and the control data terminal DC, respectively, and is used to control the potential of the first control node S according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0124] Optionally, the second voltage terminal may be a low voltage terminal, the third voltage terminal may be a high voltage terminal, and the fourth voltage terminal may be a low voltage terminal.

[0125] The pixel circuit according to at least one embodiment of the present disclosure further includes a first intermediate node control circuit;

[0126] The first intermediate node control circuit is electrically connected to the light-emitting control voltage terminal, the first intermediate node and the fourth voltage terminal respectively, and is used to control the connection between the first intermediate node and the fourth voltage terminal under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal.

[0127] In a specific implementation, the pixel circuit may further include a first intermediate node control circuit, which controls the connection between the first intermediate node and the fourth voltage terminal under the control of the light emitting control voltage provided by the light emitting control voltage terminal.

[0128] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first intermediate node control circuit 31 ;

[0129] The first intermediate node control circuit 31 is electrically connected to the light-emitting control voltage terminal HFO, the first intermediate node NZ1 and the fourth voltage terminal V4, respectively, and is used to control the connection between the first intermediate node NZ1 and the fourth voltage terminal V4 under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal HFO.

[0130] The pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0131] The first energy storage circuit is electrically connected to the light-emitting control voltage terminal, and is used to maintain the potential of the light-emitting control voltage terminal;

[0132] The second energy storage circuit is electrically connected to the on-off control node and is configured to maintain the potential of the on-off control node.

[0133] In a specific implementation, the pixel circuit may further include a first energy storage circuit and a second energy storage circuit, wherein the first energy storage circuit maintains the potential of the light emitting control voltage terminal; and the second energy storage circuit maintains the potential of the on-off control node.

[0134] Optionally, the first control node control circuit includes a third control circuit, a fourth control circuit and a second control node control circuit;

[0135] The third control circuit is electrically connected to the second control node, the fifth voltage terminal and the first control node respectively, and is used to control the connection between the first control node and the fifth voltage terminal under the control of the potential of the second control node;

[0136] The fourth control circuit is electrically connected to the sixth voltage terminal and the first control node respectively, and is used to control the potential of the first control node;

[0137] The second control node control circuit is electrically connected to the second control node, the light-emitting control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0138] In a specific implementation, the first control node control circuit may include a third control circuit, a fourth control circuit and a second control node control circuit; the third control circuit controls the potential of the first control node under the control of the potential of the second control node; the fourth control circuit controls the potential of the first control node, and the second control node control circuit controls the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal.

[0139] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 41 and a second energy storage circuit 42 ;

[0140] The first energy storage circuit 41 is electrically connected to the light-emitting control voltage terminal HFO, and is used to maintain the potential of the light-emitting control voltage terminal HFO;

[0141] The second energy storage circuit 42 is electrically connected to the on-off control node Q, and is used to maintain the potential of the on-off control node Q;

[0142] The first control node control circuit includes a third control circuit 43, a fourth control circuit 44 and a second control node control circuit 45;

[0143] The third control circuit 43 is electrically connected to the second control node R, the fifth voltage terminal V5 and the first control node S respectively, and is used to control the connection between the first control node S and the fifth voltage terminal V5 under the control of the potential of the second control node R;

[0144] The fourth control circuit 44 is electrically connected to the sixth voltage terminal V6 and the first control node S, respectively, and is used to control the potential of the first control node S;

[0145] The second control node control circuit 45 is electrically connected to the second control node R, the light-emitting control terminal EM, the light-emitting control data voltage terminal DE, the on-off data voltage terminal DS and the control data terminal DC, respectively, and is used to control the potential of the second control node R according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0146] Optionally, the fifth voltage terminal may be a control voltage terminal, and the sixth voltage terminal may be a low voltage terminal, but the present invention is not limited thereto.

[0147] In at least one embodiment of the present disclosure, the second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit, and a seventh control circuit;

[0148] The first data writing circuit is electrically connected to the light emitting control terminal, the light emitting control data voltage terminal and the second control node respectively, and is used to write the light emitting control data voltage into the second control node under the control of the light emitting control signal;

[0149] The second data writing circuit is respectively connected to the light emitting control terminal, the on-off data voltage terminal and the third control node, and is used to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under the control of the light emitting control signal;

[0150] The fifth control circuit is electrically connected to the third control node, the control data terminal and the fourth control node respectively, and is used to write the control data voltage into the fourth control node under the control of the potential of the third control node;

[0151] The sixth control circuit is electrically connected to the third control node, the sixth voltage terminal, and the fourth control node, respectively, and is configured to control the connection between the fourth control node and the sixth voltage terminal under the control of the potential of the third control node;

[0152] The seventh control circuit is electrically connected to the fourth control node, the fifth voltage terminal and the second control node respectively, and is used to control the connection between the second control node and the fifth voltage terminal under the control of the potential of the fourth control node.

[0153] In a specific implementation, the second control node control circuit may include a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit; the first data writing circuit writes the light-emitting control data voltage to the second control node under the control of the light-emitting control signal; the second data writing circuit writes the on-off data voltage to the third control node under the control of the light-emitting control signal; the fifth control circuit writes the control data voltage to the fourth control node under the control of the potential of the third control node; the sixth control circuit controls the connection between the fourth control node and the sixth voltage terminal under the control of the potential of the third control node; the seventh control circuit controls the connection between the second control node and the fifth voltage terminal under the control of the potential of the fourth control node.

[0154] The pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit and a fourth energy storage circuit;

[0155] The third energy storage circuit is electrically connected to the second control node, and is used to maintain the potential of the second control node;

[0156] The fourth energy storage circuit is electrically connected to the third control node and is configured to maintain the potential of the third control node.

[0157] In a specific implementation, the pixel circuit may include a third energy storage circuit and a fourth energy storage circuit, the third energy storage circuit maintains the potential of the second control node; the fourth energy storage circuit maintains the potential of the third control node.

[0158] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG4 , the second control node control circuit includes a first data writing circuit 51, a second data writing circuit 52, a fifth control circuit 53, a sixth control circuit 54, and a seventh control circuit 55; the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 71 and a fourth energy storage circuit 72;

[0159] The first data writing circuit 51 is electrically connected to the light emitting control terminal EM, the light emitting control data voltage terminal DE and the second control node R respectively, and is used to write the light emitting control data voltage into the second control node R under the control of the light emitting control signal;

[0160] The second data writing circuit 52 is respectively connected to the light emitting control terminal EM, the on-off data voltage terminal DS and the third control node NC3, and is used to write the on-off data voltage provided by the on-off data voltage terminal DS into the third control node NC3 under the control of the light emitting control signal;

[0161] The fifth control circuit 53 is electrically connected to the third control node NC3, the control data terminal DC, and the fourth control node NC4, respectively, and is configured to write the control data voltage into the fourth control node NC4 under the control of the potential of the third control node NC3;

[0162] The sixth control circuit 54 is electrically connected to the third control node NC3, the sixth voltage terminal V6, and the fourth control node NC4, respectively, and is configured to control the connection between the fourth control node NC4 and the sixth voltage terminal V6 under the control of the potential of the third control node NC3;

[0163] The seventh control circuit 55 is electrically connected to the fourth control node NC4, the fifth voltage terminal V5, and the second control node R, respectively, and is configured to control the connection between the second control node R and the fifth voltage terminal V5 under the control of the potential of the fourth control node NC4;

[0164] The third energy storage circuit 71 is electrically connected to the second control node R, and is used to maintain the potential of the second control node R;

[0165] The fourth energy storage circuit 72 is electrically connected to the third control node NC3 and is configured to maintain the potential of the third control node NC3.

[0166] In at least one embodiment of the present disclosure, the first control node control circuit includes an eighth control circuit and a second control node control circuit;

[0167] The eighth control circuit is electrically connected to the light-emitting control terminal, the second control node, and the first control node, respectively, and is configured to control the communication between the first control node and the second control node under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0168] The second control node control circuit is electrically connected to the light-emitting control terminal, the driving control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal and the driving control signal provided by the driving control terminal.

[0169] In a specific implementation, the first control node control circuit may include an eighth control circuit and a second control node control circuit; the eighth control circuit controls the connection between the first control node and the second control node under the control of the light-emitting control signal; the second control node control circuit controls the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal and the drive control signal.

[0170] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 41 and a second energy storage circuit 42 ;

[0171] The first energy storage circuit 41 is electrically connected to the light-emitting control voltage terminal HFO, and is used to maintain the potential of the light-emitting control voltage terminal HFO;

[0172] The second energy storage circuit 42 is electrically connected to the on-off control node Q, and is used to maintain the potential of the on-off control node Q;

[0173] The first control node control circuit includes an eighth control circuit 61 and a second control node control circuit 62;

[0174] The eighth control circuit 61 is electrically connected to the light emitting control terminal EM, the second control node R, and the first control node S, respectively, and is configured to control the connection between the first control node S and the second control node R under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0175] The second control node control circuit 62 is electrically connected to the second control node R, the light-emitting control terminal EM, the driving control terminal GA, the light-emitting control data voltage terminal DE, the on-off data voltage terminal DS and the control data terminal DC, respectively, and is used to control the potential of the second control node R according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal EM and the driving control signal provided by the driving control terminal GA.

[0176] In at least one embodiment of the present disclosure, the second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit, and a seventh control circuit;

[0177] The first data writing circuit is electrically connected to the driving control terminal, the light emitting control data voltage terminal and the second control node respectively, and is used to write the light emitting control data voltage into the second control node under the control of the driving control signal;

[0178] The second data writing circuit is respectively connected to the light emitting control terminal, the on-off data voltage terminal and the third control node, and is used to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under the control of the light emitting control signal;

[0179] The fifth control circuit is electrically connected to the third control node, the control data terminal and the fourth control node respectively, and is used to write the control data voltage into the fourth control node under the control of the potential of the third control node;

[0180] The sixth control circuit is electrically connected to the third control node, the sixth voltage terminal, and the fourth control node, respectively, and is configured to control the connection between the fourth control node and the sixth voltage terminal under the control of the potential of the third control node;

[0181] The seventh control circuit is electrically connected to the fourth control node, the sixth voltage terminal and the second control node respectively, and is used to control the connection between the second control node and the sixth voltage terminal under the control of the potential of the fourth control node.

[0182] In a specific implementation, the second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit; the first data writing circuit writes the light-emitting control data voltage to the second control node under the control of the driving control signal; the second data writing circuit writes the on-off data voltage to the third control node under the control of the light-emitting control signal; the fifth control circuit writes the control data voltage to the fourth control node under the control of the potential of the third control node; the sixth control circuit controls the connection between the fourth control node and the sixth voltage terminal under the control of the potential of the third control node; the seventh control circuit controls the connection between the second control node and the sixth voltage terminal under the control of the potential of the fourth control node.

[0183] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG6 , the second control node control circuit includes a first data writing circuit 73, a second data writing circuit 74, a fifth control circuit 75, a sixth control circuit 76, and a seventh control circuit 77; the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 71 and a fourth energy storage circuit 72;

[0184] The first data writing circuit 73 is electrically connected to the driving control terminal GA, the light emitting control data voltage terminal DE and the second control node R respectively, and is used to write the light emitting control data voltage into the second control node R under the control of the driving control signal;

[0185] The second data writing circuit 74 is electrically connected to the light emitting control terminal EM, the on-off data voltage terminal DS and the third control node NC3, respectively, and is used to write the on-off data voltage provided by the on-off data voltage terminal DS into the third control node NC3 under the control of the light emitting control signal;

[0186] The fifth control circuit 75 is electrically connected to the third control node NC3, the control data terminal DC, and the fourth control node NC4, respectively, and is configured to write the control data voltage into the fourth control node NC4 under the control of the potential of the third control node NC3;

[0187] The sixth control circuit 76 is electrically connected to the third control node NC3, the sixth voltage terminal V6, and the fourth control node NC4, respectively, and is configured to control the connection between the fourth control node NC4 and the sixth voltage terminal V6 under the control of the potential of the third control node NC3;

[0188] The seventh control circuit 77 is electrically connected to the fourth control node NC4, the sixth voltage terminal V6, and the second control node R, respectively, and is configured to control the connection between the second control node R and the sixth voltage terminal V6 under the control of the potential of the fourth control node NC4;

[0189] The third energy storage circuit 71 is electrically connected to the second control node R, and is used to maintain the potential of the second control node R;

[0190] The fourth energy storage circuit 72 is electrically connected to the third control node NC3 and is configured to maintain the potential of the third control node NC3.

[0191] Optionally, the input circuit includes a first transistor, the reset circuit includes a second transistor, the on-off control circuit includes a third transistor, the first control circuit includes a fourth transistor, and the second control circuit includes a fifth transistor;

[0192] The gate of the first transistor is electrically connected to the light emission control input terminal, the first electrode of the first transistor is electrically connected to the second voltage terminal, and the second electrode of the first transistor is electrically connected to the light emission control voltage terminal;

[0193] The gate of the second transistor and the first electrode of the second transistor are both electrically connected to the light emission control reset terminal, and the second electrode of the second transistor is electrically connected to the on-off control node;

[0194] The gate of the third transistor is electrically connected to the on-off control node, the first electrode of the third transistor is electrically connected to the third voltage terminal, and the second electrode of the third transistor is electrically connected to the light emitting control voltage terminal;

[0195] The gate of the fourth transistor is electrically connected to the light emission control reset terminal, the first electrode of the fourth transistor is electrically connected to the on-off control node, and the second electrode of the fourth transistor is electrically connected to the first intermediate node;

[0196] A gate of the fifth transistor is electrically connected to the first control node, a first electrode of the fifth transistor is electrically connected to the first intermediate node, and a second electrode of the fifth transistor is electrically connected to the fourth voltage terminal.

[0197] Optionally, the first intermediate node control circuit includes a sixth transistor;

[0198] The gate of the sixth transistor is electrically connected to the light emitting control voltage terminal, the first electrode of the sixth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first intermediate node.

[0199] Optionally, the third control circuit includes a seventh transistor, and the fourth control circuit includes an eighth transistor;

[0200] The gate of the seventh transistor is electrically connected to the second control node, the first electrode of the seventh transistor is electrically connected to the fifth voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;

[0201] The gate electrode of the eighth transistor and the first electrode of the eighth transistor are both electrically connected to the sixth voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first control node.

[0202] Optionally, the first data writing circuit includes a ninth transistor, the second data writing circuit includes a tenth transistor, the fifth control circuit includes an eleventh transistor, the sixth control circuit includes a twelfth transistor, and the seventh control circuit includes a thirteenth transistor;

[0203] The gate of the ninth transistor is electrically connected to the light emitting control terminal, the first electrode of the ninth transistor is electrically connected to the light emitting control data voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second control node;

[0204] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the on-off data voltage terminal, and the second electrode of the tenth transistor is electrically connected to the third control node;

[0205] The gate of the eleventh transistor is electrically connected to the third control node, the first electrode of the eleventh transistor is electrically connected to the control data terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth control node;

[0206] The gate of the twelfth transistor is electrically connected to the third control node, the first electrode of the twelfth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fourth control node;

[0207] A gate of the thirteenth transistor is electrically connected to the fourth control node, a first electrode of the thirteenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second control node.

[0208] Optionally, the eighth control circuit includes a fourteenth transistor;

[0209] The gate of the fourteenth transistor is electrically connected to the light emitting control terminal, the first electrode of the fourteenth transistor is electrically connected to the second control node, and the second electrode of the fourteenth transistor is electrically connected to the first control node.

[0210] Optionally, the first data writing circuit includes a ninth transistor, the second data writing circuit includes a tenth transistor, the fifth control circuit includes an eleventh transistor, the sixth control circuit includes a twelfth transistor, and the seventh control circuit includes a thirteenth transistor;

[0211] The gate of the ninth transistor is electrically connected to the driving control terminal, the first electrode of the ninth transistor is electrically connected to the light emitting control data voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second control node;

[0212] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the on-off data voltage terminal, and the second electrode of the tenth transistor is electrically connected to the third control node;

[0213] The gate of the eleventh transistor is electrically connected to the third control node, the first electrode of the eleventh transistor is electrically connected to the control data terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth control node;

[0214] The gate of the twelfth transistor is electrically connected to the third control node, the first electrode of the twelfth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fourth control node;

[0215] A gate of the thirteenth transistor is electrically connected to the fourth control node, a first electrode of the thirteenth transistor is electrically connected to the sixth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second control node.

[0216] Optionally, the first light emitting control circuit includes a fifteenth transistor, and the second light emitting control circuit includes a sixteenth transistor;

[0217] The gate of the fifteenth transistor is electrically connected to the light emission control voltage terminal, the first electrode of the fifteenth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the first node;

[0218] A gate of the sixteenth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixteenth transistor is electrically connected to the first node, and a second electrode of the sixteenth transistor is electrically connected to the first electrode of the light emitting element.

[0219] As shown in FIG8A , based on at least one embodiment of the pixel circuit shown in FIG5 , the light emitting element is an organic light emitting diode;

[0220] The input circuit includes a first transistor M1, the reset circuit includes a second transistor M2, the on-off control circuit includes a third transistor M3, the first control circuit includes a fourth transistor M4, and the second control circuit includes a fifth transistor M5;

[0221] The gate of the first transistor M1 is electrically connected to the light emission control input terminal HFI, the source of the first transistor M1 is electrically connected to the low voltage terminal VSS, and the drain of the first transistor M1 is electrically connected to the light emission control voltage terminal HFO;

[0222] The gate of the second transistor M2 and the source of the second transistor M2 are both electrically connected to the light emission control reset terminal HFR, and the drain of the second transistor M2 is electrically connected to the on-off control node Q;

[0223] The gate of the third transistor M3 is electrically connected to the on-off control node Q, the source of the third transistor M3 is electrically connected to the high voltage terminal VDD, and the drain of the third transistor M3 is electrically connected to the light emitting control voltage terminal HFO;

[0224] The gate of the fourth transistor M4 is electrically connected to the light emission control reset terminal HFR, the source of the fourth transistor M4 is electrically connected to the on-off control node Q, and the drain of the fourth transistor M4 is electrically connected to the first intermediate node NZ1;

[0225] The gate of the fifth transistor M5 is electrically connected to the first control node S, the source of the fifth transistor M5 is electrically connected to the first intermediate node NZ1, and the drain of the fifth transistor M5 is electrically connected to the low voltage terminal VSS;

[0226] The first intermediate node control circuit includes a sixth transistor M6;

[0227] The gate of the sixth transistor M6 is electrically connected to the light emitting control voltage terminal HFO, the source of the sixth transistor M6 is electrically connected to the low voltage terminal VSS, and the drain of the sixth transistor M6 is electrically connected to the first intermediate node NZ1;

[0228] The third control circuit includes a seventh transistor M7, and the fourth control circuit includes an eighth transistor M8;

[0229] The gate of the seventh transistor M7 is electrically connected to the second control node R, the source of the seventh transistor M7 is electrically connected to the control voltage terminal VSM, and the drain of the seventh transistor M7 is electrically connected to the first control node S;

[0230] The gate of the eighth transistor M8 and the source of the eighth transistor M8 are both electrically connected to the low voltage terminal VSS, and the drain of the eighth transistor M8 is electrically connected to the first control node S;

[0231] The first data writing circuit includes a ninth transistor M9, the second data writing circuit includes a tenth transistor M10, the fifth control circuit includes an eleventh transistor M11, the sixth control circuit includes a twelfth transistor M12, and the seventh control circuit includes a thirteenth transistor M13;

[0232] The gate of the ninth transistor M9 is electrically connected to the light emitting control terminal EM, the source of the ninth transistor M9 is electrically connected to the light emitting control data voltage terminal DE, and the drain of the ninth transistor M9 is electrically connected to the second control node R;

[0233] The gate of the tenth transistor M10 is electrically connected to the light emitting control terminal EM, the source of the tenth transistor M10 is electrically connected to the on-off data voltage terminal DS, and the drain of the tenth transistor M10 is electrically connected to the third control node NC3;

[0234] The gate of the eleventh transistor M11 is electrically connected to the third control node NC3, the source of the eleventh transistor M11 is electrically connected to the control data terminal DC, and the drain of the eleventh transistor M11 is electrically connected to the fourth control node NC4;

[0235] The gate of the twelfth transistor M12 is electrically connected to the third control node NC3, the source of the twelfth transistor M12 is electrically connected to the low voltage terminal VSS, and the drain of the twelfth transistor M12 is electrically connected to the fourth control node NC4;

[0236] The gate of the thirteenth transistor M13 is electrically connected to the fourth control node NC4, the source of the thirteenth transistor M13 is electrically connected to the control voltage terminal VSM, and the drain of the thirteenth transistor M13 is electrically connected to the second control node R;

[0237] The first light emitting control circuit includes a fifteenth transistor M15, and the second light emitting control circuit includes a sixteenth transistor M16;

[0238] The gate of the fifteenth transistor M15 is electrically connected to the light emitting control voltage terminal HFO, the source of the fifteenth transistor M15 is electrically connected to the power supply voltage terminal ELVDD, and the fifteenth transistor M15 is electrically connected to the first node N1;

[0239] The gate of the sixteenth transistor M16 is electrically connected to the light emitting control terminal EM, the source of the sixteenth transistor M16 is electrically connected to the first node N1, the drain of the sixteenth transistor M16 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low level terminal ELVSS.

[0240] The first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0241] A first end of the first capacitor C1 is electrically connected to the light-emitting control voltage terminal HFO, and a second end of the first capacitor C1 is electrically connected to the low voltage terminal VSS;

[0242] A first end of the second capacitor C2 is electrically connected to the on-off control node Q, and a second end of the second capacitor C2 is electrically connected to the low voltage terminal VSS;

[0243] The third energy storage circuit includes a third capacitor C3, and the fourth energy storage circuit includes a fourth capacitor C4;

[0244] A first end of the third capacitor C3 is electrically connected to the second control node R, and a second end of the third capacitor C3 is electrically connected to the control voltage terminal VSM;

[0245] A first end of the fourth capacitor C4 is electrically connected to the third control node NC3 , and a second end of the fourth capacitor C4 is electrically connected to the low voltage terminal VSS.

[0246] In at least one embodiment shown in FIG. 8A , M1 is a p-type transistor, M2 is an n-type transistor, M3 is a p-type transistor, M4 is a p-type transistor, M5 is an n-type transistor, M6 is an n-type transistor, M7 is a p-type transistor, M8 is a p-type transistor, M9 is a p-type transistor, M10 is a p-type transistor, M11 is a p-type transistor, M12 is an n-type transistor, M13 is a p-type transistor, M15 is an n-type transistor, and M16 is an n-type transistor.

[0247] In at least one embodiment shown in FIG. 8A , the control voltage terminal VSM may provide a negative voltage signal. For example, VSM may provide a −4V voltage signal.

[0248] In at least one embodiment shown in FIG. 8A , the second voltage terminal is the low voltage terminal VSS, the third voltage terminal is the high voltage terminal VDD, the fourth voltage terminal is the low voltage terminal VSS, the fifth voltage terminal is the control voltage terminal VSM, and the sixth voltage terminal is the low voltage terminal VSS.

[0249] In at least one embodiment shown in FIG. 8A , the high voltage terminal VDD may provide a 14V voltage signal, the low voltage terminal VSS may provide a -14V voltage signal, VSM may provide a -4V voltage signal, ELVDD may provide a 5V voltage signal, and ELVSS may provide a 0V voltage signal;

[0250] The high voltage value of the input signal provided by HFI is 16 V, the low voltage value of the input signal provided by HFI is -16 V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100 μs, and the ratio of the time when the potential of the input signal is maintained at the low voltage to the time when the potential of the input signal is maintained at the high voltage is 5 / 95;

[0251] The high voltage value of the reset signal provided by HFR is 25V, the low voltage value of the reset signal provided by HFR is -16V, the reset signal provided by HFR is a square wave signal, the period of the reset signal provided by HFR is 100 μs, and the ratio of the time when the potential of the reset signal is maintained at the low voltage to the time when the potential of the reset signal is maintained at the high voltage is 96 / 4;

[0252] DE can provide -4.694V voltage signal, -4.7V voltage signal, -4.8V voltage signal, -4.9V voltage signal, -5V voltage signal successively;

[0253] DS can provide -14V voltage signal or 14V voltage signal;

[0254] Taking a display frequency of 60 Hz as an example, when performing low grayscale display, the high voltage value of the control data voltage provided by the DC may be 14 V, the low voltage value of the control data voltage may be -14 V, the control data voltage may be a square wave voltage, the period of the control data voltage may be 16667 μs, and the ratio of the time during which the voltage value of the control data voltage remains at a low voltage to the time during which the voltage value of the control data voltage remains at a high voltage may be 300 / 16367;

[0255] Taking a display frequency of 60 Hz as an example, the high voltage value of the light control signal provided by the EM may be 16 V, the low voltage value of the light control signal may be -16 V, the period of the light control signal may be 16667 μs, and the ratio of the time during which the potential of the light control signal remains at a low voltage to the time during which the potential of the light control signal remains at a high voltage is 200 / 16467.

[0256] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50Ff, and the capacitance value of C4 is 50fF;

[0257] M1 and M2 are digital trigger TFTs (thin film transistors), forming a first-order digital trigger; M3, M4, M5 and M6 are duty cycle adjustment control TFTs, M9, M7 and M8 are data voltage write and hold TFTs, and M15 and M16 are light-emitting control TFTs.

[0258] When at least one embodiment of the pixel circuit shown in FIG. 8A of the present disclosure is in operation,

[0259] Before the start of a cycle (the duration of the cycle may be 100 μs, but is not limited thereto), HR provides a high voltage signal to turn on M2 and turn off M4. The potential of Q is reset to 25 V, and M3 is turned off.

[0260] After the cycle starts, HR provides a low voltage signal, closes M2, opens M4, HFI opens M1, the low voltage signal provided by VSS is written to C1, HFO outputs a low voltage signal, and at the same time closes M6, Q point discharges to VSS, and the voltage of S is written to the gate of M5. By controlling the size of the saturation current Id of M5, the discharge speed of Q point is controlled;

[0261] After a time t, when the gate-source voltage Vgs of M3 is discharged to be less than the threshold voltage of M3, M3 is turned on, the high voltage signal provided by VDD is written into C1, HF outputs a high voltage signal, and M6 is turned on at the same time, and the potential of Q is quickly discharged to a low voltage;

[0262] Before the end of the cycle (i.e., in the last 5μs of the cycle), HR provides a high voltage signal, opens M2, closes M4, resets the potential of Q to 25V, closes M3, maintains high voltage, and HFO continues to output a high voltage signal;

[0263] The next cycle begins and the above process is repeated.

[0264] In at least one embodiment of the pixel circuit shown in FIG. 8A of the present disclosure, during operation, after the cycle starts, the voltage of S is written to the gate of M5. By controlling the magnitude of M5's saturation current Id, the discharge rate of point Q is controlled. The time t required for the potential of Q to discharge until Vgs is less than the threshold voltage of M3 is the time that HFO continues to provide a low voltage. By adjusting the potential of S, light-emitting control voltages with different duty cycles can be obtained.

[0265] In at least one embodiment of the pixel circuit shown in FIG8A of the present disclosure, M1 is a p-type transistor. At the beginning of a cycle, HFI provides a low-voltage signal to turn M1 on, and a low-voltage signal provided by VSS is written. After writing is complete, HFI provides a high-voltage signal to turn M1 off. Due to the influence of M1's parasitic capacitance, the voltage value of the light-emitting control voltage provided by HFO is pulled up. Ultimately, the voltage value of the light-emitting control voltage is slightly higher than the voltage value of the low-voltage signal provided by VSS, causing the gate-source voltage of M6 to be greater than 0. There is a risk of incomplete shutdown of M6, thereby causing leakage. Based on this, at least one embodiment of the pixel circuit shown in FIG9A of the present disclosure configures M1 as an n-type transistor. At the beginning of a cycle, HFI provides a high-voltage signal to turn M1 on, and a low-voltage signal is written. After writing is complete, HFI provides a low-voltage signal to turn M1 off. Due to the influence of M1's parasitic capacitance, the voltage value of the light-emitting control voltage provided by HFO is pulled down. At this time, the gate-source voltage of M6 is less than 0, eliminating the risk of M6 being turned on.

[0266] In at least one embodiment of the pixel circuit shown in FIG. 8A of the present disclosure, during operation, M7, M8, and M9 are responsible for writing and maintaining data voltages. During the data writing phase (which may last, for example, 200 μs), EM provides a low voltage signal to turn on M9, and the light-emission control data voltage provided by DE is written to R. The potential of R controls the degree of on-state of M7. Based on the voltage-dividing principle of a series circuit, the ratio between the resistance of M7 and the resistance of M8 controls the potential of S, thereby controlling the degree of on-state of M5 and, consequently, the duty cycle of the light-emission control voltage provided by HFO.

[0267] M13, M11, M12 and M10 form a high and low grayscale switching module;

[0268] When displaying high grayscale, the duty cycle adjustment circuit works in full swing. EM provides a low voltage signal to open M10, DS provides a 14V voltage signal to close M11 and open M12, and the low voltage signal provided by VSS is written to the gate of M13 to close M13.

[0269] When displaying a low grayscale, the duty cycle adjustment circuit only works for one cycle. When EM provides a low voltage to turn on M10, DS provides a -14V voltage signal to turn on M11 and turn off M12. The control data voltage provided by DC is written to the gate of M13. After EM provides a high voltage signal to turn off M10, DC continues to provide a low voltage signal to turn off M13 for one cycle. After that, DC provides a high voltage signal to turn on M13. The control voltage provided by VSM is written to R, turning off M7. The potential of S is a low voltage, turning off M5, cutting off the discharge path to Q, and M3 remains in the off state. HFO continues to output a low voltage signal.

[0270] In a specific implementation, when PWM (pulse width modulation) driving is adopted, the N grayscale duty cycle is equal to the 255 grayscale duty cycle × (N / 255) ga ;

[0271] Wherein, ga is the gamma value, for example, ga may be greater than or equal to 2.2 and less than or equal to 2.5;

[0272] The following takes a display frequency of 60 Hz and a display cycle duration of 16667 μs as an example to illustrate a method for realizing high and low gray scales.

[0273] Assuming that the duty cycle of 255 grayscale is 100%, that is, the working time in one display cycle is 16667μs, according to the above calculation formula, the duty cycle of 1 grayscale is equal to 0.000508%. In one display cycle, the working time corresponding to 1 grayscale is 16667×0.000508%, that is, the working time corresponding to 1 grayscale is 0.1μs.

[0274] In at least one embodiment of the present disclosure, the period of the light-emission control voltage provided by the HFO is 100μs. The light-emission control data voltage is adjusted to ensure a duty cycle of 0.1%, meaning a single-cycle operating duration of 0.1μs. Controlled by DC power, after the EM provides a high-voltage signal to turn on M16, the HFO outputs a high-voltage signal for only 0.1μs. This allows O1 to illuminate for only 0.1μs within a display cycle, achieving a grayscale display of 1. The maximum duty cycle of the light-emission control voltage provided by the HFO within a single cycle is 95%, meaning any grayscale operating duration less than or equal to 95μs can be achieved through DC power. Using the above formula, grayscales 1 to 24 can be achieved through DC power. When displaying grayscales 25 to 255, the DC power control data voltage must be turned off, and the light-emission control voltage output by the HFO must operate at full capacity for the entire display cycle.

[0275] The above distinction between high and low grayscale is derived based on the example that the period of the light-emitting control voltage provided by HFO is 10000Hz and the display period is 60Hz. When the above two periods change, the distinction between high and low grayscale will also change.

[0276] In at least one embodiment of the present disclosure, M15 and M16 are light-emitting control transistors. When the grayscale is switched, DE and DS write signals, and then EM provides a high voltage signal. The light-emitting control voltage provided by HFO controls the working time of M15 and the light-emitting time of O1 to achieve grayscale display.

[0277] FIG. 8B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8A during operation when performing high grayscale display.

[0278] As shown in FIG8B , the time period labeled S1 is the first time period, the time period labeled S2 is the second time period, the time period labeled S3 is the third time period, the time period labeled S4 is the fourth time period, and the time period labeled S5 is the fifth time period;

[0279] The duration of S1, S2, S3, S4 and S5 are all 200 μs;

[0280] In S1, DE provides a -4.694V voltage signal, and the duty cycle of the light control voltage provided by HFO is 0.2%;

[0281] In S2, DE provides a -4.7V voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 2.7%;

[0282] In S3, DE provides a -4.8V voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 35.8%;

[0283] In S4, DE provides a -4.9V voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 55.3%;

[0284] In S5 , DE provides a -5V voltage signal, and the duty cycle of the light emitting control voltage provided by HFO is 67.6%.

[0285] 8C and 8D are operation timing diagrams of at least one embodiment of the pixel circuit shown in FIG. 8A during operation in a low grayscale display mode.

[0286] In Figure 8C and Figure 8D, the first 200μs is the data writing time, and the 200μs to 300μs is the working time. During the working time, M15 is turned on or off according to the light-emitting control voltage provided by the HFO. After 300μs, the DC provides a high-voltage signal to control M13 to turn on, R is connected to the VSM, M7 is turned on, S is connected to the VSM, and M5 is turned off. At this time, the discharge path of the Q point is turned off, M3 remains in the off state, and the HFO continues to output a low-voltage signal.

[0287] In FIG8D , the data writing phase is labeled SW, and the low grayscale working phase is labeled SC; the duration of SW is 200 μs, and the duration of SC is 100 μs.

[0288] The difference between at least one embodiment of the pixel circuit shown in FIG. 9A and at least one embodiment of the pixel circuit shown in FIG. 8 is that M1 is an n-type transistor.

[0289] In at least one embodiment of the pixel circuit shown in Figure 9A, the high voltage value of the input signal provided by HFI is 16V, the low voltage value of the input signal provided by HFI is -14V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100μs, and the ratio of the time when the potential of the input signal is maintained at a high voltage to the time when the potential of the input signal is a low voltage is 5 / 95.

[0290] In at least one embodiment of the present disclosure, the active layer material of the TFT is not limited, and various types such as a-Si (amorphous silicon), oxide, LTPS (low temperature polysilicon), and organic materials may be used.

[0291] FIG. 9B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9A during operation when performing high grayscale display.

[0292] As shown in FIG9B , the time period labeled S1 is the first time period, the time period labeled S2 is the second time period, the time period labeled S3 is the third time period, the time period labeled S4 is the fourth time period, and the time period labeled S5 is the fifth time period.

[0293] FIG. 9C is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8A during operation in a low grayscale display mode.

[0294] As shown in FIG10A , based on at least one embodiment of the pixel circuit shown in FIG5 , the light emitting element is an organic light emitting diode O1;

[0295] The input circuit includes a first transistor M1, the reset circuit includes a second transistor M2, the on-off control circuit includes a third transistor M3, the first control circuit includes a fourth transistor M4, and the second control circuit includes a fifth transistor M5;

[0296] The gate of the first transistor M1 is electrically connected to the light emission control input terminal HFI, the source of the first transistor M1 is electrically connected to the high voltage terminal VDD, and the drain of the first transistor M1 is electrically connected to the light emission control voltage terminal HFO;

[0297] The gate of the second transistor M2 and the source of the second transistor M2 are both electrically connected to the light emission control reset terminal HFR, and the drain of the second transistor M2 is electrically connected to the on-off control node Q;

[0298] The gate of the third transistor M3 is electrically connected to the on-off control node Q, the source of the third transistor M3 is electrically connected to the low voltage terminal VSS, and the drain of the third transistor M3 is electrically connected to the light emitting control voltage terminal HFO;

[0299] The gate of the fourth transistor M4 is electrically connected to the light emission control reset terminal HFR, the source of the fourth transistor M4 is electrically connected to the on-off control node Q, and the drain of the fourth transistor M4 is electrically connected to the first intermediate node NZ1;

[0300] The gate of the fifth transistor M5 is electrically connected to the first control node S, the source of the fifth transistor M5 is electrically connected to the first intermediate node NZ1, and the drain of the fifth transistor M5 is electrically connected to the high voltage signal terminal VDDL;

[0301] The first intermediate node control circuit includes a sixth transistor M6;

[0302] The gate of the sixth transistor M6 is electrically connected to the light-emitting control voltage terminal HFO, the source of the sixth transistor M6 is electrically connected to the high voltage signal terminal VDDL, and the drain of the sixth transistor M6 is electrically connected to the first intermediate node NZ1;

[0303] The third control circuit includes a seventh transistor M7, and the fourth control circuit includes an eighth transistor M8;

[0304] The gate of the seventh transistor M7 is electrically connected to the second control node R, the source of the seventh transistor M7 is electrically connected to the control voltage terminal VSM, and the drain of the seventh transistor M7 is electrically connected to the first control node S;

[0305] The gate of the eighth transistor M8 and the source of the eighth transistor M8 are both electrically connected to the high voltage terminal VDD, and the drain of the eighth transistor M8 is electrically connected to the first control node S;

[0306] The first data writing circuit includes a ninth transistor M9, the second data writing circuit includes a tenth transistor M10, the fifth control circuit includes an eleventh transistor M11, the sixth control circuit includes a twelfth transistor M12, and the seventh control circuit includes a thirteenth transistor M13;

[0307] The gate of the ninth transistor M9 is electrically connected to the light emitting control terminal EM, the source of the ninth transistor M9 is electrically connected to the light emitting control data voltage terminal DE, and the drain of the ninth transistor M9 is electrically connected to the second control node R;

[0308] The gate of the tenth transistor M10 is electrically connected to the light emitting control terminal EM, the source of the tenth transistor M10 is electrically connected to the on-off data voltage terminal DS, and the drain of the tenth transistor M10 is electrically connected to the third control node NC3;

[0309] The gate of the eleventh transistor M11 is electrically connected to the third control node NC3, the source of the eleventh transistor M11 is electrically connected to the control data terminal DC, and the drain of the eleventh transistor M11 is electrically connected to the fourth control node NC4;

[0310] The gate of the twelfth transistor M12 is electrically connected to the third control node NC3, the source of the twelfth transistor M12 is electrically connected to the low voltage terminal VSS, and the drain of the twelfth transistor M12 is electrically connected to the fourth control node NC4;

[0311] The gate of the thirteenth transistor M13 is electrically connected to the fourth control node NC4, the source of the thirteenth transistor M13 is electrically connected to the control voltage terminal VSM, and the drain of the thirteenth transistor M13 is electrically connected to the second control node R;

[0312] The first light emitting control circuit includes a fifteenth transistor M15, and the second light emitting control circuit includes a sixteenth transistor M16;

[0313] The gate of the fifteenth transistor M15 is electrically connected to the light emitting control voltage terminal HFO, the source of the fifteenth transistor M15 is electrically connected to the power supply voltage terminal ELVDD, and the fifteenth transistor M15 is electrically connected to the first node N1;

[0314] The gate of the sixteenth transistor M16 is electrically connected to the light emitting control terminal EM, the source of the sixteenth transistor M16 is electrically connected to the first node N1, the drain of the sixteenth transistor M16 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low level terminal ELVSS.

[0315] The first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0316] A first end of the first capacitor C1 is electrically connected to the light-emitting control voltage terminal HFO, and a second end of the first capacitor C1 is electrically connected to the high voltage terminal VDD;

[0317] A first end of the second capacitor C2 is electrically connected to the on-off control node Q, and a second end of the second capacitor C2 is electrically connected to the high voltage terminal VDD;

[0318] The third energy storage circuit includes a third capacitor C3, and the fourth energy storage circuit includes a fourth capacitor C4;

[0319] A first end of the third capacitor C3 is electrically connected to the second control node R, and a second end of the third capacitor C3 is electrically connected to the control voltage terminal VSM;

[0320] A first end of the fourth capacitor C4 is electrically connected to the third control node NC3 , and a second end of the fourth capacitor C4 is electrically connected to the high voltage terminal VDD.

[0321] In at least one embodiment shown in FIG. 10A , the second voltage terminal is a high voltage terminal VDD, the third voltage terminal is a low voltage terminal, the fourth voltage terminal is a high voltage signal terminal VDDL, the fifth voltage terminal is a control voltage terminal VSM, and the sixth voltage terminal is a high voltage terminal VDD.

[0322] Optionally, the voltage value of the high voltage signal provided by the high voltage signal terminal VDDL is slightly smaller than the voltage value of the high voltage signal provided by the high voltage terminal.

[0323] In at least one embodiment shown in FIG. 10A , the control voltage terminal VSM may provide a positive voltage signal. For example, VSM may provide a +4V voltage signal.

[0324] In at least one embodiment shown in FIG. 10A , M1 is an n-type transistor, M2 is a p-type transistor, M3 is an n-type transistor, M4 is an n-type transistor, M5 is a p-type transistor, M6 is a p-type transistor, M7 is an n-type transistor, M8 is an n-type transistor, M9 is an n-type transistor, M10 is an n-type transistor, M11 is an n-type transistor, M12 is a p-type transistor, M13 is a p-type transistor, M15 is a p-type transistor, and M16 is a p-type transistor.

[0325] In at least one embodiment shown in FIG. 10A , VDD provides a 14V voltage signal, VSS provides a −14V voltage signal, VSM provides a 4V voltage signal, ELVDD provides a 5V voltage signal, and ELVSS provides a 0V voltage signal;

[0326] The high voltage value of the input signal provided by HFI is 16V, the low voltage value of the input signal provided by HFI is -16V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100 μs, and the ratio of the time when the potential of the input signal is maintained at the high voltage to the time when the potential of the input signal is maintained at the low voltage is 5 / 95;

[0327] The high voltage value of the reset signal provided by HFR is 16V, the low voltage value of the reset signal provided by HFR is -25V, the reset signal provided by HFR is a square wave signal, the period of the reset signal provided by HFR is 100 μs, and the ratio of the time when the potential of the reset signal is maintained at the low voltage to the time when the potential of the input signal is maintained at the high voltage is 4 / 96;

[0328] DE can provide 6.86V voltage signal, 6.95V voltage signal, 7V voltage signal, 7.1V voltage signal 7.2V, 7.3V voltage signal successively;

[0329] DS provides -14V voltage signal or 14V voltage signal;

[0330] Taking a display frequency of 60 Hz as an example, when performing low grayscale display, the high voltage value of the control data voltage provided by the DC may be 14 V, the low voltage value of the control data voltage may be -14 V, the control data voltage may be a square wave voltage, the period of the control data voltage may be 16667 μs, and the ratio of the time during which the voltage value of the control data voltage remains at a low voltage to the time during which the voltage value of the control data voltage remains at a high voltage may be 300 / 16367;

[0331] Taking a display frequency of 60 Hz as an example, the high voltage value of the light control signal provided by the EM may be 16 V, the low voltage value of the light control signal may be -16 V, the period of the light control signal may be 16667 μs, and the ratio of the time during which the potential of the light control signal remains at a high voltage to the time during which the potential of the light control signal remains at a low voltage is 200 / 16467.

[0332] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50fF, and the capacitance value of C4 is 50fF.

[0333] When at least one embodiment of the pixel circuit shown in FIG. 10A of the present disclosure is in operation,

[0334] Before the start of a cycle (the duration of the cycle may be, but is not limited to, 100 μs), the HFR provides a low voltage signal to turn on M2 and turn off M4. The potential of Q is reset to -25 V, and M3 is turned off.

[0335] After the cycle starts, HFR provides a high voltage signal, turns off M2, turns on M4, HFI provides a high voltage signal, turns on M1, the high voltage signal provided by VDD is written to C1, the HFO signal outputs high voltage, and at the same time turns off M6, VDD charges Q, and the voltage at point S is written to the gate of M5. By controlling the size of the saturation current Id of M5, the charging speed of point Q is controlled;

[0336] After a time t, when the gate-source voltage Vgs of M3 is charged to a voltage greater than the threshold voltage of M3, M3 is turned on, the low voltage signal provided by VSS is written into C1, HFO outputs a low voltage signal, and M6 is turned on at the same time, and the potential of Q rises to a high voltage through rapid charging;

[0337] Before the end of the cycle (i.e., in the last 5 μs of the cycle), HFR provides a low voltage signal, opens M2, closes M4, the potential of Q is reset to -25 V, M3 is closed, C1 maintains a low voltage, and HFO continues to output a low voltage signal;

[0338] The next cycle starts and the above process is repeated.

[0339] During operation, at least one embodiment of the pixel circuit shown in FIG10A of the present disclosure writes the voltage at point S to the gate of M5. By controlling the magnitude of M5's saturation current Id, the charging speed at point Q is controlled. The time t required for Q to charge until the gate-source voltage of M3 exceeds M3's threshold voltage is the duration for which the HFO continuously outputs a high-voltage signal. By adjusting the potential of S, light-emission control voltages with different duty cycles can be obtained.

[0340] In at least one embodiment of the pixel circuit of the present disclosure as shown in FIG10A , M1 is an n-type transistor. At the beginning of a cycle, HFI provides a high voltage signal to turn on M1 and write the high voltage signal provided by VDD. After writing is completed, HFI outputs a low voltage signal to turn off M1. Affected by the parasitic capacitance of M1, the voltage value of the light-emitting control voltage output by HFO will be pulled down and eventually be slightly lower than the voltage value of the high voltage signal provided by VDD, resulting in the gate-source voltage of M6 being less than 0. There is a risk of incomplete shutdown of M6 and leakage.

[0341] Compared with at least one embodiment of the pixel circuit shown in Figure 10A of the present disclosure, in at least one embodiment of the pixel circuit shown in Figure 11A of the present disclosure, M1 is a p-type transistor. At the beginning of the cycle, HFI provides a low voltage signal to turn on M1 and write a high voltage signal provided by VDD. After writing is completed, HFI provides a high voltage signal to turn off M1. Affected by the parasitic capacitance of M1, the voltage value of the light-emitting control voltage provided by HFO will be pulled up. At this time, the gate-source voltage of M6 is greater than 0, which solves the risk of M6 being turned on.

[0342] In at least one embodiment of the pixel circuit shown in FIG10A of the present disclosure, M7, M8, and M9 are responsible for writing and maintaining data voltages. During the data writing phase, EM provides a high voltage signal to turn on M9, and the light-emission control data voltage provided by DE is written to R. The potential of R controls the degree of opening of M7. Based on the voltage-dividing principle of a series circuit, by adjusting the resistance ratio of M7 and M8, the potential of S is controlled, thereby controlling the degree of opening of M5 and the duty cycle of the light-emission control voltage output by HFO.

[0343] M13, M11, M12 and M10 form a high-low grayscale switching module. When displaying a high grayscale, the duty cycle adjustment circuit works throughout the entire process. EM provides a high voltage signal to turn on M10, DS provides a -14V voltage signal to turn off M11 and turn on M12, and the high voltage signal provided by VDD is written to the gate of M10 to turn off M10. When displaying a low grayscale, the duty cycle adjustment circuit only works for one cycle. When EM provides a high voltage signal, DS provides a 14V voltage signal to turn on M11 and turn off M12. DC writes the control data voltage to the gate of M13. After EM provides a low voltage signal, DC continues to provide a high voltage signal to turn off M13 for one cycle. After that, DC provides a low voltage signal to turn on M10. The control voltage provided by VSM is written to R to turn off M7. The potential of S becomes a high voltage to turn off M5, cutting off the Q-point discharge circuit. M3 remains in the closed state and HFO continues to output high voltage.

[0344] In a specific implementation, when PWM (pulse width modulation) driving is adopted, the N grayscale duty cycle is equal to the 255 grayscale duty cycle × (N / 255) ga ;

[0345] Wherein, ga is the gamma value, for example, ga may be greater than or equal to 2.2 and less than or equal to 2.5;

[0346] The following takes a display frequency of 60 Hz and a display cycle duration of 16667 μs as an example to illustrate a method for realizing high and low gray scales.

[0347] Assuming that the duty cycle of grayscale 255 is 100%, that is, the working time in the display cycle is 16667us, the duty cycle of grayscale 13 is calculated to be 0.14% by the above formula, and the working time corresponding to grayscale 13 in the display cycle is 16667*0.14%=23.9us.

[0348] In at least one embodiment of the present disclosure, the period of the light-emitting control voltage output by the HFO is 100 μs. The voltage of the light-emitting control data provided by the DE is adjusted to adjust the duty cycle of the light-emitting control voltage output by the HFO to 23.9%. That is, the single-cycle operating duration is 100 μs × 23.9% = 23.9 μs. Controlled by the control voltage provided by the DC, after the EM provides a low-voltage signal to turn on M16, the duty cycle of the light-emitting control voltage provided by the HFO is 23.9% in the first cycle. This means that within a display cycle of 16667 μs, the light-emitting circuit only operates for 23.9 μs, achieving 13 grayscale display.

[0349] In at least one embodiment of the pixel circuit of the present disclosure as shown in Figure 10A, M15 and M16 are light-emitting control transistors. When the grayscale is switched, DE and DS write signals, and then EM provides a low-voltage signal. The light-emitting control voltage provided by HFO controls the working duration of M15 and the light-emitting time of O1 to achieve grayscale display.

[0350] FIG. 10B is a simulation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 10A during operation and high grayscale display.

[0351] As shown in FIG10B , the time period labeled S1 is the first time period, the time period labeled S2 is the second time period, the time period labeled S3 is the third time period, the time period labeled S4 is the fourth time period, and the time period labeled S5 is the fifth time period;

[0352] The duration of S1, S2, S3, S4 and S5 are all 200 μs;

[0353] In S1, DE provides a 6.86V voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 23.9%;

[0354] In S2, DE provides a 6.95V voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 57.3%;

[0355] In S3, DE provides a 7-voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 66.9%;

[0356] In S4, DE provides a 7.1V voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 78.9%;

[0357] In S5, DE provides a 7.2V voltage signal, and the duty cycle of the light-emitting control voltage provided by HFO is 85.1%.

[0358] FIG10B is only a timing diagram of the simulation operation.

[0359] In actual operation, at least one embodiment of the pixel circuit shown in Figure 10A is provided with a data writing phase lasting 200μs before S1 during operation. During the data writing phase, EM controls M16 to be turned off; and within a display cycle (when the display frequency is 60Hz, the display cycle can last for 16667μs), DE can provide a data voltage only during the data writing phase. During the time period set after the data writing phase included in the display cycle, M16 is turned on, and the light-emitting control voltage provided by HFO controls M15 to be turned on or off.

[0360] FIG. 10B is obtained by simulation to illustrate the relationship between the voltage value of the light emission control voltage provided by the DE and the duty cycle of the light emission control voltage provided by the HFO.

[0361] 10C and 10D are simulated operation timing diagrams of at least one embodiment of the pixel circuit shown in FIG. 10A during operation when performing low grayscale display.

[0362] In Figures 10C and 10D, the first 200μs is the data writing time, and the 200μs to 300μs is the working time. During the working time, M15 is turned on or off according to the light-emitting control voltage provided by the HFO. After 300μs, the DC provides a low-voltage signal to control M13 to turn on, R is connected to the VSM, M7 is turned on, S is connected to the VSM, and M5 is turned off. At this time, the discharge path of point Q is turned off, M3 remains in the off state, and the HFO continues to output a low-voltage signal.

[0363] In FIG10D , the data writing phase is labeled SW, and the low grayscale working phase is labeled SC; the duration of SW is 200 μs, and the duration of SC is 100 μs.

[0364] The difference between at least one embodiment of the pixel circuit shown in FIG. 11A and at least one embodiment of the pixel circuit shown in FIG. 10A is that M1 is a p-type transistor.

[0365] In at least one embodiment of the pixel circuit shown in Figure 11A, the high voltage value of the input signal provided by HFI is 16V, the low voltage value of the input signal provided by HFI is -16V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100μs, and the ratio of the time when the potential of the input signal is maintained at a low voltage to the time when the potential of the input signal is a high voltage is 5 / 95.

[0366] FIG. 11B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 11A when operating and performing high grayscale display.

[0367] As shown in FIG11B , the time period labeled S1 is the first time period, the time period labeled S2 is the second time period, the time period labeled S3 is the third time period, the time period labeled S4 is the fourth time period, and the time period labeled S5 is the fifth time period.

[0368] FIG. 11C is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 11A during operation in a low grayscale display mode.

[0369] As shown in FIG12A , based on at least one embodiment of the pixel circuit shown in FIG7 , the light emitting element is an organic light emitting diode O1;

[0370] The input circuit includes a first transistor M1, the reset circuit includes a second transistor M2, the on-off control circuit includes a third transistor M3, the first control circuit includes a fourth transistor M4, and the second control circuit includes a fifth transistor M5;

[0371] The gate of the first transistor M1 is electrically connected to the light emission control input terminal HFI, the source of the first transistor M1 is electrically connected to the low voltage terminal VSS, and the drain of the first transistor M1 is electrically connected to the light emission control voltage terminal HFO;

[0372] The gate of the second transistor M2 and the source of the second transistor M2 are both electrically connected to the light emission control reset terminal HFR, and the source of the second transistor M2 is electrically connected to the on-off control node Q;

[0373] The gate of the third transistor M3 is electrically connected to the on-off control node Q, the source of the third transistor M3 is electrically connected to the high voltage terminal VDD, and the drain of the third transistor M3 is electrically connected to the light emitting control voltage terminal HFO;

[0374] The gate of the fourth transistor M4 is electrically connected to the light emission control reset terminal HFR, the source of the fourth transistor M4 is electrically connected to the on-off control node Q, and the drain of the fourth transistor M4 is electrically connected to the first intermediate node NZ1;

[0375] The gate of the fifth transistor M5 is electrically connected to the first control node S, the source of the fifth transistor M5 is electrically connected to the first intermediate node NZ1, and the drain of the fifth transistor M5 is electrically connected to the low voltage terminal VSS;

[0376] The first intermediate node control circuit includes a sixth transistor M6;

[0377] The gate of the sixth transistor M6 is electrically connected to the light emission control voltage terminal HFO, the source of the sixth transistor M6 is electrically connected to the low voltage terminal VSS, and the drain of the sixth transistor M6 is electrically connected to the first intermediate node NZ1;

[0378] The eighth control circuit includes a fourteenth transistor M14;

[0379] The gate of the fourteenth transistor M14 is electrically connected to the light emitting control terminal EM, the source of the fourteenth transistor M14 is electrically connected to the second control node R, and the drain of the fourteenth transistor M14 is electrically connected to the first control node S;

[0380] The first data writing circuit includes a ninth transistor M9, the second data writing circuit includes a tenth transistor M10, the fifth control circuit includes an eleventh transistor M11, the sixth control circuit includes a twelfth transistor M12, and the seventh control circuit includes a thirteenth transistor M13;

[0381] The gate of the ninth transistor M9 is electrically connected to the driving control terminal GA, the source of the ninth transistor M9 is electrically connected to the light emitting control data voltage terminal DE, and the drain of the ninth transistor M9 is electrically connected to the second control node R;

[0382] The gate of the tenth transistor M10 is electrically connected to the light emitting control terminal EM, the source of the tenth transistor M10 is electrically connected to the on-off data voltage terminal DS, and the drain of the tenth transistor M10 is electrically connected to the third control node NC3;

[0383] The gate of the eleventh transistor M11 is electrically connected to the third control node NC3, the source of the eleventh transistor M11 is electrically connected to the control data terminal DC, and the drain of the eleventh transistor M11 is electrically connected to the fourth control node NC4;

[0384] The gate of the twelfth transistor M12 is electrically connected to the third control node NC3, the source of the twelfth transistor M12 is electrically connected to the low voltage terminal VSS, and the drain of the twelfth transistor M12 is electrically connected to the fourth control node NC4;

[0385] The gate of the thirteenth transistor M13 is electrically connected to the fourth control node NC4, the source of the thirteenth transistor M13 is electrically connected to the low voltage terminal VSS, and the drain of the thirteenth transistor M13 is electrically connected to the second control node R;

[0386] The first light emitting control circuit includes a fifteenth transistor M15, and the second light emitting control circuit includes a sixteenth transistor M16;

[0387] The gate of the fifteenth transistor M15 is electrically connected to the light emitting control voltage terminal HFO, the source of the fifteenth transistor M15 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fifteenth transistor M15 is electrically connected to the first node N1;

[0388] The gate of the sixteenth transistor M16 is electrically connected to the light emitting control terminal EM, the source of the sixteenth transistor M16 is electrically connected to the first node N1, the drain of the sixteenth transistor M16 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low level terminal ELVSS.

[0389] The first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0390] A first terminal of C1 is electrically connected to HFO, and a second terminal of C1 is electrically connected to the high voltage terminal VDD;

[0391] The first end of C2 is electrically connected to Q, and the second end of C2 is electrically connected to the low voltage terminal VSS;

[0392] The third energy storage circuit includes a third capacitor C3, and the fourth energy storage circuit includes a fourth capacitor C4;

[0393] A first end of C3 is electrically connected to R, and a second end of C3 is electrically connected to the high voltage terminal VDD;

[0394] A first end of C4 is electrically connected to NC3 , and a second end of C4 is electrically connected to the low voltage terminal VSS.

[0395] In at least one embodiment shown in FIG. 12A , the second voltage terminal is the low voltage terminal VSS, the third voltage terminal is the high voltage terminal VDD, the fourth voltage terminal is the low voltage terminal VSS, and the sixth voltage terminal is the low voltage terminal VSS.

[0396] In at least one embodiment shown in FIG. 12A , M1 is a p-type transistor, M2 is an n-type transistor, M3 is a p-type transistor, M4 is a p-type transistor, M5 is an n-type transistor, M6 is an n-type transistor, M14 is an n-type transistor, M9 is an n-type transistor, M10 is a p-type transistor, M11 is a p-type transistor, M12 is an n-type transistor, M13 is an n-type transistor, and M15 and M16 are n-type transistors.

[0397] In at least one embodiment of the pixel circuit shown in FIG12A , when in operation, VDD provides a 14V voltage signal, VSS provides a −14V voltage signal, ELVDD provides a 5V voltage signal, and ELVSS provides a 0V voltage signal;

[0398] The high voltage value of the input signal provided by HFI is 16 V, the low voltage value of the input signal provided by HFI is -16 V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100 μs, and the ratio of the time when the potential of the input signal is maintained at the low voltage to the time when the potential of the input signal is maintained at the high voltage is 5 / 95;

[0399] The high voltage value of the reset signal provided by HFR is 25V, the low voltage value of the reset signal provided by HFR is -16V, the reset signal provided by HFR is a square wave signal, the period of the reset signal provided by HFR is 100 μs, and the ratio of the time when the potential of the reset signal is maintained at the low voltage to the time when the potential of the reset signal is maintained at the high voltage is 96 / 4;

[0400] DE provides -13.6V voltage signal (but not limited to this);

[0401] DS provides -14V voltage signal or 14V voltage signal;

[0402] Taking a display frequency of 60 Hz as an example, when performing low grayscale display, the high voltage value of the control data voltage provided by the DC may be 14 V, the low voltage value of the control data voltage may be -14 V, the control data voltage may be a square wave voltage, the period of the control data voltage may be 16667 μs, and the ratio of the time during which the voltage value of the control data voltage remains at a low voltage to the time during which the voltage value of the control data voltage remains at a high voltage may be 300 / 16367;

[0403] Taking a display frequency of 60 Hz as an example, the high voltage value of the light control signal provided by the EM may be 16 V, the low voltage value of the light control signal may be -16 V, the period of the light control signal may be 16667 μs, and the ratio of the time during which the potential of the light control signal remains at a high voltage to the time during which the potential of the light control signal remains at a low voltage is 200 / 16467.

[0404] Taking a display frequency of 60 Hz as an example, the high voltage value of the drive control signal provided by the GA may be 16 V, the low voltage value of the drive control signal may be -16 V, the period of the drive control signal may be 16667 μs, and the ratio of the time during which the potential of the drive control signal remains at a high voltage to the time during which the potential of the drive control signal remains at a low voltage is 200 / 16467.

[0405] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50fF, and the capacitance value of C4 is 50fF;

[0406] M1 and M2 are digital trigger TFTs, which together form a first-order digital trigger;

[0407] M3, M4, M5, and M6 are duty cycle adjustment control TFTs;

[0408] M14 and M9 are data voltage write-holding TFTs;

[0409] M13, M12, M11, and M10 are high and low grayscale switching TFTs;

[0410] M15 and M16 are light-emitting control TFTs;

[0411] At least one embodiment of the pixel circuit shown in FIG12A is in operation.

[0412] Before the start of the cycle (the duration of the cycle may be 100 μs), HFR provides a high voltage signal to open M2 and close M4, the potential of Q is reset to 25 V, and M3 is closed;

[0413] After the cycle starts, HFR provides a low voltage signal, turns off M2, turns on M4, HFI turns on M1, the low voltage signal provided by VSS is written to C1, HFO outputs a low voltage signal, and turns off M6 at the same time, Q point discharges to VSS, and the voltage of S is written to the gate of M5. By controlling the size of M5's saturation current Id, the discharge speed of Q point is controlled;

[0414] After time t, when the gate-source voltage of M3 is discharged to less than the threshold voltage of M3, M3 is turned on, the high voltage signal provided by VDD is written into C1, HFO outputs a high voltage signal, and M6 is turned on at the same time, and the potential of Q is quickly discharged to a low voltage;

[0415] Before the end of the cycle (i.e., the last 5μs of the cycle), HFR provides a high voltage signal, opens M2, closes M4, resets the potential of Q to 25V, closes M3, maintains high voltage, and HFO continues to output a high voltage signal;

[0416] The next cycle starts and the above process is repeated.

[0417] At least one embodiment of the pixel circuit shown in FIG12A is in operation.

[0418] The voltage of S is written to the gate of M5. By controlling the size of M5's saturation current Id, the discharge speed of point Q is controlled. The time t required for point Q to discharge until the gate-source voltage of M3 is less than the threshold voltage of M3 is the time during which HFO continuously outputs a low-voltage signal. By adjusting the voltage of S, light-emitting control voltages with different duty cycles can be obtained.

[0419] In at least one embodiment of the pixel circuit shown in FIG12A , M1 is a p-type transistor. At the beginning of the cycle, HFI provides a low voltage signal to turn on M1 and write the low voltage signal provided by VSS. After writing is completed, HFI outputs a high voltage signal to turn off M1. Affected by the parasitic capacitance of M1, the voltage value of the light-emitting control voltage output by HFO will be pulled up, and the final voltage will be slightly higher than the voltage value of the low voltage signal provided by VSS, resulting in the gate-source voltage of M6 being greater than 0, and there is a risk of leakage due to incomplete shutdown of M6.

[0420] Compared with at least one embodiment of the pixel circuit shown in Figure 12A, in at least one embodiment of the pixel circuit shown in Figure 13A, M1 is an n-type transistor. At the beginning of the cycle, HFI provides a high voltage signal to turn on M1 and write a low voltage signal provided by VSS. After writing is completed, HFI provides a low voltage signal to turn off M1. Affected by the parasitic capacitance of M1, the voltage value of the light-emitting control voltage output by HFO will be pulled down. At this time, the gate-source voltage of M6 is less than 0, which solves the risk of M6 being turned on.

[0421] At least one embodiment of the pixel circuit shown in FIG12A is in operation.

[0422] M9 and M14 are responsible for writing and maintaining the data voltage. During the data writing phase, GA provides a high voltage signal to turn on M9. The light-emitting control data voltage provided by DE is written into S to control the duty cycle of the light-emitting control voltage output by HFO. At the same time, EM turns off M14 to prevent the potential of S from being affected by the parasitic capacitance of M5.

[0423] M13, M12, M11 and M10 form a high-low grayscale switching module. When displaying a high grayscale, the duty cycle adjustment circuit works throughout the entire process. EM outputs a low voltage signal, opens M10, DS writes a 14V voltage signal, closes M11, opens M12, VSS writes a low voltage signal to the gate of M13, and closes M13. When displaying a low grayscale, the duty cycle adjustment circuit only works for one cycle. When EM provides a low voltage signal, DS writes a -14V voltage signal, opens M11, closes M12, and the control voltage provided by DC is written to the gate of M13. After EM provides a high voltage signal, DC continues to provide a low voltage signal and closes M13 for one cycle. After that, DC provides a high voltage signal to open M13, and VSS writes a low voltage signal to S to close M5, cutting off the Q-point discharge circuit. M3 remains closed and HFO continues to output a low voltage signal.

[0424] M15 and M16 are light-emitting control TFTs. When the grayscale is switched, the light-emitting control data voltage and the on-off data voltage are written. Then EM provides a high-voltage signal. The light-emitting control voltage output by HFO controls the working time of M15 and the light-emitting time of the organic light-emitting diode to achieve grayscale display.

[0425] FIG. 12B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 12A when in operation and displaying a high grayscale.

[0426] In a specific implementation, by switching the voltage value of the light-emitting control data voltage provided by DE, the voltage of S can be adjusted, the opening degree of M5 can be controlled, and the duty cycle of the light-emitting control voltage output by HFO can be adjusted.

[0427] FIG. 12C is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 12A when in operation and displaying a low grayscale.

[0428] As shown in FIG12C , when displaying low grayscale, under the control of the control voltage provided by the DC, the HFO provides a square wave signal only in one cycle. In this cycle, the time for the HFO to provide a high voltage signal is 75.1 μs, achieving 22 grayscale display.

[0429] In FIG12B , the first time period is labeled S1 , and the second time period is labeled S2 . The first time period S1 lasts for 200 μs.

[0430] In FIG. 12B , DE provides a voltage signal of -13.6V. In the second time period S2 , the potential of S is around -12.92V, and the duty cycle of the light-emitting control voltage provided by HFO is 75.1%.

[0431] In FIG. 12C , the data writing phase is labeled SW, and the low grayscale working phase is labeled SC; the duration of SW is 200 μs, and the duration of SC is 100 μs.

[0432] In the data writing phase SW, DE provides a -13.6V voltage signal. In the low grayscale working phase SC, HFO provides a light emitting control voltage with a duty cycle of 75.1%.

[0433] The difference between at least one embodiment of the pixel circuit shown in FIG. 13A and at least one embodiment of the pixel circuit shown in FIG. 12A is that M1 is an n-type transistor.

[0434] When at least one embodiment of the pixel circuit shown in Figure 13A is in operation, the high voltage value of the input signal provided by HFI is 16V, the low voltage value of the input signal provided by HFI is -16V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100μs, and the ratio of the time when the potential of the input signal is maintained at a high voltage to the time when the potential of the input signal is a low voltage is 5 / 95.

[0435] FIG. 13B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 13A when in operation and displaying a high grayscale.

[0436] FIG. 13C is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 13A when in operation and displaying a low grayscale.

[0437] As shown in FIG14A , based on at least one embodiment of the pixel circuit shown in FIG7 , the light emitting element is an organic light emitting diode O1;

[0438] The input circuit includes a first transistor M1, the reset circuit includes a second transistor M2, the on-off control circuit includes a third transistor M3, the first control circuit includes a fourth transistor M4, and the second control circuit includes a fifth transistor M5;

[0439] The gate of the first transistor M1 is electrically connected to the light emission control input terminal HFI, the source of the first transistor M1 is electrically connected to the high voltage terminal VDD, and the drain of the first transistor M1 is electrically connected to the light emission control voltage terminal HFO;

[0440] The gate of the second transistor M2 and the source of the second transistor M2 are both electrically connected to the light emission control reset terminal HFR, and the source of the second transistor M2 is electrically connected to the on-off control node Q;

[0441] The gate of the third transistor M3 is electrically connected to the on-off control node Q, the source of the third transistor M3 is electrically connected to the low voltage terminal VSS, and the drain of the third transistor M3 is electrically connected to the light emitting control voltage terminal HFO;

[0442] The gate of the fourth transistor M4 is electrically connected to the light emission control reset terminal HFR, the source of the fourth transistor M4 is electrically connected to the on-off control node Q, and the drain of the fourth transistor M4 is electrically connected to the first intermediate node NZ1;

[0443] The gate of the fifth transistor M5 is electrically connected to the first control node S, the source of the fifth transistor M5 is electrically connected to the first intermediate node NZ1, and the drain of the fifth transistor M5 is electrically connected to the high voltage signal terminal VDDL;

[0444] The first intermediate node control circuit includes a sixth transistor M6;

[0445] The gate of the sixth transistor M6 is electrically connected to the light-emitting control voltage terminal HFO, the source of the sixth transistor M6 is electrically connected to the high voltage signal terminal VDDL, and the drain of the sixth transistor M6 is electrically connected to the first intermediate node NZ1;

[0446] The eighth control circuit includes a fourteenth transistor M14;

[0447] The gate of the fourteenth transistor M14 is electrically connected to the light emitting control terminal EM, the source of the fourteenth transistor M14 is electrically connected to the second control node R, and the drain of the fourteenth transistor M14 is electrically connected to the first control node S;

[0448] The first data writing circuit includes a ninth transistor M9, the second data writing circuit includes a tenth transistor M10, the fifth control circuit includes an eleventh transistor M11, the sixth control circuit includes a twelfth transistor M12, and the seventh control circuit includes a thirteenth transistor M13;

[0449] The gate of the ninth transistor M9 is electrically connected to the driving control terminal GA, the source of the ninth transistor M9 is electrically connected to the light emitting control data voltage terminal DE, and the drain of the ninth transistor M9 is electrically connected to the second control node R;

[0450] The gate of the tenth transistor M10 is electrically connected to the light emitting control terminal EM, the source of the tenth transistor M10 is electrically connected to the on-off data voltage terminal DS, and the drain of the tenth transistor M10 is electrically connected to the third control node NC3;

[0451] The gate of the eleventh transistor M11 is electrically connected to the third control node NC3, the source of the eleventh transistor M11 is electrically connected to the control data terminal DC, and the drain of the eleventh transistor M11 is electrically connected to the fourth control node NC4;

[0452] The gate of the twelfth transistor M12 is electrically connected to the third control node NC3, the source of the twelfth transistor M12 is electrically connected to the high voltage terminal VDD, and the drain of the twelfth transistor M12 is electrically connected to the fourth control node NC4;

[0453] The gate of the thirteenth transistor M13 is electrically connected to the fourth control node NC4, the source of the thirteenth transistor M13 is electrically connected to the high voltage terminal VDD, and the drain of the thirteenth transistor M13 is electrically connected to the second control node R;

[0454] The first light emitting control circuit includes a fifteenth transistor M15, and the second light emitting control circuit includes a sixteenth transistor M16;

[0455] The gate of the fifteenth transistor M15 is electrically connected to the light emitting control voltage terminal HFO, the source of the fifteenth transistor M15 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fifteenth transistor M15 is electrically connected to the first node N1;

[0456] The gate of the sixteenth transistor M16 is electrically connected to the light emitting control terminal EM, the source of the sixteenth transistor M16 is electrically connected to the first node N1, the drain of the sixteenth transistor M16 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low level terminal ELVSS.

[0457] The first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0458] A first terminal of C1 is electrically connected to HFO, and a second terminal of C1 is electrically connected to the high voltage terminal VDD;

[0459] The first end of C2 is electrically connected to Q, and the second end of C2 is electrically connected to the high voltage terminal VDD;

[0460] The third energy storage circuit includes a third capacitor C3, and the fourth energy storage circuit includes a fourth capacitor C4;

[0461] A first end of C3 is electrically connected to R, and a second end of C3 is electrically connected to the high voltage terminal VDD;

[0462] A first end of C4 is electrically connected to NC3 , and a second end of C4 is electrically connected to the high voltage terminal VDD.

[0463] In at least one embodiment shown in FIG. 14A , the second voltage terminal is a high voltage terminal VDD, the third voltage terminal is a low voltage terminal VSS, the fourth voltage terminal is a high voltage signal terminal VDDL, and the sixth voltage terminal is a high voltage terminal VDD.

[0464] Optionally, the voltage value of the high voltage signal provided by the high voltage signal terminal VDDL is slightly smaller than the voltage value of the high voltage signal provided by the high voltage terminal.

[0465] In at least one embodiment shown in FIG. 14A , M1 is an n-type transistor, M2 is a p-type transistor, M3 is an n-type transistor, M4 is an n-type transistor, M5 is a p-type transistor, M6 is a p-type transistor, M14 is a p-type transistor, M9 is a p-type transistor, M10 is an n-type transistor, M11 is an n-type transistor, M12 is a p-type transistor, M13 is a p-type transistor, and M15 and M16 are p-type transistors.

[0466] In at least one embodiment shown in FIG. 14A of the present disclosure, during operation, VDD provides a 14V voltage signal, VSS provides a -14V voltage signal, ELVDD provides a 5V voltage signal, and ELVSS provides a 0V voltage signal;

[0467] The high voltage value of the input signal provided by HFI is 16V, the low voltage value of the input signal provided by HFI is -16V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100 μs, and the ratio of the time when the potential of the input signal is maintained at the high voltage to the time when the potential of the input signal is maintained at the low voltage is 5 / 95;

[0468] The high voltage value of the reset signal provided by HFR is 16V, the low voltage value of the reset signal provided by HFR is -25V, the reset signal provided by HFR is a square wave signal, the period of the reset signal provided by HFR is 100 μs, and the ratio of the time when the potential of the reset signal is maintained at the low voltage to the time when the potential of the reset signal is maintained at the high voltage is 4 / 96;

[0469] DE can provide 9.6V voltage signal or 9.88V voltage signal (but not limited to this);

[0470] DS can provide -14V voltage signal or 14V voltage signal;

[0471] Taking a display frequency of 60 Hz as an example, when performing low grayscale display, the high voltage value of the control data voltage provided by the DC may be 14 V, the low voltage value of the control data voltage may be -14 V, the control data voltage may be a square wave voltage, the period of the control data voltage may be 16667 μs, and the ratio of the time during which the voltage value of the control data voltage remains high to the time during which the voltage value of the control data voltage remains low may be 300 / 16367;

[0472] Taking a display frequency of 60 Hz as an example, the high voltage value of the drive control signal provided by the GA may be 16 V, the low voltage value of the drive control signal may be -16 V, the period of the drive control signal may be 16667 μs, and the ratio of the time during which the potential of the drive control signal remains at a low voltage to the time during which the potential of the drive control signal remains at a high voltage is 200 / 16467;

[0473] Taking a display frequency of 60 Hz as an example, the high voltage value of the light control signal provided by the EM may be 16 V, the low voltage value of the light control signal may be -16 V, the period of the light control signal may be 16667 μs, and the ratio of the time during which the potential of the light control signal remains at a high voltage to the time during which the potential of the light control signal remains at a low voltage is 200 / 16467.

[0474] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50fF, and the capacitance value of C4 is 50fF;

[0475] M1 and M2 are digital trigger TFTs, which together form a first-order digital trigger.

[0476] M3, M4, M5 and M6 are duty cycle adjustment control TFTs;

[0477] M79 and M14 are data voltage write-holding TFTs;

[0478] M13, M12, M11, and M10 are high-low grayscale switching TFTs;

[0479] M15 and M16 are light-emitting control TFTs.

[0480] At least one embodiment shown in FIG. 14A is in operation.

[0481] Before the start of the cycle (the cycle duration can be 100μs), HFR provides a low voltage signal to open M2, close M4, reset the potential of Q to -25V, and close M3;

[0482] After the cycle starts, HFR provides a high voltage signal, turns off M2, turns on M4, HFI provides a high voltage signal, turns on M1, the high voltage signal provided by VDD is written to C1, HFO outputs a high voltage signal, and at the same time turns off M6, VDD charges Q, and the voltage of S is written to the gate of M5. By controlling the size of the saturation current Id of M5, the charging speed of point Q is controlled;

[0483] After time t, when the gate-source voltage of charging M3 is greater than the threshold voltage of M3, M3 is turned on, the low voltage signal provided by VSS is written into C1, HFO outputs a low voltage signal, and M6 is turned on at the same time, and the potential of Q is quickly charged to a high voltage;

[0484] Before the end of the cycle (i.e., the last 5 μs of the cycle), HFR provides a low-voltage signal, opens M2, closes M4, resets the potential of Q to -25 V, closes M3, keeps C1 at a low voltage, and HFO continues to output a low-voltage signal.

[0485] The next cycle starts and the above process is repeated.

[0486] At least one embodiment shown in FIG. 14A is in operation.

[0487] The voltage of S is written to the gate of M5. By controlling the size of M5's saturation current Id, the charging speed of point Q is controlled. The time t required for the potential of Q to charge the gate-source voltage of M3 to be greater than the threshold voltage of M3 is the time during which the HFO continues to output a high voltage. By adjusting the voltage of S, the light-emitting control voltage with different duty cycles can be obtained.

[0488] In at least one embodiment shown in FIG14 , M1 is an n-type transistor. At the beginning of a cycle, HFI provides a high voltage signal to turn on M1 and write the high voltage signal provided by VDD. After writing is completed, HFI provides a low voltage signal to turn off M1. Affected by the parasitic capacitance of M1, the voltage value of the light-emitting control voltage provided by HFO will be pulled down, and the final voltage will be slightly lower than the voltage value of the high voltage signal provided by VDD, resulting in a gate-source voltage of M6 less than 0, and there is a risk of incomplete shutdown of M6 and leakage.

[0489] Compared with at least one embodiment shown in FIG14A , in at least one embodiment shown in FIG15A , M1 is a p-type transistor. At the start of the cycle, HFI provides a low voltage signal to turn on M1 and write a high voltage signal provided by VDD. After writing is completed, HFI provides a high voltage signal to turn off M1. Affected by the parasitic capacitance of M1, the voltage value of the light-emitting control voltage provided by HFO will be pulled up. At this time, the gate-source voltage of M6 is greater than 0, thereby eliminating the risk of M6 being turned on.

[0490] At least one embodiment shown in FIG. 14A is in operation.

[0491] M9 and M14 are responsible for writing and maintaining data voltages. During the data writing phase, GA provides a low voltage signal to turn on M9. The light-emitting control data voltage provided by DE is written into S to control the duty cycle of the light-emitting control voltage output by HFO. At the same time, EM provides a high voltage signal to turn off M14 to prevent the voltage of S from being affected by the parasitic capacitance of M5.

[0492] M13, M12, M11, and M10 form a high-low grayscale switching module. When displaying a high grayscale, the duty cycle adjustment circuit operates fully. EM provides a high voltage signal, turning on M10. DS writes a -14V voltage signal, closing M11, opening M12, and writing a high voltage signal from VDD to the gate of M13, which then closes M13. When displaying a low grayscale, the duty cycle adjustment circuit operates for only one cycle. When EM provides a high voltage signal, DS writes a 14V voltage signal, turning on M11, closing M12, and DC writes a control voltage to the gate of M13. After EM provides a low voltage signal, DC continues to provide a high voltage signal, closing M13 for one cycle, and then providing a low voltage signal. M13 opens, VDD writes a high voltage signal to S, closing M5, and disconnecting the Q-point discharge circuit. M3 remains closed, and HFO continuously outputs a high voltage signal.

[0493] M15 and M16 are light-emitting control TFTs. When the grayscale is switched, the light-emitting control data voltage and the on-off data voltage are written. Then EM provides a low-voltage signal. The light-emitting control voltage output by HFO controls the on-time of M15 and the light-emitting time of the organic light-emitting diode O1 to achieve grayscale display.

[0494] FIG. 14B is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 14A when displaying a high grayscale.

[0495] In FIG14B , the data writing phase is labeled SW, and the duration of the data writing phase SW may be 200 μs. In the data writing phase SW, DC provides a low voltage signal, and DE writes the light emitting control data voltage. In at least one embodiment shown in FIG14B , DE writes a 9.6V voltage signal.

[0496] In Figure 14B, the high grayscale working stage is labeled SG, which can last for 16476μs. In the high grayscale working stage SG, the duty cycle of the light-emitting control voltage provided by HFO is 85.2%; in the high grayscale working stage SG, EM provides a low voltage signal, M16 is turned on, and when HFO provides a low voltage signal, M15 is turned on, and O1 emits light.

[0497] In FIG14B , the voltage of S is 9.6V.

[0498] In FIG. 14C , the data writing phase is labeled SW, and the low grayscale working phase is labeled SC; the duration of SW is 200 μs, and the duration of SC is 100 μs.

[0499] In the data writing phase, SW and DE provide a 9.88V voltage signal. In the low grayscale working phase, SC and HFO provide a light emitting control voltage with a duty cycle of 20%, thus realizing 12 grayscale display.

[0500] The difference between at least one embodiment of the pixel circuit shown in FIG. 15A and at least one embodiment of the pixel circuit shown in FIG. 14A is that M1 is a p-type transistor.

[0501] When at least one embodiment shown in FIG. 15A of the present disclosure is in operation, the high voltage value of the input signal provided by the HFI is 16 V, the low voltage value of the input signal provided by the HFI is -16 V, the input signal provided by the HFI is a square wave signal, the period of the input signal provided by the HFI is 100 μs, and the ratio of the time when the potential of the input signal is maintained at a low voltage to the time when the potential of the input signal is maintained at a high voltage is 5 / 95.

[0502] FIG15B is a timing diagram of a simulated operation of at least one embodiment of the pixel circuit shown in FIG15A when displaying a high grayscale;

[0503] FIG. 15C is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 15A when displaying a low grayscale.

[0504] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0505] The first light emitting control circuit controls the power supply voltage terminal to be connected to the first node under the control of the light emitting control voltage;

[0506] The second light emitting control circuit controls the connection between the first node and the first electrode of the light emitting element under the control of the light emitting control signal;

[0507] The light-emitting control voltage control circuit controls the light-emitting control voltage provided by the light-emitting control input terminal, the reset signal provided by the light-emitting control reset terminal, and the light-emitting control signal provided by the light-emitting control terminal, according to the light-emitting control data voltage provided by the light-emitting control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal, and the control data voltage provided by the control data terminal.

[0508] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0509] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit and a light-emitting control voltage control circuit; The first light-emitting control circuit is electrically connected to the light-emitting control voltage terminal, the power supply voltage terminal and the first node respectively, and is used to control the connection between the power supply voltage terminal and the first node under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the first node and the first electrode of the light emitting element respectively, and is used to control the connection between the first node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; the second electrode of the light emitting element is electrically connected to the first voltage terminal; The light-emitting control voltage control circuit is electrically connected to the light-emitting control voltage terminal, the light-emitting control input terminal, the light-emitting control reset terminal, the light-emitting control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the light-emitting control voltage provided by the light-emitting control voltage terminal according to the light-emitting control data voltage provided by the light-emitting control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal and the control data voltage provided by the control data terminal, under the control of the input signal provided by the light-emitting control input terminal, the reset signal provided by the light-emitting control reset terminal and the light-emitting control signal provided by the light-emitting control terminal.

2. The pixel circuit according to claim 1, wherein: The light emitting control voltage control circuit comprises an input circuit, a reset circuit, an on-off control circuit, a first control circuit, a second control circuit and a first control node control circuit; The input circuit is electrically connected to the light-emitting control input terminal, the second voltage terminal and the light-emitting control voltage terminal respectively, and is used to control the connection between the light-emitting control voltage terminal and the second voltage terminal under the control of the input signal provided by the light-emitting control input terminal; The reset circuit is electrically connected to the light emitting control reset terminal and the on-off control node respectively, and is used to control the potential of the on-off control node under the control of the reset signal provided by the light emitting control reset terminal; The on-off control circuit is electrically connected to the on-off control node, the third voltage terminal and the light-emitting control voltage terminal respectively, and is used to control the connection between the light-emitting control voltage terminal and the third voltage terminal under the control of the potential of the on-off control node; The first control circuit is electrically connected to the light emitting control reset terminal, the on-off control node and the first intermediate node respectively, and is used to control the connection between the on-off control node and the first intermediate node under the control of the reset signal; The second control circuit is electrically connected to the first control node, the first intermediate node and the fourth voltage terminal respectively, and is used to control the connection between the first intermediate node and the fourth voltage terminal under the control of the potential of the first control node; The first control node control circuit is electrically connected to the first control node, the light emitting control terminal, the light emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal respectively, and is used to control the light emitting control signal provided by the light emitting control terminal according to the light emitting control data voltage, the on-off data voltage and the control data voltage. Controlling the potential of the first control node.

3. The pixel circuit according to claim 2, wherein: Also included is a first intermediate node control circuit; The first intermediate node control circuit is electrically connected to the light-emitting control voltage terminal, the first intermediate node and the fourth voltage terminal respectively, and is used to control the connection between the first intermediate node and the fourth voltage terminal under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal.

4. The pixel circuit according to claim 2, wherein: Also includes a first energy storage circuit and a second energy storage circuit; The first energy storage circuit is electrically connected to the light emitting control voltage terminal, and is used to maintain the potential of the light emitting control voltage terminal; The second energy storage circuit is electrically connected to the on-off control node and is used to maintain the potential of the on-off control node.

5. The pixel circuit according to claim 2, wherein: The first control node control circuit includes a third control circuit, a fourth control circuit and a second control node control circuit; The third control circuit is electrically connected to the second control node, the fifth voltage terminal and the first control node respectively, and is used to control the connection between the first control node and the fifth voltage terminal under the control of the potential of the second control node; The fourth control circuit is electrically connected to the sixth voltage terminal and the first control node respectively, and is used to control the potential of the first control node; The second control node control circuit is electrically connected to the second control node, the light-emitting control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal.

6. The pixel circuit according to claim 5, wherein: The second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit; The first data writing circuit is electrically connected to the light emitting control terminal, the light emitting control data voltage terminal and the second control node respectively, and is used to write the light emitting control data voltage into the second control node under the control of the light emitting control signal; The second data writing circuit is respectively connected to the light emitting control terminal, the on-off data voltage terminal and the third control node, and is used to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under the control of the light emitting control signal; The fifth control circuit is electrically connected to the third control node, the control data terminal and the fourth control node respectively, and is used to write the control data voltage into the fourth control node under the control of the potential of the third control node; The sixth control circuit is respectively connected to the third control node, the sixth voltage terminal, and between the fourth control node and the sixth voltage terminal; The seventh control circuit is electrically connected to the fourth control node, the fifth voltage terminal and the second control node respectively, and is used to control the connection between the second control node and the fifth voltage terminal under the control of the potential of the fourth control node.

7. The pixel circuit according to claim 2, wherein: The first control node control circuit includes an eighth control circuit and a second control node control circuit; The eighth control circuit is electrically connected to the light emitting control terminal, the second control node and the first control node respectively, and is used to control the connection between the first control node and the second control node under the control of the light emitting control signal provided by the light emitting control terminal; The second control node control circuit is electrically connected to the light-emitting control terminal, the driving control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is used to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal and the driving control signal provided by the driving control terminal.

8. The pixel circuit according to claim 7, wherein: The second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit; The first data writing circuit is electrically connected to the driving control terminal, the light emitting control data voltage terminal and the second control node respectively, and is used to write the light emitting control data voltage into the second control node under the control of the driving control signal; The second data writing circuit is respectively connected to the light emitting control terminal, the on-off data voltage terminal and the third control node, and is used to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under the control of the light emitting control signal; The fifth control circuit is electrically connected to the third control node, the control data terminal and the fourth control node respectively, and is used to write the control data voltage into the fourth control node under the control of the potential of the third control node; The sixth control circuit is electrically connected to the third control node, the sixth voltage terminal and the fourth control node respectively, and is used to control the connection between the fourth control node and the sixth voltage terminal under the control of the potential of the third control node; The seventh control circuit is electrically connected to the fourth control node, the sixth voltage terminal and the second control node respectively, and is used to control the connection between the second control node and the sixth voltage terminal under the control of the potential of the fourth control node.

9. The pixel circuit according to claim 6 or 8, wherein: Also includes a third energy storage circuit and a fourth energy storage circuit; The third energy storage circuit is electrically connected to the second control node, and is used to maintain the potential of the second control node; The fourth energy storage circuit is electrically connected to the third control node, and is used to maintain the potential of the third control node.

10. The pixel circuit according to claim 2, wherein: The input circuit includes a first transistor, the reset circuit includes a second transistor, the on-off control circuit includes a third transistor, the first control circuit includes a fourth transistor, and the second control circuit includes a fifth transistor; The gate of the first transistor is electrically connected to the light emission control input terminal, the first electrode of the first transistor is electrically connected to the second voltage terminal, and the second electrode of the first transistor is electrically connected to the light emission control voltage terminal; The gate electrode of the second transistor and the first electrode of the second transistor are both electrically connected to the light emission control reset terminal, and the second electrode of the second transistor is electrically connected to the on-off control node; The gate of the third transistor is electrically connected to the on-off control node, the first electrode of the third transistor is electrically connected to the third voltage terminal, and the second electrode of the third transistor is electrically connected to the light emitting control voltage terminal; The gate of the fourth transistor is electrically connected to the light emission control reset terminal, the first electrode of the fourth transistor is electrically connected to the on-off control node, and the second electrode of the fourth transistor is electrically connected to the first intermediate node; A gate of the fifth transistor is electrically connected to the first control node, a first electrode of the fifth transistor is electrically connected to the first intermediate node, and a second electrode of the fifth transistor is electrically connected to the fourth voltage terminal.

11. The pixel circuit according to claim 3, wherein: The first intermediate node control circuit includes a sixth transistor; A gate of the sixth transistor is electrically connected to the light emission control voltage terminal, a first electrode of the sixth transistor is electrically connected to the fourth voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first intermediate node.

12. The pixel circuit according to claim 5, wherein: The third control circuit includes a seventh transistor, and the fourth control circuit includes an eighth transistor; The gate of the seventh transistor is electrically connected to the second control node, the first electrode of the seventh transistor is electrically connected to the fifth voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first control node; The gate of the eighth transistor and the first electrode of the eighth transistor are both electrically connected to the sixth voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first control node.

13. The pixel circuit according to claim 6, wherein: The first data writing circuit includes a ninth transistor, the second data writing circuit includes a tenth transistor, the fifth control circuit includes an eleventh transistor, the sixth control circuit includes a twelfth transistor, and the seventh control circuit includes a thirteenth transistor; The gate of the ninth transistor is electrically connected to the light emitting control terminal, the first electrode of the ninth transistor is electrically connected to the light emitting control data voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second control node; The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the on-off data voltage terminal, and the second electrode of the tenth transistor is electrically connected to the third control node; The gate of the eleventh transistor is electrically connected to the third control node, the first electrode of the eleventh transistor is electrically connected to the control data terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth control node; The gate of the twelfth transistor is electrically connected to the third control node, the first electrode of the twelfth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fourth control node; A gate of the thirteenth transistor is electrically connected to the fourth control node, a first electrode of the thirteenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second control node.

14. The pixel circuit according to claim 7, wherein: The eighth control circuit includes a fourteenth transistor; A gate of the fourteenth transistor is electrically connected to the light emitting control terminal, a first electrode of the fourteenth transistor is electrically connected to the second control node, and a second electrode of the fourteenth transistor is electrically connected to the first control node.

15. The pixel circuit according to claim 8, wherein: The first data writing circuit includes a ninth transistor, the second data writing circuit includes a tenth transistor, the fifth control circuit includes an eleventh transistor, the sixth control circuit includes a twelfth transistor, and the seventh control circuit includes a thirteenth transistor; The gate of the ninth transistor is electrically connected to the driving control terminal, the first electrode of the ninth transistor is electrically connected to the light emitting control data voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second control node; The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the on-off data voltage terminal, and the second electrode of the tenth transistor is electrically connected to the third control node; The gate of the eleventh transistor is electrically connected to the third control node, the first electrode of the eleventh transistor is electrically connected to the control data terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth control node; The gate of the twelfth transistor is electrically connected to the third control node, the first electrode of the twelfth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fourth control node; A gate of the thirteenth transistor is electrically connected to the fourth control node, a first electrode of the thirteenth transistor is electrically connected to the sixth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second control node.

16. The pixel circuit according to claim 2, wherein: The first light emitting control circuit includes a fifteenth transistor, and the second light emitting control circuit includes a sixteenth transistor; The gate of the fifteenth transistor is electrically connected to the light emitting control voltage terminal, the first electrode of the fifteenth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the first node; A gate of the sixteenth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixteenth transistor is electrically connected to the first node, and a second electrode of the sixteenth transistor is electrically connected to a first electrode of the light emitting element.

17. A driving method, applied to the pixel circuit according to any one of claims 1 to 16, the driving method comprising: The first light emitting control circuit controls the power supply voltage terminal to be connected to the first node under the control of the light emitting control voltage; The second light emitting control circuit controls the connection between the first node and the first electrode of the light emitting element under the control of the light emitting control signal; The luminescence control voltage control circuit controls the luminescence control voltage provided by the luminescence control voltage terminal according to the luminescence control data voltage provided by the luminescence control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal and the control data voltage provided by the control data terminal, under the control of the input signal provided by the luminescence control input terminal, the reset signal provided by the luminescence control reset terminal and the luminescence control signal provided by the luminescence control terminal.

18. A display device comprising the pixel circuit according to any one of claims 1 to 16.

Images