Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises sub-pixels; each sub-pixel comprises a pixel circuit; the pixel circuit comprises a light-emitting device and a driving transistor, and the driving transistor is configured to control, on the basis of a data signal, the magnitude of a driving current flowing through the light-emitting device; the pixel circuit also comprises a control transistor, and a first electrode of the control transistor is electrically connected to a gate of the driving transistor; the material of an active layer of the driving transistor is a first semiconductor material, the material of an active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; an electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

Description

Display substrate, manufacturing method thereof, and display device

[0001] This application claims priority to Chinese Patent Application No. 202310956228.7 filed on July 31, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] At least one embodiment of the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0003] LTPO display substrates integrate oxide transistors (Oxide TFTs) and low-temperature polysilicon transistors (LTPS TFTs). They offer the advantage of low-frequency drive, which can reduce the power consumption of display products. They are increasingly being used in organic light-emitting diode (OLED) display substrates, such as flexible active-active organic light-emitting diode (AMOLED) display substrates for mobile display products. However, because LTPO display substrates integrate both LTPS TFTs and oxide TFTs, the low-hydrogen process of the oxide TFTs is susceptible to the high-hydrogen and high-temperature process of the LTPS TFTs, resulting in poor device stability. Furthermore, the integration of both LTPS TFTs and oxide TFTs complicates the signal line layout in the pixel area, affecting the aperture ratio and transmittance of the LTPO display substrate and increasing design complexity.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a display substrate, which includes a sub-pixel, the sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a control transistor, the first electrode of the control transistor is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

[0006] For example, at least one embodiment of the present disclosure provides a display substrate in which the active layer of the driving transistor and the active layer of the control transistor are arranged in different layers, and the gate of the driving transistor is located between the electrodes where the active layer of the driving transistor and the active layer of the control transistor are located.

[0007] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, the driving transistor is arranged on the main surface of the base substrate; the active layer of the driving transistor is located on the side of the active layer of the control transistor close to the base substrate.

[0008] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit includes a first reset transistor, and the first reset transistor is configured to write a first reset signal to the gate of the driving transistor under the control of a first reset control signal; the control transistor includes the first reset transistor, and the electrode where the active layer of the first reset transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the first reset transistor.

[0009] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first pole of the first reset transistor, the material of the first pole of the first reset transistor is the material after the second semiconductor material is conductive, the active layer of the first reset transistor and the first pole of the first reset transistor are arranged in the same layer and constitute an integrated structure; the gate of the driving transistor and the electrode where the active layer of the first reset transistor is located are arranged in a different layer, and the first pole of the first reset transistor contacts the gate of the driving transistor through a first via exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first pole of the first reset transistor.

[0010] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the first reset transistor is located also includes the second pole of the first reset transistor, and the material of the second pole of the first reset transistor is the material after the second semiconductor material is conductive; the pixel circuit also includes a first reset signal line arranged in a different layer from the second pole of the first reset transistor, and the second pole of the first reset transistor contacts the first reset signal line through a second via exposing the first reset signal line to directly electrically connect to the first reset signal line.

[0011] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a compensation transistor, and the compensation transistor is configured to compensate for the signal applied to the gate of the driving transistor in response to the compensation scanning signal and the data signal; the control transistor also includes the compensation transistor, and the electrode where the active layer of the compensation transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the compensation transistor.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the compensation transistor is located also includes the first electrode of the compensation transistor, the materials of the active layer of the compensation transistor and the first electrode of the compensation transistor are both the materials after the second semiconductor material is conductive, the active layer of the compensation transistor and the first electrode of the compensation transistor are arranged in the same layer and constitute an integrated structure; the gate of the driving transistor and the electrode where the active layer of the compensation transistor is located are arranged in a different layer, and the first electrode of the compensation transistor contacts the gate of the driving transistor through a third via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the compensation transistor.

[0013] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the control transistor includes a reset transistor, the electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first electrode of the first reset transistor, the material of the first electrode of the first reset transistor is the material after the second semiconductor material is conductive, the active layer of the first reset transistor and the first electrode of the first reset transistor are arranged in the same layer and form an integrated structure, the gate of the driving transistor and the electrode where the active layer of the first reset transistor is located are arranged in a different layer, and the first electrode of the first reset transistor is in direct contact with the gate of the driving transistor through a first via hole exposing the gate of the driving transistor. When the gate of the driving transistor and the first electrode of the first reset transistor are electrically connected, the electrode where the active layer of the compensation transistor is located is arranged on the same layer as the electrode where the active layer of the first reset transistor is located and constitutes an integrated structure, the first electrode of the first reset transistor and the first electrode of the compensation transistor are integrated, and the first via and the second via are the same via; the material of the active layer of the compensation transistor is the second semiconductor material, the material of the first electrode of the compensation transistor is the material after the second semiconductor material is conductive, the first electrode of the first reset transistor, the first electrode of the compensation transistor and the active layer of the compensation transistor are connected in sequence, arranged on the same layer and constitute an integrated structure.

[0014] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit further includes a first light-emitting control transistor, which is configured to enable the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor and the active layer of the control transistor are arranged in different layers; the electrode where the active layer of the compensation transistor is located further includes a connecting portion, the material of the connecting portion is the material after the second semiconductor material is conductively converted, and the connecting portion is arranged in the same layer as the active layer of the compensation transistor to form an integrated structure; the connecting portion contacts the active layer of the first light-emitting control transistor through a fourth via hole that exposes the active layer of the first light-emitting control transistor to electrically connect the active layer of the first light-emitting control transistor, and the connecting portion serves as the first electrode of the first light-emitting control transistor and the second electrode of the compensation transistor.

[0015] For example, at least one embodiment of the present disclosure provides a display substrate in which the active layer of the first light-emitting control transistor and the active layer of the driving transistor are arranged on the same layer, and / or the gate of the driving transistor and the gate of the first light-emitting control transistor are arranged on the same layer.

[0016] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit further includes a first light-emitting control transistor, and the first light-emitting control transistor is configured to enable the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor is arranged in a different layer from the active layer of the control transistor; the electrode where the active layer of the control transistor is located is arranged in a different layer from the second pole of the first light-emitting control transistor, and the electrode where the active layer of the control transistor is located is in contact with the active layer of the first light-emitting control transistor through a fourth via hole exposing the active layer of the first light-emitting control transistor, and the second pole of the first light-emitting control transistor is in contact with the active layer of the first light-emitting control transistor through a fifth via hole exposing the active layer of the first light-emitting control transistor.

[0017] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, the driving transistor is arranged on the main surface of the base substrate; the second electrode of the first light-emitting control transistor is located on the side of the electrode where the active layer of the control transistor is located, away from the base substrate.

[0018] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the control transistor includes a first reset transistor, the electrode where the active layer of the first reset transistor is located also includes the second pole of the first reset transistor, the material of the second pole of the first reset transistor is the material after the second semiconductor material is conductive, the pixel circuit also includes a first reset signal line set with the second pole different layer of the first reset transistor, and the second pole of the first reset transistor is electrically connected to the first reset signal line through a second via exposing the first reset signal line, and the first reset signal line is set with the second pole different layer of the first light-emitting control transistor.

[0019] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the first reset signal line and the gate of the driving transistor are both located between the gate of the driving transistor and the electrode where the active layer of the control transistor is located; the first reset signal line and the gate of the driving transistor are arranged in different layers or in the same layer.

[0020] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the control transistor is a single-gate transistor, and the gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the driving transistor; or, the control transistor is a dual-gate transistor, and the first gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the driving transistor, and the second gate of the control transistor is located between the active layer of the control transistor and the active layer of the driving transistor, and the second gate of the control transistor is set on the same layer or on a different layer as the first reset signal line.

[0021] For example, at least one embodiment of the present disclosure provides a display substrate in which the second gate of the control transistor and the gate of the driving transistor are arranged in the horizontal direction; when the control transistor is a dual-gate transistor, the line width of the second gate of the control transistor in the horizontal direction is greater than the line width of the first gate of the control transistor in the horizontal direction.

[0022] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, the driving transistor is arranged on the main surface of the base substrate; the first reset signal line and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the base substrate.

[0023] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a first light-emitting control transistor, which is configured to enable the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor and the active layer of the control transistor are arranged in different layers; the electrode where the active layer of the compensation transistor is located also includes the second pole of the compensation transistor, the material of the second pole of the compensation transistor is the material after the second semiconductor material is conductive, and the second pole of the compensation transistor and the active layer of the compensation transistor are arranged in the same layer and constitute an integrated structure; the pixel circuit includes a first connection structure, and the first connection structure, the second pole of the compensation transistor and the electrode where the active layer of the control transistor are located are all arranged in different layers; the first connection structure is electrically connected to the second pole of the compensation transistor through a sixth via hole, and is electrically connected to the active layer of the first light-emitting control transistor through a seventh via hole.

[0024] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, and the driving transistor is arranged on the main surface of the base substrate; the fifth via penetrates the second pole of the compensation transistor, and the first connection structure includes an inner hole portion located in the sixth via, and the side surface of the inner hole portion contacts the second pole of the compensation transistor, and the surface where the side surface of the inner hole portion is located intersects with the surface where the main surface of the base substrate is located; or, the fifth via exposes the upper surface of the second pole of the compensation transistor, and the upper surface of the second pole of the compensation transistor is away from the main surface of the base substrate, and the first connection structure includes an inner hole portion located in the sixth via, and the bottom surface of the inner hole portion contacts the upper surface of the second pole of the compensation transistor.

[0025] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit further includes a first light-emitting control transistor, which is configured to apply the driving current to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor is arranged in a different layer from the active layer of the control transistor; the electrode where the active layer of the compensation transistor is located further includes the second pole of the compensation transistor, the material of the second pole of the compensation transistor is the material after the second semiconductor material is conductively converted, and the connecting portion is arranged in the same layer as the active layer of the compensation transistor to form an integrated structure; the pixel circuit further includes a second connection structure and a third connection structure, the second pole of the compensation transistor, the second connection structure, the third connection structure and the active layer of the first light-emitting control transistor are all arranged in different layers; the second pole of the compensation transistor is electrically connected to the second connection structure through an eighth via hole, the third connection structure is electrically connected to the second connection structure through a ninth via hole, and the third connection structure is electrically connected to the active layer of the first light-emitting control transistor through a tenth via hole.

[0026] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material.

[0027] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the transparent metal oxide semiconductor material includes indium gallium zinc oxide (IGZO).

[0028] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0029] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: forming sub-pixels, including forming pixel circuits, wherein the forming of the pixel circuit includes forming a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the forming of the pixel circuit also includes: forming a control transistor, wherein the first electrode of the control transistor is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

[0030] For example, at least one embodiment of the present disclosure provides a method for manufacturing a display substrate, including: forming a first type of via, wherein the first type of via exposes at least an active layer composed of the first semiconductor material; forming a first conductive structure to electrically connect to the surface of the active layer composed of the first semiconductor material exposed by the first type of via through the first type of via; after forming the first type of via, performing a high-temperature annealing process on the display substrate; and performing contact resistance reduction treatment on the surface of the active layer composed of the first semiconductor material exposed by the first type of via.

[0031] For example, at least one embodiment of the present disclosure provides a method for manufacturing a display substrate, including: forming a second semiconductor layer using the second semiconductor material through a single patterning process; conducting a portion of the second semiconductor layer to form a second conductive structure, wherein the second conductive structure serves as an electrode where the active layer of the control transistor is located, and includes a conducting portion and a non-conductorized portion, and the conducting portion and the non-conductorized portion constitute an integrated structure; the non-conductorized portion constitutes the active layer of the control transistor, the conducting portion directly electrically connects the gate of the driving transistor and the first electrode of the control transistor, and the material of the conducting portion is the material after the second semiconductor material is conducted; and forming a second type of via, the conducting portion of the second conductive structure directly electrically connects the gate of the driving transistor and the first electrode of the control transistor through the second type of via.

[0032] For example, at least one embodiment of the present disclosure provides a method for manufacturing a display substrate, wherein the high-temperature annealing process is performed on the display substrate after forming the second type of via holes and before forming the second conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0034] FIG1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0035] FIG2 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0036] FIG3 is a partial cross-sectional schematic diagram of a pixel circuit of a display substrate provided by at least one embodiment of the present disclosure;

[0037] FIG4 is a partial cross-sectional schematic diagram of a pixel circuit;

[0038] FIG5 is a partial plan view of a pixel circuit;

[0039] FIG6 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0040] FIG7 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0041] FIG8 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0042] FIG9 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0043] FIG10 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0044] FIG11 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0045] FIG12 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0046] FIG13 is a schematic diagram of a display device provided by an embodiment of the present disclosure;

[0047] 14A-14D are schematic diagrams of a method for manufacturing a display substrate according to an embodiment of the present disclosure;

[0048] 15A-15D are schematic diagrams of a method for manufacturing a display substrate provided in one embodiment of the present disclosure;

[0049] 16A-16D are schematic diagrams of a method for manufacturing a display substrate according to an embodiment of the present disclosure;

[0050] 17A-17D are schematic diagrams of a method for manufacturing a display substrate provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0053] The terms in this disclosure are explained as follows:

[0054] (1) Meaning of an integrated structure: The description of structure A and structure B as an integrated structure means that there is no joint between structure A and structure B, and the structure is a uniform, one-piece structure, for example, formed by the same construction process. The letters A and B are used to refer to the corresponding structures described in the text.

[0055] (2) The meaning of "same-layer arrangement" refers to the relationship between multiple structures formed by the same material after the same patterning process. "Same-layer arrangement" here does not always mean that the multiple structures have the same thickness or the same height in the cross-sectional view.

[0056] (3) The meaning of a patterning process: a film layer is patterned by using a mask plate and a single exposure process.

[0057] The drawings in this disclosure are not drawn strictly to scale, and the number of sub-pixels in the display substrate is not limited to the number shown in the drawings. The specific size and number of each structure can be determined according to actual needs. The drawings described in this disclosure are only schematic diagrams of the structures.

[0058] At least one embodiment of the present disclosure provides a display substrate, which includes a sub-pixel, the sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a control transistor, the first electrode of the control transistor is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

[0059] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0060] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: forming sub-pixels, including forming pixel circuits, wherein the forming of the pixel circuit includes forming a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the forming of the pixel circuit also includes: forming a control transistor, wherein the first electrode of the control transistor is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

[0061] FIG1 is a planar schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. As shown in FIG1 , for example, the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least some of the plurality of pixels 100 include a plurality of sub-pixels, and at least some of the plurality of sub-pixels include a light-emitting device and a pixel circuit that drives the light-emitting device to emit light. For example, the pixel circuit may include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, or an nTmC (n, m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit may further include a compensation subcircuit, and the compensation subcircuit includes an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, and the like. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control subcircuit, a detection circuit, and the like.

[0062] For example, as shown in FIG1 , a plurality of pixels 100 are located in a display area. For example, in a display substrate 10 provided in some embodiments, some of the plurality of pixels 100 are dummy pixels 101. The dummy pixels 101 do not participate in display operations. Each dummy pixel 101 includes a plurality of dummy sub-pixels, but does not include sub-pixels that perform a display driving function.

[0063] For example, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED. The display substrate 10 may further include a plurality of scan lines and a plurality of data lines for providing scan signals (e.g., gate lines, control signals, see FIG. 5 ) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels. As needed, the display substrate 10 may further include power lines, detection lines, etc.

[0064] The pixel circuit of the display substrate 10 provided in the embodiment of the present disclosure includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a control transistor, and the first electrode of the control transistor is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor, that is, the electrode where the active layer of the control transistor is located serves as a connecting line electrically connecting the gate of the driving transistor and the first electrode of the control transistor.

[0065] It should be noted that the phrase “the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor” here means that the electrode where the active layer of the control transistor is located is in direct contact with the gate of the driving transistor and the first electrode of the control transistor, thereby electrically connecting the gate of the driving transistor and the first electrode of the control transistor, rather than indirectly electrically connecting the first electrode of the active layer of the control transistor to the gate of the driving transistor through other conductive structures (for example, conductive structures located on other layers).

[0066] For example, FIG2 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure. Here, the structure of the sub-pixel of the display substrate is introduced by taking the 7T1C pixel circuit shown in FIG2 as an example.

[0067] Referring to Figure 2 , the pixel circuit includes a light-emitting device EL and a driving transistor T3. The driving transistor T3 is configured to control the magnitude of the driving current flowing through the light-emitting device EL based on a data signal Vd. For example, the pixel circuit includes a first reset transistor T1. The first reset transistor T1 is configured to write a first reset signal Vinit1 to the gate T3g of the driving transistor T3 under the control of a first reset control signal Rst1. For example, the first reset signal Vinit1 and the second reset signal Vinit2 are the same signal and are derived from the same reset signal line connected to the same reset signal terminal, thereby saving one reset signal line. Of course, the first reset signal Vinit1 and the second reset signal Vinit2 can also be independent signals.

[0068] FIG3 is a partial cross-sectional schematic diagram of a pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. In conjunction with FIG2 and FIG3 , for example, the control transistor includes a first reset transistor T1, and the electrode ET on which the active layer T1a of the first reset transistor T1 is located is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. The electrode ET on which the active layer T1a of the first reset transistor T1 is located is an integrated structure and includes the active layer T1a of the first reset transistor T1 and other parts. That is, the active layer T1a of the first reset transistor T1 and other parts constitute the electrode ET of the integrated structure. In this case, the material of the active layer T3a of the driving transistor T3 is a first semiconductor material, and the material of the active layer T1a of the first reset transistor T1 is a second semiconductor material. The electrode ET on which the active layer T1a of the first reset transistor T1 is located further includes a conductive portion. The conductive portion and the active layer T1a of the first reset transistor T1 form an integrated structure. The conductive portion includes the first electrode T1s of the first reset transistor T1. For example, the first electrode T1s of the first reset transistor T1 is adjacent to the active layer T1a of the first reset transistor T1 and forms an integrated structure. Furthermore, the conductive portion contacts the gate T3g of the driving transistor T3, thereby electrically connecting the first electrode T1s of the first reset transistor T1 to the active layer T1a of the first reset transistor T1 and to the gate T3g of the driving transistor T3. For example, the conductive portion is made of a material obtained by conductively converting the second semiconductor material.

[0069] Figure 4 is a partial cross-sectional schematic diagram of a pixel circuit (Figure 4 does not represent the prior art. Figure 4 is a design made by the inventor based on the structure of the pixel circuit of the display substrate provided in the embodiment of the present application, but the connection design of the control transistor and other transistors is different from that in the embodiment of the present application). The circuit diagram of the pixel circuit shown in FIG4 may be the same as that shown in FIG2 . However, in the pixel circuit shown in FIG4 , the first reset transistor T1 includes dual gates T10g1 and T10g2, an active layer T10a, a first electrode, and a second electrode. The active layer T10a of the first reset transistor T1 is electrically connected to the gate T30g of the drive transistor T3 via a first connection structure S1. The first connection structure S1 serves as the first electrode of the first reset transistor T1. The first connection structure S1, the active layer T10a of the first reset transistor T1, and the gate T30g of the drive transistor T3 are all located on different layers. For example, the first connection structure S1 is located on a side of the active layer T10a of the first reset transistor T1 and the gate T30g of the drive transistor T3 that is away from the substrate 010. The first connection structure S1 is electrically connected to the active layer T10a of the first reset transistor T1 and the gate T30g of the drive transistor T3 via two types of vias. For example, the first connection structure S1 is often located on the same layer as a data line that provides a data signal. In Figure 4 , the first connection structure S1 also electrically connects the gate T30g of the drive transistor T3 and the active layer T20a of the compensation transistor T2 via vias, and serves as the first electrode of the compensation transistor T2. The compensation transistor T2 includes dual gates T20g1 and T20g2. In Figure 4 , the second electrode of the first reset transistor T1 is electrically connected to the active layer T10a of the first reset transistor T1 and the first reset signal line LVinitial0 via the second connection structure S2 and two types of vias, respectively. The second connection structure S2 is arranged in the same layer or in a different layer as the first connection structure S1. However, an insulating layer is provided between the second connection structure S2 and the first connection structure S1 and the active layer T10a of the first reset transistor T1, an insulating layer is provided between the second connection structure S2 and the first reset signal line LVinitial0, and an insulating layer is provided between the second connection structure S2 and the active layer T20a of the compensation transistor T2. The second connection structure S2 is an additional conductive structure provided outside the layers where the active layer T10a of the first reset transistor T1, the first reset signal line LVinitial0, and the active layer T20a of the compensation transistor T2 are respectively located, so as to achieve electrical connection between the above three or electrical connection between the above three and other structures through these conductive structures.

[0070] In the display substrate provided in the embodiment of the present disclosure, the electrode ET on the active layer T1a of the first reset transistor T1 having a conductive portion is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. Thus, compared to the structure of the pixel circuit shown in FIG4 , the display substrate provided in the embodiment of the present disclosure can achieve at least the following technical effects: Firstly, in the display substrate provided in the embodiment of the present disclosure, the electrode ET on the active layer T1a of the first reset transistor T1 is reused as a connecting electrode to achieve electrical connection between the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. This eliminates the need to provide a dedicated connecting electrode on other layers (e.g., the conductive layer SD1 on the side of the active layer T1a of the first reset transistor T1 that is away from the base substrate BS) to electrically connect the connecting electrode to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two vias, thereby greatly simplifying the structure of the pixel circuit. On the other hand, using the display substrate provided by the embodiment of the present disclosure, other signal lines, such as data lines providing data signals Vd or connecting electrodes for electrical connection between other elements of the pixel circuit, can be set in other layers (for example, the conductive layer SD1), without setting connecting electrodes to connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, thereby reducing the number of conductive structures set in the other layers and the number of connecting vias, thereby simplifying the process of making vias, which is conducive to reducing design difficulty and improving the yield of the display panel. At the same time, the density of the conductive structures set in the other layers (for example, the conductive layer SD1) is reduced, reducing the parasitic capacitance generated by the overly dense conductive structures, and improving the display quality.

[0071] For example, the first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material. For example, the transparent metal oxide semiconductor material includes indium gallium zinc oxide (IGZO). In this case, the display substrate 10 is an LTPO display substrate that integrates oxide transistors (Oxide TFT) and low-temperature polysilicon transistors (LTPS TFT), which has the advantage of low-frequency driving and can reduce the power consumption of the display product. Of course, the first semiconductor material and the second semiconductor material are not limited to the types listed above, and the embodiments of the present disclosure do not limit the specific types of the first semiconductor material and the second semiconductor material.

[0072] 2 and 3 , for example, the electrode ET where the active layer T1 a of the first reset transistor T1 is located includes the first electrode T1 s of the first reset transistor T1 and is electrically connected to the gate T3 g of the driving transistor T3 through the first via hole V1 .

[0073] 2 and 3 , the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the active layer T1a of the first reset transistor T1 and the first electrode T1s of the first reset transistor T1. The conductive portion of the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the first electrode T1s of the first reset transistor T1. For example, the material of the first electrode T1s of the first reset transistor T1 is a material obtained by conductively converting the second semiconductor material. The active layer T1a of the first reset transistor T1 and the first electrode T1s of the first reset transistor T1 are arranged on the same layer and form an integrated structure. That is, the material of the conductive portion of the electrode ET where the active layer T1a of the first reset transistor T1 is a material obtained by conductively converting the second semiconductor material. The first electrode T1s of the first reset transistor T1 belongs to the conductive portion of the electrode ET where the active layer T1a of the first reset transistor T1 is located, and the active layer T1a of the first reset transistor T1 is a non-conductive portion. For example, the gate T3g of the driving transistor T3 is arranged in a different layer from the electrode ET where the active layer T1a of the first reset transistor T1 is located, and the first electrode T1s of the first reset transistor T1 contacts the gate T3g of the driving transistor T3 through the first via hole V1 exposing the gate T3g of the driving transistor T3 to directly electrically connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. In this way, for example, the conductive portion of the electrode ET where the active layer T1a of the first reset transistor T1 is located can be electrically connected to the gate T3g of the driving transistor T3 only through the first via V1. The active layer T1a of the first reset transistor T1 and the active layer T1a of the first reset transistor T1 form an integrated structure, thereby achieving electrical connection between the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. There is no need to provide a separate connection structure in other layers to electrically connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two vias, as shown in FIG. 3 . This fully utilizes the electrode EL where the material of the active layer T1a of the first reset transistor T1 is located, simplifies the structure of the sub-pixel, reduces connection wiring, and thus increases light transmittance. In addition, the number of conductive structures provided in other layers is further reduced, which helps to reduce design difficulty, reduce the density of conductive structures provided in other layers, and reduce parasitic capacitance generated by overly dense conductive structures.

[0074] For example, referring to Figures 2 and 3 , the electrode ET where the active layer T1a of the first reset transistor T1 is located also includes the second electrode T1d of the first reset transistor T1. The material of the second electrode T1d of the first reset transistor T1 is also the material after the second semiconductor material has been converted into a conductor. The second electrode T1d of the first reset transistor T1 is also part of the conductive portion of the electrode ET where the active layer T1a of the first reset transistor T1 is located. The pixel circuit also includes a first reset signal line LVini1 that is disposed in a different layer from the second electrode T1d of the first reset transistor T1. The second electrode T1d of the first reset transistor T1 is in contact with the first reset signal line LVini1 via a second via V2 that exposes the first reset signal line LVini1, thereby directly electrically connecting to the first reset signal line LVini1. In this way, the second electrode T1d of the first reset transistor T1 (the material after the second semiconductor material has been converted into a conductor) can be electrically connected to the first reset signal line LVini1 simply through the second via V2. There is no need to provide additional connection junctions (such as the second connection structure S2 in FIG. 4 ) in other layers to be electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two vias, thereby fully utilizing the electrode EL where the material of the active layer T1a of the first reset transistor T1 is located, simplifying the structure of the sub-pixel, reducing the connection wiring, and thus increasing the transmittance; and further reducing the number of conductive structures provided in the other layers, reducing the number of connection vias, thereby simplifying the process of manufacturing the vias, which is conducive to reducing the design difficulty and improving the yield of the display panel. At the same time, the density of the conductive structures provided in the other layers is reduced, thereby reducing the parasitic capacitance generated by the overly dense conductive structures.

[0075] For example, referring to FIG3 , the active layer T3a of the driving transistor T3 and the active layer T1a of the first reset transistor T1 are arranged in different layers, and the gate T3g of the driving transistor T3 is located between the active layer T3a of the driving transistor T3 and the electrode ET where the active layer T1a of the first reset transistor T1 is located. That is, the gate T3g of the driving transistor T3 is located on a side of the active layer T3a of the driving transistor T3 that is close to the electrode ET where the active layer T1a of the first reset transistor T1 is located. This facilitates contact between the gate T3g of the driving transistor T3 and the conductive portion of the electrode ET where the active layer T1a of the first reset transistor T1 is located during the manufacturing process of the display substrate, while not affecting the function of the driving transistor T3.

[0076] For example, referring to FIG3 , a display substrate includes a base substrate BS, with a driving transistor T3 disposed on a major surface of the base substrate BS. The active layer T3a of the driving transistor T3 is located on a side of the active layer T1a of the first reset transistor T1 that is closer to the base substrate BS. That is, the active layer of the oxide TFT is located above, and the low-temperature polysilicon TFT (LTPS TFT) is located below. Here, the "lower" direction is closer to the base substrate BS than the "upper" direction. Therefore, during the display substrate manufacturing process, the active layer of the low-temperature polysilicon TFT (LTPS TFT) is formed first, followed by the active layer of the oxide TFT. This prevents the performance of the oxide TFT from being affected by the process of forming the active layer of the low-temperature polysilicon TFT (e.g., IGZO) after forming the active layer of the oxide TFT.

[0077] For example, referring to Figures 2 and 4 , the pixel circuit further includes a compensation transistor T2, which is configured to compensate for a signal applied to the gate T3g of the drive transistor T3 in response to a compensation scan signal and a data signal Vd. For example, the control transistor further includes the compensation transistor T2, and the electrode ET on which the active layer T2a of the compensation transistor T2 resides is also directly electrically connected to the gate T3g of the drive transistor T3 and the first electrode T2s of the compensation transistor T2. The electrode ET on which the active layer T2a of the compensation transistor T2 resides is an integrated structure and includes the active layer T2a of the compensation transistor T2 and other parts. The active layer T2a of the compensation transistor T2 and other parts constitute the integrated electrode ET. In this case, the material of the active layer T3a of the drive transistor T3 is a first semiconductor material, and the material of the active layer T2a of the compensation transistor T2 is a second semiconductor material. For example, the electrode ET on which the active layer T2a of the compensation transistor T2 is located further includes a conductive portion. This conductive portion forms an integrated structure with the active layer T2a of the compensation transistor T2. The conductive portion is in contact with the first electrode T2s of the compensation transistor T2 and the gate T3g of the driving transistor T3, respectively, to achieve electrical connection with both. For example, the conductive portion is made of a material obtained by conductively converting the second semiconductor material. In this way, the electrode ET on which the active layer T2a of the compensation transistor T2 is located, which includes the conductive portion, is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. On the one hand, the electrode ET on which the active layer T1a of the first reset transistor T1 is located can be reused as a connecting electrode to achieve electrical connection between the gate T3g of the driving transistor T3 and the first electrode T2s of the compensation transistor T2, eliminating the need for additional dedicated connecting electrodes on other layers (e.g., on the conductive layer on the side of the active layer T2a of the compensation transistor T2 away from the substrate BS) to connect to the gate T3g of the driving transistor T3 through at least two vias. 3 is electrically connected to the first electrode T2s of the compensation transistor T2, thereby simplifying the structure of the pixel circuit; on the other hand, other signal lines, such as a data line for providing a data signal Vd or a connection electrode for electrical connection between other elements of the pixel circuit, can be provided in other layers, without the need to additionally provide a connection electrode to connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, thereby reducing the number of conductive structures provided in the other layers, which is conducive to reducing design difficulty, reducing the density of the conductive structures provided in the other layers, reducing parasitic capacitance generated by overly dense conductive structures, and improving display quality.

[0078] For example, referring to FIG3 , the electrode ET where the active layer T2a of the compensation transistor T2 is located includes the active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2. The materials of the active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2 are both materials obtained by conductively converting the second semiconductor material, and both belong to the conductive portion of the electrode ET where the active layer T2a of the compensation transistor T2 is located. The active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2 are arranged on the same layer and constitute an integrated structure. The gate T3g of the driving transistor T3 is arranged on a different layer from the electrode where the active layer T2a of the compensation transistor T2 is located. The first electrode T2s of the compensation transistor T2 contacts the gate T3g of the driving transistor T3 through a third via V3 that exposes the gate T3g of the driving transistor T3, so as to directly electrically connect the gate T3g of the driving transistor T3 and the first electrode T2s of the compensation transistor T2.

[0079] For example, in the embodiment shown in FIG3 , the electrode ET on which the active layer T2a of the compensation transistor T2 is located is co-located with the electrode ET on which the active layer T1a of the first reset transistor T1 is located, forming an integrated structure. Specifically, the electrode ET on which the active layer T2a of the compensation transistor T2 is located is the same electrode as the electrode ET on which the active layer T1a of the first reset transistor T1 is located. The first electrode T1s of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 are integrally connected, and the first via V1 and the third via V3 are the same via. The electrode ET on which the active layer T2a of the compensation transistor T2 is located also includes the first electrode T2s of the compensation transistor T2. The material of the active layer T2a of the compensation transistor T2 is the second semiconductor material, and the material of the first electrode T2s of the compensation transistor T2 is the second semiconductor material that has been converted into a conductor. The first electrode T1s of the first reset transistor T1, the first electrode T2s of the compensation transistor T2, and the active layer T2a of the compensation transistor T2 are sequentially connected, co-located, and form an integrated structure.

[0080] For example, as shown in Figure 3, the first electrode T1s of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 are adjacent to each other and are integrally formed to form a conductive connection portion CS, that is, the conductorized portion of the electrode ET where the active layer of the control transistor is located includes the conductive connection portion CS, and the conductive connection portion CS is electrically connected to the gate T3g of the driving transistor T3 through the third via V3.

[0081] In the embodiment shown in FIG3 , the same electrode ET including the active layer of the control transistor and the conductive portion is used to electrically connect the gate T3g of the drive transistor T3 to the first electrode T1s of the first reset transistor T1, to electrically connect the gate T3g of the drive transistor T3 to the first electrode T2s of the compensation transistor T2, and to electrically connect the second electrode T1d of the first reset transistor T1 to the first reset signal line LVini1. This fully utilizes the active layer including the control transistor, greatly reduces the number and density of conductive structures provided in other layers (e.g., the conductive layer on the side of the active layer T1a of the first reset transistor T1 that is away from or close to the base substrate BS) for connecting various transistors, capacitors, and other components of the sub-pixels, thereby greatly reducing the design difficulty and the parasitic capacitance caused by the excessive density of conductive structures in these other layers, thereby improving the display quality of the display substrate.

[0082] Of course, in other embodiments, the gate T3g of the driving transistor T3 may be electrically connected to the first electrode T1s of the first reset transistor T1, but not to the first electrode T2s of the compensation transistor T2; or the gate T3g of the driving transistor T3 may be electrically connected to the first electrode T2s of the compensation transistor T2, but not to the first electrode T1s of the first reset transistor T1. The above-mentioned methods can achieve the above-mentioned technical effects of the display substrate provided by the present application to varying degrees, and solve the corresponding technical problems.

[0083] 2 , the pixel circuit further includes a first light emission control transistor T6 configured to enable a driving current to be applied to the light emitting device EL under the control of a first light emission control signal EM1 . 3 , the material of the active layer T6a of the first emission control transistor T6 is the first semiconductor material (silicon semiconductor material) described above, and the active layer T6a of the first emission control transistor T6 is disposed in a different layer from the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the compensation transistor T2). The electrode where the active layer T2a of the compensation transistor T2 is located further includes a connecting portion C1. The material of the connecting portion C1 is a conductive material of the second semiconductor material. The connecting portion C1 is disposed in the same layer as the active layer T2a of the compensation transistor T2 to form an integrated structure. The connecting portion C1 contacts the active layer T6a of the first emission control transistor T6 through a fourth via V4 that exposes the active layer T6a of the first emission control transistor T6 to be electrically connected to the active layer T6a of the first emission control transistor T6. Thus, the connecting portion C1 serves as the first electrode T6s of the first emission control transistor T6 and the second electrode T2d of the compensation transistor T2.

[0084] For example, referring to Figure 3, the active layer T6a of the first light-emitting control transistor T6 and the active layer T3a of the driving transistor T3 are arranged on the same layer, and / or the gate T3g of the driving transistor T3 and the gate T6g of the first light-emitting control transistor T6 are arranged on the same layer, so that the active layer T6a of the first light-emitting control transistor T6 and the active layer T3a of the driving transistor T3 are formed by performing the same patterning process on the same semiconductor layer (the material is the first semiconductor material), and the gate T3g of the driving transistor T3 and the gate T6g of the first light-emitting control transistor T6 are formed by performing the same patterning process on the same conductive layer.

[0085] For example, referring to Figure 3, the material of the active layer T6a of the first light-emitting control transistor T6 is the above-mentioned first semiconductor material, and the active layer T6a of the first light-emitting control transistor T6 is arranged in a different layer from the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the compensation transistor T2); the electrode ET where the active layer of the control transistor is located is arranged in a different layer from the second electrode T6d of the first light-emitting control transistor T6, and the electrode where the active layer of the control transistor is located contacts the active layer T6a of the first light-emitting control transistor T6 through a fourth via hole V4 that exposes the active layer T6a of the first light-emitting control transistor T6, and the second electrode T6d of the first light-emitting control transistor T6 contacts the active layer T6a of the first light-emitting control transistor T6 through a fifth via hole V5 that exposes the active layer T6a of the first light-emitting control transistor T6. For example, the second electrode T6d of the first light-emitting control transistor T6 is located in the conductive layer SD1. This reduces the wiring of the conductive layer SD1, avoids the situation where the conductive layer SD1 is wound to avoid the structure on the same layer, reduces the design difficulty of the conductive layer SD1, and avoids parasitic capacitance.

[0086] For example, referring to FIG3 , the second electrode T6d of the first light-emitting control transistor T6 is located on a side of the electrode ET where the active layer of the control transistor is located that is away from the substrate BS, that is, the conductive layer SD1 is located on a side of the electrode ET where the active layer of the control transistor is located that is away from the substrate BS, so as to avoid the second electrode T6d of the first light-emitting control transistor T6 being located between the electrode ET where the active layer of the control transistor is located and the gate T6g of the first light-emitting control transistor T6, thereby avoiding interference with the arrangement of the electrode ET where the active layer of the control transistor is located and the gate T6g of the first light-emitting control transistor T6, reducing the difficulty of layout and the difficulty of the manufacturing process. While optimizing the above-mentioned performance of the pixel circuit, reducing the difficulty of the manufacturing process is very important for ensuring the yield of the product.

[0087] For example, the data line providing the aforementioned data signal Vd is also located in the conductive layer SD1, that is, arranged in the same layer as the second electrode T6d of the first light-emitting control transistor T6. In the disclosed embodiment, the conductive layer SD1 does not contain at least a connecting electrode for electrically connecting the active layer of the first reset transistor T1 and the gate of the driving transistor T3, a connecting electrode for electrically connecting the active layer of the first reset transistor T1 and the gate of the driving transistor T3, and a connecting electrode for electrically connecting the active layer of the first reset transistor and the first reset signal line. This significantly reduces the number of wires or conductive structures in the conductive layer SD1, lowers the density of the wires or conductive structures arranged in the conductive layer SD1, reduces parasitic capacitance generated by overly dense conductive structures, and improves display quality.

[0088] For example, in the embodiment shown in FIG3 , the first reset signal line LVini1 is disposed in a different layer from the second electrode T6d of the first emission control transistor T6 . This prevents the first reset signal line LVini1 from being located in the conductive layer SD1 and requiring the first reset signal line LVini1 to avoid other conductive structures and have a winding design, that is, to bypass other structures to avoid intersecting with other conductive structures. For example, FIG5 is a schematic planar structure diagram of a current pixel circuit. Referring to FIG5 , the circuit diagram of the pixel circuit can be, for example, the equivalent circuit shown in FIG2 . The rectangular dashed box in FIG5 is a schematic planar structure diagram of a pixel circuit of a sub-pixel unit. Referring to FIG5 , the first scan line LGa1 provides the first scan signal Ga1 (data scan signal) in FIG2 , the second scan line LGa2 provides the second scan signal (compensation scan signal) Ga2 in FIG2 , the emission control scan line LEM provides the first emission control signal EM1 and the second emission control signal EM2 in FIG2 , the first reset scan line LRst1 provides the first reset scan signal Rst1 in FIG2 , and the second reset scan line LRst2 provides the second reset scan signal Rst2 in FIG2 . The first reset signal line LV1 is provided on the same layer as the first connection electrode S1 (also referred to as the first connection electrode S1 in FIG. 4 ) that implements the first node N1 in FIG. To avoid the first connection electrode S1, the first reset signal line LV1 includes a winding design, namely, it meanders upward and then extends rightward, including a winding portion R. The above-described solution shown in FIG. 5 , on the one hand, increases parasitic capacitance between the conductive layer SD1 and other conductive layers. On the other hand, due to wiring difficulties, the first reset signal line LV1 is forced to pass directly above the channel region of the first reset transistor T1 (near the position indicated by T1 in FIG. 5 ), which affects the switching characteristics of the first reset transistor T1. However, in the display substrate provided in the embodiment of the present application, since the electrode ET (the conductive portion of the electrode ET) where the active layer of the control transistor is located is directly electrically connected to the gate T3g of the drive transistor T3 and the first electrode of the control transistor, there is no need to provide an additional gate T3g in the conductive layer SD1 specifically for electrically connecting to the gate of the drive transistor T3. The conductive portion of the electrode ET where the active layer of the control transistor is located is connected to the conductive portion, thereby reducing the number and density of the conductive structures in the conductive layer SD1, and improving the technical problem that the density of the conductive structures in the conductive layer SD1 is too high, resulting in winding and thus excessive parasitic capacitance and affecting the switching characteristics of the first reset transistor T1; further, since the first reset signal line LVini1 and the second electrode T6d of the first light-emitting control transistor T6 are arranged in different layers, the above-mentioned technical problem can be further improved.

[0089] For example, referring to FIG3 , the first reset signal line LVini1 and the gate T3g of the driving transistor T3 are both located between the active layer T3a of the driving transistor T3 and the electrode ET where the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the active layer T2a of the compensation transistor T2) is located. For example, referring to FIG3 , the first reset signal line LVini1 and the gate T3g of the driving transistor T3 are disposed in different layers to avoid excessive density of conductive structures in the conductive layer where the first reset signal line LVini1 and the gate T3g of the driving transistor T3 are located. This is particularly true for high-PPI display substrates, where the space for each sub-pixel is more limited. This allows the structure of the pixel circuit to meet the requirements of display substrates with higher PPI. For example, the gate T3g of the driving transistor T3 is located in the first conductive layer Gate1, the first reset signal line LVini1 is located in the second conductive layer Gate2, and the second conductive layer Gate2 is located on the side of the first conductive layer Gate1 away from the substrate BS. In this way, in the direction perpendicular to the main surface of the substrate BS, the second conductive layer Gate2 is closer to the electrode ET where the active layer T1a of the first reset transistor T1 is located, so that the active layer T1a of the first reset transistor T1 is in contact with the first reset signal line LVini1 located in the second conductive layer Gate2 through the second via V2 to be electrically connected.

[0090] Alternatively, in other embodiments, the first reset signal line LVini1 and the gate T3g of the driving transistor T3 may also be provided on the same layer.

[0091] For example, in the embodiment shown in FIG3 , the control transistor is a dual-gate transistor, for example, the first reset transistor T1 and the compensation transistor T2 are both dual-gate transistors, the first reset transistor T1 includes a first gate T1g1 and a second gate T1g2, and the compensation transistor T2 includes a first gate T2g1 and a second gate T2g2. Of course, at least one of the first reset transistor T1 and the compensation transistor T2 is a dual-gate transistor, and the first gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the first gate T2g1 of the compensation transistor T2) is located on a side of the active layer of the control transistor away from the active layer T3a of the driving transistor T3, for example, located on the third conductive layer Gate3; the second gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2) is located between the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the active layer T2a of the compensation transistor T2) and the active layer T3a of the driving transistor T3, and the second gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2) is arranged on the same layer as the first reset signal line LVini1, for example, both are located on the second conductive layer Gate2.

[0092] Alternatively, in other embodiments, the second gate of the control transistor and the first reset signal line LVini1 may be provided in different layers.

[0093] For example, referring to FIG3 , the second gate T1g2 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2 are laterally aligned with the gate T3g of the drive transistor T3 and are laterally parallel to the main surface of the substrate BS. That is, the second gate of the control transistor and the gate T3g of the drive transistor T3 are laterally aligned. If the control transistor is a dual-gate transistor, the lateral width of the second gate of the control transistor is greater than the lateral width of the first gate of the control transistor. For example, the lateral width of the second gate T1g2 of the first reset transistor T1 is greater than the lateral width of the first gate T1g1 of the first reset transistor T1, and the lateral width of the second gate T2g2 of the compensation transistor T2 is greater than the lateral width of the first gate T2g1 of the compensation transistor T2.

[0094] For example, referring to FIG. 3 , the first reset signal line LVini1 and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the base substrate BS to prevent parasitic capacitance caused by the overlap of the two in a direction perpendicular to the main surface of the base substrate BS.

[0095] For example, referring to FIG3 , the display substrate further includes a first flexible layer PI1, a second flexible layer PI2, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a bottom shield electrode BSM, a third barrier layer Barrier2-2, a first buffer layer Buffer1, a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second buffer layer Buffer2, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2, all disposed on a base substrate BS. Each insulating layer directly insulates each conductive layer, and each buffer layer can isolate impurities from a film layer subsequently formed on the corresponding buffer layer. The material of the first flexible layer PI1 and the second flexible layer PI2 is, for example, polyimide (PI), so that the display substrate is a flexible substrate. The polyimide (PI) substrate contains movable fixed charges. When the gate voltage of the driving transistor T3 changes, the movable charges move up and down in response to the electric field generated by the gate voltage of the driving transistor T3, forming a built-in electric field that varies with the gate voltage of the driving transistor T3. This, in turn, affects the characteristics of the driving transistor T3 and the image quality of the display substrate. Applying a fixed voltage to the bottom shielding electrode BSM can shield the fixed charges in the polyimide (PI) from affecting the characteristics of the driving transistor T3, thereby improving display quality. For example, the bottom shielding electrode BSM is connected to the first voltage signal VDD.

[0096] Figure 6 is a partial cross-sectional diagram of a pixel circuit of another display substrate provided by an embodiment of the present disclosure. The technical solution of Figure 6 differs from the technical solution of Figure 3 described above in the following ways.

[0097] Referring to FIG. 6 , the electrode ET on which the active layer T2a of the compensation transistor T2 is located also includes the second electrode T2d of the compensation transistor T2. The material of the second electrode T2d of the compensation transistor T2 is the conductive material of the aforementioned second semiconductor material. The second electrode T2d of the compensation transistor T2 is disposed on the same layer as the active layer T2a of the compensation transistor T2, forming an integrated structure. The pixel circuit includes a first connection structure CS1. The first connection structure CS1, the second electrode T2d of the compensation transistor T2, and the electrode ET on which the active layer of the control transistor is located are all disposed on different layers. For example, the first connection structure CS1 is disposed on the same layer as the second electrode T6d of the first emission control transistor T6, for example, both are located on the conductive layer SD1. The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 via a sixth via V6, and is electrically connected to the active layer T6a of the first emission control transistor T6 via a seventh via V7. In the embodiment shown in FIG6 , the gate electrode T3g of the driving transistor T3 and the first electrode of the control transistor are directly electrically connected via the electrode ET on which the active layer of the control transistor is located, which can greatly simplify the structure of the pixel circuit. This eliminates the need for additional connecting electrodes on other layers to connect the gate electrode T3g of the driving transistor T3 and the first electrode of the control transistor, thereby reducing the number of conductive structures provided on these other layers. Furthermore, in the embodiment shown in FIG6 , the first connecting structure CS1 contacts the second electrode T2d of the compensation transistor T2 and the active layer T6a of the first light-emitting control transistor T6 through the sixth via V6 and the seventh via V7, respectively, to electrically connect the two. The material of the first connecting structure CS1 can be a common conductive material, such as a metallic conductive material such as aluminum, copper, chromium, and alloys thereof. This can also avoid the problem of high contact resistance caused by direct electrical contact between the conductive portion of the electrode ET composed of conductive IGZO and P-Si, thereby improving display uniformity and enhancing display quality in the pixel array of the display substrate.

[0098] Referring to FIG6 , for example, a sixth via V6 extends through the second electrode T2d of the compensation transistor T2 in a direction perpendicular to the main surface of the substrate BS. A first connection structure CS1 includes an intra-hole portion PIV located within the sixth via V6. A side surface of the intra-hole portion PIV contacts the second electrode T2d of the compensation transistor T2, thereby electrically connecting the via to the second electrode T2d of the compensation transistor T2. The side surface of the intra-hole portion PIV intersects the main surface of the substrate BS, i.e., the surface of the intra-hole portion PIV that contacts the wall of the via extending through the second electrode T2d of the compensation transistor T2. FIG6 utilizes a side-lap joint to electrically connect the first connection structure CS1 to the second electrode T2d of the compensation transistor T2.

[0099] Other features and corresponding technical effects of the embodiment shown in FIG6 are the same as those in FIG3 , and reference may be made to the previous description.

[0100] FIG7 is a partial cross-sectional diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure. The technical solution of FIG7 differs from the technical solution of FIG6 described above in the following ways.

[0101] Referring to FIG. 7 , the sixth via hole V6 exposes the upper surface of the second electrode T2d of the compensation transistor T2. The upper surface of the second electrode T2d of the compensation transistor T2 is spaced from the main surface of the substrate BS. The first connection structure CS1 includes an inner portion PIV located within the sixth via hole V6. The bottom surface of the inner portion PIV (the surface facing the substrate BS) contacts the upper surface of the second electrode T2d of the compensation transistor T2, thereby electrically connecting the first connection structure CS1 to the second electrode T2d of the compensation transistor T2. FIG. 7 uses a bottom-stack method to electrically connect the first connection structure CS1 to the second electrode T2d of the compensation transistor T2.

[0102] On the basis of the technical effects achieved by the embodiment of FIG3 , the display substrate shown in FIG7 can also avoid the problem of high contact resistance caused by direct electrical connection between the conductive portion of the electrode ET composed of the conductive IGZO and the P-Si, thereby improving the display uniformity of the pixel array of the display substrate and enhancing the display effect.

[0103] Other features and corresponding technical effects of the embodiment shown in FIG7 are the same as those in FIG6 or FIG3 , and reference may be made to the previous description.

[0104] FIG8 is a partial cross-sectional view of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure. The technical solution of FIG8 differs from the technical solution of FIG6 described above in the following ways.

[0105] 8 , the material of the active layer T6a of the first light-emitting control transistor T6 is a first semiconductor material, and the active layer T6a of the first light-emitting control transistor T6 is arranged in a different layer from the active layer of the control transistor; the electrode ET where the active layer T2a of the compensation transistor T2 is located also includes the second electrode T2d of the compensation transistor T2, and the material of the second electrode T2d of the compensation transistor T2 is a material after the second semiconductor material is conductively converted, that is, the conductive portion of the electrode ET includes the second electrode T2d of the compensation transistor T2; the second electrode T2d of the compensation transistor T2 and the active layer T2a of the compensation transistor T2 are arranged in the same layer and constitute an integrated structure; the pixel circuit includes a second connection structure CS2 and a third connection structure CS3, and the second electrode T2d of the compensation transistor T2, the second connection structure CS2, the third connection structure CS3 and the active layer T6a of the first light-emitting control transistor T6 are all arranged in different layers. The second electrode T2d of the compensation transistor T2 is electrically connected to the second connection structure CS2 via an eighth via V8. The third connection structure CS3 is electrically connected to the second connection structure CS2 via a ninth via V9. The third connection structure CS3 is electrically connected to the active layer T6a of the first emission control transistor T6 via a tenth via V10. Thus, the third connection structure CS3 functions as the first electrode T6s of the first emission control transistor T6. Building on the technical effects achieved by the embodiment of FIG3 , the display substrate shown in FIG8 also avoids the high contact resistance caused by direct electrical contact between the conductive portion of the conductive IGZO electrode ET and P-Si, thereby improving display uniformity and enhancing display quality in the pixel array of the display substrate.

[0106] 8 , the second connection structure CS2 is disposed on the same layer as the gate T6g of the first emission control transistor T6, both located on the first conductive layer Gate1; for example, the third connection structure CS3 is disposed on the same layer as the second electrode T6d of the first emission control transistor T6, ie, located on the conductive layer SD1.

[0107] Other features and corresponding technical effects of the embodiment shown in FIG8 are the same as those in FIG6 or FIG3 , and reference may be made to the previous description.

[0108] For example, in some embodiments of the present disclosure, the control transistor may be a single-gate transistor, with the gate of the control transistor located on a side of the active layer of the control transistor away from the active layer of the drive transistor. The control transistor may further include at least one of a first reset transistor T1 and a compensation transistor T2.

[0109] For example, FIG9 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. The technical solution of FIG9 differs from the technical solution of FIG3 described above in the following ways. Referring to FIG9 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor. FIG9 illustrates the case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors, the first reset transistor T1 having a gate T1g, and the compensation transistor T2 having a gate T2g. For example, the gate T1g of the first reset transistor T1 is located on a side of the active layer T1a of the first reset transistor T1 that is away from the substrate BS, and the gate T2g of the compensation transistor T2 is located on a side of the active layer T2a of the compensation transistor T2 that is away from the substrate BS. For example, the gates T1g of the first reset transistor T1 and T2g of the compensation transistor T2 are located on different layers from the first reset signal line Lvinil and the gate T3g of the drive transistor T3 to avoid excessive parasitic capacitance or increased manufacturing difficulty caused by excessive density of conductive structures on the same layer. This problem, particularly in high-resolution (high PPI) display substrates where the space per subpixel is more limited, can have a greater impact on display quality. For example, referring to FIG9 , the gates T1g and T2g are located on the third conductive layer Gate3; the first reset signal line Lvinil is located on the second conductive layer Gate2; and the gate T3g of the drive transistor T3 is located on the first conductive layer Gate1. This is a preferred method considering the convenience of manufacturing and preventing the density of conductive structures in the same layer from being too high. However, the conductive layer where the gates T1g, T2g, and T3g are located is not limited to this method.

[0110] For example, at least one embodiment of the present application provides a method for fabricating a pixel circuit, including: forming a first-type via hole, wherein the first-type via hole exposes at least an active layer composed of a first semiconductor material (e.g., P-Si), and forming a first conductive structure to electrically connect to the surface of the active layer exposed by the first-type via hole through the first-type via hole. After forming the first-type via hole, a high-temperature annealing process is required on the display substrate to improve the characteristics of the LTPS TFT device. For example, the method for fabricating the pixel circuit includes: performing a contact resistance reduction treatment on the surface of the active layer composed of the first semiconductor material exposed by the first-type via hole to reduce the contact resistance of the exposed surface, for example, by achieving ohmic contact between the surface and the conductive structure contacted by the first-type via hole. For example, the surface of the active layer composed of the first semiconductor material exposed by the first-type via hole can be etched to remove an oxide layer on the exposed surface, thereby reducing the contact resistance of the exposed surface. For example, the first-type via hole includes a fifth via hole V5 that exposes the active layer T6a of the first light-emitting control transistor T6.

[0111] For example, the manufacturing method of the pixel circuit provided in an embodiment of the present application further includes: forming a second conductive structure, wherein the second conductive structure is an electrode on which the active layer of the control transistor is located, the second conductive structure includes the active layer of the control transistor and a conductive portion forming an integrated structure with the active layer of the control transistor, the active layer of the control transistor being composed of a second semiconductor material (e.g., IGZO), and the conductive portion is a material obtained by conductively converting the second semiconductor material; and forming a second-type via, wherein the conductive portion of the second conductive structure contacts and electrically connects to a structure exposed by the second-type via through the second-type via, for example, the conductive portion of the second conductive structure directly electrically connects the gate of the drive transistor to the first electrode of the control transistor through the second-type via. For example, the contact resistance reduction process can be performed after forming the second-type via and before forming the second conductive structure, so that the contact resistance reduction process does not affect the performance of the control transistor, maintaining the stability of the control transistor characteristics. Therefore, the control transistor can achieve ideal performance using a single gate, thereby simplifying the structure.

[0112] Referring to FIG9 , compared to the structure shown in FIG3 , for the first reset transistor T1, the first gate T1g1, which has a shorter lateral length, is retained, while the second gate T1g2, which has a longer lateral length, is removed. Similarly, for the compensation transistor T2, the first gate T2g1, which has a shorter lateral length, is retained, while the second gate T2g2, which has a longer lateral length, is removed. This reduces the lateral length of the gates of the control transistors (the first reset transistor T1 and / or the compensation transistor T2). For example, in the embodiment shown in FIG9 where the control transistors employ a single-gate structure, the lateral length of the first gate T1g1 of the first reset transistor T1 and / or the first gate T2g1 of the compensation transistor T2 is shorter than the lateral length of the gates of other transistors in the pixel circuit, such as the lateral length of the gate of the drive transistor T3, the lateral length of the gate of the first light-emitting control transistor T6, or the lateral length of the gate of the data transistor T4. Since the gate material is typically an opaque conductive material, such as a metal, the aforementioned length of the gate of the single-gate control transistor is reduced, thereby increasing the aperture ratio of the display substrate. Furthermore, for the corresponding control transistor, taking the first reset transistor T1 as an example, the length of the channel region of the first reset transistor T1 in the direction from the first electrode T1s of the first reset transistor T1 to the second electrode T1d of the first reset transistor T1 is L, i.e., the length in the horizontal direction in FIG9 is L, and the width of the channel region in the direction perpendicular to the horizontal direction is W. Therefore, when W remains unchanged and L decreases, the width-to-length ratio W / L of the first reset transistor T1 increases, i.e., the width-to-length ratio of the first reset transistor T1 is increased, which helps reduce the heat generation of the first reset transistor T1 and improve the lifespan of the first reset transistor T1. Similarly, the same is true for the compensation transistor T2 with a single gate having a shorter length.

[0113] Other features and corresponding technical effects of the embodiment shown in FIG9 are the same as those in FIG3 , and reference may be made to the previous description.

[0114] FIG10 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. The technical solution of FIG10 differs from the technical solution of FIG6 described above in the following ways. Referring to FIG10 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor. FIG10 illustrates a case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors, with the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g.

[0115] Other features and corresponding technical effects of the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g shown in FIG10 are the same as those in FIG9 , and reference may be made to the description of FIG9 , which will not be repeated here.

[0116] Other unmentioned features and corresponding technical effects of the embodiment shown in FIG10 are the same as those in FIG6 , and reference may be made to the previous description.

[0117] FIG11 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. The technical solution of FIG11 differs from the technical solution of FIG7 described above in the following ways. Referring to FIG11 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor. FIG11 illustrates a case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors, with the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g.

[0118] Other features and corresponding technical effects of the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g shown in FIG11 are the same as those in FIG9 , and reference may be made to the description of FIG9 , which will not be repeated here.

[0119] Other unmentioned features and corresponding technical effects of the embodiment shown in FIG11 are the same as those in FIG7 , and reference may be made to the previous description.

[0120] FIG12 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. The technical solution of FIG12 differs from the technical solution of FIG8 described above in the following ways. Referring to FIG12 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor. FIG12 illustrates a case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors, with the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g.

[0121] Other features and corresponding technical effects of the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g shown in FIG12 are the same as those in FIG9 , and reference may be made to the description of FIG9 , which will not be repeated here.

[0122] Other unmentioned features and corresponding technical effects of the embodiment shown in FIG12 are the same as those in FIG8 , and reference may be made to the previous description.

[0123] FIG13 is a schematic diagram of a display device provided in accordance with an embodiment of the present disclosure. Referring to FIG13 , at least one embodiment of the present disclosure further provides a display device 100, comprising any one of the display substrates 10 provided in accordance with the present disclosure. The display device may be, for example, a display panel, or any product or component with a display function, such as a monitor, an OLED panel, an OLED TV, electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, or a navigation system. Of course, the display devices provided in accordance with the present disclosure are not limited to the types listed above.

[0124] Accordingly, the display panel and display device provided by the embodiments of the present disclosure both have the technical effects of the pixel circuit and display substrate provided by the embodiments of the present disclosure.

[0125] At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, which includes: forming sub-pixels, including forming pixel circuits, wherein the forming of the pixel circuits includes forming a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the forming of the pixel circuits also includes: forming a control transistor, wherein the first electrode of the control transistor is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

[0126] For example, a method for manufacturing a display substrate includes: forming a second semiconductor layer using the second semiconductor material through a single patterning process; conducting a portion of the second semiconductor layer to form a second conductive structure, wherein the second conductive structure serves as an electrode where the active layer of the control transistor is located, and includes a conducting portion and a non-conductorized portion, and the conducting portion and the non-conductorized portion constitute an integrated structure; the non-conductorized portion constitutes the active layer of the control transistor, the conducting portion directly electrically connects the gate of the driving transistor and the first electrode of the control transistor, and the material of the conducting portion is the material after the second semiconductor material is conducted; and forming a second type of via, wherein the conducting portion of the second conductive structure directly electrically connects the gate of the driving transistor and the first electrode of the control transistor through the second type of via.

[0127] The "direct electrical connection" here means that at least part of the conductive portion is in direct contact with the gate of the driving transistor and the first electrode of the control transistor to be electrically connected thereto, rather than the conductive portion needing to be indirectly connected to the gate of the driving transistor and the first electrode of the control transistor through other non-integrated conductive structures or even conductive structures arranged in different layers.

[0128] For example, the conductive portion of the electrode where the active layer of the control transistor is located includes the first electrode of the control transistor, and the first electrode of the control transistor and the active layer of the control transistor are arranged in the same layer to form an integrated structure.

[0129] In this way, in the manufacturing method of the display substrate provided in the embodiment of the present disclosure, the second semiconductor layer can be formed through a single patterning process, and the number of electrodes and vias used for switching is reduced, thereby simplifying the manufacturing process and design difficulty of the display substrate, greatly reducing the density of the conductive structure on the same layer, and reducing the wiring difficulty of the conductive structure or wire on the same layer, which plays an important role in improving the yield of the display substrate.

[0130] In a conventional method for manufacturing a display substrate, for example, in the manufacturing process of the display substrate shown in FIG4 , after forming the first type of via hole, taking the first type of via hole including the via hole V01 that exposes the surface of the active layer T60a composed of the first semiconductor material of the first light emission control transistor T6 as an example, the surface of the active layer T60a exposed by the via hole V01 is etched to remove the oxide film on its surface and reduce the contact resistance; then, a process of forming the via hole V02 on the surface of the active layer T10a / T20a composed of the second semiconductor material is performed, and then the first connection structure S1, the second connection structure S2 and the third connection structure S3 are formed to electrically connect the first reset transistor T1, the compensation transistor T2 and the first light emission control transistor T6 through the via hole V01 and the via hole V02. In this manufacturing method, a certain amount of time is required between the etching process on the surface of the active layer T60a exposed by the via V01 and the formation of the first connection structure S1, the second connection structure S2 and the third connection structure S3 (for example, usually formed by deposition or sputtering). During this interval, on the one hand, an oxide layer will form again on the surface of the active layer T60a exposed by the via V01, thereby affecting the ohmic contact between the active layer T60a and the third connection structure S3; on the other hand, the presence of foreign matter such as impurity particles at some vias V01 will affect the electrical connection between the active layer T60a and the third connection structure S3, thereby affecting the yield of the display substrate.

[0131] For example, at least one embodiment of the present application provides a method for fabricating a pixel circuit, including: forming a first-type via hole, wherein the first-type via hole exposes at least an active layer composed of a first semiconductor material (e.g., P-Si), and forming a first conductive structure to electrically connect, through the first-type via hole, the surface of the active layer composed of the first semiconductor material exposed by the first-type via hole. After forming the first-type via hole, to improve the characteristics of the LTPS TFT device, a high-temperature annealing process is required on the display substrate. For example, the method for fabricating the pixel circuit includes: performing a contact resistance reduction treatment on the surface of the active layer composed of the first semiconductor material exposed by the first-type via hole to reduce the contact resistance of the exposed surface, for example, by achieving ohmic contact between the surface and the conductive structure contacted by the first-type via hole. For example, the surface of the active layer composed of the first semiconductor material exposed by the first-type via hole can be etched to remove an oxide layer from the exposed surface, thereby reducing the contact resistance of the exposed surface. For example, the first-type via hole includes a fifth via hole V5 that exposes the active layer T6a of the first light-emitting control transistor T6.

[0132] For example, the manufacturing method of the pixel circuit provided in the embodiment of the present application also includes: forming a second type of via, and forming a second conductive structure in the second type of via; the electrode where the second conductive structure is located includes the active layer of the above-mentioned control transistor, and the active layer of the control transistor is composed of a second semiconductor material (for example, IGZO), and the electrode where the second conductive structure is located also includes a conductorized portion that forms an integrated structure with the active layer of the control transistor, and the conductorized portion is the material after the second semiconductor material is conductorized. For example, the portion of the second conductive structure located in the second type of via contacts the structure exposed by the second type of via through the second type of via to be electrically connected. For example, the above-mentioned process of reducing contact resistance can be performed after forming the second type of via and before forming the second conductive structure, so that the process of reducing contact resistance will not affect the performance of the control transistor. Therefore, the control transistor can achieve ideal performance by using a single gate, thereby simplifying the structure.

[0133] For example, FIG14A to FIG14D are schematic diagrams of a method for manufacturing a display substrate provided in an embodiment of the present disclosure. For example, FIG14A to FIG14D illustrate a method for manufacturing the display substrate shown in FIG3 .

[0134] Referring to FIG. 14A , a substrate BS is provided. A first flexible layer PI1, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a BSM, a third barrier layer Barrier2-2, a first buffer layer Buffer1, an active layer composed of a first semiconductor material, including but not limited to the active layer T3a of the driving transistor T3 and the active layer T6a of the first emission control transistor T6, a first gate insulating layer GI1, a first metal layer Gate1, a second gate insulating layer GI2, a second metal layer Gate2, a first interlayer insulating layer ILD1, and a second buffer layer Buffer2 are formed on the substrate BS. Then, a patterning process is performed to form the aforementioned second-type vias, which include a first via V1, a second via V2 (in this embodiment, the second via V2 is also the third via V3), and a fourth via V4. For example, within a single pixel circuit, these three second-type vias are formed. Of course, the number of second-type vias is not limited to this.

[0135] Next, referring to FIG. 14B , a second semiconductor layer (not shown) is formed using the aforementioned second semiconductor material. For example, the second semiconductor layer is formed using a deposition method, and a patterning process is performed on the second semiconductor layer to form a connection electrode pattern. A portion of the connection electrode pattern is then conductively processed to form a second conductive structure. A portion of the second conductive structure is located within the first via V1, the second via V2, and the fourth via V4. The second conductive structure is the electrode ET where the active layer of the control transistor is located. The second conductive structure includes the active layer T1a of the first reset transistor T1, the active layer T2a of the compensation transistor T2, and a conductive portion that forms an integrated structure with the active layers T1a and T2a of the first reset transistor T1 and T2. Thus, the active layers T1a and T2a of the first reset transistor T1 and T2 are both made of the second semiconductor material (e.g., IGZO). The conductive portion is the material after the second semiconductor material has been conductively processed. For example, the conductive portion includes: For example, the portion of the second conductive structure located in the second-type via is electrically connected to the structure exposed by the second-type via through the second-type via. Thus, a second conductive structure is formed, which is the electrode ET where the active layer T1a of the first reset transistor T1 shown in FIG3 is located. For the specific connection relationship of the second conductive structure, please refer to the description of FIG3.

[0136] Then, as shown in FIG14C , a third gate insulating layer GI3 , a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are sequentially formed, and the first type vias are formed by a single patterning process. For example, the first type vias include the fifth via V5 .

[0137] Then, after forming the first-type via hole (e.g., the fifth via hole V5), a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first emission control transistor T6). Then, a contact resistance reduction process is performed on the surface of the active layer T6a composed of the first semiconductor material of the first emission control transistor T6 exposed by the fifth via hole V5 to reduce the contact resistance of the exposed surface so that the surface achieves ohmic contact with the second electrode T6d of the first emission control transistor T6, which is subsequently formed and contacts the surface through the fifth via hole V5. For example, the surface of the active layer T6a exposed by the fifth via hole V5 can be etched to remove the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5, thereby reducing the contact resistance of the exposed surface.

[0138] Then, as shown in FIG14D , a conductive layer SD1 is formed, for example, using a deposition method and a single patterning process. The conductive layer SD1 includes the second electrode T6d of the first emission control transistor T6. The second electrode T6d of the first emission control transistor T6 is electrically connected to the active layer T6a of the first emission control transistor T6 through a fifth via V5.

[0139] Thus, in the display substrate manufacturing method provided in at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth via V5, the conductive layer SD1 can be immediately formed, without the need for a second-type via formation process in between. This effectively improves the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1. Furthermore, it effectively prevents the formation of foreign matter such as impurities in the fifth via V5, thereby preventing the impurities from affecting the electrical connection between the active layer composed of the first semiconductor material and the conductive layer SD1, thereby improving the yield of the display substrate.

[0140] For example, in another method for manufacturing a display substrate shown in Figure 3, a high-temperature annealing process can be performed on the display substrate after forming the second type of via and before forming the second conductive structure (i.e., the electrode ET where the active layer of the above-mentioned control transistor is located) to prevent the high-temperature annealing process from affecting the performance of the second conductive structure composed of the second semiconductor material, thereby not affecting the performance of the control transistor.

[0141] 15A-15D are schematic diagrams of a method for manufacturing a display substrate provided in an embodiment of the present disclosure. For example, FIG. 15A-15D illustrate a method for manufacturing the display substrate shown in FIG. 6 .

[0142] Referring to Figure 15A, the difference from the step shown in Figure 14A is that the above-mentioned second type of vias are formed through a composition process. The second type of vias include the first via V1 and the second via V2 (the second via V2 in this embodiment is also the third via V3), and the fourth via V4 in Figure 14A is not formed.

[0143] Next, referring to FIG15B , a second semiconductor layer (not shown) is formed using the aforementioned second semiconductor material, for example, by deposition. A patterning process is then performed on the second semiconductor layer to form a connection electrode pattern. A portion of the connection electrode pattern is then conductively treated to form a second conductive structure. This second conductive structure is the electrode ET on which the active layer T1a of the first reset transistor T1 shown in FIG6 is located. The detailed structure and connection relationship of the second conductive structure are described in conjunction with FIG6 . Then, a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are formed in sequence, and the above-mentioned first-type vias are formed through a single patterning process. For example, the first-type vias include a fifth via V5 and a seventh via V7, and the fifth via V5 and the seventh via V7 expose the surface of the active layer T1a of the first reset transistor T1 composed of the first semiconductor material; here, the first-type vias also include a sixth via V6 that exposes the conductive portion of the second conductive structure (that is, the integrated electrode ET), and the sixth via V6 exposes the end of the electrode ET that is laterally close to the first light-emitting control transistor T6, and the end of the electrode ET that is laterally close to the first light-emitting control transistor T6 is reused as the second electrode T2d of the compensation transistor T2.

[0144] Next, referring to FIG15C , a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first emission control transistor T6). The surface of the active layer T6a of the first emission control transistor T6, which is made of the first semiconductor material and is exposed by the fifth and seventh vias V5 and V7, is then subjected to a contact resistance reduction process. For example, the surface of the active layer T6a exposed by the fifth and seventh vias V5 and V7 can be etched to remove the oxide layer on the surface of the active layer T6a exposed by the fifth and seventh vias V5 and V7, thereby reducing the contact resistance of the exposed surface. This etching process etches through the end of the electrode ET exposed by the sixth via V6 in FIG15B , which is laterally adjacent to the first emission control transistor T6. This etched end, in other words, pierces the second electrode T2d of the compensation transistor T2, thereby allowing the sixth via V6 to penetrate the second electrode T2d of the compensation transistor T2 in a direction perpendicular to the main surface of the base substrate BS.

[0145] Next, referring to FIG. 15D , a conductive layer SD1 is formed, for example, using a deposition method and a single patterning process. The conductive layer SD1 includes the second electrode T6d of the first emission control transistor T6 and a first connection structure CS1. The second electrode T6d of the first emission control transistor T6 is electrically connected to the active layer T6a of the first emission control transistor T6 via a fifth via V5. The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 via a sixth via V6, and is electrically connected to the active layer T6a of the first emission control transistor T6 via a seventh via V7.

[0146] Thus, the display substrate shown in Figure 6 is formed. Figure 6 uses a side-lap joint to electrically connect the first connection structure CS1 to the second electrode T2d of the compensation transistor T2. In the display substrate manufacturing method provided in at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth via V5 and the seventh via V7, the conductive layer SD1 can be immediately formed, without the need for a process to form the second-type vias in between. This effectively improves the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1, and effectively prevents the formation of foreign matter such as impurity particles in the fifth via V5.

[0147] 16A-16D are schematic diagrams of a method for manufacturing a display substrate provided in an embodiment of the present disclosure. For example, FIG. 16A-16D illustrate a method for manufacturing the display substrate shown in FIG. 7 .

[0148] Referring to FIG. 16A , the steps are the same as those shown in FIG. 15A .

[0149] Next, referring to FIG16B , a second semiconductor layer (not shown) is formed using the aforementioned second semiconductor material, for example, by deposition. A patterning process is then performed on the second semiconductor layer to form a connection electrode pattern. A portion of the connection electrode pattern is then conductively processed to form a second conductive structure. This second conductive structure is the electrode ET, shown in FIG6 , on which the active layer T1a of the first reset transistor T1 resides. The detailed structure and connection relationship of the second conductive structure are described in FIG6 . Next, a third gate insulating layer GI3, a third conductive layer Gate3, and a second interlayer insulating layer ILD2 are sequentially formed, and the aforementioned first-type vias are formed through a single patterning process. Unlike the steps shown in FIG15B , the first-type vias here do not include the sixth via V6 that exposes the conductive portion of the second conductive structure (i.e., the integrated electrode ET). Instead, the first-type vias include a fifth via V5 and a seventh via V7. The fifth and seventh vias V5 and V7 expose the surface of the active layer T1a of the first reset transistor T1, which is formed of the first semiconductor material.

[0150] Next, referring to FIG16C , a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first emission control transistor T6). The surface of the active layer T6a of the first emission control transistor T6, which is made of the first semiconductor material and is exposed by the fifth and seventh vias V5 and V7, is then subjected to a contact resistance reduction process. For example, the surface of the active layer T6a exposed by the fifth and seventh vias V5 and V7 can be etched to remove the oxide layer on the surface of the active layer T6a exposed by the fifth and seventh vias V5 and V7, thereby reducing the contact resistance of the exposed surface. After this etching process, a sixth via V6 is formed through a single patterning process. The sixth via V6 exposes the upper surface of the end of the electrode ET that is laterally adjacent to the first emission control transistor T6. The end of the electrode ET that is laterally adjacent to the first emission control transistor T6 serves as the second electrode T2d of the compensation transistor T2.

[0151] Next, referring to FIG. 16D , a conductive layer SD1 is formed, for example, using a deposition method and a single patterning process. The conductive layer SD1 includes a second electrode T6d of the first emission control transistor T6 and a first connection structure CS1. The second electrode T6d of the first emission control transistor T6 is electrically connected to the active layer T6a of the first emission control transistor T6 via a fifth via V5. The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 via a sixth via V6, and is electrically connected to the active layer T6a of the first emission control transistor T6 via a seventh via V7.

[0152] Thus, the display substrate shown in Figure 7 is formed. Figure 7 uses a bottom-stack method to electrically connect the first connection structure CS1 to the second electrode T2d of the compensation transistor T2. In the method for manufacturing a display substrate provided in at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth via V5 and the seventh via V7, the conductive layer SD1 can be immediately formed, without the need for a process to form the second-type vias in between. This effectively improves the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1, and effectively prevents the formation of foreign matter such as impurity particles in the fifth via V5 and the seventh via V7.

[0153] 17A-17D are schematic diagrams of a method for manufacturing a display substrate provided in an embodiment of the present disclosure. For example, FIG. 17A-17D illustrate a method for manufacturing the display substrate shown in FIG. 8 .

[0154] Referring to FIG17A , unlike the step shown in FIG15A , the first metal layer Gate1 further includes a second connection structure CS2. The second type of vias are formed through the same patterning process. Here, the second type of vias include a first via V1, a second via V2 (in this embodiment, the second via V2 is also the third via V3), and an eighth via V8 that exposes the second connection structure CS2.

[0155] Next, referring to FIG17B , a second semiconductor layer (not shown) is formed using the aforementioned second semiconductor material, for example, by deposition. A patterning process is then performed on the second semiconductor layer to form a connection electrode pattern. A portion of the connection electrode pattern is then conductively treated to form a second conductive structure. This second conductive structure is the electrode ET on which the active layer T1a of the first reset transistor T1 shown in FIG8 is located. The detailed structure and connection relationship of the second conductive structure are described in conjunction with FIG8 .

[0156] Then, referring to FIG17C , a third gate insulating layer GI3, a third conductive layer Gate3, and a second interlayer insulating layer ILD2 are sequentially formed, and the first-type vias described above are formed through a single patterning process. Unlike the steps shown in FIG15B , the first-type vias here do not include the sixth via V6 exposing the conductive portion of the second conductive structure (i.e., the integrated electrode ET). Instead, the first-type vias include the fifth and tenth vias V5 and V10, respectively exposing the source and drain regions of the active layer T6a of the first emission control transistor T6, and the ninth via V9 exposing the second connection structure CS2.

[0157] Next, a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first emission control transistor T6). Then, a contact resistance reduction process is performed on the surface of the active layer T6a of the first emission control transistor T6, which is made of the first semiconductor material and is exposed by the fifth and seventh via holes V5 and V7. For example, the surface of the active layer T6a exposed by the fifth and tenth via holes V5 and V10 can be etched to remove the oxide layer on the surface of the active layer T6a exposed by the fifth and seventh via holes V5 and V7, thereby reducing the contact resistance of the exposed surface.

[0158] Next, referring to FIG. 17D , a conductive layer SD1 is formed, for example, using a deposition method and a single patterning process. The conductive layer SD1 includes a first connection structure CS1, a second connection structure CS2, and a third connection structure CS3. The second electrode T6d of the first emission control transistor T6 is electrically connected to the active layer T6a of the first emission control transistor T6 via a fifth via V5. The second electrode T2d of the compensation transistor T2 is electrically connected to the second connection structure CS2 via an eighth via V8. The third connection structure CS3 is electrically connected to the second connection structure CS2 via a ninth via V9. The third connection structure CS3 is electrically connected to the active layer T6a of the first emission control transistor T6 via a tenth via V10. Thus, the third connection structure CS3 serves as the first electrode T6s of the first emission control transistor T6.

[0159] Thus, the display substrate shown in Figure 8 is formed. In the display substrate manufacturing method provided in at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth and tenth vias V5 and V10, the conductive layer SD1 can be immediately formed, without the need for a process to form the second-type vias in between. This effectively improves the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1, and effectively prevents the formation of foreign matter such as impurity particles in the fifth and tenth vias V5 and V10.

[0160] The display substrate manufacturing methods shown in Figures 9 to 12 are based on the display substrate manufacturing methods shown in Figures 3, 6, 7, and 8, respectively. During the patterning process for forming the second metal layer Gate2, the patterning pattern is modified to eliminate the second gate T1g2 of the first reset transistor T1 and the second gate T2g2 of the compensation transistor T2. All other method steps can refer to the display substrate manufacturing methods shown in Figures 3, 6, 7, and 8, respectively. This method also achieves the technical effects of the display substrate manufacturing methods shown in Figures 3, 6, 7, and 8, and the removal of the second gate simplifies the mask design and process.

[0161] There are a few points to note:

[0162] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0163] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0164] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the appended claims.

Claims

1. A display substrate, comprising sub-pixels, wherein: The sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; The pixel circuit further comprises a control transistor, wherein a first electrode of the control transistor is electrically connected to a gate electrode of the driving transistor; The material of the active layer of the driving transistor is a first semiconductor material, the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; The electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the drive transistor and the first electrode of the control transistor.

2. The display substrate according to claim 1, wherein: The active layer of the driving transistor and the active layer of the control transistor are arranged in different layers, and the gate of the driving transistor is located between the electrodes where the active layers of the driving transistor and the control transistor are located.

3. The display substrate according to claim 2, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The active layer of the driving transistor is located on a side of the active layer of the control transistor close to the base substrate.

4. The display substrate according to claim 1, wherein: The pixel circuit comprises a first reset transistor, wherein the first reset transistor is configured to write a first reset signal to a gate of the driving transistor under the control of a first reset control signal; The control transistor includes the first reset transistor, and an electrode where an active layer of the first reset transistor is located is directly electrically connected to a gate of the drive transistor and a first electrode of the first reset transistor.

5. The display substrate according to claim 4, wherein: The electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first electrode of the first reset transistor, the material of the first electrode of the first reset transistor is the material after the second semiconductor material is converted into a conductor, and the active layer of the first reset transistor and the first electrode of the first reset transistor are arranged in the same layer and form an integrated structure; The gate of the driving transistor is arranged in a different layer from the electrode where the active layer of the first reset transistor is located, and the first electrode of the first reset transistor contacts the gate of the driving transistor through a first via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the first reset transistor.

6. The display substrate according to claim 5, wherein: The electrode where the active layer of the first reset transistor is located also includes a second electrode of the first reset transistor, and a material of the second electrode of the first reset transistor is a material obtained by converting the second semiconductor material into a conductor; The pixel circuit also includes a first reset signal line disposed at a different layer from the second electrode of the first reset transistor, and the second electrode of the first reset transistor contacts the first reset signal line through a second via hole exposing the first reset signal line to be directly electrically connected to the first reset signal line.

7. The display substrate according to any one of claims 1 to 6, wherein: The pixel circuit further includes a compensation transistor configured to compensate a signal applied to a gate of the driving transistor in response to a compensation scan signal and the data signal; The control transistor also includes the compensation transistor, and the electrode where the active layer of the compensation transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the compensation transistor.

8. The display substrate according to claim 7, wherein: The electrode where the active layer of the compensation transistor is located also includes the first electrode of the compensation transistor, the materials of the active layer of the compensation transistor and the first electrode of the compensation transistor are both the materials after the second semiconductor material is converted into a conductor, and the active layer of the compensation transistor and the first electrode of the compensation transistor are arranged in the same layer and form an integrated structure; The gate of the driving transistor is arranged at a different layer from the electrode where the active layer of the compensation transistor is located, and the first electrode of the compensation transistor contacts the gate of the driving transistor through a third via hole that exposes the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the compensation transistor.

9. The display substrate according to claim 8, wherein: In the case where the control transistor includes a first reset transistor, the electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first electrode of the first reset transistor, the material of the first electrode of the first reset transistor is the material after the second semiconductor material is conductive, the active layer of the first reset transistor and the first electrode of the first reset transistor are arranged in the same layer and form an integrated structure, the gate of the driving transistor and the electrode where the active layer of the first reset transistor is located are arranged in different layers, and the first electrode of the first reset transistor contacts the gate of the driving transistor through a first via hole that exposes the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the first reset transistor, The electrode where the active layer of the compensation transistor is located is arranged in the same layer as the electrode where the active layer of the first reset transistor is located and forms an integrated structure, the first electrode of the first reset transistor and the first electrode of the compensation transistor are integrated, and the first via hole and the second via hole are the same via hole; The material of the active layer of the compensation transistor is the second semiconductor material, the material of the first electrode of the compensation transistor is the material after the second semiconductor material is conductive, the first electrode of the first reset transistor, the first electrode of the compensation transistor and the active layer of the compensation transistor are connected in sequence, arranged in the same layer and constitute an integrated structure.

10. The display substrate according to claim 7, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the compensation transistor is located further includes a connection portion, the material of the connection portion is the material after the second semiconductor material is converted into a conductor, and the connection portion is arranged in the same layer as the active layer of the compensation transistor to form an integrated structure; The connection portion contacts the active layer of the first emission control transistor through a fourth via hole exposing the active layer of the first emission control transistor to electrically connect the active layer of the first emission control transistor, and the connection portion serves as a first electrode of the first emission control transistor and a second electrode of the compensation transistor.

11. The display substrate according to claim 10, wherein: The active layer of the first light emitting control transistor and the active layer of the driving transistor are arranged in the same layer, and / or, The gate of the driving transistor is arranged in the same layer as the gate of the first light emitting control transistor.

12. The display substrate according to any one of claims 1 to 6, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the control transistor is located is arranged at a different layer from the second pole of the first light-emitting control transistor, the electrode where the active layer of the control transistor is located is in contact with the active layer of the first light-emitting control transistor through a fourth via hole exposing the active layer of the first light-emitting control transistor, and the second pole of the first light-emitting control transistor is in contact with the active layer of the first light-emitting control transistor through a fifth via hole exposing the active layer of the first light-emitting control transistor.

13. The display substrate according to claim 12, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The second electrode of the first light emitting control transistor is located on a side of the electrode where the active layer of the control transistor is located, away from the substrate.

14. The display substrate according to claim 12, wherein: In the case where the control transistor includes a first reset transistor, the electrode where the active layer of the first reset transistor is located also includes a second electrode of the first reset transistor, a material of the second electrode of the first reset transistor is a material obtained by converting the second semiconductor material into a conductor, the pixel circuit also includes a first reset signal line provided at a different layer from the second electrode of the first reset transistor, and the second electrode of the first reset transistor is electrically connected to the first reset signal line via a second via hole exposing the first reset signal line, The first reset signal line is arranged at a second polarization layer with respect to the first light emission control transistor.

15. The display substrate according to claim 14, wherein: The first reset signal line and the gate of the driving transistor are both located between the gate of the driving transistor and the electrode where the active layer of the control transistor is located; The first reset signal line and the gate of the driving transistor are arranged in a different layer or in the same layer.

16. The display substrate according to claim 15, wherein: The control transistor is a single-gate transistor, and the gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the drive transistor; or, The control transistor is a dual-gate transistor, wherein the first gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the drive transistor, and the second gate of the control transistor is located between the active layer of the control transistor and the active layer of the drive transistor. The second gate of the control transistor is arranged at the same layer or at a different layer as the first reset signal line.

17. The display substrate according to claim 15, wherein: The second gate of the control transistor and the gate of the driving transistor are arranged in a lateral direction; In the case where the control transistor is a dual-gate transistor, a line width of the second gate of the control transistor in the lateral direction is greater than a line width of the first gate of the control transistor in the lateral direction.

18. The display substrate according to claim 14, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The first reset signal line and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the base substrate.

19. The display substrate according to claim 7, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the compensation transistor is located also includes a second electrode of the compensation transistor, the material of the second electrode of the compensation transistor is the material after the second semiconductor material is converted into a conductor, and the second electrode of the compensation transistor is arranged in the same layer as the active layer of the compensation transistor to form an integrated structure; The pixel circuit comprises a first connection structure, wherein the first connection structure, the second electrode of the compensation transistor and the electrode where the active layer of the control transistor is located are all arranged in different layers from each other; The first connection structure is electrically connected to the second electrode of the compensation transistor through a sixth via hole, and is electrically connected to the active layer of the first light emission control transistor through a seventh via hole.

20. The display substrate according to claim 19, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The fifth via hole penetrates the second electrode of the compensation transistor, the first connection structure includes an inner hole portion located in the sixth via hole, a side surface of the inner hole portion contacts the second electrode of the compensation transistor, and a surface where the side surface of the inner hole portion is located is adjacent to a surface where the main surface of the substrate is located. intersect; or, The fifth via hole exposes the upper surface of the second electrode of the compensation transistor, and the upper surface of the second electrode of the compensation transistor is far away from the main surface of the substrate substrate. The first connection structure includes an inner hole portion located in the sixth via hole, and the bottom surface of the inner hole portion is in contact with the upper surface of the second electrode of the compensation transistor.

21. The display substrate according to claim 7, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the compensation transistor is located also includes a second electrode of the compensation transistor, the material of the second electrode of the compensation transistor is the material after the second semiconductor material is converted into a conductor, and the connecting portion is arranged at the same layer as the active layer of the compensation transistor to form an integrated structure; The pixel circuit further includes a second connection structure and a third connection structure, and the second electrode of the compensation transistor, the second connection structure, the third connection structure and the active layer of the first light emission control transistor are all arranged in different layers; The second electrode of the compensation transistor is electrically connected to the second connection structure through an eighth via hole, the third connection structure is electrically connected to the second connection structure through a ninth via hole, and the third connection structure is electrically connected to the active layer of the first light emission control transistor through a tenth via hole.

22. The display substrate according to any one of claims 1 to 6, wherein: The first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material.

23. The display substrate according to claim 22, wherein: The transparent metal oxide semiconductor material includes indium gallium zinc oxide (IGZO).

24. A display device, comprising the display substrate according to any one of claims 1-23.

25. A method for manufacturing a display substrate, comprising: Forming a sub-pixel, including forming a pixel circuit, wherein the forming the pixel circuit includes forming a light-emitting device and a driving transistor, wherein the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; The forming of the pixel circuit further comprises: forming a control transistor, wherein the control transistor The first electrode is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

26. The method for manufacturing a display substrate according to claim 25 comprises: forming a first type of via hole, wherein the first type of via hole at least exposes the active layer composed of the first semiconductor material; forming a first conductive structure to electrically connect to the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole through the first type of via hole; After forming the first type via hole, performing a high temperature annealing process on the display substrate; and The surface of the active layer made of the first semiconductor material and exposed by the first type via hole is processed to reduce contact resistance.

27. The method for manufacturing a display substrate according to claim 26, comprising: Using the second semiconductor material to form a second semiconductor layer through a single patterning process; Conducting a portion of the second semiconductor layer to form a second conductive structure, wherein the second conductive structure serves as an electrode where the active layer of the control transistor is located, and includes a conductive portion and a non-conductive portion, wherein the conductive portion and the non-conductive portion form an integrated structure; the non-conductive portion constitutes the active layer of the control transistor, the conductive portion directly electrically connects the gate of the drive transistor and the first electrode of the control transistor, and the conductive portion is made of a material obtained by conducting the second semiconductor material; and A second type of via is formed, and the conductorized portion of the second conductive structure is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor through the second type of via.

28. The method for manufacturing a display substrate according to claim 27, wherein: After forming the second type via hole and before forming the second conductive structure, the high temperature annealing process is performed on the display substrate.

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