Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a display area (1) and a first bezel area (57); the first bezel area (57) is arranged on one side of the display area (1) in the circumferential direction; the first bezel area (57) comprises a signal access area (2); the signal access area (2) is provided with initial signal ports (14); the initial signal ports (14) access the display area (1) by means of an initial signal line (3); the initial signal line (3) comprises a plurality of electrically-connected metal traces (6); at least one of the plurality of metal traces (6) is configured as a source / drain metal trace. The display device comprises the display panel.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed on July 31, 2023, with application number 202310954188.2 and invention name “Display Panel and Display Device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display devices, and in particular to a display panel and a display apparatus. Background Art

[0003] OLED (Organic Light Emitting Diode) display technology has the advantages of being light, thin, self-luminous, having a wide viewing angle, fast response speed, low brightness and low power consumption, and has become the main development direction in the field of display technology.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] At least one embodiment of the present disclosure provides a display panel, comprising a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction;

[0007] The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, the initial signal line includes a plurality of electrically connected metal traces, and at least one of the plurality of metal traces is set as a source-drain metal trace.

[0008] In some exemplary embodiments, the signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area;

[0009] The initial signal port is provided in the driver chip area or the circuit binding area, or the driver chip area and the circuit binding area are provided with the initial signal port.

[0010] In some exemplary embodiments, the initial signal port includes a chip port located in the driver chip area;

[0011] The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip ports, and the other end thereof is respectively connected to the first access terminals of the display area;

[0012] The first metal wiring is configured such that one end is connected to the second metal wiring and the other end is connected to the second access end of the display area.

[0013] In some exemplary embodiments, there are two chip ports, and the two chip ports are configured to input the same signal;

[0014] There are two first metal traces, one end of each of the two second metal traces is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end thereof is respectively connected to the two first access terminals of the display area;

[0015] The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

[0016] In some exemplary embodiments, the first metal trace has three terminals, two of the terminals are respectively connected to two of the second metal traces, and the other terminal is connected to the second access terminal.

[0017] In some exemplary embodiments, both of the second metal traces are provided with a first connection point, the first metal trace is configured as a source-drain metal trace, the first metal trace includes a first branch and a second branch, and the first branch is provided with a centrally arranged second connection point;

[0018] The two ends of the first branch line are configured as two connection terminals of the first metal line, and the two ends of the first branch line are electrically connected to the first connection points of the two second metal lines respectively;

[0019] One end of the second branch line is configured as the other connection end of the first metal wiring and is connected to the second connection point, and the other end of the second branch line is connected to the second access end.

[0020] In some exemplary embodiments, a first power line is further included, the first power line is arranged between the signal access area and the display area, and the first power line includes a first metal layer and a second metal layer stacked in a first direction;

[0021] The first metal layer is arranged in the same layer as the second branch line in the first direction and is provided with a gap, and the second branch line passes through the gap.

[0022] In some exemplary embodiments, the initial signal port further comprises a plurality of circuit board ports disposed on the circuit binding area, the circuit board ports being configured to input the same signal as the chip port;

[0023] The plurality of metal traces further include a third metal trace, one end of which is configured to be electrically connected to the second metal trace, and the other end of which is configured to be connected to the port on the circuit board.

[0024] In some exemplary embodiments, the device further includes a power line group, the power line group being arranged between the signal access area and the display area, the second metal trace crossing the power line group, the second metal trace further having a third connection point, and the first connection point and the third connection point being respectively arranged on either side of the power line group;

[0025] The plurality of circuit board ports include a first port and a second port, the second port being disposed near an edge of the circuit binding area, the first port being disposed on a side of the second port facing the driver chip area, and the first port and the second port being electrically connected via an internal wiring located within the circuit binding area;

[0026] One end of the third metal wiring is configured to be connected to the third connection point, and the other end is connected to the second port. The third metal wiring is configured to be a source-drain metal wiring.

[0027] In some exemplary embodiments, the device further includes a power line group, the power line group being arranged between the signal access area and the display area, the second metal trace crossing the power line group, and the second metal trace further having a plurality of third connection points, the third connection points being arranged to correspond one-to-one with the circuit board ports;

[0028] One end of the third metal trace is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port. The third metal trace is configured to be a source-drain metal trace.

[0029] In some exemplary embodiments, the first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area;

[0030] The initial signal ports are all arranged in the circuit binding area;

[0031] The plurality of metal traces include a first metal trace and a second metal trace connected to each other, one end of the first metal trace is connected to the initial signal port, and the other end is connected to the bending area;

[0032] One end of the second metal trace is connected to the bending area and electrically connected to the first metal trace, and the other end is connected to the display area;

[0033] The first metal wiring is configured as a source-drain metal wiring.

[0034] In some exemplary embodiments, the resistance value of the initial signal line is set to be less than or equal to 60 ohms.

[0035] In some exemplary embodiments, there are multiple initial signal ports, and the multiple initial signal ports include a first initial signal port, a second initial signal port, and a third initial signal port for inputting different signals;

[0036] The first initial signal port is configured to access the display area through a first signal line, the second initial signal port is configured to access the display area through a second signal line, and the third initial signal port is configured to access the display area through a third signal line;

[0037] Among the first signal line, the second signal line, and the third signal line, at least the second signal line is provided as the initial signal line.

[0038] In some exemplary embodiments, the first signal line, the second signal line, and the third signal line are all provided as the initial signal lines and are arranged in parallel.

[0039] At least one embodiment of the present disclosure provides a display panel, comprising a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction;

[0040] The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, and the initial signal line includes a plurality of electrically connected metal traces;

[0041] The metal wiring includes at least three metal layers stacked in a first direction, and an insulating layer is provided between adjacent metal layers.

[0042] In some exemplary embodiments, the at least three metal layers include three gate metal layers stacked sequentially, or include three gate metal layers and at least one source / drain metal layer stacked sequentially.

[0043] In some exemplary embodiments, the signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area;

[0044] The initial signal port includes a chip port located in the driver chip area;

[0045] The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip ports, and the other end thereof is respectively connected to the first access terminals of the display area;

[0046] One end of the first metal wiring is connected to the second metal wiring, and the other end is connected to another access end of the display area.

[0047] In some exemplary embodiments, there are two chip ports, and the two chip ports are configured to input the same signal;

[0048] There are two first metal traces, one end of each of the two second metal traces is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end thereof is respectively connected to the two first access terminals of the display area;

[0049] The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

[0050] In some exemplary embodiments, both of the second metal traces are provided with a first connection point, the first metal trace includes a first branch line and a second branch line, and the first branch line is provided with a centrally arranged second connection point;

[0051] The two ends of the first branch line are configured as two connection terminals of the first metal line, and the two ends of the first branch line are electrically connected to the first connection points of the two second metal lines respectively;

[0052] One end of the second branch line is configured as the other connection end of the first metal wiring and is connected to the second connection point, and the other end of the second branch line is connected to the second access end.

[0053] In some exemplary embodiments, the initial signal port further comprises a plurality of circuit board ports disposed on the circuit binding area, the circuit board ports being configured to input the same signal as the chip port;

[0054] The plurality of metal traces further include a third metal trace, one end of which is configured to be electrically connected to the second metal trace, and the other end of which is configured to be connected to the port on the circuit board.

[0055] In some exemplary embodiments, the device further includes a power line group, the power line group being arranged between the signal access area and the display area, the second metal trace crossing the power line group, the second metal trace further having a third connection point, and the first connection point and the third connection point being respectively arranged on either side of the power line group;

[0056] The plurality of circuit board ports include a first port and a second port, the second port being disposed near an edge of the circuit binding area, the first port being disposed on a side of the second port facing the driver chip area, and the first port and the second port being electrically connected via an internal wiring located within the circuit binding area;

[0057] One end of the third metal trace is configured to be connected to the third connection point, and the other end is connected to the second port.

[0058] In some exemplary embodiments, the device further includes a power line group, the power line group being arranged between the signal access area and the display area, the second metal trace crossing the power line group, and the second metal trace further having a plurality of third connection points, the third connection points being arranged to correspond one-to-one with the circuit board ports;

[0059] One end of the third metal trace is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port.

[0060] In some exemplary embodiments, the first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area;

[0061] The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area;

[0062] The initial signal ports are all arranged in the circuit binding area;

[0063] The plurality of metal traces include a first metal trace and a second metal trace connected to each other, one end of the first metal trace is connected to the initial signal port, and the other end is connected to the bending area;

[0064] One end of the second metal wiring is connected to the bending area and electrically connected to the first metal wiring, and the other end is connected to the display area.

[0065] At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel.

[0066] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0067] Summary of the Figures

[0068] FIG1 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0069] FIG2 is a partial enlarged schematic diagram of point A in FIG1 ;

[0070] FIG3 is a partial schematic diagram of the display panel in FIG1 ;

[0071] FIG4 is a schematic diagram of wiring of the display panel in FIG1 ;

[0072] FIG5 is a schematic diagram of wiring of the display panel in FIG1 ;

[0073] FIG6 is a schematic diagram of local wiring in FIG5;

[0074] FIG7 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0075] FIG8 is a partial schematic diagram of the display panel in FIG7 ;

[0076] FIG9 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0077] FIG10 is a partial schematic diagram of the display panel in FIG9 ;

[0078] FIG11 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0079] FIG12 is a schematic diagram of a related display panel;

[0080] FIG13 is a schematic diagram of a partial circuit of the display panel in FIG12 ;

[0081] FIG14 is a schematic cross-sectional view of the first metal trace in FIG12 ;

[0082] FIG15 is a circuit diagram of the display panel in FIG12 ;

[0083] FIG16 is a timing diagram of the display panel in FIG12 ;

[0084] FIG17 is a schematic cross-sectional view of a display panel according to another embodiment of the present disclosure;

[0085] FIG18 is a schematic cross-sectional view of the metal trace at CC in FIG12 ;

[0086] FIG19 is a schematic cross-sectional view of metal wiring of a display panel according to another embodiment of the present disclosure;

[0087] FIG20 is a schematic cross-sectional view of metal wiring of a display panel according to another embodiment of the present disclosure;

[0088] FIG21 is a schematic cross-sectional view of metal wiring of a display panel according to another embodiment of the present disclosure.

[0089] Explanation of the accompanying symbols: 1-display area, 2-signal access area, 3-initial signal line, 4-circuit binding area, 5-driver chip area, 6-metal routing, 7-power line group, 8-second metal routing, 9-first metal routing, 10-first branch line, 11-second branch line, 12-first connection point, 13-second connection point, 14-initial signal port, 15-second power line, 16-first power line, 17-binding area, 18-first fan-out area, 19-circuit board port, 20-first port, 21-second port, 22-third metal routing, 23-third connection point, 24-first gate metal layer, 25-second gate metal layer, 26-second gate insulation layer, 27-third gate metal layer, 28-third gate insulation layer, 29-interlayer dielectric Layer, 30-first source and drain metal layer, 31-passivation layer, 32-first planarization layer, 33-second source and drain metal layer, 34-second planarization layer, 35-third source and drain metal layer, 36-first metal layer, 37-second metal layer, 38-gap, 39-second fan-out area, 40-first signal line, 41-second signal line, 42-third signal line, 43-dielectric layer, 44-first filling layer, 45-second filling layer, 47-first initial signal port, 48-second initial signal port, 49-third initial signal port, 50-chip port, 51-third branch line, 52-fourth branch line, 53-fifth branch line, 54-first access terminal, 55-second access terminal, 56-pin line, 57-first border area.

[0090] Details

[0091] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0092] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0093] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0094] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0095] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0096] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0097] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0098] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0099] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0100] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0101] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0102] LTPO (Low Temperature Polycrystalline and Oxide) technology is an improved OLED screen driving technology. Currently, LTPO 2.0 has become the mainstream design for current mobile phones. LTPO 2.0 is based on the LTPO structure and can achieve different frequency switching to meet the screen requirements in different application scenarios. However, during the high-precision screen switching process, display devices using LTPO 2.0 have an undesirable phenomenon of three-part screen. In the LTPO 2.0 circuit, as shown in Figures 12 to 15, the pixel circuit of this example may include eight transistors (i.e., the first transistor T1 to the eighth transistor T8) and a storage capacitor Cst. The first transistor T1 is also called the first reset transistor, the second transistor T2 is also called the threshold compensation transistor, the third transistor T3 is also called the drive transistor, the fourth transistor T4 is also called the data writing transistor, the fifth transistor T5 is also called the first light-emitting control transistor, the sixth transistor T6 is also called the second light-emitting control transistor, the seventh transistor T7 is also called the second reset transistor, and the eighth transistor T8 is also called the third reset transistor. The light-emitting element is an OLED. The first transistor T1, the third transistor T3 to the eighth transistor T8 can be first-type transistors, and the first-type transistors can be low-temperature polysilicon thin-film transistors. The second transistor T2 can be a second-type transistor, and the second-type transistor can be an oxide thin-film transistor. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can utilize the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality. When the seventh transistor T7 is turned on, the second initial signal provided by the second signal line (Vinit2) is provided to the fourth node (N1) to initialize the fourth node (N1). The resistance value of the second signal line affects the initialization of the fourth node (N1). The first signal line (Vinit1) and the third signal line (Vinit3) provide corresponding initial signals to affected nodes when the connected transistors are turned on.Due to the use of LTPO 2.0, the wiring of the display panel located on the lining board may have a multi-layer structure. For example, the multi-layer structure may have a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a first direction, or the wiring may have one or more layers in the multi-layer structure, the first direction is set to be perpendicular to the lining board, and many wirings are arranged in a first plane, and the first direction is perpendicular to the first plane.

[0103] Display panels using LTPO 2.0 employ high-precision frequency switching, which slows down the OLED's startup speed and results in a dim display. In particular, during high-precision frequency switching, a three-part screen splitting phenomenon occurs. The applicant discovered that in the LTPO 2.0 circuit, the three-pulse cycle timing shown in FIG14 results in a difference in the load of the second signal line between the blanking region (the porch region, i.e., the period between the previous and next frames) and the normal display region (the normal region). This results in a lower voltage on the initial signal line in the blanking region, slowing down the OLED's startup speed and causing a dim display. Furthermore, the input resistance of the primary second signal line significantly affects the transient current of the second signal line. The greater the resistance, the more severe the voltage fluctuation of the second initial signal network in the display area 1 with load changes. As shown in FIG12 and FIG13 , in the relevant display panel, two chip ports 50 on the driver chip area 5 are connected to the display area 1 on the left and right sides via a first metal trace 8. Only the first metal trace 8 serves as the second signal line, and the resistance of the first metal trace 8 is equal to the resistance of the second signal line, i.e., R. The first metal trace 8 is long and is mostly made of Mo gate metal layer, so it has a relatively high impedance. The resistance of this trace from the chip port 50 to the position where it starts to connect to the display area 1 is generally around 150Ω.

[0104] As shown in Figures 1, 3 and 5, at least one embodiment of the present disclosure provides a display panel, which includes a display area 1 (AA area) and a first frame area 57, and the first frame area 57 is arranged on one side of the circumference of the display area 1. The first frame area 57 may include a signal access area 2, and the signal access area 2 is provided with an initial signal port 14. The initial signal port 14 is connected to the display area 1 (AA area) through an initial signal line 3, and the initial signal line 3 includes a plurality of electrically connected metal traces 6, and at least one of the plurality of metal traces 6 is set as a source-drain metal trace, that is, a trace structure in the source-drain metal layer. As a result, the initial signal line 3 has a smaller impedance, which can improve the display effect and avoid the phenomenon of poor display of the three-divided screen during the high-precision screen cutting process.

[0105] In some exemplary embodiments, as shown in FIG1 , the display panel includes a display area 1 and a peripheral area surrounding the periphery of the display area 1. The peripheral area may include a first frame area 57 located on one side of the display area 1 and frame areas located on other sides of the display area 1. The first frame area 57 may be the lower frame of the display panel, and the frame areas on the other sides may include the upper frame, left frame and right frame of the display panel. The first frame area 57 may include a first fan-out area 18, a bending area 17, a second fan-out area 39 and a signal access area 2, which are sequentially arranged in a direction away from the display area 1. The first fan-out area 18 may be connected to the display area 1, and the bending area 17 may be connected between the first fan-out area 18 and the second fan-out area 39, and may be configured so that the signal access area 2 is bent to the back of the display area 1. The first fan-out area 18 may be provided with at least a power line and a plurality of display lead lines, and the bending area 17 may be provided with a plurality of bending connection lines.

[0106] In some exemplary embodiments, as shown in Figures 1, 3 and 5, the signal access area 2 includes a driver chip area 5 and a circuit binding area 4, and the circuit binding area 4 is arranged on the side of the driver chip area 5 away from the display area 1, and the driver chip area 5 is close to the second fan-out area 39. The driver chip area 5 can be provided with a plurality of contact pads (Bump), and the plurality of contact pads can be configured to be bound and connected with at least one driver chip. The driver chip can be configured to generate a driving signal required for driving the sub-pixel and provide the driving signal to the data line of the display area 1. The circuit binding area 4 can be provided with a plurality of contact pads, and the plurality of contact pads can be configured to be bound and connected with at least one circuit board, for example, a flexible printed circuit (FPC). The driver chip of the driver chip area 5 is connected to the circuit board of the circuit binding area 4 through a pin line 56.

[0107] In some exemplary embodiments, as shown in FIG6 , there may be multiple initial signal ports 14 , each of which may include a first initial signal port 47 , a second initial signal port 48 , and a third initial signal port 49 . The first initial signal port 47 , the second initial signal port 48 , and the third initial signal port 49 are configured to input different signals. The first initial signal port 47 , the second initial signal port 48 , and the third initial signal port 49 are arranged close to each other. For example, the driver chip area 5 may include a second initial signal port 48 , and one first initial signal port 47 and one third initial signal port 49 are arranged close to the second initial signal port 48 , so that each second initial signal port 48 forms a group of ports with one first initial signal port 47 and one third initial signal port 49 and are arranged in a centralized manner. The display panel may include a first signal line 40 , a second signal line 41 , and a third signal line 42 . The first signal line 40 may electrically connect the first initial signal port 47 to the display area 1 , the second signal line 41 may electrically connect the second initial signal port 48 to the display area 1 , and the third signal line 42 may electrically connect the third initial signal port 49 to the display area 1 . The first signal line 40, the second signal line 41, and the third signal line 42 are arranged in parallel within a plane defined by the second and third directions, extending in the same direction, with the first, second, and third directions being perpendicular to each other. Of the first signal line 40, the second signal line 41, and the third signal line 42, only the second signal line 41 may adopt the routing structure of the initial signal line 3; alternatively, the first signal line 40, the second signal line 41, and the third signal line 42 may adopt the routing structure of the initial signal line 3; or alternatively, in addition to the first signal line 40 adopting the routing structure of the initial signal line 3, one of the first signal line 40 and the third signal line 42 may adopt the routing structure of the initial signal line 3. Thus, while the second signal line 41 has a relatively low impedance, the first signal line 40 and the third signal line 42 may also have relatively low impedance, further ensuring a good display effect.

[0108] The following uses the second signal line 41 and the second initial signal port 48 as an example to specifically explain the routing structure of the initial signal line. In some exemplary embodiments, as shown in Figures 3 and 5, the driver chip area 5 may be provided with two chip ports 50, and the two chip ports 50 can input the same signal. The two chip ports 50 serve as the second initial signal port 48. The chip ports 50 are located on the side of the driver chip area 5 close to the display area 1, and the two chip ports 50 are symmetrical about the center line C1. The two chip ports 50 are symmetrically arranged about the center line C1, which is the center line passing through the geometric center of the driver chip area 5. At the same time, the first initial signal port 47 and the third initial signal port 49 may also be arranged with corresponding ports corresponding to the chip ports 50 of the second initial signal port 48, and are also symmetrical about the center line C1. The second signal line 41 is configured as an initial signal line. The second signal line 41 may include a first metal line 9 and a second metal line 8. The two second metal lines 8 are arranged in a mirror image about the center line C1. One end of the two second metal lines 8 may be connected to the two chip ports 50 in a one-to-one correspondence, and the other ends of the two second metal lines 8 may both be configured to connect to the display area 1. The second metal line 8 may be a gate metal line located in the gate metal layer, but is not limited thereto. For example, the second metal line 8 may be a source-drain metal line, which is a metal line located in the source-drain metal layer. The first metal line 9 may be a source-drain metal line and may be connected in parallel with part of the second metal line 8.

[0109] In some exemplary embodiments, as shown in FIG3 , the second metal trace 8 includes a third branch 51, a fourth branch 52, and a fifth branch 53, which are connected in sequence. One end of the third branch 51 is connected to the chip port 50 and extends away from the driver chip area 5 along the second direction. One end of the fourth branch 52 is connected to the third branch 51, with the connection point between the fourth branch 52 and the third branch 51 being the first connection point 12. The other end of the fourth branch 52 extends away from the first connection point 12, and the fourth branch 52 extends along the third direction. One end of the fifth branch 53 is connected to the fourth branch 52, with the connection point between the fourth branch 52 and the fifth branch 53 being the third connection point 23. The other end of the fifth branch 53 extends away from the circuit bonding area 4 along the second direction and to a first access port 54 of the display area 1. The two second metal traces 8 are also arranged symmetrically about the centerline C1, and the two second metal traces 8 are connected to the two first access ports 54 of the display area 1, respectively.

[0110] In some exemplary embodiments, as shown in FIG3 , the first metal trace 9 includes two traces: a first branch 10 and a second branch 11. The first and second branches 10, 11 are made of the same material and are both source-drain metal traces. A second connection point 13 is located at the center of the first branch 10. The first branch 10 extends along a third direction, with both ends electrically connected to the first connection points 12 of the two second metal traces 8, thereby connecting the two second metal traces 8. Furthermore, the second branch 11 extends along a second direction, which is perpendicular to the third direction. One end of the second branch 11 connects to the second connection point 13, and the other end connects to the second access terminal 55 of the display area 1. The location where the first branch 10 connects to the two first connection points 12 serves as the two connection terminals of the first metal trace 9, while the location where the second branch 11 connects to the second access terminal 55 serves as the other connection terminal of the first metal trace 9, resulting in three connection terminals for the first metal trace 9. The first metal trace 9 can be a source-drain metal trace, and the second metal trace 8 can be a gate metal trace. The materials of the two are different, and the gate metal trace and the source-drain metal trace are in different layers in the first direction. The connection between the first branch line 10 and the second metal trace 8 at the first connection point 12 can be connected by punching, and the first direction is perpendicular to the plane formed by the second direction and the third direction.

[0111] In some exemplary embodiments, as shown in Figures 1, 2, and 5, the display panel further includes a power line group 7, which may include a first power line 16 (VDD) and a second power line 15 (VSS). The first power line 16 and the second power line 15 are disposed between the circuit binding area 4 and the display area 1, and can be electrically connected to the circuit binding area 4 to access the connection of the bending area 17. In addition, the first fan-out area 18 also has corresponding first power lines 16 and second power lines 15 (not shown in the figures), so that the first power lines 16 and the second power lines 15 continue to access the connection lines of the display area 1. The second metal trace 8 needs to cross the power line group 7 to connect to the display area 1 during its extension to the display area, and the second branch line 11 also needs to cross the power line group 7 to connect to the display area 1. First power line 16 can be a dual source-drain metal trace. First power line 16 can include a first metal layer 35 and a second metal layer 36 stacked in a first direction. The first metal layer 35 and the second branch line 11 can both have a first source-drain metal layer trace structure, and the second metal layer 36 can have a second source-drain metal layer trace structure, so that the first metal layer 35 and the second branch line 11 are arranged in the same layer in the first direction. The first metal layer 35 is disposed on a dielectric layer 43, and the second metal layer 36 is located on the side of the first metal layer 35 away from the dielectric layer 43. The first metal layer 35 has a notch 37 corresponding to the second branch line 11, which disconnects the first metal layer 35. The second branch line 11 can pass through the notch 37. The second branch line 11 is spaced apart from the edge of the notch 37, so that the first metal layer 35 and the second branch line 11 are kept away from each other and are not electrically connected. The second metal layer 36 passes over the second branch line 11 and is spaced apart from the second branch line 11. The first filling layer 44 and the second filling layer 45 can be filled in the notch 37 and between the second metal layer 36 and the second branch line 11. As a result, the second branch line 11 crosses the power line group 7 and connects to the display area 1. The second metal trace 8 can be a gate metal trace. The second metal trace 8 and the power line group 7 are on different layers, that is, the gate metal trace and the source and drain metal traces are on different layers in the first direction. The second metal trace 8 and the power line group 7 do not affect each other.

[0112] As shown in Figures 1 and 3, in this example, relative to the relevant display panel, the second signal line 41 adds a first metal trace 9. The first metal trace 9 and part of the second metal trace 8 are connected in parallel. The overall resistance of the second metal trace 8 is approximately 150Ω, and the resistance of the first metal trace 9 is approximately 50Ω. After resistance calculation, the resistance of the second signal line 41 is approximately 37.5Ω. The second signal line 41 adopts the routing structure of the initial signal line 3 described above, which can reduce the impedance and improve the poor display phenomenon. In particular, when the resistance is controlled below 60 ohms, the display effect is significantly improved. The equivalent resistance of the second signal line 41 is approximately 37.5Ω, which is significantly reduced compared to 150Ω, which can improve the display effect. The first signal line 40 and the third signal line 42 can also adopt the routing structure of the second signal line 41 in Figure 3, which is also the initial signal line.

[0113] In some exemplary embodiments, as shown in Figures 7 and 8, the circuit binding area 4 is further provided with a plurality of circuit board ports 19, which also serve as the second initial signal port 48. Thus, the second initial signal port 48 includes a circuit board port 19 located in the circuit binding area 4 and a chip port 50 located on the driver chip 5. The circuit board port 19 and the chip port 50 input the same signal. Simultaneously, the first initial signal port and the third initial signal port may also be arranged correspondingly to the chip port 50 and the circuit board port 19 of the second initial signal port 48, and are also symmetrical about the center line C1. The chip port 50 is connected to the three access terminals (two first access terminals 54 and one second access terminal 55) of the display area 1 via the first metal trace 9 and the second metal trace 8, and the circuit board port 19 is connected to the initial signal line via the third metal trace 22. Four circuit board ports 19 are provided. These four circuit board ports 19 include two first ports 20 and two second ports 21. The two first ports 20 and the two second ports 21 correspond one to one. One first port 20 and one second port 21 are located on one side of the driver chip area 5, while the other first port 20 and the other second port 21 are located on the other side of the driver chip area 5, forming a symmetrical arrangement about the centerline C1. The second port 21 can be located near the edge of the driver chip area 5, and the first port 20 can be located on the side of the second port 21 facing the driver chip area 5 in the third direction. The corresponding first ports 20 and second ports 21 are electrically connected via internal wiring located in the circuit binding area 4. The circuit board ports 19 are not limited to four; for example, six can be provided, including three first ports 20 and three second ports 21.

[0114] In some exemplary embodiments, as shown in Figures 7 and 8 , the second metal trace 8 has a third connection point 23 in addition to the first connection point 12. The second metal trace 8 includes a third branch line 51, a fourth branch line 52, and a fifth branch line 53, which are connected in sequence. One end of the third branch line 51 is connected to the chip port 50 and extends away from the driver chip area 5 along the second direction. One end of the fourth branch line 52 is connected to the third branch line 51. The connection point between the fourth branch line 52 and the third branch line 51 is the first connection point 12. The other end of the fourth branch line 52 extends away from the first connection point 12 and extends along the third direction. One end of the fifth branch line 53 is connected to the fourth branch line 52. The connection point between the fourth branch line 52 and the fifth branch line 53 is the third connection point 23. The other end of the fifth branch line 53 extends away from the circuit binding area 4 along the second direction and extends to a first access terminal 54 of the display area 1. The fourth branch line 52 crosses the power line group 7, and the first connection point 12 and the third connection point 23 are respectively located on both sides of the power line group 7 in the third direction. The third metal trace 22 is a source-drain metal trace, that is, a trace structure in the source-drain metal layer. The third metal trace 22 extends along the second direction. One end of the third metal trace 22 can be connected to the third connection point 23, and the other end is connected to the second port 21. The third metal trace 22 and the second metal trace 8 are in different layers in the first direction. The connection between the third metal trace 22 and the second metal trace 8 at the position of the third connection point 23 can be connected by punching. Therefore, the display panel is provided with multiple initial signal ports, and multiple parallel lines are connected to the display area 1, which effectively reduces the resistance of the second signal line 41 and improves the display effect. The first signal line and the third signal line can also adopt the trace structure of the second signal line 41 as shown in Figure 8, which is also an initial signal line.

[0115] In some exemplary embodiments, as shown in Figures 9 and 10, the circuit binding area 4 is further provided with a plurality of circuit board ports 19, which also serve as the second initial signal port 48. Thus, the second initial signal port 48 includes a circuit board port 19 located in the circuit binding area 4 and a chip port 50 located on the driver chip 5. The circuit board port 19 and the chip port 50 input the same signal. Simultaneously, the first initial signal port and the third initial signal port may also be arranged correspondingly to the chip port 50 and the circuit board port 19 of the second initial signal port 48, and are also symmetrical about the center line C1. The chip port 50 is connected to the three access terminals (two first access terminals 54 and one second access terminal 55) of the display area 1 via the first metal trace 9 and the second metal trace 8, and the circuit board port 19 is connected to the initial signal line via the third metal trace 22. Four circuit board ports 19 are provided. These four circuit board ports 19 include two first ports 20 and two second ports 21. The two first ports 20 and the two second ports 21 correspond one to one. One first port 20 and one second port 21 are located on one side of the driver chip area 5, while the other first port 20 and the other second port 21 are located on the other side of the driver chip area 5, forming a symmetrical arrangement about the centerline C1. The second port 21 can be located near the edge of the driver chip area 5, and the first port 20 can be located on the side of the second port 21 facing the driver chip area 5 in the third direction. The two circuit board ports 19 are not electrically connected. The two circuit board ports 19 on one side of the driver chip area 5 are located on either side of the connection between the power cord assembly 7 and the circuit binding area 4. The number of circuit board ports 19 is not limited to four; for example, six circuit board ports can be provided, with three first ports 20 and three second ports 21.

[0116] In some exemplary embodiments, as shown in Figures 9 and 10 , each second metal trace 8 has two third connection points 23 in addition to the first connection point 12, such that the number of third connection points 23 is the same as the number of circuit board ports 19. In addition to the first connection point 12, the second metal trace 8 also has the third connection point 23. The second metal trace 8 includes a third branch line 51, a fourth branch line 52, and a fifth branch line 53 connected in sequence. One end of the third branch line 51 is connected to the chip port 50 and extends away from the driver chip area 5 along the second direction. One end of the fourth branch line 52 is connected to the third branch line 51. The connection point between the fourth branch line 52 and the third branch line 51 is the first connection point 12. The other end of the fourth branch line 52 extends away from the first connection point 12. The fourth branch line 52 extends along the third direction. One end of the fifth branch line 53 connects to the fourth branch line 52. The connection point between the fourth branch line 52 and the fifth branch line 53 is the third connection point 23. The other end of the fifth branch line 53 extends along the second direction away from the circuit binding area 4 and extends to a first access port 54 of the display area 1. The fourth branch line 52 spans the power line group 7. Two third connection points 23 are located on either side of the power line group 7 in the third direction. One third connection point 23 and the first connection point 12 are located on the same side of the power line group 7. Each third connection point 23 has a corresponding circuit board port 19 in the second direction. The third metal trace 22 is a source-drain metal trace, i.e., a trace structure located in the source-drain metal layer. The third metal trace 22 extends along the second direction. One end of the third metal trace 22 can be connected to the third connection point 23, and the other end can be connected to the circuit board port 19. The third metal trace 22 and the second metal trace 8 are located on different layers in the first direction. The connection between the third metal trace 22 and the second metal trace 8 at the third connection point 23 can be made by punching. Thus, the display panel is provided with multiple initial signal ports, and multiple parallel lines are connected to the display area 1, effectively reducing the resistance of the second signal line 41 and improving the display effect. The first signal line and the third signal line can also adopt the routing structure of the second signal line 41 in Figure 10, which is also an initial signal line.

[0117] In some exemplary embodiments, as shown in FIG11 , the circuit binding area 4 is provided with two circuit board ports 19, which serve as second initial signal ports 48. The two circuit board ports 19 are located at the two end edges of the circuit binding area 4 in the third direction, and are symmetrical about the center line C1 of the driver chip area 5. At the same time, the first initial signal port and the third initial signal port may also be arranged with corresponding ports corresponding to the circuit board ports 19 of the second initial signal port 48, and are also symmetrical about the center line C1. The second signal line 41 may include two first metal traces 9 and two second metal traces 8, and the two first metal traces 9 and the two second metal traces 8 are connected in a one-to-one correspondence. The second metal traces 8 may be source-drain metal traces, i.e., trace structures located in the source-drain metal layer, and the first metal traces 9 may be gate metal traces, i.e., trace structures located in the gate metal layer. The second metal traces 8 and the first metal traces 9 may be connected by punching, i.e., a jumper connection is made in the bending area 17. Among them, the second metal trace 8 and the first metal trace 9 both extend along the second direction, one end of the first metal trace 9 can be connected to the circuit board port 19, and the other end is connected to the bending area 17, one end of the second metal trace 8 is connected to the bending area 17 and electrically connected to the first metal trace 9, and the other end is connected to the first access terminal 54 of the display area 1. In addition, the second signal line 41 does not need to cross the power line group 7, which reduces the trace length and reduces the manufacturing difficulty. Compared with the relevant display panel of Figure 9, this example cancels the port on the driver chip area 5, directly inputs the initial signal trace from the circuit binding area 4, and uses source and drain metal as the trace to connect to the bending area 17. The dielectric constant of the source and drain metal is 0.042, which is smaller than the dielectric constant of the gate metal of 0.41, so that the overall impedance will have at least ten times the benefit, and the purpose of reducing resistance can also be achieved.

[0118] In some exemplary embodiments, based on the relevant display panel shown in Figure 9, the two chip ports 50 on the driver chip area 5 are connected to the display area 1 on the left and right sides through the first metal trace 8, and only the first metal trace 8 is used as the second signal line. The first metal trace 8 uses a source-drain metal trace. The main material of the source-drain metal trace is source-drain metal, and the dielectric constant of the source-drain metal is 0.042. Compared with the dielectric constant of 0.41 of the gate metal dielectric used in the related art, the dielectric constant is smaller, so that the overall impedance will have at least ten times the benefit, and the purpose of reducing resistance can also be achieved.

[0119] In some exemplary embodiments, a display panel, as shown in Figures 17 and 18, includes a display area 1 (AA area) and a first frame area 57, and the first frame area 57 is arranged on one side of the circumference of the display area 1. The first frame area 57 may include a signal access area 2, and the signal access area 2 is provided with an initial signal port 14. The initial signal port 14 is connected to the display area 1 (AA area) through an initial signal line 3, and the initial signal line 3 includes a plurality of electrically connected metal traces 6, and the metal traces 6 include at least three layers of metal layers stacked in a first direction, and an insulating layer is provided between adjacent metal layers. As a result, the initial signal line 3 has a smaller impedance, which can improve the display effect and avoid the phenomenon of poor display of the three-divided screen during the high-precision screen cutting process.

[0120] In some exemplary embodiments, as shown in FIG17 , the routing layout of the initial signal line 3 adopts the same routing method as the second signal line 41 shown in FIG3 . The plurality of metal traces 6 include the second metal trace 8 and the first metal trace 9 shown in FIG3 . The second metal trace 8 and the first metal trace 9 each have at least three metal layers stacked in a first direction. But not limited to this, for example, the routing layout of the initial signal line 3 of this example adopts the same routing method as the second signal line 41 shown in Figures 8 and 10, and the multiple metal routings 6 include the second metal routing 8, the first metal routing 9, and the third metal routing 22 as shown in Figures 8 and 10, and the second metal routing 8, the first metal routing 9, and the third metal routing 22 all have at least three layers of metal layers stacked in the first direction; for another example, the routing layout of the initial signal line 3 of this example adopts the same routing method as the second signal line 41 shown in Figure 11, and the multiple metal routings 6 include the second metal routing 8 and the first metal routing 9 as shown in Figure 11, and the second metal routing 8 and the first metal routing 9 all have at least three layers of metal layers stacked in the first direction; for another example, the routing layout of the initial signal line 3 of this example adopts the same routing method as the first metal routing 8 shown in Figure 12, and the first metal routing 8 has at least three layers of metal layers stacked in the first direction. Figure 18 is a schematic cross-sectional view of metal trace 6 at CC in Figure 17 . This metal trace may include three metal layers stacked in a first direction, with an insulating layer interposed between adjacent metal layers. The three metal layers are disposed on a backing plate (not shown) and connected in parallel, with the first direction perpendicular to the second and third directions. The three metal layers, arranged from the side close to the backing plate (not shown) to the side away from the backing plate (not shown), comprise a first gate metal layer 24, a second gate metal layer 25, and a third gate metal layer 27. A second gate insulating layer 26 is disposed between the first gate metal layer 24 and the second gate metal layer 25, serving as an insulating layer; and a third gate insulating layer 28 is disposed between the second gate metal layer 25 and the third gate metal layer 27, serving as an insulating layer. The schematic cross-sectional view of the second metal trace 8 of the related display panel, shown in Figure 11 , employs a two-layer metal stacking structure, with the first gate metal layer 24 and the second gate metal layer 25 stacked in the first direction. Therefore, in this example, three metal layers are used, which adds one metal layer compared to related display panels. By connecting multiple metal layers in parallel, the resistance of the trace is effectively reduced. In some exemplary embodiments, there are multiple initial signal lines 3, and all initial signal lines 3 can use the same metal trace 6, all having a three-layer structure.

[0121] In some exemplary embodiments, as shown in FIG19 , the metal trace includes four metal layers stacked in a first direction, with an insulating layer provided between adjacent metal layers. The four metal layers are disposed on a substrate (not shown) and connected in parallel. The four metal layers, from the side closest to the substrate (not shown) to the side away from the substrate (not shown), are, in order: a first gate metal layer 24, a second gate metal layer 25, a third gate metal layer 27, and a first source / drain metal layer 30, forming three gate metal layers and one source / drain metal layer. A second gate insulating layer 26 is provided between the first gate metal layer 24 and the second gate metal layer 25, serving as an insulating layer; a third gate insulating layer 28 is provided between the second gate metal layer 25 and the third gate metal layer 27, serving as an insulating layer; and an interlayer dielectric layer 29 is provided between the third gate metal layer 27 and the first source / drain metal layer 30, serving as an insulating layer. Therefore, in this example, four metal layers are used, which adds two metal layers compared to related display panels. By connecting multiple metal layers in parallel, the trace resistance is effectively reduced. In some exemplary embodiments, there are multiple initial signal lines 3 , and all initial signal lines 3 may use the same metal routing 6 and have a four-layer structure.

[0122] In some exemplary embodiments, as shown in FIG20 , the metal trace includes five metal layers stacked in a first direction, with an insulating layer provided between adjacent metal layers, and the five metal layers are arranged on a substrate (not shown) and connected in parallel. The five metal layers are, from the side close to the liner (not shown in the figure) to the side away from the liner (not shown in the figure), the first gate metal layer 24, the second gate metal layer 25, the third gate metal layer 27, the first source-drain metal layer 30, and the second source-drain metal layer 33, forming three gate metal layers and two source-drain metal layers. A second gate insulating layer 26 is provided between the first gate metal layer 24 and the second gate metal layer 25 as an insulating layer; a third gate insulating layer 28 is provided between the second gate metal layer 25 and the third gate metal layer 27 as an insulating layer; an interlayer dielectric layer 29 is provided between the third gate metal layer 27 and the first source-drain metal layer 30 as an insulating layer; a passivation layer 31 and a first planarizing layer 32 are provided between the first source-drain metal layer 30 and the second source-drain metal layer 33, the passivation layer 31 and the first planarizing layer 32 serve as insulating layers, the first filling layer 44 is made of the same material as the passivation layer 31, and the second filling layer 45 is made of the same material as the first planarizing layer 32. Therefore, in this example, five metal layers are used, which is three more than in related display panels. By connecting multiple metal layers in parallel, the resistance of the traces is effectively reduced. In some exemplary embodiments, there are multiple initial signal lines 3, and all initial signal lines 3 can use the same metal trace 6, all having a five-layer structure.

[0123] In some exemplary embodiments, as shown in FIG21 , the metal routing includes six metal layers stacked in a first direction, with an insulating layer provided between adjacent metal layers, and the six metal layers are arranged on a substrate (not shown) and connected in parallel. The six metal layers are arranged in order from the side close to the liner (not shown) to the side away from the liner (not shown), namely, a first gate metal layer 24, a second gate metal layer 25, a third gate metal layer 27, a first source-drain metal layer 30, a second source-drain metal layer 33, and a third source-drain metal layer 35, forming three gate metal layers and two source-drain metal layers. A second gate insulating layer 26 is provided between the first gate metal layer 24 and the second gate metal layer 25 as an insulating layer; a third gate insulating layer 28 is provided between the second gate metal layer 25 and the third gate metal layer 27 as an insulating layer; an interlayer dielectric layer 29 is provided between the third gate metal layer 27 and the first source-drain metal layer 30 as an insulating layer; a passivation layer 31 and a first planarization layer 32 are provided between the first source-drain metal layer 30 and the second source-drain metal layer 33; the passivation layer 31 and the first planarization layer 32 serve as insulating layers. A second planarization layer 34 is provided between the second source-drain metal layer 33 and the third source-drain metal layer 35 as an insulating layer. Therefore, in this example, five metal layers are used, which is three more than in related display panels. By connecting multiple metals in parallel, the resistance of the traces is effectively reduced. In some exemplary embodiments, there are multiple initial signal lines 3, and all initial signal lines 3 can use the same metal trace 6, all having a six-layer structure.

[0124] In some exemplary embodiments, a display device includes the above-mentioned display panel. The display device may be an OLED display device, such as a mobile phone, a monitor, etc.

[0125] In combination with the above embodiments, the display panel forms a parallel routing method by adopting source-drain metal routing and multi-port routing of the second initial signal, thereby reducing the impedance and making the resistance target value of the second signal line 41 as close to 50Ω as possible, thereby avoiding the undesirable phenomenon of three-part screen cutting during high-precision screen cutting and improving the display effect.

[0126] The above-described embodiments merely represent several embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed. However, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure shall still be defined by the appended claims.

Claims

1. A display panel, wherein: It includes a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction; The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, the initial signal line includes a plurality of electrically connected metal traces, and at least one of the plurality of metal traces is configured as a source-drain metal trace.

2. The display panel according to claim 1, wherein: The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area; The initial signal port is provided in the driving chip area or the circuit binding area, or the driving chip area and the circuit binding area are provided with the initial signal port.

3. The display panel according to claim 2, wherein: The initial signal port includes a chip port located in the driver chip area; The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip port, and the other end is respectively connected to the first access end of the display area; The first metal wiring is configured such that one end is connected to the second metal wiring and the other end is connected to the second access end of the display area.

4. The display panel according to claim 3, wherein: There are two chip ports, and the two chip ports are configured to input the same signal; There are two second metal wires, one end of each of the two second metal wires is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end of each second metal wire is respectively connected to the two first access terminals of the display area; The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

5. The display panel according to claim 4, wherein: The first metal wiring is provided with three connection terminals, two of the connection terminals are respectively connected to two of the second metal wirings, and the other connection terminal is connected to the second access terminal.

6. The display panel according to claim 5, wherein: Both of the two second metal routings are provided with a first connection point, the first metal routing is configured as a source-drain metal routing, the first metal routing includes a first branch line and a second branch line, and the first branch line is provided with a centrally arranged second connection point; Two ends of the first branch line are configured as two connection terminals of the first metal wiring, and the two ends of the first branch line are electrically connected to two first connection points of the second metal wiring respectively; One end of the second branch line is configured as the other connection terminal of the first metal wiring and connected to the second connection point, and the other end of the second branch line is connected to the second access terminal.

7. The display panel according to claim 6, further comprising a first power line, the first power line being arranged between the signal access area and the display area, the first power line comprising a first metal layer and a second metal layer stacked in a first direction; The first metal layer is arranged in the same layer as the second branch line in the first direction and is provided with a gap, and the second branch line passes through the gap.

8. The display panel according to claim 7, wherein: The initial signal port also includes a plurality of circuit board ports arranged on the circuit binding area, and the circuit board ports are arranged to input the same signal as the chip port; The plurality of metal traces further include a third metal trace, one end of the third metal trace being arranged to be connected to the second The metal wiring is electrically connected, and the other end is configured to be connected to the port on the circuit board.

9. The display panel according to claim 8, further comprising a power line group, wherein the power line group is arranged between the signal access area and the display area, the second metal wiring crosses the power line group, the second metal wiring is further provided with a third connection point, and the first connection point and the third connection point are respectively arranged on both sides of the power line group; The plurality of circuit board ports include a first port and a second port, the second port is arranged close to an edge of the circuit binding area, the first port is arranged on a side of the second port facing the driver chip area, and the first port and the second port are electrically connected via an internal wiring located in the circuit binding area; One end of the third metal routing is configured to be connected to the third connection point, and the other end is connected to the second port. The third metal routing is configured to be a source-drain metal routing.

10. The display panel according to claim 8, further comprising a power line group, wherein the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, and the second metal line is further provided with a plurality of third connection points, wherein the third connection points are arranged to correspond one to one with the circuit board ports; One end of the third metal routing line is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port. The third metal routing line is configured to be a source-drain metal routing line.

11. The display panel according to claim 2, wherein: The first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area; The initial signal ports are all arranged in the circuit binding area; The plurality of metal routings include a first metal routing and a second metal routing connected to each other, one end of the first metal routing is connected to the initial signal port, and the other end is connected to the bending area; One end of the second metal wiring is connected to the bending area and electrically connected to the first metal wiring, and the other end is connected to the display area; The first metal wiring is configured as a source-drain metal wiring.

12. The display panel according to any one of claims 1 to 11, wherein: The resistance value of the initial signal line is set to be less than or equal to 60 ohms.

13. The display panel according to any one of claims 1 to 11, wherein: There are multiple initial signal ports, and the multiple initial signal ports include a first initial signal port, a second initial signal port and a third initial signal port for inputting different signals; The first initial signal port is configured to access the display area through a first signal line, the second initial signal port is configured to access the display area through a second signal line, and the third initial signal port is configured to access the display area through a third signal line; Among the first signal line, the second signal line, and the third signal line, at least the second signal line is set as the initial signal line.

14. The display panel according to claim 13, wherein: The first signal line, the second signal line, and the third signal line are all set as the initial signal line and arranged in parallel.

15. A display panel, wherein: It includes a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction; The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, and the initial signal line includes a plurality of electrically connected metal traces; The metal wiring includes at least three metal layers stacked in a first direction, and adjacent metal layers With insulation layer.

16. The display panel according to claim 15, wherein: The at least three metal layers include three gate metal layers stacked in sequence, or include three gate metal layers stacked in sequence and at least one source / drain metal layer.

17. The display panel according to claim 16, wherein: The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area; The initial signal port includes a chip port located in the driver chip area; The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip port, and the other end is respectively connected to the first access end of the display area; One end of the first metal wiring is connected to the second metal wiring, and the other end is connected to another access end of the display area.

18. The display panel according to claim 17, wherein: There are two chip ports, and the two chip ports are configured to input the same signal; There are two second metal wires, one end of each of the two second metal wires is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end of each second metal wire is respectively connected to the two first access terminals of the display area; The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

19. The display panel according to claim 18, wherein: The two second metal routing lines are both provided with a first connection point, the first metal routing line includes a first branch line and a second branch line, and the first branch line is provided with a centrally arranged second connection point; Two ends of the first branch line are configured as two connection terminals of the first metal wiring, and the two ends of the first branch line are electrically connected to two first connection points of the second metal wiring respectively; One end of the second branch line is configured as the other connection terminal of the first metal wiring and connected to the second connection point, and the other end of the second branch line is connected to the second access terminal.

20. The display panel according to claim 19, wherein: The initial signal port also includes a plurality of circuit board ports arranged on the circuit binding area, and the circuit board ports are arranged to input the same signal as the chip port; The plurality of metal traces further include a third metal trace, one end of the third metal trace being electrically connected to the second metal trace, and the other end of the third metal trace being connected to a port on the circuit board.

21. The display panel according to claim 20, further comprising a power line group, wherein the power line group is arranged between the signal access area and the display area, the second metal wiring crosses the power line group, the second metal wiring is further provided with a third connection point, and the first connection point and the third connection point are respectively arranged on both sides of the power line group; The plurality of circuit board ports include a first port and a second port, the second port is arranged close to an edge of the circuit binding area, the first port is arranged on a side of the second port facing the driver chip area, and the first port and the second port are electrically connected via an internal wiring located in the circuit binding area; One end of the third metal wiring is configured to be connected to the third connection point, and the other end is connected to the second port.

22. The display panel according to claim 20, further comprising a power line group, wherein the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, and the second metal line is further provided with a plurality of third connection points, wherein the third connection points are arranged to correspond one to one with the circuit board ports; One end of the third metal trace is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port.

23. The display panel according to claim 15, wherein: The first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area; The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area; The initial signal ports are all arranged in the circuit binding area; The plurality of metal routings include a first metal routing and a second metal routing connected to each other, one end of the first metal routing is connected to the initial signal port, and the other end is connected to the bending area; One end of the second metal wiring is connected to the bending area and electrically connected to the first metal wiring, and the other end is connected to the display area.

24. A display device, wherein: Comprising a display panel as described in any one of claims 1 to 23.

Images