Micro-display circuit and control method therefor, and display chip and electronic device

Abstract

Provided in the embodiments of the present application are a micro-display circuit and a control method therefor, and a display chip and an electronic device, The micro-display circuit comprises: a pixel array, which comprises a plurality of pixel circuits, wherein each pixel circuit among the plurality of pixel circuits comprises a pulse width modulation signal generation branch, a light-emitting diode and a mirror image current branch, and the pulse width modulation signal generation branch comprises a first static memory; and a pixel array sharing circuit, which is used for transmitting a current signal to the pixel array, wherein the plurality of pixel circuits receive the current signal of the pixel array sharing circuit in a sequential and orderly manner, the pixel array sharing circuit comprises a second static memory and a reference current branch, the mirror image current branch in each pixel circuit forms a current mirror symmetrical structure with the reference current branch, and the circuit structure of the first static memory is consistent with the circuit structure of the second static memory.

Description

Micro display circuit and control method, display chip and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on July 29, 2023, with application number 202310945508.8 and invention name "A micro display circuit and control method, display chip and electronic device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a micro display circuit and control method, a display chip, and an electronic device. Background Art

[0004] Silicon-based microdisplay technology is an emerging display technology that cleverly integrates single-crystal silicon CMOS integrated circuit technology with display technology. This reduces display system costs and product footprint while achieving ultra-high display resolution, meeting the near-eye display requirements of emerging electronic technologies such as augmented reality, virtual reality, and merged reality. This display utilizes driver circuitry and luminescent display materials fabricated on a single-crystal silicon CMOS substrate, amplifying image information through a suitable optical engine system. It has applications across a wide range of fields, including military, aerospace, automotive driver assistance, and industrial electronics, and has recently begun to be applied to consumer electronics.

[0005] Traditional silicon-based micro-display technologies include liquid crystal on silicon (LCoS) technology and organic light-emitting diode (OLED on Silicon) technology. The latest silicon-based micro-display technology is silicon-based micro-light-emitting diode (Micro-LED) micro-display technology.

[0006] Based on the basic principles of display driving, pixel circuit drive signal modulation methods are divided into pulse amplitude modulation (PAM) and pulse width modulation (PWM). In traditional organic light-emitting diode microdisplays, grayscale display is mainly achieved by voltage-controlled current flowing through the pixel, which is the PAM driving method.

[0007] However, because the wavelength and luminous efficiency of micro-LEDs vary with the current density flowing through them, PAM is not suitable for driving micro-LEDs. A constant current is required to drive the micro-LEDs, and then pulse width modulation (PWM) is used to adjust the proportion of time the micro-LED branch is on.

[0008] However, in the circuit that generates the PWM signal, additional data storage units are required, resulting in a larger circuit area. In addition, during the transmission of the current signal, there are problems such as inaccurate current replication, which leads to instability of the current signal.

[0009] Summary of the Invention

[0010] The embodiments of the present application provide a micro display circuit and control method, a display chip, and an electronic device, which meet the application requirements of smaller area size and higher current replication accuracy.

[0011] To achieve the above objectives, this application adopts the following technical solutions:

[0012] In a first aspect, an embodiment of the present application provides a micro-display circuit, comprising: a pixel array including a plurality of pixel circuits, each of the plurality of pixel circuits including a pulse-width modulation signal generating branch, a light-emitting diode, and a mirror current branch. The pulse-width modulation signal generating branch includes a first static memory. A pixel array common circuit is used to transmit a current signal to the pixel array, and the plurality of pixel circuits sequentially and orderly receive the current signal from the pixel array common circuit. The pixel array common circuit includes a second static memory and a reference current branch. The mirror current branch in each pixel circuit forms a current mirror symmetrical structure with the reference current branch. The circuit structure of the first static memory is consistent with that of the second static memory.

[0013] The reference current branch of the pixel array common circuit and the mirror current branch of the pixel circuit form a current mirror, replicating the current of the pixel array common circuit and transmitting it to the pixel circuit. The pulse width modulation signal generation branch of the pixel circuit generates a pulse width modulation signal PWM, which controls whether the light-emitting diode emits light and the duration of the light-emitting diode's conduction. The first static memory of the pixel circuit and the second static memory of the pixel array common circuit have the same circuit structure, ensuring that the potential of the input terminal of the reference current branch of the current mirror is consistent with the potential of the input terminal of the mirror current branch. This circuit structure design improves the accuracy of current replication. The same pixel array common circuit provides current signals to multiple pixel circuits. This one-to-many structural design also correspondingly reduces the required pixel circuit area.

[0014] In one possible design, a pulse-width modulation signal generation branch is configured to generate a pulse-width modulation signal; the output of the pulse-width modulation signal generation branch is coupled in series with the mirror current branch. This direct series connection of the pulse-width modulation signal generation branch with the mirror current branch suppresses grayscale loss caused by transistor leakage.

[0015] In one possible design, the mirror current branch includes a first transistor; the output of the pulse-width modulation signal generating branch is coupled to the first electrode of the first transistor. Directly connecting the pulse-width modulation signal to the branch containing the light-emitting diode further suppresses light leakage from the light-emitting diode due to transistor leakage when the light-emitting diode is in the off state.

[0016] In a possible design, the pulse width modulation signal has multiple duty cycles; the pulse width modulation signals with different duty cycles are used to control different on-times of the light emitting diode.

[0017] In one possible design, the first static memory receives and stores the data voltage signal. The first static memory includes a first inverter, a second inverter, a first scan switch, and a second scan switch. The first inverter and the second inverter form a cross-coupled bistable structure.

[0018] In a possible design, the data voltage signal received by the input terminal of the first scan switch and the data voltage signal received by the input terminal of the second scan switch have opposite phases.

[0019] In one possible design, the pulse-width modulation signal generation branch also includes a logic control branch, which receives the transmit enable signal and the data signal of the first static memory to generate a pulse-width modulation signal. The output signal of the logic control branch determines whether the pixel micro-LED emits light. This unique logic control branch effectively solves the problem of insufficient display accuracy caused by the off-state current of the transistor.

[0020] In one possible design, the logic control branch includes a first enabling switch tube, the second electrode of the first enabling switch tube is coupled to the first electrode of the first transistor, the first electrode of the first enabling switch tube is coupled to the reference ground voltage terminal, and the control electrode of the first enabling switch tube receives an enable transmission signal.

[0021] In one possible design, the mirror current branch also includes a second transistor, the second electrode of the first transistor is coupled to the first electrode of the second transistor, the second electrode of the second transistor is coupled to the first electrode of the light-emitting diode, and the second electrode of the light-emitting diode is coupled to the DC voltage end.

[0022] In one possible design, the pixel circuit also includes a reverse-biased diode, with the LED connected in parallel. By incorporating the reverse-biased diode into the pixel circuit, the reverse-biased current flowing through the diode is used to shunt the transistor's leakage current, thereby reducing the off-state current flowing through the micro-LED.

[0023] In one possible design, the reference current branch includes a third transistor and a fourth transistor, the first electrode of the third transistor is coupled to the output end of the second static memory, the second electrode of the third transistor is coupled to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is coupled to the control electrode of the third transistor; the control electrode of the first transistor and the control electrode of the third transistor are both coupled to the second electrode of the fourth transistor, and the control electrode of the second transistor is coupled to the control electrode of the fourth transistor.

[0024] In one possible design, the pixel array common circuit further includes a bias generating branch, which is used to generate a constant bias voltage; the bias generating branch includes a first bias transistor, a second bias transistor, and a bandgap reference current source. The bias voltage causes the first transistor, the second transistor, the third transistor, and the fourth transistor to all operate in the saturation region. When all four transistors operate in the saturation region, the current flowing through the transistor depends only on the gate-source voltage VGS and has nothing to do with the drain-source voltage VDS. In this way, by simply controlling the gate-source voltages of the first and third transistors to be consistent, and the gate-source voltages of the second and fourth transistors to be consistent, the current replication accuracy can be ensured to be more accurate.

[0025] In one possible design, the first electrode of the first bias tube is coupled to the power supply voltage terminal, the second electrode of the first bias tube is coupled to the first electrode of the second bias tube, the second electrode of the second bias tube is coupled to the bandgap reference current source, and the control electrode of the first bias tube, the control electrode of the second bias tube, and the second electrode of the second bias tube are all coupled to the control electrode of the fourth transistor.

[0026] In one possible design, the micro display circuit also includes a constant current generating circuit, which includes a first constant current switch tube, a second constant current switch tube and a third constant current switch tube; the control electrode of the first constant current switch tube and the control electrode of the second constant current switch tube are coupled; the first electrode of the first constant current switch tube and the first electrode of the second constant current switch tube are commonly coupled to the DC voltage end.

[0027] In one possible design, the constant current generating circuit further includes a first operational amplifier; a first input of the first operational amplifier is coupled to the second electrode of the first constant current switch tube; a second input of the first operational amplifier is coupled to the control electrode of the first constant current switch tube, the control electrode of the second constant current switch tube, and the second electrode of the second constant current switch tube; and an output of the first operational amplifier is coupled to the control electrode of the third constant current switch tube. The virtual short characteristic of the operational amplifier is utilized to improve the current replication accuracy of the first-stage current mirror, and the structural symmetry and matching within the pixel array are utilized to improve the replication accuracy of the second-stage current mirror.

[0028] In a possible design, a second electrode of the third constant current switch N9 is coupled to an input terminal of the pixel array common circuit.

[0029] In a second aspect, an embodiment of the present application also provides a control method for a micro-display circuit, including: generating a constant current signal; receiving and copying the constant current signal; generating a pulse width modulation signal, under the action of the pulse width modulation signal, the constant current signal drives the light-emitting diode to display light.

[0030] In a third aspect, an embodiment of the present application further provides a display chip, comprising the micro display circuit according to the first aspect, and a processor coupled to the micro display circuit.

[0031] In a fourth aspect, an embodiment of the present application further provides an electronic device comprising the display chip according to the third aspect and a printed circuit board. The display chip is disposed on the printed circuit board and is used to display light. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic diagram of an electronic device provided in an embodiment of the present application;

[0033] FIG2 is a schematic diagram of a display chip provided in an embodiment of the present application;

[0034] FIG3 is a schematic diagram of a micro display circuit structure provided in an embodiment of the present application;

[0035] FIG4 is a schematic diagram of another micro-display circuit structure provided in an embodiment of the present application;

[0036] FIG5 is a schematic diagram of the overall architecture of a micro-display circuit structure provided in an embodiment of the present application;

[0037] FIG6 a is a schematic diagram showing the relationship between a pixel array and a pixel circuit according to an embodiment of the present application;

[0038] FIG6 b is a schematic diagram showing the relationship between the pixel circuit and the pixel array common circuit provided in an embodiment of the present application;

[0039] FIG7 is a schematic diagram of a micro display circuit structure provided in an embodiment of the present application;

[0040] FIG8 is a schematic diagram of another micro-display circuit structure provided in an embodiment of the present application;

[0041] FIG9 is a schematic diagram of a pixel circuit structure provided by an embodiment of the present application;

[0042] FIG10 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application;

[0043] FIG11 is a schematic diagram of another pixel circuit structure provided in an embodiment of the present application;

[0044] FIG12 is a schematic diagram of another micro-display circuit structure provided in an embodiment of the present application;

[0045] FIG13 is a schematic diagram of another micro-display circuit structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0047] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0048] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0049] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0050] The terms "coupling" and "coupling" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or they may refer to an indirect connection achieved through an electronic device, such as a connection achieved through a resistor, inductor, capacitor or other electronic device. In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B may be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0051] First, some basic concepts involved in the embodiments of this application are explained:

[0052] Silicon-based microdisplay technology: Traditional silicon-based microdisplay technologies include silicon-based liquid crystal technology (LCoS) and silicon-based organic light-emitting diode technology (OLEDoS). The latest silicon-based microdisplay technology is silicon-based Micro-LED (LEDoS) microdisplay technology.

[0053] Light-emitting diodes (LEDs) are made from compounds containing gallium (Ga), arsenic (As), phosphorus (P), and nitrogen (N). They are manufactured based on the principle that electrons (electrons) and holes (holes) can emit visible light when they recombine. Gallium arsenide (GaAs)-based LEDs emit red light, gallium phosphide (GP)-based LEDs emit green light, silicon carbide (SiC)-based LEDs emit yellow light, and gallium nitride (GN)-based LEDs emit blue light. LEDs were initially used for indicator lighting in instruments and meters, and later expanded to traffic lights. They were then used in landscape lighting, automotive lighting, and mobile phone keypads and backlights. Later, a new technology, micro light-emitting diodes (MLEDs), was developed. These MLEDs significantly reduced the size of conventional LEDs, arranging independently emitting red, blue, and green microLEDs in arrays to form display arrays for application in display technology. MLEDs exhibit self-luminous properties. Compared to self-luminous organic light-emitting diodes (OLEDs), MLEDs offer higher efficiency, longer lifespan, and are less susceptible to environmental influences and more stable materials.

[0054] Like ordinary diodes, light-emitting diodes (LEDs) consist of a PN junction and exhibit unidirectional conductivity. The core of an LED is a wafer composed of a P-type semiconductor and an N-type semiconductor, separated by a transition layer called the PN junction. In certain semiconductor materials, when injected minority carriers recombine with majority carriers in the PN junction, they release excess energy as light, thereby directly converting electrical energy into light. When a reverse voltage is applied to the PN junction, minority carriers are difficult to inject, resulting in no light. When a forward voltage is applied to the LED, holes injected from the P region into the N region and electrons injected from the N region into the P region recombine with electrons in the N region and holes in the P region, respectively, within a few microns of the PN junction, generating spontaneous fluorescence. The energy states of electrons and holes in different semiconductor materials vary. The amount of energy released when electrons and holes recombine varies; the greater the energy released, the shorter the wavelength of the emitted light. LEDs are commonly found emitting red, green, or yellow light. When it is in the forward working state (that is, a forward voltage is applied to both ends), when the current flows from the anode to the cathode of the LED, the semiconductor crystal emits light of different colors from ultraviolet to infrared, and the intensity of the light is related to the current.

[0055] Pulse amplitude modulation signal driving method: Different voltage values ​​are applied between the two electrodes of the light-emitting diode, and the voltage is used to control the magnitude of the current flowing through the light-emitting diode to change the brightness of the light-emitting diode.

[0056] The driving mode of the pulse width modulation signal is to modulate the time ratio of the light-emitting diode branch to control the conduction time of the light-emitting diode branch to adjust the grayscale.

[0057] Pixel: A digital image is composed of many dots, called pixels. A pixel is the smallest imaging unit of a display screen and is typically composed of one or more light-emitting diodes. For example, some display designs may use the pixel 2R1G1B, meaning the display's smallest imaging unit is composed of two red LEDs, one green LED, and one blue LED. (In the display industry, red, green, and blue LEDs are typically represented by their respective letters, R, G, and B.)

[0058] Grayscale: Grayscale represents the different levels of brightness from brightest to darkest. The more grayscale levels there are, the more detailed the image will be.

[0059] An embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronic products include communication equipment such as servers, storage devices, radars, and base stations.

[0060] The following description will be given by taking a mobile phone as an example of an electronic device.

[0061] Figure 1 is a schematic diagram of an electronic device 10 provided in an embodiment of the present application. As shown in Figure 1 , electronic device 10 primarily includes a cover plate 11, a display panel 12, a midframe 13, and a rear housing 14. The rear housing 14 and display panel 12 are located on either side of the midframe 13, respectively. The midframe 13 and display panel 12 are disposed within the rear housing 14. The cover plate 11 is disposed on the side of the display panel 12 away from the midframe 13, with the display surface of the display panel 12 facing the cover plate 11.

[0062] The display panel 12 may be a liquid crystal display (LCD) panel. In this case, the LCD panel includes a liquid crystal display panel and a backlight module. The LCD panel is disposed between the cover plate 11 and the backlight module, and the backlight module is used to provide light for the LCD panel. The display panel 12 may also be an organic light emitting diode (OLED) display panel. Since OLED display panels are self-luminous, a backlight module is not required.

[0063] The display chip is one of the main control components of the display panel 12. Its main function is to display images on the screen by controlling the screen brightness and color. As shown in Figure 2, the display chip can include one or more of the following components: a processor 21, a memory 22, and a micro-display circuit 23.

[0064] The processor 21 may include one or more processing cores. The processor 21 utilizes various interfaces and lines to connect the various parts of the entire display chip. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 22, and calling data stored in the memory 22, the processor 21 performs various functions of the display chip and processes data. For example, the processor 21 can be implemented in the form of at least one hardware of digital signal processing (DSP) and programmable logic array (PLA). The processor 21 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), an application processor (AP), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs. The GPU is responsible for rendering and drawing the content to be displayed. The NPU is used to implement artificial intelligence (AI) functions. The modem is used to handle wireless communications. It is understandable that the above-mentioned modem can also be implemented separately through a chip without being integrated into the processor 21.

[0065] The memory 22 may include a random access memory (RAM) or a read-only memory (ROM). For example, the memory 22 includes a non-transitory computer-readable storage medium (non-transitory computer-readable storage medium), and the memory 22 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 22 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing various method embodiments of the present application, etc. The data storage area may store data created according to the use of the display chip, etc.

[0066] The micro display circuit 23 is used to receive instructions from the processor 21 and control the grayscale display of the silicon-based micro display of the micro light emitting diode.

[0067] As shown in Figure 3, in some embodiments, the micro-display circuit includes a static random access memory (SRAM), a counter, a comparator, a cascaded current mirror circuit, and a switch tube. The comparator generates a pulse width modulation signal PWM to control the time of the current flowing through the light-emitting diode, thereby realizing the modulation of the display grayscale. Specifically, by comparing the data stored in the static random access memory (SRAM) with the data of the counter, a pulse width modulation signal PWM with different pulse widths is obtained, and then the signal is used to control the on and off of the switch tube of the light-emitting path to control the brightness of the micro light-emitting diode. The micro-display circuit also includes a cascaded current mirror circuit and a switch tube. The cascaded current mirror circuit adopts a low-voltage common source and common gate structure to generate a precise and constant current.

[0068] However, in this embodiment, the circuit structure for generating the pulse width modulation signal PWM is very complex, including a static random access memory (SRAM), a counter, and a comparator, which occupies a large amount of circuit area outside the pixel array. This makes it difficult to apply to micro-display applications that have strict requirements on external storage space.

[0069] In other embodiments, as shown in Figure 4, the micro-display circuit includes a static random access memory (SRAM), an enable transistor M33, and a switch control transistor M29. The output of the static random access memory (SRAM) is coupled to the gate of the switch control transistor M29, and the enable transistor M33 is connected in parallel with the light-emitting diode D1. The data storage signal SPWM and the enable emission signal EM jointly generate a pulse width modulation signal PWM, which is used to control whether the light-emitting diode D1 is turned on and the on-time.

[0070] For example, when the pulse-width modulation signal PWM is high, the switch control transistor M29 is turned on, and the light-emitting diode D1 emits light. Simultaneously, the duty cycle of the pulse-width modulation signal modulated to a high level (i.e., the proportion of the effective pulse width, which is controlled by the enable emission signal EM) can adjust the duration of the light-emitting diode D1. When the pulse-width modulation signal PWM is low, the switch control transistor M29 is not turned on, and the light-emitting diode D1 does not emit light.

[0071] The micro display circuit further includes a constant current driving transistor M1, a current data writing transistor M12, and a first storage capacitor C11 and a second storage capacitor C32. The first storage capacitor C11 and the second storage capacitor C32 maintain a constant current by holding the current signal.

[0072] However, in this embodiment, due to leakage in the data write transistor M12, the stored charge in the first storage capacitor C11 and the second storage capacitor C32 changes, which in turn causes the current flowing through the constant current drive transistor M1 to change, becoming not completely constant, thereby affecting the luminous efficiency and wavelength of the light-emitting diode D1. In addition, the circuit structure for generating the pulse width modulation signal PWM is not streamlined enough, requiring at least 8 transistors. Furthermore, since the output terminal of the static random access memory SRAM is coupled to the gate of the switch control transistor M29, and the first electrode of the switch control transistor M29 is coupled to the power supply voltage VDD, the gate-source voltage VGS of the switch control transistor M29 is at least 0V. At this time, although the switch control transistor M29 is in the off state, it still suffers from transistor leakage, causing the light-emitting diode D1 to be dimly illuminated and not completely turned off.

[0073] Based on this, an embodiment of the present application proposes a micro-display circuit, which includes a constant current generating circuit, a pixel array common circuit, and a pixel array composed of multiple pixel circuits. The micro-display circuit uses fewer transistors, thereby making the area size of the pixel circuit smaller. In addition, the coupling method of the transistor devices in the micro-display circuit can alleviate the leakage problem of the transistors in the pixel circuit. On this basis, the constant current generating circuit and the pixel array common circuit both adopt a current mirror structure with high replication accuracy to provide a constant current to ensure the high luminous efficiency and stable luminous wavelength of the light-emitting diode D1.

[0074] As shown in FIG5 , a micro display circuit proposed in an embodiment of the present application mainly includes:

[0075] The constant current generating circuit is used to generate a constant current signal to provide a constant current to the pixel array common circuit and the pixel array.

[0076] The two important control signals for driving the micro-light emitting diode to display light are: pulse width modulation signal PWM and constant current signal. In the embodiment of the present application, the constant current generating circuit adopts a current mirror structure to generate a constant current signal. Since the light-emitting wavelength and light-emitting efficiency of the micro-light emitting diode will change with the current density flowing through it, in order to maintain the stable light-emitting wavelength and high light-emitting efficiency of the micro-light emitting diode, it is necessary to maintain a constant current to drive it to display light. Then, the pulse width modulation signal PWM is used to adjust the proportion of time that the branch where the micro-light emitting diode is located is turned on to control whether the light-emitting diode on the branch is lit and to control the light intensity of the light-emitting diode on the branch.

[0077] The pixel array common circuit is coupled to the output end of the constant current generating circuit, and is used for receiving the current signal of the constant current generating circuit and transmitting the current signal to the pixel array.

[0078] The pixel array includes a plurality of pixel circuits, which sequentially and orderly receive the current signal of the pixel array common circuit. The relationship between the overall framework of the pixel array, the pixel circuit, and the pixel array common circuit is shown in Figures 6a and 6b. The pixel array includes M×N blocks, and each block includes K×L pixel circuits. All K×L pixel circuits in each block sequentially receive the reference current provided by the same pixel array common circuit. The pixel circuit includes a mirror current branch, and the pixel array common circuit includes a reference current branch. The mirror current branch and the reference current branch form a current mirror structure to reduce the area and power consumption of the entire circuit layout.

[0079] The number of blocks is determined based on power consumption and layout area.

[0080] The number of pixel circuits within a block needs to be determined based on the replication accuracy of the current mirror. Due to manufacturing errors, such as inconsistent channel width-to-length ratios and different threshold voltages of the two symmetrical transistors of the current mirror, the replication of the current mirror may be inaccurate.

[0081] This situation causes inaccurate replication by the current mirror.

[0082] As the number of pixel circuits within a block increases, the spacing between them increases, increasing the distance between the transistors in the mirror current branch within the pixel circuit and the transistors in the reference current branch within the pixel array shared circuit. During chip manufacturing, the greater the distance between two symmetrical transistors within the current mirror, the greater the deviation in their aspect ratio and threshold voltage. This reduces the matching between the two symmetrical transistors within the current mirror, leading to a decrease in the current mirror's replication accuracy. In summary, the number of pixel circuits within a block should be appropriately arranged, taking into account the impact and limitations of chip manufacturing technology on current mirror replication accuracy.

[0083] In the overall microdisplay circuit topology, the current mirror outside the pixel array is responsible for replicating and transmitting current to the pixel array. This branch consumes the greatest static power. By dividing the pixel array into blocks, the number of current transmission branches can be reduced. The number of current transmission branches corresponds to the number of blocks. While meeting the required current replication accuracy, maximizing the number of blocks can achieve lower power consumption.

[0084] As shown in FIG. 7 , in some embodiments, each of the plurality of pixel circuits includes a pulse width modulation signal generating branch and a light emitting diode D1 .

[0085] The pulse width modulation signal generating branch is used to generate a pulse width modulation signal. The output end of the pulse width modulation signal generating branch is coupled in series with the mirror current branch.

[0086] In some possible designs, the mirror current branch includes a first transistor P1 , and an output terminal of the pulse width modulation signal generating branch is coupled to a first electrode of the first transistor P1 .

[0087] The PWM signal has various duty cycles, and the PWM signals with different duty cycles are used to control whether the light-emitting diode emits light and the duration of the conduction.

[0088] The pulse width modulation signal generating branch includes a first static memory.

[0089] In some possible designs, as shown in FIG7 , the first static memory SRAM1 includes a first inverter, a second inverter, a first scan switch N3, and a second scan switch N6. The first inverter includes a first coupling transistor N4 and a second coupling transistor P5, and the second inverter includes a third coupling transistor N5 and a fourth coupling transistor P6. The first inverter and the second inverter form a cross-coupled topology structure, wherein the first pole of the first scan switch N3, the output end of the first inverter, and the input end of the second inverter are all coupled to node a', and the first pole of the second scan switch N6, the output end of the second inverter, and the input end of the first inverter are all coupled to node b'. This dual-inverter cross-coupling connection method ensures that the data voltage signal is maintained for a long time. Due to the positive feedback mechanism of the circuit structure, the data voltage signal can be maintained for a long time in the first static memory SRAM1. For example, the first data voltage signal at the same node a' The data voltage signal stored at the node a′ is strengthened by both writing through the first scan switch N3 and inputting the second data voltage signal DL through the second inverter.

[0090] The data voltage signal received at the input terminal of the first scan switch N3 and the data voltage signal received at the input terminal of the second scan switch N6 have opposite phases.

[0091] Specifically, the second electrode of the first scan switch N3 is connected to the first data voltage signal The first electrode of the first scan switch N3, the control electrode of the third coupling transistor N5, and the control electrode of the fourth coupling transistor P6 are commonly coupled to node a', and the second electrode of the third coupling transistor N5 and the second electrode of the fourth coupling transistor P6 are coupled to node b'. The second electrode of the second scan switch N6 receives the second data voltage signal DL, the first electrode of the second scan switch N6, the control electrode of the first coupling transistor N4 and the control electrode of the second coupling transistor P5 are commonly coupled to node b', and the second electrode of the first coupling transistor N4 and the second electrode of the second coupling transistor P5 are commonly coupled to node a'. The first electrode of the second coupling transistor P5 and the first electrode of the fourth coupling transistor P6 are both coupled to the power supply voltage terminal VDD, and the first electrode of the first coupling transistor N4 and the first electrode of the third coupling transistor N5 are both coupled to the reference ground voltage terminal VSS.

[0092] When the second data voltage signal DL is transmitted to the node b' through the second scan switch N6, it is transmitted to the node a' through the first inverter composed of the first coupling transistor N4 and the second coupling transistor P5. At this time, it becomes a signal with an opposite phase to the input second data voltage signal DL. and the first data voltage signal at the other end The signal transmitted to the node a' through the first scan switch N3 is consistent, so the data voltage signal stored in the node a' is strengthened. When transmitted to node a' through the first scan switch N3, the signal transmitted to node b' through the second inverter composed of the third coupling transistor N5 and the fourth coupling transistor P6 is consistent with the signal of the second data voltage signal DL at the other end transmitted to node b' through the second scan switch N6. The data voltage signal at node b' is also strengthened.

[0093] Therefore, the cross-coupled bistable structure formed by the dual inverters can achieve long-term storage of the data voltage signal due to the positive feedback mechanism in the circuit.

[0094] In some possible designs, the pulse width modulation signal generating branch further includes a logic control branch, which is configured to receive the emission enable signal EM and the data signal of the first static memory SRAM1 to generate the pulse width modulation signal PWM.

[0095] In some possible designs, the logic control branch includes a first enabling switch N1. A first electrode of the first enabling switch N1 is coupled to a reference ground voltage terminal VSS. A second electrode of the first enabling switch N1 and an output terminal of a first static memory SRAM1 are both coupled to a first node A. The output terminal of the first static memory SRAM1 is configured to output a data storage signal SPWM, which controls whether a light-emitting diode D1 emits light. The light-emitting diode D1 may only turn on and emit light when the pulse-width modulation signal PWM is at an active level. Whether the light-emitting diode D1 emits light depends on the first enabling switch N1.

[0096] The control electrode of the first enabling switch N1 receives the emission enable signal EM, which is used to control the duration of the light-emitting diode D1's illumination. This signal, combined with the data storage signal SPWM output from the first static memory SRAM1, generates a pulse-width modulation signal PWM. The pulse-width modulation signal PWM is only valid, and the light-emitting diode D1 is turned on and illuminated, only when both the emission enable signal EM and the data storage signal SPWM output from the first static memory SRAM1 are simultaneously valid.

[0097] When the emission enable signal EM is at a high level, it is transmitted to the control electrode of the first enable switch N1. Since the first electrode of the first enable switch N1 is coupled to the reference ground voltage terminal VSS, the first enable switch N1 is turned on. The signal at the first node A is affected not only by the signal at the reference ground voltage terminal VSS, but also by the second data voltage signal DL of the first static memory SRAM1. Therefore, the signal at the first node A is in an unstable state. However, when the emission enable signal EM is at a low level, the gate-source voltage of the first enable switch N1 is less than the threshold voltage, and the first enable switch N1 is in an off state. The signal at the first node A is the second data voltage signal DL, which serves as the output signal of the pulse width modulation signal generation branch.

[0098] Therefore, the output signal PWM of the pulse width modulation signal generating branch is valid only when the enable emission signal EM is at a low level. The low level duration of the enable emission signal EM controls the effective level duration of the output signal PWM of the pulse width modulation signal generating branch, thereby controlling the light-emitting duration of the light-emitting diode D1.

[0099] The pixel circuit includes not only the pulse width modulation signal generating branch mentioned above, but also a mirror current branch.

[0100] The pixel array common circuit comprises a reference current branch, and the reference current branch and the mirror current branch form a current mirror symmetrical structure.

[0101] In some embodiments, as shown in FIG7 , the current mirror symmetrical structure formed by the reference current branch and the mirror current branch is a low-voltage common-source common-gate current mirror structure, and the mirror current branch is used to receive the reference current signal provided by the reference current branch and generate a replica current.

[0102] This current mirror structure has two obvious advantages: first, all transistors in the reference current branch and the mirror current branch can obtain a smaller source and drain voltage difference, that is, a smaller voltage margin, thereby ensuring that each transistor operates in a saturated state; second, since the low-voltage common source and common gate structure is conducive to reducing the influence of the channel modulation effect in the transistor on the current replication accuracy, the mirror current branch can obtain higher current replication accuracy.

[0103] In other possible designs, the current mirror symmetrical structure composed of the reference current branch and the mirror current branch is the most basic current mirror structure, which consists of a diode-connected transistor and a single-tube amplifier. The former converts the current of the input bandgap reference current source into voltage, and the latter converts the voltage into current.

[0104] In some other possible designs, the current mirror symmetrical structure formed by the reference current branch and the mirror current branch is a common-gate common-source current mirror, or a current mirror structure of a bipolar current source.

[0105] In some possible designs, the current mirror branch includes a first transistor P1 and a second transistor P3. The second electrode of the first transistor P1 is coupled to the first electrode of the second transistor P3, the second electrode of the second transistor P3 is coupled to the first electrode of the light-emitting diode D1, and the second electrode of the light-emitting diode D1 is coupled to the DC voltage terminal VSSA.

[0106] As shown in Figure 7, the branch containing LED D1 is connected in parallel with the branch containing reverse-biased diode D2. The anode of LED D1 and the cathode of reverse-biased diode D2 are both coupled to node E. The cathode of LED D1 and the anode of reverse-biased diode D2 are both coupled to DC voltage terminal VSSA. The voltage value of DC voltage terminal VSSA depends on the manufacturing process of LED D1.

[0107] When the data storage signal SPWM and the enable emission signal EM of the first enable switch tube N1 are both at valid levels, the light-emitting diode D1 is driven to turn on, and the current flowing through the light-emitting diode D1 is on the order of microamperes, and the current flowing through the reverse-biased diode D2 is on the order of picoamperes. Therefore, the current in the branch where the reverse-biased diode D2 is located has almost no effect on the current in the branch where the light-emitting diode D1 is located.

[0108] When one of the data storage signal SPWM and the enable emission signal EM received by the control electrode of the first enable switch tube N1 is at an invalid level, the light-emitting diode D1 is turned off. Ideally, the branch where the light-emitting diode D1, the first transistor P1, and the second transistor P3 are located is open circuit. However, due to leakage between the first transistor P1 and the second transistor P3, a small amount of picoampere-level current still flows through the light-emitting diode D1, causing the light-emitting diode D1 to glow slightly. Therefore, the light-emitting diode D1 cannot reach a true off state. The presence of the reverse-biased diode D2 serves to shunt the current for the light-emitting diode D1. The current flowing out of the second electrode of the second transistor P3 is shunted by the light-emitting diode D1 and the reverse-biased diode D2, thereby further reducing the current flowing through the light-emitting diode D1, making the light-emitting diode D1 in a darker state.

[0109] Due to the limitations of the manufacturing process, the light-emitting diode D1 adopts a common cathode connection mode under the joint action of multiple pixels.

[0110] In other embodiments, as shown in FIG8 , a common anode connection method may be used, with a topology similar to that of a common cathode connection method. For a pixel circuit with a common anode connection method, the current mirror module may be fabricated using N-type transistors. The remaining circuit logic, current mirror topology, and timing scheme of the pulse width modulation signal generation branch are consistent with those of the common cathode connection pixel circuit described above.

[0111] In some possible designs, the pixel array common circuit further includes a second static memory SRAM 2. The circuit structure of the second static memory SRAM 2 is the same as that of the first static memory SRAM 1.

[0112] The circuit structure consisting of the second static memory SRAM2 and the second enabling switch N2 is mirrored with the circuit structure consisting of the first static memory SRAM1 and the first enabling switch N1. This allows the current mirror to replicate the current more accurately when the pulse width modulation signal PWM at the first node A is valid.

[0113] The first input terminal of the second static memory SRAM2 is coupled to the power supply voltage terminal VDD, and the second input terminal of the second static memory SRAM2 is coupled to the reference ground voltage terminal VSS. Therefore, the output signal at the second node B is always at a high level, thereby ensuring that the third transistor P2 and the fourth transistor P4 always operate in the saturation region. If the output signal at the second node B is at a low level, the operating states of the third transistor P2, the fourth transistor P4, the third constant current switch N9, and the first constant current switch N7 all leave the saturation region, resulting in a loss of the replication accuracy of the current mirror in the constant current generation circuit, which will be further described later.

[0114] The reference current branch is used to receive the output current of the constant current generating circuit. The reference current branch includes a third transistor P2 and a fourth transistor P4. The first electrode of the third transistor P2 and the output end of the second static memory SRAM2 are both coupled to the second node B, the second electrode of the third transistor P2 is coupled to the first electrode of the fourth transistor P4, and the second electrode of the fourth transistor P4 is coupled to the output end of the constant current generating circuit. The control electrode of the first transistor P1, the control electrode of the third transistor P2, and the second electrode of the fourth transistor P4 are all coupled to the third node C, and the control electrode of the second transistor P3 is coupled to the control electrode of the fourth transistor P4.

[0115] The reference current branch and the mirror current branch form a low-voltage cascode current mirror structure. The main structural features of this low-voltage cascode current mirror are: the second electrode of the first transistor P1 is coupled to the first electrode of the second transistor P3, the second electrode of the third transistor P2 is coupled to the first electrode of the fourth transistor P4, the control electrode of the first transistor P1 is coupled to the control electrode of the third transistor P2, and the control electrode of the second transistor P3 is coupled to the control electrode of the fourth transistor P4. The first electrode of the first transistor P1 is coupled to the first node A for receiving a pulse width modulation signal PWM. The pulse width modulation signal PWM flows from the first electrode of the first transistor P1 through the second electrode of the first transistor P1, then through the first and second electrodes of the second transistor P3, and finally drives the light-emitting diode D1 to operate.

[0116] Although this low-voltage cascode current mirror structure is beneficial for reducing the impact of the channel modulation effect on the current replication accuracy and improving the current replication accuracy, it also adds an additional bias generation branch, resulting in an increase in circuit cost and area.

[0117] The bias generation branch is used to provide a bias voltage Vbias1. This bias voltage causes the first transistor P1, the second transistor P3, the third transistor P2, and the fourth transistor P4 to operate in the saturation region. When all four transistors operate in the saturation region, the current flowing through the transistor depends only on the gate-source voltage VGS and is independent of the drain-source voltage VDS. In this way, by simply controlling the gate-source voltages of the first transistor P1 and the third transistor P2 to be consistent, and the gate-source voltages of the second transistor P3 and the fourth transistor P4 to be consistent, the current replication accuracy can be ensured to be more accurate.

[0118] In some possible designs, the bias generating branch includes a first bias transistor p1', a second bias transistor p2' and a bandgap reference current source. The first electrode of the first bias transistor p1' is coupled to the power supply voltage terminal VDD, the second electrode of the first bias transistor p1' is coupled to the first electrode of the second bias transistor p2', and the second electrode of the second bias transistor p2' is coupled to the bandgap reference current source I BIASThe control electrode of the first bias transistor p1 ′, the control electrode of the second bias transistor p2 ′, and the second electrode of the second bias transistor p2 ′ are all coupled to the control electrode of the fourth transistor P4 .

[0119] The bias voltage generation branch also consumes power, and the power consumption is proportional to the number of bias voltage generation branches. In order to reduce the number of bias voltage generation branches, multiple blocks can share one bias voltage generation circuit.

[0120] In some possible designs, the constant current generating circuit includes a first constant current switch transistor N7, a second constant current switch transistor N8, and a third constant current switch transistor N9. The control electrode of the first constant current switch transistor N7 is coupled to the control electrode of the second constant current switch transistor. The first electrode of the first constant current switch transistor N7 and the first electrode of the second constant current switch transistor N8 are commonly coupled to the DC voltage terminal Vbias.

[0121] In some possible designs, the constant current generating circuit further includes a first operational amplifier AMP. A first input terminal of the first operational amplifier AMP is coupled to the second electrode of the first constant current switch tube N7, a second input terminal of the first operational amplifier AMP is coupled to the control electrode of the first constant current switch tube N7, the control electrode of the second constant current switch tube N8, and the second electrode of the second constant current switch tube N8, and an output terminal of the first operational amplifier AMP is coupled to the control electrode of the third constant current switch tube N9.

[0122] The first constant current switch tube N7, the second constant current switch tube N8, the third constant current switch tube N9 and the first operational amplifier AMP together form a current mirror structure, and the bandgap reference current source I BIAS A constant current is fed into the current mirror.

[0123] A first electrode of the third constant current switch tube N9 is coupled to a second electrode of the first constant current switch tube N7 , and a second electrode of the third constant current switch tube N9 is coupled to an input end of the pixel array common circuit to provide a constant current to the pixel array common circuit.

[0124] Since the first electrode of the first constant current switch tube N7 and the first electrode of the second constant current switch tube N8 are commonly coupled to the DC voltage terminal Vbias, the control electrode voltage values ​​of the first constant current switch tube N7 and the second constant current switch tube N8 are the same. Since the control electrode of the first constant current switch tube N7 and the control electrode of the second constant current switch tube N8 are commonly coupled to the second input terminal of the first operational amplifier AMP, the first electrode voltage values ​​of the first constant current switch tube N7 and the second constant current switch tube N8 are the same.

[0125] Due to the virtual short characteristic of the first operational amplifier AMP's input terminals, the voltages at the two input terminals of the first operational amplifier AMP are equal. Therefore, the voltages at the second terminals of the first constant current switch N7 and the second constant current switch N8, which are respectively coupled to the two input terminals of the first operational amplifier AMP, are also equal. Therefore, the presence of the first operational amplifier AMP further improves the accuracy of current replication in the current mirror.

[0126] The topology of the pulse width modulation signal generating branch provided in the embodiment of the present application is more streamlined and can be implemented with only 7 transistors, thereby minimizing the area of ​​the digital logic part and being suitable for applications in pixel circuits of micron size.

[0127] Since the current accuracy directly affects the wavelength and luminous efficiency of the micro-LED, it is directly related to the layout area and the topology of the circuit. BIAS A constant current is input, replicated by a current mirror consisting of the first constant-current switch N7, the second constant-current switch N8, the third constant-current switch N9, and the first operational amplifier AMP. This constant current is then delivered to the pixel array common circuit. A low-voltage cascode current mirror, comprised of a mirror current branch and a reference current branch, replicates this current and transmits it to the pixel circuit. Under the combined control of the pixel circuit's data storage signal SPWM and the emission enable signal EM, a pulse-width modulation signal PWM is generated, which controls whether the light-emitting diode D1 emits light and the duration of its on-state.

[0128] The low-voltage common-gate and common-source current mirror structure not only improves the current replication accuracy, but also correspondingly reduces the pixel circuit area required by the current mirror part.

[0129] In addition, the mirror branches of multiple pixel circuits are used to correspond to the reference current branch of the same pixel array common circuit. In different time periods, the mirror branches of multiple pixel circuits alternately receive the current signal of the reference current branch and replicate the reference current.

[0130] Because the transistor still has picoampere-level leakage when it is off, the off-state current of the micro-LED cannot be reduced to below picoamperes, and light leakage still occurs in the dark state. By introducing a reverse-biased diode in the pixel circuit, the reverse current conducted by the diode is used to shunt the transistor's leakage, thereby reducing the off-state current flowing through the micro-LED.

[0131] There are many other implementations of the pulse-width modulation signal generation branch. In other embodiments, as shown in FIG9 , the pulse-width modulation signal generation branch includes a first static memory SRAM1 and a logic control branch. The logic control branch includes a first series enable transistor P7 and a second series enable transistor P8, which are connected in series. The first electrode of the first series enable transistor P7 is coupled to the second electrode of the second transistor P3 of the mirror current branch. The second electrode of the first series enable transistor P7 is coupled to the first electrode of the second series enable transistor P8. The second electrode of the second series enable transistor P8 is coupled to the first electrode of the light-emitting diode D1. The control electrode of the first series enable transistor P7 is coupled to the output terminal of the first static memory SRAM1 for receiving the data signal DS. The control electrode of the second series enable transistor P8 is used to receive the enable transmit signal EM. The light-emitting diode D1 will only turn on and illuminate when both the data signal DS and the enable transmit signal EM are valid.

[0132] The topology of this pulse-width modulation signal generation branch is relatively simple, but it requires a total of eight transistors. Because the light-emitting path, where the first transistor P1, the second transistor P3, the first series-connected enabling transistor P7, and the second series-connected enabling transistor P8 are located, contains a large number of transistors, which consumes a significant amount of voltage margin. This causes the drain-source voltage of the first transistor P1 and the second transistor P3 in the mirror current branch to be squeezed and continuously reduced, causing the operating states of the first transistor P1 and the second transistor P3 to leave the saturation region, resulting in a loss of current replication accuracy in the mirror current branch where the first transistor P1 and the second transistor P3 are located.

[0133] In other embodiments, as shown in Figure 10, the logic control branch includes a first series-connected enable transistor P7, a second series-connected enable transistor P8, a first NOR transistor N1, and a second NOR transistor N2. These four transistors are coupled using a NOR gate structure. LED D1 turns on and illuminates only when both the data signal DS and the emission enable signal EM are simultaneously valid. In this embodiment, the pulse-width modulation signal generation branch requires a total of 10 transistors.

[0134] In other embodiments, as shown in FIG11 , the logic control branch utilizes pseudo-NMOS logic, reducing the number of transistors by one compared to the embodiment shown in FIG10 . The control electrode of the first series enable transistor P7 is coupled to the reference ground voltage terminal VSS, and the first electrode of the first series enable transistor P7 is coupled to the power supply voltage terminal VDD. Therefore, the first series enable transistor P7 is always on. However, when the enable emission signal EM is at a high level, the first NOR transistor N1 is turned on. At this time, since both the first series enable transistor P7 and the first NOR transistor N1 are turned on, the potential of the first node A is affected by both the power supply voltage terminal signal Vdd and the reference ground voltage terminal signal Vss, which may result in an unstable state.

[0135] There are many other implementations of the current mirror structure consisting of the mirror current branch and the reference current branch. In some embodiments, as shown in FIG12 , a cascode structure is used for the current mirror structure consisting of the mirror current branch and the reference current branch. Compared to the low-voltage cascode current mirror structure shown in FIG7 , no additional bias generation branch is required, which can reduce the power consumption and area of ​​the bias generation branch. However, this will consume a larger voltage margin.

[0136] In other embodiments, as shown in FIG13 , a mirror current branch and a reference current branch form the most basic current mirror structure. The mirror current branch includes a first transistor P1, and the reference current branch includes a third transistor P2. This current mirror has the simplest circuit structure and the fewest transistors, making it easier to modulate the transistors to operate in the saturation region. However, this structure is significantly affected by the channel modulation effect, resulting in low current replication accuracy, necessitating an increase in transistor size to achieve higher current replication accuracy.

[0137] The present application also provides a method for controlling a micro-display circuit, comprising: generating a constant current signal; receiving and replicating the constant current signal; and generating a pulse width modulation signal (PWM). Under the control of the pulse width modulation signal (PWM), the constant current signal drives a light-emitting diode (LED) to display light.

[0138] In the embodiments of the present application, the above description assumes that each transistor can be an N-type transistor (such as a metal-oxide-semiconductor field-effect transistor (N-Metal-Oxide-Semiconductor, NMOS)), or a P-type metal-oxide-semiconductor field-effect transistor transistor, a complementary metal-oxide-semiconductor field-effect transistor transistor, or other circuit structure types.

[0139] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0140] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0141] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0142] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0143] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0144] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0145] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0146] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A micro display circuit, characterized in that: include: A pixel array, comprising a plurality of pixel circuits, each of the plurality of pixel circuits comprising a pulse width modulation signal generating branch, a light emitting diode and a mirror current branch; The pulse width modulation signal generating branch includes a first static memory; A pixel array common circuit, used for delivering a current signal to the pixel array, wherein the plurality of pixel circuits sequentially and orderly receive the current signal from the pixel array common circuit; The pixel array common circuit includes a second static memory and a reference current branch; The mirror current branch in each pixel circuit forms a current mirror symmetrical structure with the reference current branch; The circuit structure of the first static memory is consistent with that of the second static memory.

2. The micro display circuit according to claim 1, characterized in that: The pulse width modulation signal generating branch is used to generate a pulse width modulation signal; the output end of the pulse width modulation signal generating branch is coupled in series with the mirror current branch.

3. The micro display circuit according to claim 1 or 2, characterized in that: The mirror current branch includes a first transistor; the output end of the pulse width modulation signal generating branch is coupled to the first electrode of the first transistor.

4. The micro display circuit according to any one of claims 1 to 3, characterized in that: The pulse width modulation signal has a variety of duty cycles; the pulse width modulation signals with different duty cycles are used to control different conduction times of the light emitting diodes.

5. The micro display circuit according to any one of claims 1 to 4, characterized in that: The first static memory receives and stores a data voltage signal, and includes a first inverter, a second inverter, a first scan switch, and a second scan switch; the first inverter and the second inverter form a cross-coupled bistable structure.

6. The micro display circuit according to any one of claims 1 to 5, characterized in that: The data voltage signal received at the input end of the first scan switch and the data voltage signal received at the input end of the second scan switch have opposite phases.

7. The micro display circuit according to any one of claims 1 to 6, characterized in that: The pulse width modulation signal generating branch further includes a logic control branch, and the logic control branch is used to receive the transmission enable signal and the data signal of the first static memory to generate the pulse width modulation signal.

8. The micro display circuit according to any one of claims 1 to 7, characterized in that: The logic control branch includes a first enabling switch tube, a second electrode of the first enabling switch tube is coupled to a first electrode of the first transistor, a first electrode of the first enabling switch tube is coupled to a reference ground voltage terminal, and a control electrode of the first enabling switch tube receives the enabling transmission signal.

9. The micro display circuit according to any one of claims 1 to 8, characterized in that: The mirror current branch also includes a second transistor, the second electrode of the first transistor is coupled to the first electrode of the second transistor, the second electrode of the second transistor is coupled to the first electrode of the light-emitting diode, and the second electrode of the light-emitting diode is coupled to the DC voltage terminal.

10. The micro display circuit according to any one of claims 1 to 9, characterized in that: The pixel circuit further includes a reverse biased diode, and the light emitting diode is connected in parallel with the reverse biased diode.

11. The micro display circuit according to any one of claims 1 to 10, characterized in that: The reference current branch includes a third transistor and a fourth transistor, the first electrode of the third transistor is coupled to the output end of the second static memory, the second electrode of the third transistor is coupled to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is coupled to the control electrode of the third transistor; the control electrode of the first transistor is coupled to the control electrode of the third transistor, and the control electrode of the second transistor is coupled to the control electrode of the fourth transistor.

12. The micro display circuit according to any one of claims 1 to 11, characterized in that: The pixel array common circuit also includes a bias generating branch, and the bias generating branch is used to generate a constant bias voltage; the bias generating branch includes a first bias tube, a second bias tube and a bandgap reference current source.

13. The micro display circuit according to any one of claims 1 to 12, characterized in that: The first electrode of the first bias tube is coupled to the power supply voltage terminal, the second electrode of the first bias tube is coupled to the first electrode of the second bias tube, the second electrode of the second bias tube is coupled to the bandgap reference current source, and the control electrode of the first bias tube, the control electrode of the second bias tube and the second electrode of the second bias tube are all coupled to the control electrode of the fourth transistor.

14. The micro display circuit according to any one of claims 1 to 13, characterized in that: The micro display circuit also includes a constant current generating circuit, which is used to generate a constant current signal. The constant current generating circuit includes a first constant current switch tube, a second constant current switch tube and a third constant current switch tube; the control electrode of the first constant current switch tube and the control electrode of the second constant current switch tube are coupled; the first electrode of the first constant current switch tube and the first electrode of the second constant current switch tube are commonly coupled to the DC voltage end.

15. The micro display circuit according to any one of claims 1 to 14, characterized in that: The constant current generating circuit also includes a first operational amplifier; the first input end of the first operational amplifier is coupled to the second pole of the first constant current switch tube, the second input end of the first operational amplifier is coupled to the control pole of the first constant current switch tube, the control pole of the second constant current switch tube, and the second pole of the second constant current switch tube, and the output end of the first operational amplifier is coupled to the control pole of the third constant current switch tube.

16. The micro display circuit according to any one of claims 1 to 15, characterized in that: The second electrode of the third constant current switch tube N9 is coupled to the second electrode of the fourth transistor.

17. A control method for a micro display circuit, characterized in that: The control method of the micro display circuit comprises: Generate a constant current signal; receiving and replicating the constant current signal; A pulse width modulation signal is generated, and under the action of the pulse width modulation signal, the constant current signal drives the light emitting diode to emit light.

18. A display chip, characterized in that: It comprises a micro display circuit as described in any one of claims 1 to 16, and a processor; the processor is coupled to the micro display circuit.

19. An electronic device, characterized in that: It comprises the display chip as claimed in claim 18, and a printed circuit board; the display chip is arranged on the printed circuit board, and the display chip is used to display luminescence.

Images