Die-to-die communication

Abstract

A semiconductor die device comprises a die-to-die communication module (104) for communicating with a separate semiconductor die device. The die-to-die communication module includes a sideband interface (302) comprising at least one sideband data pin (306) for communicating under control of a first clock signal, and a main band interface (300) comprising two or more main band data pins (304) for communicating with the external interface. The die-to-die communication module comprises selection circuitry (308) configured to select whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.

Description

[0001] DIE-TO-DIE COMMUNICATION

[0002] The present technique relates to the field of data processing. More specifically, the technique relates to communication between semiconductor dies.

[0003] Circuitry for different parts of a data processing apparatus may be provided on different semiconductor dies. To allow communication between different parts of the system, an interface may be provided to communicate data between different dies.

[0004] At least some examples provide a semiconductor die device, comprising a die-to-die communication module for communicating with a separate semiconductor die device, the die-to-die communication module comprising: a sideband interface comprising at least one sideband data pin for communicating with an external interface of the separate semiconductor die device under control of a first clock signal received from a first clock source; and a main band interface comprising two or more main band data pins for communicating with the external interface, wherein the number of main band data pins is larger than the number of sideband data pins; and selection circuitry configured to select whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.

[0005] At least some examples provide a computer-readable medium to store computer- readable code for fabrication of a semiconductor die device, comprising a die-to-die communication module for communicating with a separate semiconductor die device, the die-to-die communication module comprising: a sideband interface comprising at least one sideband data pin for communicating with an external interface of the separate semiconductor die device under control of a first clock signal received from a first clock source; and a main band interface comprising two or more main band data pins for communicating with the external interface, wherein the number of main band data pins is larger than the number of sideband data pins; and selection circuitry configured to select whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.

[0006] At least some examples provide a method for a semiconductor die device, comprising communicating with a separate semiconductor die device using a die-to-die communication module of the semiconductor die device, the communication comprising: communicating, using a sideband interface comprising at least one sideband data pin, with an external interface of the separate semiconductor die device under control of a first clock signal received from a first clock source; and communicating, using a main band interface comprising two or more main band data pins, with the external interface, wherein the number of main band data pins is larger than the number of sideband data pins; and selecting whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.

[0007] Further aspects, features and advantages of the present technique will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings, in which:

[0008] Figure 1 illustrates a first example of a system-in-package.

[0009] Figure 2 illustrates a second example of a system-in-package.

[0010] Figure 3 illustrates a die-to-die communication module according to aspects of the present technique.

[0011] Figure 4 is a state diagram illustrating modes of a die-to-die communication module.

[0012] Figure 5 is a state diagram illustrating modes of a die-to-die communication module according to the present technique.

[0013] Figure 6 illustrates a semiconductor die device comprising two die-to-die communication modules.

[0014] Figure 7 is a graph illustrating bandwidth and power characteristics of a die-to-die communication module according to examples of the present technique.

[0015] Figure 8 is a flow diagram illustrating a method of operating a die-to-die communication module.

[0016] Figure 9 illustrates a system and a chip-containing product.

[0017] In some approaches to manufacturing a data processing device, the data processing device can be provided comprising several parts of the data processing device on the same semiconductor die, known as an integrated circuit (or monolithic integrated circuit). During manufacturing, many integrated circuits (ICs) may be printed on a wafer of semiconductor material, which may then be diced into individual dies each containing one IC. Each die is packaged separately (provided with a supporting casing and contacts to allow the IC to be installed on a circuit board). In such an integrated circuit, a large number of electrical components are provided together on the same piece of semiconductor material to provide circuitry allowing data to be processed. The integrated circuit may comprise circuitry for fetching instructions from a memory (the memory may or may not be provided as part of the integrated circuit), decoding the instructions, performing processing operations based on the instructions, storing local copies of data (in registers and caches), and so on. Providing the components of the system on the same semiconductor die allows electrical components to be provided at an extremely high density with very short propagation distances between components, enabling data processing with high performance and low power consumption. However, it has been recognised that, for some data processing devices, there can be some drawbacks associated with providing a data processing system on one die. First, when a device is manufactured there is a chance that defects may occur in some electrical components. As the size of the die increases, it becomes more likely that the die will have a defect and need to be discarded, and therefore the yield of manufacturing integrated circuits on a single die can reduce as the size of the circuit increases. Secondly, the entire integrated circuit is manufactured using the same method (which may be referred to as a process node). To allow improved performance, from time to time it may be desired to begin manufacturing certain parts of the system using a new process node. There may be minimal improvements associated with porting certain other components to the new process node, but the high cost associated with porting components to a new process node has to be incurred for all components in a monolithic IC even if performance gains are minimal for some components. Thirdly, different parts of a data processing system may benefit from being manufactured using different techniques. For example, different parts of a system may benefit from using a different semiconductor technology. However, this is not possible when manufacturing the device on a single die.

[0018] Certain problems associated with providing a circuit on a single die can be addressed by manufacturing certain parts of a data processing system on different dies, and using the combination of dies to provide the data processing system. Separate dies could be packaged together so they appear externally to be equivalent to a monolithic IC, but are in fact provided using more than one die. Benefits include increased yield because discarding a faulty die involves discarding much fewer good components (the other dies of the same device containing no faults do not need to be discarded, whereas the entire device would be discarded if the device were provided on a single die). In addition, different parts of the system can be made using different methods. This means that all components do not need to be ported to new process nodes, and different semiconductor technologies can be used for different parts of the device. The individual dies making up a device which might otherwise be made on a single die can be referred to as “chiplets”. It would be desirable to obtain the above benefits by splitting an IC up over several dies, without severely impacting the performance of the device. In particular, it would be desirable to provide communication between the individual dies making up the device at high bandwidth, low latency and low power.

[0019] To enable communication between dies, each die may be provided with at least one communication module to physically transmit data over a transmission medium to the communication module of another die. The communication module may be referred to as a physical layer (PHY).

[0020] One example of a die-to-die communication module includes a main band interface and a sideband interface. Both the main band interface and the sideband interface comprise data pins for transmitting data via data channels, with the main band interface having more data pins (and hence more data channels) than the sideband interface. The data pins may include metallic contacts, which could be referred to as bumps or microbumps, over which data can be transferred. In some examples, the main band interface is used for the system data path between dies, responsible for transmitting the system data, and the sideband interface is used for setting up communication over the main band interface, for example by establishing a link with another die and training and maintaining the main band data link (to be discussed further below). The sideband interface may communicate under control of a first clock signal received from a first clock source, which may be external to the die and provided as an input to the die, or which may be generated on the die. The first clock signal may be a relatively low frequency clock signal, selected for a robust communication channel rather than for transmitting data quickly (discussed further below).

[0021] In some examples, the main band interface may communicate under control of a second clock signal, the second clock signal having a higher clock frequency than the first clock signal controlling communication over the sideband interface. Using a higher frequency clock signal for the main band can allow the rate of data transfer over each main band pin to be greater than the rate of data transfer over each sideband pin, which can enable the system data to be transferred with a high data transfer rate, reducing the performance impacts of providing parts of the system on separate dies.

[0022] The power consumption of the main band interface controlled by the second clock signal can be high because of the higher clock frequency of the second clock signal, and the link maintenance that may be associated with the higher clock frequency. For example, clock distribution, bias currents, tracking per-lane delays and / or the generation of the high-speed clock (such as using a phase-locked loop (PLL)) can all contribute to the higher power consumption associated with use of the second clock signal. The inventors have realised that the power consumption can be unacceptable, especially in cases where only a small amount of data is required to be transmitted using the main band interface. A mobile phone is an example of a use case where power consumption is a key concern but where the amount of data transfer may at times be low, and therefore where it would be undesirable for the main band interface to constantly incur the power cost associated with using the second clock signal.

[0023] One option for reducing power consumption of the communication module is to clock gate the main band interface by preventing the clock signal from being distributed to the main band interface when data is not required to be transmitted, reducing dynamic power associated with distributing the high-speed clock signal. However, power savings depend on the traffic pattern, with the overhead associated with gating and restarting the main band interface meaning that the amount of power saved can be relatively small in data patterns requiring relatively frequent transmission of small amounts of data since for a lot of the time the interface may not be clock gated, even if only small amounts of data are being transmitted. In addition, the minimum power consumption in a clock gated interface (and therefore the maximum power saving) can be limited because the circuitry for generating the high-speed clock signal (such as PLLs) may remain active.

[0024] The present technique allows power consumption of a die-to-die communication module to be reduced. The power reduction is particularly present in cases where low bandwidth communication using the main band interface can be required at times. According to the present technique, the die-to-die communication module is provided with selection circuitry configured to select whether communication over the main band data pins is controlled based on the second clock signal, or whether communication over the main band data pins is controlled based on the first clock signal also used for controlling communication over the sideband interface. That is, the main band interface can be selectively controlled by either a high-speed clock or the lower frequency clock otherwise used for the sideband interface.

[0025] It would appear to be quite unusual and counter-intuitive to use the first clock signal, under control of which the sideband interface transmits data, for controlling communication over the main band interface because the first clock signal may be selected primarily for robust, but slow, communication (such as for establishing a communication link, rather than actually transmitting system data). The main band may be expected to require significantly higher clock frequencies to meet bandwidth demands. However, the inventors realised that in use cases where the bandwidth requirements are low, the data transfer rate of the main band interface under control of the first clock signal can be sufficient to meet said bandwidth requirements, without incurring the power cost of using the second clock signal. Compared to the sideband interface, the main band interface has more data pins, so even if communication under control of the first clock signal using the sideband interface were unable to meet a bandwidth requirement, communication under control of the first clock signal using the main band interface may be able to meet the bandwidth requirement. The power cost is reduced because distributing the lower frequency first clock signal has a reduced power consumption compared to distributing the higher frequency second clock signal, and because using the first clock signal can allow the second clock signal generator to be powered down. In addition, as will be discussed below, use of the first clock signal rather than the second clock signal can allow certain link maintenance to be avoided, which can also reduce power overhead. By providing selection circuitry with the option of using the second clock signal, the main band interface is still able to be controlled by the second clock signal in cases where bandwidth requirements increase. In essence, the present technique provides a mode of operation for communicating over the main band interface which has a bandwidth higher than the zero bandwidth of the clock gated mode, and a power consumption less than a mode where the second clock signal is used to control data transmission over the main band pins. Because the first clock signal may already be used for controlling communication over the sideband interface, an entirely new clock path does not need to be added, and therefore the additional circuitry required to allow the main band interface to be controlled using the first clock signal may be relatively low. Use of the first clock signal for controlling communication over the main band data pins can lead to reduced power consumption compared to using the second clock signal, because the power associated with distributing the lower frequency first clock signal to the main band interface can be lower than the power associated with distributing the second clock signal. This is true even if the second clock signal is still generated but not provided to the main band interface. However, power usage can be further reduced by selectively powering down circuitry for generating the second clock signal when communication over the main band interface is controlled using the first clock signal. Therefore, in some examples, clock control circuitry is configured to make a determination of whether to power down the second clock source based on whether the selection circuitry selects the first clock signal or the second clock signal for controlling communication over the main band. It will be appreciated that the determination of whether to power down the second clock source may be based on other factors in addition to the state of the selection circuitry, as for example there may be other circuitry (such as a further communication module) using the second clock signal which could prevent the second clock source from being powered down even if the second clock signal is not being used for communication over the main band interface. Nevertheless, it will be appreciated that by identifying, based at least on which clock signal is selected by the selection circuitry for controlling communication over the main band interface, opportunities where the second clock source can be powered down, power can be reduced in certain situations.

[0026] In some examples, the die-to-die communication module may be configured to require, as a condition of entry into a main-band-using-second-clock communication state in which communication over the main band data pins is performed under control of the second clock signal, that a link training procedure is performed prior to entry to the main-band-using-second- clock communication state. The link training procedure may be performed due to the higher clock frequency of the second clock signal. With a higher clock frequency, each clock cycle takes a shorter amount of time. Therefore timing margins are smaller, and smaller differences in the amount of time taken for a die-to-die communication signal to propagate over some distance can lead to errors in receiving the transmitted data. Link training may involve setting up communication parameters to compensate for variations in propagation times (which may be dependent on random manufacturing process variation occurring at the time of manufacture, and so may not be predictable in advance of manufacture), to enable communication at higher clock frequencies.

[0027] Compared to the second clock signal, the first clock signal has a lower clock frequency. By having a lower clock frequency, each clock cycle of the first clock signal takes more time than each clock cycle of the second clock signal. Therefore, variations in propagation time have a less significant effect on the first clock signal than the second clock signal, because the same variation is less likely to lead to an error in a longer clock cycle as there is more margin for error. In some examples, the first clock frequency may be low enough that communication can be performed under control of the first clock signal and the risk of errors when communicating without performing link training may be acceptably low. In other words, an assumption can be made that variations caused by the hardware are typically within the margin for error of communication under control of the first clock signal. Therefore, in some examples, the die-to-die communication module may be configured to permit entry to a main-band-using-first-clock communication state in which communication over the main band data pins is performed under control of the first clock signal, even if the link training procedure has not been performed prior to entry to the main-band- using-first-clock communication state.

[0028] Allowing communication over the main band pins under control of the first clock signal can therefore allow communication to begin from a powered down state much quicker than in cases where communication over the main band pins can only be controlled using the second clock signal, because it can allow the link training procedure to be skipped. Hence, if there is only a relatively small amount of data to be transmitted, then rather than incurring the latency of link training and the high power cost of using the second clock signal, the present technique (in which communication over the main band pins can be controlled using the same clock signal as used for the sideband pins) can provide lower latency entry into a lower power mode for transmitting the data. As the latency penalty for entering the lower power mode is reduced, this means it becomes more practical to enter the lower power mode more frequently (as it is possible to enter it even in periods with no data to transmit that would be too short to accommodate the training before the next data is needed). Hence, in practice, there can be a significant power saving achieved by supporting the use of the first clock signal for the main band interface, by enabling the lower power state to be used more often than would otherwise be practical in a system not supporting communication on the main band interface using the first clock signal.

[0029] As discussed above, in some examples the link training procedure is based on the die-to- die communication module communicating with the external interface of the separate semiconductor die device using the sideband interface. Therefore, the sideband interface may be an interface for performing the link training procedure used in establishing communication sessions with a separate die device.

[0030] Although in some examples the semiconductor die device may comprise only a single die- to-die communication module, the technique is not limited to such examples. In other examples, the semiconductor die device comprises one or more further die-to-die communication modules for communicating with the separate semiconductor die device, the one or more further communication modules each comprising a further sideband interface comprising at least one further sideband data pin for communicating with the external interface under control of the first clock signal, and a further main band interface comprising two or more further main band data pins for communicating with the external interface under control of at least the second clock signal, wherein the number of further main band data pins is larger than the number of further sideband data pins. Including more than one communication module can allow the die-to-die communication bandwidth to be increased. The one or more further communication modules may share the same first and second clock sources for the first and second clock signals as used in the communication module discussed above.

[0031] The semiconductor die device may comprise routing circuitry arranged to selectively route data to any one or more of the die-to-die communication modules and the one or more further die-to-die communication modules. Hence, data to be communicated can be sent via a particular communication module, or via two or more communication modules. This can allow flexibility in the use of the communication modules, and significantly can allow communication modules to be used cooperatively when establishing a communication link. For example, it will be discussed below how a first communication module can be used to transmit data under control of the first clock signal whilst a second communication module is undergoing link training - the routing circuitry can allow data transmission to be switched from the first communication module to the second communication module when link training is complete.

[0032] In some examples, the selection circuitry is configured to select whether communication over the main band pins of the further communication module (or one or more of the further communication modules) is controlled based on the first clock signal or the second clock signal. In this way, the further communication module may be capable of controlling data transmission over the further main band pins under control of the first clock signal, providing the further communication module with access to the lower power, lower bandwidth mode of operation.

[0033] The semiconductor die device may comprise clock control circuitry. The clock control circuitry may be configured to power down the second clock source in response to determining that the selection circuitry has selected the first clock signal to control communication over both the main band data pins and the further main band data pins, and therefore that the second clock signal is not required for either communication module. In examples comprising more than one further communication module, the clock control circuitry may be configured to power down the second clock source in response to determining that the selection circuitry has selected the first clock signal to control communication over all of the main band data pins (that is, the main band data pins of the communication module and the further main band pins of the one or more further communication modules). In this way, the power associated with generating the second clock signal, which can be significant in some examples, can be reduced when the second clock signal is not being used.

[0034] As discussed above, there are some examples where transmission over the main band data pins can be performed in a main-band-using-first-clock state under control of the first clock signal without previously undergoing link training, or in a main-band-using-second-clock state under control of the second clock signal after undergoing link training. In some examples, the use of more than one communication module, at least one of which having access to an untrained main-band-using-first-clock state, can allow data transfer to undergo fewer interruptions resulting from link training. In systems having only a main-band-using-second-clock state, starting from a state in which no data is transmitted, if bandwidth requirements increase then data transmission cannot begin until the one or more communication modules finish link training. In comparison to such systems, use of the main-band-using-first-clock state means that when bandwidth requirements increase from zero, then data transmission can begin quickly by using a module in the main-band- using-first-clock state. Whilst one module is in the main-band-using-first-clock state, a second module could undergo link training, but compared to systems having no main-band-using-first- clock state, some data can still be transferred via the untrained main-band-using-first-clock module whilst another module is undergoing link training.

[0035] In some systems having only one communication module, there may be an interruption in bandwidth whilst the communication module undergoes link training. Compared to these systems, providing two or more communication modules (one of which having access to a main-band- using-first-clock state) means that link training can be performed without interrupting bandwidth because whilst one module is undergoing link training, another module can maintain some bandwidth using the main-band-using-first-clock state. Therefore, the use of at least two modules allows interruption-free connectivity with one module operating in the main-band-using-first-clock state while the other performs link training for high-bandwidth operation in the main-band-using- second-clock state.

[0036] Hence, in some examples, when the die-to-die communication module is in an untrained main-band-using-first-clock communication state in which communication over the main band data pins of the die-to-die communication module is controlled based on the first clock signal, in response to determination that the further die-to-die communication module is to enter the main- band-using-second-clock communication state, the selection circuitry may be configured to select that communication over the main band data pins of the die-to-die communication module is controlled based on the first clock signal until the link training procedure has completed.

[0037] In some examples, the main band interface and sideband interface could be configured to transmit the same number of bits per clock cycle per data pin. For example, each interface could transmit one bit per clock cycle. However, in some examples, in each clock cycle the main band interface may be configured to transmit a greater number of bits per main band data pin than the sideband interface transmits per sideband data pin. This may allow even greater rates of data transfer over the main band interface than over the sideband interface, to support greater system bandwidth between dies.

[0038] However, if the first clock signal is used to transmit data over the main band data pins, then the main band interface transmitting a greater number of bits per cycle per pin than the sideband interface could lead to timing issues. In particular, the first clock frequency may be selected to allow communication at the data rate of the sideband interface in a state which has not undergone link training, because the data rate means that bits are spaced out in time sufficiently that timing adjustments to account for variations in timing are not required. However, if the main band interface transmits more bits per cycle per pin than the sideband interface, then the data rate per pin of the main band interface under control of the same first clock signal will be higher than the data rate of the sideband interface. This may cause the data rate of the main band interface under control of the first clock signal to exceed a threshold above which the time between bits is too short to allow communication in an untrained state. Hence, despite the first clock signal being suitable for untrained communication on the sideband interface, the increased data rate of the main band interface could cause the same clock signal to be unsuitable for untrained communication over the main band interface.

[0039] Hence, in some examples the semiconductor die device may comprise dividing circuitry to divide the first clock signal for controlling communication over the main band data pins, by reducing the clock frequency of the first clock signal. In some examples, the dividing circuitry reduces the frequency of the first clock signal to a level where the data rate per pin of the main band interface under control of the divided first clock signal is the same as the sideband interface under control of the undivided first clock signal. However, it will be appreciated that the dividing circuitry is not so limited, as long as the data rate of the main band interface under control of the divided clock signal is sufficiently low that the data rate does not exceed a threshold above which link training is required.

[0040] In some examples, the main band interface may be configured to transmit data at a double data rate where bits are transmitted twice per clock cycle, once on the rising edge and once on the falling edge. In such examples, the sideband interface may be configured to transmit data once per clock cycle, and therefore the main band interface may transmit twice the number of bits per pin in each clock cycle as the sideband interface. The dividing circuitry may therefore be configured to halve the clock frequency of the first clock signal when used for the main band interface, so that the resulting data rate per pin of the main band interface under control of the divided first clock signal is the same as that of the sideband interface under control of the undivided first clock signal.

[0041] In some examples, the pin data rate of the main band interface under control of the first clock signal may be low enough that the link does not require link training even if the first clock signal is undivided. For example, when the main band interface uses a double data rate, the device may support untrained communication even at twice the sideband pin data rate. Whether or not this is the case may vary depending on factors including the frequency of the first clock signal, device-specific variations in signal path lengths (which may be dependent on manufacturing process variations), and environmental conditions. Hence, whilst in some instances there may not be a requirement to divide the first clock signal for controlling untrained communication over the main band interface, in other instances the first clock signal should be divided. Performing communication using the undivided clock signal may be preferable to dividing the clock signal, since higher data rates can be achieved. To allow advantage to be taken of the higher data rate of the undivided first clock signal in cases where link training is not required to perform main band communication using the undivided clock signal, but also allow the first clock signal to be used in an untrained state when the undivided first clock signal would require link training, some examples comprise dividing control circuitry configured to determine whether or not to divide the first clock signal for controlling communication over the main band data pins.

[0042] The dividing control circuitry may be configured to determine whether to divide the first clock signal depending on various factors, such as the clock frequency of the first clock signal. In some examples, the dividing control circuitry may be configured to determine whether or not to divide the first clock signal on the basis of at least one on-die measurement of die-to-die communication reliability when communicating over the main band data pins under the control of the undivided first clock signal. By measuring communication reliability, it can be determined when it is acceptable to take advantage of the higher bandwidth achievable using the undivided first clock signal and when instead the first clock signal should be divided for use in the main band interface to increase link reliability.

[0043] In some examples, the second clock source comprises a phase-locked loop (PLL). PLLs may provide a reliable high frequency clock signal. However, PLLs may have significant power usage. Hence, providing a mode of operating the main band interface whilst allowing a PLL to be powered down is advantageous from a power perspective.

[0044] The first clock signal is generated by a first clock source. As mentioned above, in some examples the first clock source is provided separately from the semiconductor die device, and the first clock signal is provided to the semiconductor die device via an external clock pin. In other examples, the semiconductor die device comprises the first clock source.

[0045] The die-to-die communication module may be configured to communicate with the separate semiconductor die device in one of several ways. The data pins of the die-to-die communication module may be directly connected to pins of the separate semiconductor die device. However, in practice it may be more common that the die-to-die communication module communicates with the separate semiconductor die device via intermediate transmission circuitry, which could take different forms depending on how the dies are combined. The intermediate transmission circuitry is for carrying electrical signals between dies, and does not typically perform any processing on the transmitted signals, although this is a possibility with active interposers. Different examples of transmission circuitry may include an organic substrate, silicon interposer, silicon bridge, and a fanout interposer, but it will be appreciated that these are merely examples.

[0046] As discussed above, it has been recognised that there are advantages associated with manufacturing a data processing system on several dies compared to manufacturing the system as a monolithic integrated circuit.

[0047] Figure 1 illustrates a first example of a system-in-package 101 provided using two separate dies 100 which have been packaged together on a substrate 108. In the example of Figure 1, the substrate 108 provides the paths 106 by which data is communicated between dies 100. The dies 100 are in electrical contact with contacts on the substrate 108 via solder balls 102, which may be referred to as bumps. A subset of the bumps 102 may be for forming connections for communicating between dies 100 via a communication module 104 (or physical layer PHY). It will be appreciated that while a small number of bumps have been illustrated in Figure 1, in practice a greater number will be provided. Bumps 102 other than those used by the PHYs 104 for communication between dies 100 may be routed via the substrate to contacts for communication outside of the set of dies 100. Packaging as illustrated in Figure 1 may be referred to as 2D integration, or standard packaging.

[0048] Figure 2 illustrates a second example of a system-in-package 101. In the example of Figure 2, the dies 100 are mounted on an interposer 110, which is in turn mounted on a substrate 108. Compared to Figure 1 , in Figure 2 the paths 112 between dies 100 are routed via the interposer 110 instead of the substrate 108. Typically, interposers 110 allow the definition of much finer traces than substrates 108, so the density of connections between dies 100 can be much greater. To enable connection with a much greater number of traces, the bumps 114 connecting the dies 100 to the interposer 110 may be smaller and placed at a finer pitch than the bumps 102 connecting the interposer 110 to the substrate, and may be referred to as microbumps 114. Packaging as illustrated in Figure 2 is an example of 2.5D integration, which is an example of advanced packaging. When an interposer 110 is used to connect dies 100, the number of data pins in each PHY 104 may be greater than the number of data pins in 2D integration, and therefore the bandwidth of die-to-die communication can be greater.

[0049] It will be appreciated that other examples of advanced packaging can also be used. For example, rather than providing an interposer 110 as a separate element, regions of silicon (“silicon bridges”) can be embedded in an organic substrate 108 between dies 100 to provide high density connections between dies. In addition, dies 100 could be physically stacked on top of each other to provide a 3D integrated circuit, in which PHY modules 104 may be used to communicate between dies forming different layers of the 3D integrated circuit.

[0050] In any case, physical layer (PHY) modules 104 may be used to provide an interface between a die 100 and another die 100. Figure 3 illustrates an example of a PHY module 104 according to examples of the present technique.

[0051] The PHY module 104 illustrated in Figure 3 comprises a main band interface 300 and a sideband interface 302. The main band interface 300 is for transmitting system data to another die 100 whereas the sideband interface 302 is for controlling the transmission of data over the main band interface 300, such as by establishing and training a link with another die 100. The main band interface 300 comprises two or more main band data pins 304 for each of transmit and receive. In some examples, such as when a system is provided according to the Universal Chiplet Interconnect Express™ (UCIe™) standard, the number of main band data pins 304 may be 16, 32, or 64 depending on the type of interface used (choice of interface may depend on the type of packaging used), although it will be appreciated that these numbers are not limiting. Examples using an interposer 110 or equivalent may provide more pins than examples without an interposer because they can support denser connections between dies 100. The sideband interface 302 comprises one or more sideband data pins 306 for each of transmit and receive. The number of sideband data pins 306 is smaller than the number of main band data pins 304, since the bandwidth requirements for the sideband interface 302 are much smaller than those of the main band interface 300. In some examples, the sideband interface may only comprise a single data pin 306 for serial data transfer for each transmit and receive, whereas the two or more main band data pins 304 can be used for parallel data transfer.

[0052] The sideband interface 302 is controlled using a first clock signal SB_CLK. The first clock signal (or sideband clock signal) has a relatively low clock frequency, which can enable the signal transmission controlled by the first clock signal to be robust. In particular, the sideband interface may not require any link training because the low frequency sideband clock has clock cycles which are relatively long, and have sufficient margin to account for variations which may arise from independent variations in manufacturing process between the die 100, supply voltages and temperature, which may affect timing of the data transmitted via the sideband interface. The sideband interface may also be configured for single data rate communication, where one bit is transmitted per pin per clock cycle. Again, this allows more robust communication without a requirement for link training. The bandwidth of the sideband interface 302 is relatively low as a result of the lower clock frequency, single data rate, and limited number of data pins 306, but is sufficient for setting up a communication link on the main band interface and for performing link maintenance, and importantly can do so without a requirement for its own link training.

[0053] In some examples, the main band interface 300 is controlled using a second clock signal MB_CLK. The second clock signal (or main band clock signal) has a higher clock frequency than the SB_CLK, which can help the main band interface achieve higher pin data rates than the sideband interface. The MB_CLK may have a frequency high enough that prior to starting communication, a link training procedure is performed to set up communication parameters to compensate for variations in propagation times. The parameters may include tuning delays for individual data pins to minimise the bit-error-rate and optimise the timing of data capture on the receiving end of the link, thus enable communication at higher clock frequencies. With a higher frequency clock signal, more bits are transferred in a given amount of time, meaning that the window of time for a given bit to arrive is much smaller than with a lower clock frequency. Hence, smaller variations in timing can be allowed before a bit is transmitted outside of its allowed window and errors occur. The link training aims to compensate for the variations to reduce error in communicating with a high frequency clock signal.

[0054] In one example of a link training procedure, a transmitter may send a training pattern to a receiver, along with a clock signal (the MB_CLK) used for reading the training pattern. The receiver adjusts relative delays between sampling of the received signal (the training pattern) and the capture clock, such that the signal as read by the receiver matches the expected training pattern and maximises the difference in level between binary 1 and binary 0 values represented by the signal. The training pattern may be sent over the main band data pins, with the side band interface (which is robust and does not require link training to begin communication) being used to arrange the link training procedure, for example performing a handshake between the transmitter and receiver.

[0055] The main band interface may also be configured for double data rate communication, whereby a bit is transmitted on each rising edge and falling edge of a clock signal, for a total of two bits per clock cycle. The larger number of main band pins 304, higher clock frequency, and double data rate means that the main band interface under control of the MB_CLK can achieve significantly higher data rates than the sideband interface 302 under control of the SB_CLK. In one example, SB_CLK has a frequency of 8MHz giving each pin of the sideband interface a bandwidth of 800Mb / s whereas MB_CLK has a frequency of 8GHz giving each pin of the main band interface a bandwidth of 16Gb / s.

[0056] A PHY module 104 as described above has a high bandwidth, but may also have a high power overhead when the available bandwidth for communication is only partially used. The MB_CLK may be generated using a phase-locked loop (PLL) which has a high power consumption. In addition, the dynamic switching power associated with propagating the MB_CLK throughout the main band interface 300 may be high. Further, there may be power overhead associated with maintaining the link parameters so that the main band interface remains in a trained state tracking changes in environmental conditions of voltage and temperature. In certain applications, the power overhead of the PHY module 140 may limit the usefulness of providing the system on several different dies 100. In particular, applications that require long periods of maintaining connectivity at low bandwidth utilisation where power efficiency is important can be difficult where the main band interface is powered using the MB_CLK. An example of such an application is a partitioned compute function using a system-in-package for use in mobile devices.

[0057] Some approaches may reduce the power consumption of the PHY module 104 through clock gated power modes or reducing the width of a die-to-die interface consisting of multiple parallel PHY modules 140. But these approaches may not provide sufficient power reduction, and may be associated with high latency when attempting to ramp up bandwidth.

[0058] An example of the use of lower power modes is provided in Figure 4, which is a state diagram illustrating modes of a PHY module 104 having a sideband interface controlled by SB_CLK and a main band interface controlled by MB_CLK.

[0059] Initially, the PHY module 104 is in a reset state 400 in which it has no links with another die, and therefore is unable to transmit data. At steps 402 and 404 respectively the sideband interface 302 and main band interface 300 are initialised. The sideband interface 302 is able to transmit data to a second die 100 at this point because it does not require training, but the main band interface has not been trained and therefore cannot transmit data.

[0060] At step 406, the sideband interface 302 communicates with a separate die 100 (e.g., a sideband interface of a separate die) to carry out a main band training procedure. This is associated with some latency, in some examples in the millisecond range. If link training at step 406 encounters an error, the system may be reset to state 400 via state 416. Following training at step 406, the main band interface can initialise a link at step 408, and the module transitions into the active state 410 in which the main band interface can transmit data at high bandwidth under control of MB_CLK. As discussed above, this active state has a high power cost. In some examples, the power consumption could exceed 100mW at zero bandwidth, which is very significant in a mobile application. Therefore, some lower power states can be provided.

[0061] The module 104 can transition from the active state into an L1 or L2 low power state 414. In the low power state 414 the MB_CLK clock source may be turned off. However, this means that the main band interface is unable to transmit any data, and bandwidth drops to zero. Additionally, returning to the active state 410 requires main band training 406 to be performed again. Hence, ramping up bandwidth is associated with a high latency and power overhead during training, therefore limiting how frequently the power saving states 414 can be used (as they can only be used if the period having no data to transmit is long enough to accommodate the latency of training 406 and for periods for which power saving during sleep exceed the energy used for training).

[0062] A clock gating technique 412 could be used in which the MB_CLK signal is not distributed throughout the main band interface when the bandwidth requirements are zero (e.g., when buffers are empty). This does not require full retraining on resumption, but may require periodic wake-up of the main-band to maintain the link parameters. Also, the clock is still generated and power may still be too high for some applications (for example, exceeding 10mW).

[0063] According to aspects of the present technique, power saving modes are provided which provide greater than zero bandwidth, have low power overhead, and allow uninterrupted data transfer whilst ramping up to peak bandwidth.

[0064] In particular, as illustrated in Figure 3, selection circuitry 308 is provided which can select whether the main band interface 300 communicates under control of the high frequency MB_CLK, or the low frequency SB_CLK. Under control of the SB_CLK, the main band interface may require no link training, and can therefore begin communication with very low latency (e.g., on the order of a couple of clock cycles). Additionally, because link training is not required, the power overhead of maintaining link parameters is not incurred when the main band communicates using SB_CLK. Under control of the SB_CLK, the MB_CLK source can be powered down, saving power. Additionally, distributing the SB_CLK through the main band interface has lower power requirements than distributing MB_CLK, since it has a lower frequency.

[0065] As the clock frequency of SB_CLK is lower than that of MB_CLK, the data rate of the main band interface under control of SB_CLK is lower than under control of MB_CLK. A single sideband data pin under control of SB_CLK may have too low bandwidth to be of much use in transmitting system data. However, the inventors have realised that the bandwidth achievable by using the SB_CLK for the main band interface, due to its larger number of data pins, can be high enough even under control of SB_CLK to be of use in transmitting system data.

[0066] In some examples, the main band interface 300 has a double data rate. Link training for the sideband interface under control of SB_CLK may be avoided due to the pin data rate being within a threshold where timing margins are long enough to account for typical variations in propagation times. However, the main band interface may exceed said threshold even under control of SB_CLK as a result of doubling the data rate. Hence, in some examples, to ensure that training is not required when the main band interface is using SB_CLK, dividing circuitry 310 can be provided to reduce the clock frequency of SB_CLK before it is used to control communication on the main band interface. For example, dividing circuitry 310 may halve the clock frequency of SB_CLK if the main band interface has a double data rate, so that the pin data rate remains the same as the sideband data pins 306 and training can be avoided.

[0067] In some examples, depending on variable factors of the apparatus, a data rate doubled (or otherwise increased) with respect to that of the sideband pins 306 may still fall within the acceptable threshold where link training is not required. In such cases, greater bandwidth can be achieved by bypassing the dividing circuitry 310. Hence, dividing control circuitry 312 may be provided to modify or bypass the dividing circuitry 310 in cases where the undivided SB_CLK can be used to safely communicate in an untrained state on the main band interface 300. On-die sensors may be provided to determine when this is the case, by monitoring communication reliability when communicating over the main band data pins under the control of the undivided SB_CLK. If communication reliability falls below an acceptable level, the dividing control circuitry 312 may select to not bypass the dividing circuitry 310.

[0068] One or more such PHY modules 104 may be provided. Two PHY modules 104 are provided in the example of Figure 6, which schematically illustrates an example of the present technique. The two or more PHY modules 104 may both have access to the same clock signals SB_CLK and F_CLK (which is equivalent to MB_CLK in Figure 3). Provision of two PHY modules 104 can be useful because, when ramping up bandwidth, one module can continue communicating with the main band interface under control of SB_CLK whilst the other is undergoing link training for communication under MB_CLK, and therefore bandwidth is uninterrupted and some data can be communicated throughout the link training. In cases where more than one PHY module 104 is provided, routing circuitry 600 (“Multi-Module Die-to-Die Adapter1’) may be provided to route system data to a particular PHY 104. For example, if a first PHY 104 is in a state where it can transmit data under control of SB_CLK and a second PHY 104 is in a link training state, then data may be routed to the first PHY. However, when the second PHY completes link training and enters a higher bandwidth state, system data may be routed to the second PHY 104 instead of the first. Figure 5 is a state diagram illustrating states of a system having more than one PHY modules, wherein for each PHY a main band interface can communicate under control of SB_CLK or MB_CLK.

[0069] States 500, 502, 522 and 504 are equivalent to states 400, 402, 416 and 404.

[0070] State 506 is a new low power communication state LP_ACTIVE in which the main band interfaces of all PHY modules communicate under control of SB_CLK. Therefore, in state 506 data can be communicated with a separate die 100, so forward progress can be made, in comparison to zero bandwidth states such as 406 and 414 (and a clock gated state). Entry into state 506 does not require link training, so state 506 can be entered quickly after reset. In state 506, the MB_CLK source can be powered down, and does not need to be distributed throughout the main band interface. Hence, in state 506, power consumption is much lower than in ACTIVE state 410 or 514.

[0071] When bandwidth requirements increase, the system can transition into state 508 in which one or more of the PHY modules 104 is undergoing link training, and the main band interface of at least one PHY module 104 is communicating under control of SB_CLK. In state 508, bandwidth of the die-to-die communication link is greater than zero and therefore system data can still be transmitted, even whilst a communication module is undergoing link training.

[0072] Once the link training of state 508 has completed, the system transitions into MI_ACTIVE state 510 in which the main band interface of one or more PHY modules 104 communicates using SB_CLK, and the main band interface of one or more other PHY modules 104 communicates using MB_CLK. In this state, the MB_CLK source is not powered down, but power consumption can be reduced with respect to a fully active state because the higher speed clock MB_CLK does not need to be distributed throughout every main band interface. Clock stop state 516 is accessible from MI_ACTIVE state 510 if bandwidth requirements drop, in which the MB_CLK is not transmitted across the interface.

[0073] If bandwidth requirements increase further, then at state 512 one or more further PHY modules can undergo link training, so that the system transitions into a fully active state 514 in which the main band interfaces of all PHY modules are communicating using the MB_CLK.

[0074] L1 / L2 low power modes 520 may still be accessible from states 510 and 514 in which the MB_CLK source is powered down. From state 520, either the system may be reset or communication can restart in state 506. Exit from the L1 / L2 power states to state 506 allows communication to restart without incurring the latency of link training due to the option of using SB_CLK for the main band interface, compared to restarting communication from state 414 in which link training is required (communication is at state 410, reached via states 406 and 408).

[0075] Hence, it will be seen that providing the option for the main band interface to communicate under control of the lower frequency SB_CLK provides new communication states LP_ACTIVE and MI_ACTIVE. The LP_ACTIVE state can be entered with low latency, has a non-zero bandwidth, and has a low power consumption relative to states using MB_CLK for communication. Due to the larger number of main band pins, and optional use of the double data rate, the bandwidth achievable over the main band interface even using SB_CLK can be sufficient for use in lower bandwidth applications and can therefore support the use of die-to-die communication even in applications such as mobile where power efficiency has a high importance.

[0076] Figure 7 is a graph illustrating peak bandwidth and static power consumption of the LP_ACTIVE 506, MI_ACTIVE 510, and ACTIVE 514 states illustrated in Figure 5, and the transitions between these states. The vertical scale is a logarithmic scale, with values referring to peak bandwidth in GB / s and static power consumption in mW.

[0077] Figure 7 is an example corresponding to a semiconductor die device comprising two PHY modules 104, each with a single sideband pin and 64 main band pins. The SB_CLK is 800MHz (0.8GHz) and the MB_CLK is 8GHz.

[0078] Initially, the system is in an LP_ACTIVE state with both PHY modules controlling communication using SB_CLK at double data rate. Hence, bandwidth is 1.6GT / S per pin (where GT stands forgiga-transfers), or 25.6GB / s across both interfaces. This bandwidth is large enough to have practical value in die-to-die communication in lower bandwidth applications, and is much larger than the data rate of 0.2GB / S which would be achievable if the SB_CLK were only used to transmit data using the sideband interfaces in each PHY module.

[0079] If bandwidth requirements increase, one of the PHY modules undergoes link training. This is illustrated in Figure 7 as a gap between LP_ACTIVE and MI_ACTIVE states (the training state is 508 in Figure 5). During link training, power consumption increases because the MB_CLK source is powered up and distributed to one of the PHY modules, and peak bandwidth is temporarily halved because only the one module not being trained is capable of communicating (using the SB_CLK).

[0080] After a training delay of around 1ms, the MI_ACTIVE state is entered. It will be seen that the peak bandwidth is higher in the MI_ACTIVE state (5.5 times that of the LP_ACTIVE state), and also the power consumption is higher due to the MB_CLK source being active and the MB_CLK signal being distributed. An example of clock gating is shown at a time of around 24ms in the MI_ACTIVE state. During clock gating, the clock signals are not distributed to the PHY modules 104, and power consumption decreases. However, despite bandwidth dropping to zero, power consumption remains significant (as the MB_CLK signal is still generated and the link exercised with a test sequence to maintain the training parameters).

[0081] From MI_ACTIVE, a further link training procedure can be performed for the PHY module previously communicating system data using SB_CLK. During this second training phase, power consumption again increases as the MB_CLK is distributed more widely, to include the training PHY module. Bandwidth temporarily drops because only the trained PHY module is available for communication. After a training delay (state 512), the ACTIVE state (labelled Hl_ in Figure 7 for conciseness) is entered in which both PHY modules are configured to communicate using the MB_CLK. The peak bandwidth in the active state is 10 times higher than the bandwidth of the LP_ACTIVE state, because MB_CLK is 10 times higher than SB_CLK. However, it will be seen that the static power consumption of the ACTIVE state is much higher than that of the LP_ACTIVE state (the static power cost will be incurred even if no data is transferred).

[0082] It will be seen from Figure 7 that the ratio of peak bandwidth to power consumption can be much greater in the LP_ACTIVE mode than the ACTIVE mode or during clock gating.

[0083] Figure 8 is a flow diagram illustrating a method of controlling communication over a main band interface. At step 800, a first clock signal (SB_CLK) is received from a first clock source. At step 802, the first clock signal is used to control communication over a sideband interface.

[0084] At step 804 it is determined whether to use the first (SB_CLK) clock signal to also control communication over the main band interface, or whether a second clock signal (MB_CLK) should be used.

[0085] When it is determined that the first clock signal should be used, then at step 810 the same clock signal used for the sideband interface is also used to control communication over the main band interface.

[0086] When it is determined that the second clock signal should be used, then at step 806 the main band interface receives a second clock signal (MB_CLK) having a higher clock frequency than the first clock signal (SB_CLK), and at step 808 uses the higher frequency clock signal to control communication over the main band interface.

[0087] Concepts described herein may be embodied in a system comprising at least one packaged chip. The semiconductor die device described earlier is implemented in the at least one packaged chip, where it may be combined with one or more further semiconductor die devices such that the packaged chip is a system-in-package. The at least one packaged chip is assembled on a board with at least one system component. A chip-containing product may comprise the system assembled on a further board with at least one other product component. The system or the chip-containing product may be assembled into a housing or onto a structural support (such as a frame or blade).

[0088] As shown in Figure 9, one or more packaged chips 900 comprising the semiconductor die device described above are manufactured by a semiconductor chip manufacturer. In some examples, the chip product 900 made by the semiconductor chip manufacturer may be provided as a semiconductor package which comprises a protective casing (e.g. made of metal, plastic, glass or ceramic) containing the semiconductor devices implementing the semiconductor die device described above and connectors, such as lands, balls or pins, for connecting the semiconductor devices to an external environment..

[0089] The one or more packaged chips 900 are assembled on a board 902 together with at least one system component 904 to provide a system 906. For example, the board may comprise a printed circuit board. The board substrate may be made of any of a variety of materials, e.g. plastic, glass, ceramic, or a flexible substrate material such as paper, plastic or textile material. The at least one system component 904 comprise one or more external components which are not part of the one or more packaged chip(s) 900. For example, the at least one system component 904 could include, for example, any one or more of the following: another packaged chip (e.g. provided by a different manufacturer or produced on a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor and / or a sensor.

[0090] A chip-containing product 916 is manufactured comprising the system 906 (including the board 902, the one or more chips 900 and the at least one system component 904) and one or more product components 912. The product components 912 comprise one or more further components which are not part of the system 906. As a non-exhaustive list of examples, the one or more product components 912 could include a user input / output device such as a keypad, touch screen, microphone, loudspeaker, display screen, haptic device, etc.; a wireless communication transmitter / receiver; a sensor; an actuator for actuating mechanical motion; a thermal control device; a further packaged chip; an interface module; a resistor; a capacitor; an inductor; a transformer; a diode; and / or a transistor. The system 906 and one or more product components 912 may be assembled on to a further board 914.

[0091] The board 902 or the further board 914 may be provided on or within a device housing or other structural support (e.g. a frame or blade) to provide a product which can be handled by a user and / or is intended for operational use by a person or company.

[0092] The system 906 or the chip-containing product 916 may be at least one of: an end-user product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automation control system. For example, as a non-exhaustive list of examples, the chipcontaining product could be any of the following: a telecommunications device, a mobile phone, a tablet, a laptop, a computer, a server (e.g. a rack server or blade server), an infrastructure device, networking equipment, a vehicle or other automotive product, industrial machinery, consumer device, smart card, credit card, smart glasses, avionics device, robotics device, camera, television, smart television, DVD players, set top box, wearable device, domestic appliance, smart meter, medical device, heating / lighting control device, sensor, and / or a control system for controlling public infrastructure equipment such as smart motorway or traffic lights.

[0093] Concepts described herein may be embodied in computer-readable code for fabrication of an apparatus that embodies the described concepts. For example, the computer-readable code can be used at one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising the apparatus embodying the concepts. The above computer-readable code may additionally or alternatively enable the definition, modelling, simulation, verification and / or testing of an apparatus embodying the concepts described herein. For example, the computer-readable code for fabrication of an apparatus embodying the concepts described herein can be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register-transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define a HDL representation of the one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High-Speed Integrated Circuit Hardware Description Language) as well as intermediate representations such as FIRRTL. Computer-readable code may provide definitions embodying the concept using system-level modelling languages such as SystemC and SystemVerilog or other behavioural representations of the concepts that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0094] Additionally or alternatively, the computer-readable code may define a low-level description of integrated circuit components that embody concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. The one or more netlists or other computer-readable representation of integrated circuit components may be generated by applying one or more logic synthesis processes to an RTL representation to generate definitions for use in fabrication of an apparatus embodying the invention. Alternatively or additionally, the one or more logic synthesis processes can generate from the computer-readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purposes of verification and test of the concepts prior to fabrication in an integrated circuit or the FPGA may be deployed in a product directly.

[0095] The computer-readable code may comprise a mix of code representations for fabrication of an apparatus, for example including a mix of one or more of an RTL representation, a netlist representation, or another computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus embodying the invention. Alternatively or additionally, the concept may be defined in a combination of a computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus and computer- readable code defining instructions which are to be executed by the defined apparatus once fabricated.

[0096] Such computer-readable code can be disposed in any known transitory computer- readable medium (such as wired or wireless transmission of code over a network) or non- transitory computer-readable medium such as semiconductor, magnetic disk, or optical disc. An integrated circuit fabricated using the computer-readable code may comprise components such as one or more of a central processing unit, graphics processing unit, neural processing unit, digital signal processor or other components that individually or collectively embody the concept.

[0097] In the present application, the words “configured to...” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a "configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation.

[0098] In the present application, lists of features preceded with the phrase “at least one of’ mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of: [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in combination (without C), A and C in combination (without B), B and C in combination (without A), or A, B and C in combination.

[0099] Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

CLAIMS1. A semiconductor die device, comprising a die-to-die communication module for communicating with a separate semiconductor die device, the die-to-die communication module comprising: a sideband interface comprising at least one sideband data pin for communicating with an external interface of the separate semiconductor die device under control of a first clock signal received from a first clock source; and a main band interface comprising two or more main band data pins for communicating with the external interface, wherein the number of main band data pins is larger than the number of sideband data pins; and selection circuitry configured to select whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.

2. The semiconductor device according to claim 1, wherein clock control circuitry is configured to make a determination of whether to power down the second clock source based on whether the selection circuitry selects the first clock signal or the second clock signal for controlling communication over the main band interface.

3. The semiconductor die device according to any preceding claim, wherein the die-to-die communication module is configured to require, as a condition of entry into a main-band-using-second-clock communication state in which communication over the main band data pins is performed under control of the second clock signal, that a link training procedure is performed prior to entry to the main-band-using-second-clock communication state; and the die-to-die communication module is configured to permit entry to a main-band-using- first-clock communication state in which communication over the main band data pins is performed under control of the first clock signal, even if the link training procedure has not been performed prior to entry to the main-band-using-first-clock communication state.

4. The semiconductor die device according to claim 3, wherein the link training procedure is based on communicating with the external interface using the sideband interface.

5. The semiconductor die device according to any preceding claim, comprising a further die-to-die communication module for communicating with the separate semiconductor die device, the further communication module comprising:a further sideband interface comprising at least one further sideband data pin for communicating with the external interface under control of the first clock signal; and a further main band interface comprising two or more further main band data pins for communicating with the external interface under control of at least the second clock signal, wherein the number of further main band data pins is larger than the number of further sideband data pins.

6. The semiconductor die device according to claim 5, comprising routing circuitry arranged to selectively route communication data to any one or more of the die-to-die communication module and the further die-to-die communication module.

7. The semiconductor die device according to any of claims 5 and 6, wherein the selection circuitry is configured to select whether communication over the further main band data pins is controlled based on the first clock signal or the second clock signal.

8. The semiconductor die device according to claim 7, wherein clock control circuitry is configured to power down the second clock source in response to determining that the selection circuitry has selected the first clock signal to control communication over both the main band data pins and the further main band data pins.

9. The semiconductor die device according to any of claims 5 to 8, wherein the die-to-die communication module is configured to require, as a condition of entry into a main-band-using-second-clock communication state in which communication over the main band data pins or the further main band data pins is performed under control of the second clock signal, that a link training procedure is performed prior to entry to the main-band-using- second-clock communication state; and when the die-to-die communication module is in a main-band-using-first-clock communication state in which communication over the main band data pins of the die-to-die communication module is controlled based on the first clock signal, in response to determination that the further die-to-die communication module is to enter the main-band-using-first-clock communication state, the selection circuitry is configured to select that communication over the main band data pins of the die-to-die communication module is controlled based on the first clock signal until the link training procedure has completed.

10. The semiconductor die device according to any preceding claim, wherein in each clock cycle, the main band interface is configured to transmit a greater number of bits per main band data pin than the sideband interface transmits per sideband data pin; andthe semiconductor die device comprises dividing circuitry to divide the first clock signal for controlling communication over the main band data pins, by reducing the clock frequency of the first clock signal.

11. The semiconductor die device according to claim 10, wherein the dividing circuitry is configured to halve the clock frequency of the first clock signal.

12. The semiconductor die device according to any of claims 10 and 11 , comprising dividing control circuitry configured to determine whether or not to divide the first clock signal for controlling communication over the main band data pins.

13. The semiconductor die device according to claim 12, wherein the dividing control circuitry is configured to determine whether or not to divide the first clock signal on the basis of at least one on-die measurement of die-to-die communication reliability when communicating over the main band data pins under the control of the undivided first clock signal.

14. The semiconductor die device according to any preceding claim comprising, as the second clock source, at least one phase-locked loop.

15. The semiconductor die device according to any preceding claim, comprising the first clock source.

16. The semiconductor die device according to any preceding claim, wherein the die-to-die communication module is configured to communicate with the separate semiconductor die device via intermediate transmission circuitry.

17. A system comprising: the semiconductor die device of any preceding claim, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.

18. A chip-containing product comprising the system of claim 17 assembled on a further board with at least one other product component.

19. A computer-readable medium to store computer-readable code for fabrication of a semiconductor die device, comprising a die-to-die communication module for communicating with a separate semiconductor die device, the die-to-die communication module comprising: a sideband interface comprising at least one sideband data pin for communicating with an external interface of the separate semiconductor die device under control of a first clock signal received from a first clock source; and a main band interface comprising two or more main band data pins for communicating with the external interface, wherein the number of main band data pins is larger than the number of sideband data pins; and selection circuitry configured to select whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.

20. A method for a semiconductor die device, comprising communicating with a separate semiconductor die device using a die-to-die communication module of the semiconductor die device , the communication comprising: communicating, using a sideband interface comprising at least one sideband data pin, with an external interface of the separate semiconductor die device under control of a first clock signal received from a first clock source; and communicating, using a main band interface comprising two or more main band data pins, with the external interface, wherein the number of main band data pins is larger than the number of sideband data pins; and selecting whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.

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