Decoder, decoding method, memory controller and memory system

Abstract

Provided in the embodiments of the present disclosure are a decoder, a decoding method, a memory controller and a memory system. The decoder comprises: a cache module and a flipping instruction module, wherein the cache module is configured to cache soft data related to a codeword to be decoded; and the flipping instruction module is configured to acquire the soft data from the cache module, and when hard-decision decoding is executed on said codeword, at least use the soft data in a first flipping iteration to assist in determining the number of bits in said codeword that do not satisfy a check.

Description

Decoder, decoding method, memory controller and memory system Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a decoder, a decoding method, a memory controller, and a memory system. Background Art

[0002] With the development of storage technology, 3D NAND flash memory (Flash) has evolved from single-level cells (SLC) capable of storing 1 bit of information, double-level cells (DLC) capable of storing 2 bits of information, to triple-level cells (TLC) capable of storing 3 bits of information, and even quadruple-level cells (QLC) capable of storing 4 bits of information; and the number of stacked layers is also increasing. Faced with memory devices with an increasing number of layers and storage bits, in order to enhance the reliability of the data stored in the memory devices, low-density parity check (LDPC) is usually used for error correction when reading data. However, as the structure of 3D NAND Flash becomes more complex and more data is stored, the types of errors it contains are becoming more and more complex. Sampling the current error correction method, the error correction speed is slow and the efficiency is reduced, which seriously affects the reading rate.

[0003] Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a decoder comprising: a cache module and a flip indication module, wherein;

[0007] The cache module is configured to: cache soft data related to the codeword to be decoded;

[0008] The flip indication module is configured to: obtain the soft data from the cache module; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check in at least the first flip iteration.

[0009] In the above solution, the flip indication module is further configured to:

[0010] Determining an initial error bit indicator vector corresponding to the codeword to be decoded;

[0011] The soft data is used to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not meet the parity check.

[0012] In the above solution, the decoder further includes: a variable node module and a check node module, wherein the variable node module and the check node module are connected according to a pre-constructed check matrix to form a variable-check connection network; wherein,

[0013] The variable node module is configured to: receive hard read data and generate the codeword to be decoded according to the hard read data; send the codeword to be decoded to the check node module; send the codeword to be decoded and the hard read data to the flip indication module;

[0014] The check node module is configured to: receive the codeword to be decoded; determine a checksum vector according to the codeword to be decoded and the check matrix; and send the checksum vector to the flip indication module;

[0015] The flip indication module is further configured to: receive the codeword to be decoded and the hard-read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; and determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard-read data, the codeword to be decoded, the checksum vector and the check matrix.

[0016] In the above solution, the flip indication module is further configured to:

[0017] Determining a soft data vector corresponding to the soft data;

[0018] Performing an AND operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector;

[0019] determining, according to the target error bit vector, the number of each bit in the codeword to be decoded that fails to meet the parity check;

[0020] Each element in the target error bit vector corresponds to the number of bits that do not meet the parity check.

[0021] In the above solution, the flip indication module is further configured to:

[0022] Performing a sum operation on the hard read data and the codeword to be decoded and then performing a modulo operation to obtain a first bit vector;

[0023] multiplying the transpose of the checksum vector by the check matrix to obtain a second bit vector;

[0024] Perform an AND operation on the first bit vector and the second bit vector to obtain the initial error bit indication vector.

[0025] In the above solution, the flip indication module is further configured to:

[0026] generating a flip indication vector according to the number of bits that do not meet the checksum and the flip criterion; wherein the flip indication vector includes the bits that need to be flipped in the codeword to be decoded;

[0027] The variable node module is further configured to: receive the flip indication vector, and flip the bits to be flipped in the codeword to be decoded according to the flip indication vector.

[0028] In the above solution, the flipping criteria include:

[0029] Flipping the largest number of bits that fail to meet the parity check in the codeword to be decoded;

[0030] Alternatively, bits in the codeword to be decoded, the number of which not meeting the parity check being greater than or equal to a preset threshold, are flipped.

[0031] In the above solution, the decoder further includes: a counting module and a termination decision module, wherein:

[0032] The counting module is configured to: count the number of iterations of performing hard decision on the codeword to be decoded;

[0033] The termination decision module is configured to: determine whether the number of iterations reaches a maximum number of iterations and determine whether the checksum vector is a zero vector; when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, output a first stop decoding signal; the first stop decoding signal is configured to indicate a hard decision decoding failure of the codeword to be decoded.

[0034] In the above solution, the decoder further includes: a rearrangement module;

[0035] The termination decision module is further configured to: output a second stop decoding signal when determining that the checksum vector is a zero vector;

[0036] The rearrangement module is configured to: in response to the second stop decoding signal, rearrange the codewords to be decoded; and output the codewords to be decoded in a correct order.

[0037] In the above scheme, the termination decision module is further configured to: output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the variable node module, the check node module and the flip indication module to continue to perform hard decision decoding operations on the codeword to be decoded.

[0038] In a second aspect, an embodiment of the present disclosure provides a decoding method, including:

[0039] Obtaining soft data corresponding to the codeword to be decoded;

[0040] When performing hard decision decoding on the codeword to be decoded, the soft data is used to assist in determining the number of bits in the codeword to be decoded that fail a parity check in at least a first flipping iteration.

[0041] In the above solution, the using the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check includes:

[0042] Determining an initial error bit indicator vector corresponding to the codeword to be decoded;

[0043] The soft data is used to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not meet the parity check.

[0044] In the above solution, the using the soft data to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not satisfy the parity check includes:

[0045] Determining a soft data vector corresponding to the soft data;

[0046] Performing an AND operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector;

[0047] determining, according to the target error bit vector, the number of each bit in the codeword to be decoded that fails to meet the parity check;

[0048] Each element in the target error bit vector corresponds to the number of bits that do not meet the parity check.

[0049] In the above scheme, determining the initial error bit indicator vector corresponding to the codeword to be decoded includes:

[0050] receiving hard read data, and generating the codeword to be decoded according to the hard read data;

[0051] Determining a checksum vector based on the codeword to be decoded and a pre-constructed check matrix;

[0052] An initial error bit indicator vector corresponding to the codeword to be decoded is determined according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix.

[0053] In the above solution, determining the initial error bit indicator vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix includes:

[0054] Performing a sum operation on the hard read data and the codeword to be decoded and then performing a modulo operation to obtain a first bit vector;

[0055] multiplying the transpose of the checksum vector by the check matrix to obtain a second bit vector;

[0056] Perform an AND operation on the first bit vector and the second bit vector to obtain the initial error bit indication vector.

[0057] In the above solution, the method further includes:

[0058] generating a flip indication vector according to the number of bits that do not meet the checksum and the flip criterion; wherein the flip indication vector includes the bits that need to be flipped in the codeword to be decoded;

[0059] The bits to be flipped in the codeword to be decoded are flipped according to the flip indication vector.

[0060] In the above solution, the method further includes:

[0061] generating a flip indication vector according to the number of bits that do not meet the checksum and the flip criterion; wherein the flip indication vector includes the bits that need to be flipped in the codeword to be decoded;

[0062] The bits to be flipped in the codeword to be decoded are flipped according to the flip indication vector.

[0063] In the above solution, the flipping criteria include:

[0064] Flipping the largest number of bits that fail to meet the parity check in the codeword to be decoded;

[0065] Alternatively, bits in the codeword to be decoded, the number of which not meeting the parity check being greater than or equal to a preset threshold, are flipped.

[0066] In the above solution, the method further includes:

[0067] Counting the number of iterations of performing hard decision on the codeword to be decoded;

[0068] Determining whether the number of iterations reaches a maximum number of iterations and determining whether the checksum vector is a zero vector;

[0069] When the number of iterations reaches a maximum number of iterations and the checksum vector is a non-zero vector, a first stop-decoding signal is output; the first stop-decoding signal is configured to indicate that hard decision decoding of the codeword to be decoded has failed.

[0070] In the above solution, the method further includes:

[0071] Determining whether the checksum vector is a zero vector; outputting a second stop decoding signal when determining that the checksum vector is a zero vector;

[0072] In response to the second stop decoding signal, the code words to be decoded are rearranged, and the code words to be decoded in a correct order are output.

[0073] In the above solution, the method further includes:

[0074] When the checksum vector is not a zero vector and the number of iterations does not reach the maximum number of iterations, a continue decoding signal is output; the continue decoding signal is configured to instruct to perform a hard decision decoding operation on the codeword to be decoded.

[0075] In a third aspect, an embodiment of the present disclosure further provides a memory controller, comprising a processor and any one of the above decoders, wherein the processor is configured to: read soft data corresponding to a codeword to be decoded from the memory device;

[0076] The decoder is configured to: cache the soft data; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check in at least a first flipping iteration.

[0077] In a fourth aspect, an embodiment of the present disclosure provides a memory system, including:

[0078] a memory device configured to: store data;

[0079] A memory controller is coupled to the memory device and includes a processor and a decoder; wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device;

[0080] The decoder is configured to: cache the soft data; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check in at least a first flipping iteration.

[0081] In the above solution, the processor is further configured to: read hard read data from the memory device; send the hard read data to the decoder;

[0082] The decoder is further configured to: receive the hard read data; and generate the codeword to be decoded according to the hard read data.

[0083] In the above solution, the decoder includes: a cache module, a variable node module, a check node module and a flip indication module, wherein;

[0084] The cache module is configured to: cache the soft data read by the processor;

[0085] The variable node module is configured to: receive the hard read data read by the processor; generate the codeword to be decoded according to the hard read data; and send the codeword to be decoded to the check node module;

[0086] The check node module is configured to: receive the codeword to be decoded sent by the variable node module; determine a checksum vector according to the codeword to be decoded and a pre-constructed check matrix; and send the checksum vector to the flip indication module;

[0087] The flip indication module is configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix; and use the soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check check.

[0088] The present disclosure provides a decoder, a decoding method, a memory controller, and a memory system. The decoder includes a cache module and a flip indicator module, wherein the cache module is configured to cache soft data associated with a codeword to be decoded; the flip indicator module is configured to retrieve the soft data from the cache module; and when performing hard decision decoding on the codeword to be decoded, the soft data is used to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check, at least in the first flip iteration. The decoder provided by the present disclosure caches the soft data associated with the codeword to be decoded through the included cache module. The flip indicator module then uses the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check, in one or more iterations, when performing hard decision decoding on the codeword to be decoded. Thus, the soft data is used to assist in the flip decision of hard decision decoding, achieving the high throughput and low power consumption characteristics of hard decision decoding and significantly improving the error correction capability of hard decision decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0090] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0091] FIG2a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0092] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0093] FIG3 is a schematic diagram of the structure of a memory controller provided by an embodiment of the present disclosure;

[0094] FIG4 is a schematic diagram of an exemplary memory device including peripheral circuits according to an embodiment of the present disclosure;

[0095] FIG5 is a cross-sectional schematic diagram of a memory array including NAND memory strings according to an embodiment of the present disclosure;

[0096] FIG6 is a schematic diagram of an exemplary memory device including a memory array and peripheral circuits according to an embodiment of the present disclosure;

[0097] FIG7 is a schematic structural diagram of a decoder provided by an embodiment of the present disclosure;

[0098] FIG8 is an exemplary schematic diagram of obtaining soft data and hard read data according to an embodiment of the present disclosure;

[0099] FIG9 is a schematic structural diagram of a decoder provided by another embodiment of the present disclosure;

[0100] FIG10 is a schematic diagram of a Tanner graph provided by an embodiment of the present disclosure;

[0101] FIG11 is an exemplary Tanner graph provided by an embodiment of the present disclosure;

[0102] FIG12 is a schematic structural diagram of a decoder provided by another embodiment of the present disclosure;

[0103] FIG13 is a schematic structural diagram of a decoder provided by another embodiment of the present disclosure;

[0104] FIG14 is a schematic diagram of a workflow of a decoder provided in one embodiment of the present disclosure;

[0105] FIG15 is a schematic diagram of a flowchart of a decoding method provided in an embodiment of the present disclosure;

[0106] FIG16 is a schematic diagram of the structure of a memory controller provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0107] The following describes various embodiments of the present disclosure in more detail with reference to the accompanying drawings. Other embodiments that can be used as variations of any disclosed embodiment can be formed by configuring or arranging the elements and features in the embodiments of the present disclosure in different ways. Therefore, the embodiments of the present disclosure are not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the embodiments of the present disclosure are thorough and complete, and the scope of the embodiments of the present disclosure is fully conveyed to those skilled in the art of the technical field to which the embodiments of the present disclosure belong. It should be noted that references to "embodiment", "another embodiment" and the like do not necessarily represent only one embodiment, and different references to any such phrases are not necessarily for the same embodiment. It should be understood that although the terms "first", "second", "third" and the like may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. Therefore, without departing from the spirit and scope of the embodiments of the present disclosure, the first element in one embodiment may also be referred to as the second or third element in another embodiment.

[0108] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may be present.

[0109] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified or can be clearly understood from the context to be singular, the articles "one" and / or "an" used in the embodiments of the present disclosure and the appended claims should be collectively interpreted as meaning "one or more". It should be further understood that the terms "include", "including", "comprising" and "comprising" used in the embodiments of the present disclosure specify the presence of the elements and do not exclude the presence or addition of one or more other elements. The term "and / or" used in the embodiments of the present disclosure includes any and all combinations of one or more associated listed items. Unless otherwise defined, all terms including technology and science used in the embodiments of the present disclosure have the same meaning as those of ordinary skill in the art to which the present disclosure belongs in view of the embodiments of the present disclosure. It should be further understood that, unless the embodiments of the present disclosure are clearly defined, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the embodiments of the present disclosure and the related art, and should not be interpreted in an idealized or overly formal manner.

[0110] In the following description, many specific details are set forth to provide a thorough understanding of the present disclosure, and the present disclosure can be practiced without some or all of these specific details. In other cases, well-known processing structures and / or processes are not described in detail to avoid unnecessarily obscuring the present disclosure. It should also be understood that in some cases, unless otherwise specified, it will be apparent to those skilled in the relevant art that features or elements described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of the embodiments of the present disclosure. Well-known technical details may be omitted to avoid obscuring the features and aspects of the embodiments of the present disclosure.

[0111] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0112] Memory devices are memory devices used to store information in modern information technology. As a typical non-volatile memory device, 3D NAND (Not-And) memory devices have become mainstream products in the storage market due to their high storage density, controllable production costs, suitable programming and erasing speeds, and retention characteristics. As the number of storage bits in the memory cell increases and the number of stacked layers increases, the types of errors that occur during the read operation of the memory device become more and more complex. In this case, when the LDPC hard decision decoding in the decoder is used to decode the codeword to be decoded (data read from the memory device), the decoding time is long and the error correction capability is weak, which seriously affects the reading rate.

[0113] Based on one or more of the above problems, the embodiments of the present disclosure provide a decoder that uses soft data to assist the flip decision of hard decision decoding, thereby achieving the high throughput and low power consumption characteristics of hard decision decoding, and greatly improving the error correction capability of hard decision decoding.

[0114] The embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific embodiments.

[0115] FIG1 is a schematic diagram of an exemplary system with a memory system provided by an embodiment of the present disclosure. In FIG1 , system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system therein. As shown in FIG1 , system 100 may include a host 108 and a memory system 102, wherein the host 108 may include a processor such as a central processing unit (CPU) or a system on a chip (SoC), wherein the system on a chip may be, for example, an application processor (AP). The host 108 also includes at least one operating system (OS) that can generally manage and control the functions and operations executed in the host 108. The OS can enable the host 108 coupled to the memory system 102 and a user who needs and uses the memory system 102 to operate with each other. The OS can support functions and operations corresponding to user requests. For example, and not limitation, depending on whether the host 102 is a mobile host, the OS can be categorized as a general-purpose operating system or a mobile operating system. General-purpose operating systems can include personal operating systems and enterprise operating systems. Personal operating systems can be operating systems such as Windows and Chrome that are generally used to support services; enterprise operating systems can be operating systems such as Windows Server, Linux, and Unix that are specifically designed to ensure and support high performance. Mobile operating systems can refer to operating systems that provide services or functions specific to mobility (such as power saving functions). Generally, mobile operating systems can include operating systems such as Android, iOS, and Windows Mobile. In some embodiments, the host 108 can include multiple OSs; accordingly, the host 108 can run multiple operating systems associated with the memory system 102. In other embodiments, the host 108 converts the user's request into one or more commands and transmits the one or more commands to the memory system 102, causing the memory system 102 to perform operations associated with the one or more commands.

[0116] Among them, the memory system 102 can operate or perform specific functions or perform various internal operations in response to a request from the host 108. In some embodiments, the memory system 102 can store data accessed by the host 108. The memory system 102 can be used as a main memory system or an auxiliary memory system of the host 108. The memory system 102 and the host 108 can be electrically connected and communicated according to corresponding protocols. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as, but not limited to: solid state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced size MMC (RSMMC), micro MMC, secure digital (SD) card, mini SD, micro SD, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash (CF) card, smart media (SM) card and memory stick, etc.

[0117] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a storage device configured in a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured in a home network, one of various electronic devices configured in a computer network, one of various electronic devices configured in a telematics network, a radio frequency identification (RFID) device, or one of various components configured in a computing system.

[0118] Returning to FIG. 1 , the memory system 102 may include one or more memory devices 104 and a memory controller 106 . The memory controller 106 may respond to requests from the host 108 and thereby control the memory device 104 . For example, the memory controller 106 may read data from the memory device 104 and transmit the read data to the host 108 ; it may also receive data to be stored from the host 108 and store the data to be stored in the memory device 104 . In other words, the memory controller 106 is capable of controlling write (or program) operations, read operations, erase operations, background operations, and the like of the memory device 104 . Furthermore, the memory system 102 may be implemented and packaged into different types of terminal electronic products. In an example as shown in FIG. 2 a , the memory controller 106 and a single memory device 104 may be integrated into a memory card 202 . The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, or the like. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1 ). In another example, as shown in FIG. 2 b , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0119] 3 , the memory controller 106 may include a host I / F (or front-end interface) 301, a memory I / F (or back-end interface) 302, a processor 303, and a memory 304. The components 301, 302, 303, and 304 in the memory controller 106 may share transmission signals within the memory controller 106 via an internal bus. In some embodiments, the host I / F 301 may interface the host 108 with the memory system 102 in response to a protocol of the host 108, and the host I / F 301 may exchange transmission commands and data operations between the host 108 and the memory system 102. Host I / F 301 can process commands and data sent by host 108 and can include at least one of the following: Universal Serial Bus (USB), MultiMediaCard (MMC), Peripheral Component Interconnect Express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced MiniDisk Interface (ESDI), and Integrated Drive Electronics (IDE). In some embodiments, host I / F 301 is a component used by memory system 102 to exchange data with host 108 and can be implemented through firmware called a host interface layer (HIL).

[0120] The memory I / F 302 may be an interface for commands and data transmitted between the memory controller 106 and the memory device 104, allowing the memory controller 106 to control the memory device 104 in response to a request passed from the host 108. The memory I / F 302 may generate control signals for controlling the memory device 104. In some embodiments, if the memory device 104 is a NAND flash memory, the memory I / F 302 may write data to the memory device 104 or read data from the memory device 104 under the control of the processor 303. The memory I / F 302 may process commands and data between the memory controller 106 and the memory device 104, for example, operations of a NAND flash memory interface, particularly operations between the memory controller 106 and the memory device 104. According to an embodiment, the memory I / F 302 may be implemented as a component for exchanging data with the memory device 104 through firmware referred to as a flash interface layer (FIL).

[0121] The processor 303 may be implemented as a microprocessor or a central processing unit (CPU). The memory system 102 may include one or more processors 303. The processor 303 may control all operations of the memory system 102. As an example and not a limitation, the processor 303 may control programming operations or read operations of the memory device 104 in response to a write request or a read request from the host 108. According to an embodiment, the processor 303 may use or run firmware to control all operations of the memory system 102. In the present disclosure, the firmware may be referred to as a flash translation layer (FTL). The FTL may perform operations as an interface between the host 108 and the memory device 104. The host 108 may transmit requests related to write operations and read operations to the memory device 104 through the FTL. For example, when executing an operation requested by the host 108 in the memory device 104, the memory controller 106 uses the processor 303. The processor 303 coupled to the memory device 104 may process instructions or commands related to commands from the host 108. The memory controller 106 may perform foreground operations such as command operations corresponding to commands input from the host 108, for example, a program operation corresponding to a write command, a read operation corresponding to a read command, an erase / discard operation corresponding to an erase / discard command, and a parameter setting operation corresponding to a set parameter command or a set feature command having a set command.

[0122] For another example, the memory controller 106 may perform background operations on the memory device 104 via the processor 303. By way of example and not limitation, these background operations may include garbage collection (GC) operations, wear leveling (WL) operations, map cleanup operations, and bad block management operations for checking or searching for bad blocks. Garbage collection operations may include operations for copying and processing data stored in a memory block in the memory device 104 to another memory block. Wear leveling operations may include operations for exchanging and processing stored data between memory blocks in the memory device 104. Map cleanup operations may include operations for storing map data stored in the memory controller 106 in memory blocks in the memory device 104. Bad block management operations may include operations for checking and processing bad blocks in memory blocks in the memory device 104. The memory controller 106 may respond to operations for accessing memory blocks in the memory device 104, wherein the operations for accessing memory blocks in the memory device 104 may include foreground operations or background operations performed on the memory blocks in the memory device 104.

[0123] The memory 304 may be a working memory of the memory controller 106 and is configured to store data for driving the memory controller 106. More specifically, when the memory controller 106 controls the memory device 104 in response to a request from the host 108, the memory 304 may store firmware driven by the processor 303 and data required to drive the firmware (e.g., metadata). The memory 304 may also be a buffer memory of the memory controller 106 and is configured to temporarily store write data transferred from the host 108 to the memory device 104 and read data transferred from the memory device 104 to the host 108. The memory 304 may include a program memory for storing write data and read data, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, and a mapping buffer / cache. The memory 304 may be implemented using a volatile memory. The memory 304 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0124] 3 shows that memory 304 is included in memory controller 106, the present disclosure is not limited thereto. In an embodiment, memory 304 may be included outside memory controller 106, and memory controller 106 may input and output data to memory 304 through a separate memory interface (not shown).

[0125] The error correction (ECC) module 305 includes an encoding unit 3051 and a decoding unit 3052. The encoding unit 3051 can perform an encoding operation such as LDPC on the data to be programmed into the semiconductor memory device 104 and output data including additional parity bits. The parity bits can be stored in the semiconductor memory device 104. The decoding unit 3052 can perform error correction decoding on the data read from the semiconductor memory device 104; it can also determine whether the error correction decoding is successful and output a command signal based on the determination result; it can also use the parity bits generated by the LDPC encoding operation to correct erroneous bits in the data.

[0126] Here, although FIG3 shows that the error correction module 305 is included in the memory controller 106, the present disclosure is not limited thereto. In an embodiment, the error correction module 305 may be included outside the memory controller 106, and the memory controller 106 may communicate data with the error correction module 305 through a separate interface (not shown).

[0127] Referring back to FIG. 1 , the memory device 104 may include a non-volatile memory that retains data stored therein even when power is not supplied. The memory device 104 may also include a volatile storage memory. The device 104 may store data provided from the host 108 through a write operation; the memory device 104 may also provide the stored data to the host 108 through a read operation. In embodiments of the present disclosure, the memory device 104 may include any disclosed memory, such as a volatile memory device such as a dynamic random access memory (DRAM) and a static RAM (SRAM), or a non-volatile memory device such as a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM or ReRAM), and a flash memory (e.g., a three-dimensional NAND flash memory).

[0128] Memory devices are described using a three-dimensional NAND flash memory as an example. Referring to FIG. 4 , a schematic circuit diagram of an exemplary memory device 400 including peripheral circuitry according to some aspects of the present disclosure is shown. Memory device 400 may be an example of memory device 104 in FIG. Memory device 400 may include a memory array 401 and peripheral circuitry 402 coupled to memory array 401. For purposes of illustration, memory array 401 is described as a three-dimensional NAND-type memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0129] In some embodiments, each memory cell 406 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 406 is a two-bit memory cell (MLC) that can store more than one bit of data in more than four memory states. For example, an MLC can store two bits per memory cell, three bits per memory cell (also known as a three-bit memory cell (TLC), four bits per cell (also known as a four-bit memory cell (QLC), or five bits per cell (also known as a five-bit memory cell (PLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0130] As shown in FIG4 , each NAND memory string 408 may include a lower select gate (BSG) 410 at its source terminal and a top select gate (TSG) 412 at its drain terminal. The BSG 410 and TSG 412 may be configured to activate a selected NAND memory string 408 during read and program operations. In some embodiments, the sources of the NAND memory strings 408 in the same memory block 404 are coupled via the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the TSG 412 of each NAND memory string 408 is coupled to a corresponding bit line (BL) 416, from which data may be read or written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 412) or a deselect voltage (e.g., 0V) to a corresponding TSG 412 via one or more TSG lines 413 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 410) or a deselect voltage (e.g., 0V) to a corresponding BSG 410 via one or more BSG lines 415.

[0131] As shown in FIG4 , a NAND memory string 408 can be organized into a plurality of memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic unit of data for erase operations, i.e., all memory cells 406 on the same memory block 404 are erased simultaneously. To erase the memory cells 406 in a selected memory block 404, the source lines 414 coupled to the selected memory block 404 and to unselected memory blocks 404 in the same plane as the selected memory block 404 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled by word lines 418, which select which row of memory cells 406 is affected by read and program operations.

[0132] FIG5 illustrates a cross-sectional schematic diagram of an exemplary memory array 401 including a NAND memory string 408 according to aspects of the present disclosure. As shown in FIG5 , the NAND memory string 408 may include a stacked structure 510 comprising a plurality of gate layers 511 and a plurality of insulating layers 512 alternately stacked in sequence, and a memory string 408 vertically extending through the gate layers 511 and insulating layers 512. The gate layers 511 and insulating layers 512 may be alternately stacked, with adjacent gate layers 511 separated by an insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 may determine the number of memory cells included in the memory array 401.

[0133] The constituent material of the gate layer 511 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 may extend laterally as an upper selection gate line 513, the gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a lower selection gate line 514, and the gate layer 511 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer 503.

[0134] In some embodiments, the stacked structure 510 may be disposed on a substrate 501. The substrate 501 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0135] In some embodiments, NAND memory string 408 includes a channel structure extending vertically through stacked structure 510. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polysilicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0136] Referring back to FIG4 , the peripheral circuitry 402 can be coupled to the memory array 401 via bit lines 416, word lines 418, source lines 414, BSG lines 415, and TSG lines 413. The peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 401 by applying and sensing voltage and / or current signals to and from each target memory cell 406 via the bit lines 416, word lines 418, source lines 414, BSG lines 415, and TSG lines 413. The peripheral circuitry 402 can include various types of circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, FIG6 illustrates some exemplary peripheral circuitry, including a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, registers 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 6 may also be included.

[0137] The page buffer / sense amplifier 604 can be configured to read data from the memory array 401 and program (write) data to the memory array 401 according to control signals from the control logic 612. In one example, the page buffer / sense amplifier 604 can store program data (write data) to be programmed into the memory array 401. In another example, the page buffer / sense amplifier 604 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 can also sense a low-power signal from the bit line 416 representing a data bit stored in the memory cell 406 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 606 can be configured to be controlled by the control logic 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from the voltage generator 610.

[0138] The row decoder / word line driver 608 can be configured to be controlled by control logic 612 and select / deselect memory blocks 404 of the memory array 401 and select / deselect word lines 418 of the memory blocks 404. The row decoder / word line driver 608 can also be configured to drive the word lines 418 using word line voltages generated from a voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive the BSG lines 415 and the TSG lines 413. The row decoder / word line driver 608 can be configured to perform a program operation on the memory cells 406 coupled to the selected word line(s) 418. The voltage generator 610 can be configured to be controlled by control logic 612 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boosting voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0139] The control logic 612 can be coupled to each of the peripheral circuits described above, such as the voltage generator 610, the row decoder / word line driver 608, and the like, and is configured to control the operation of each circuit. The register 614 can be coupled to the control logic 612 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 616 can be coupled to the control logic 612 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 612, as well as to buffer status information received from the control logic 612 and relay it to the host. The interface 616 can also be coupled to the column decoder / bit line driver 606 via the data bus 618 and act as a data I / O interface and a data buffer to buffer data and relay it to or from the memory array 401.

[0140] In 3D NAND memory devices, single-cell (SLC) memory devices occupy a certain share of the memory market due to their advantages such as fast read and write speeds, high reliability, and long service life. Meanwhile, multi-cell (MLC), triple-cell (TLC), and quad-cell (QLC) memory devices are becoming the development trend of the memory market due to their higher storage density and larger storage capacity.

[0141] However, as the number of storage bits in a memory cell increases and the number of stacked layers increases, the types of errors it contains become increasingly complex. When performing a read operation on the memory device, using LDPC hard decision decoding to decode the codeword to be decoded takes a long time and has a weak error correction capability, which seriously affects the reading rate.

[0142] Based on the memory device and memory system described above, in order to solve one or more of the above-mentioned problems, refer to FIG7 , which is a schematic diagram of the structure of a decoder provided in an embodiment of the present disclosure.

[0143] Specifically, the decoder 700 includes: a cache module 701 and a flip indication module 702, wherein;

[0144] The cache module 701 is configured to: cache soft data related to the codeword to be decoded;

[0145] The flip indication module 702 is configured to: obtain the soft data from the cache module 701; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check in at least the first flip iteration.

[0146] It should be noted that the decoder provided in the embodiments of the present disclosure can be applied to a memory system such as the aforementioned one, and the decoder 700 can be provided within a decoding unit of a memory controller as shown in FIG3 , and configured to perform a decoding operation on a codeword to be decoded. The codeword to be decoded herein can refer to hard read data, which can be read from a memory device by a memory controller according to a hard read voltage, or the codeword to be decoded can be a codeword that is flipped during a certain iteration of the decoding process. Whether the codeword to be decoded is hard read data or a codeword that is flipped during a certain iteration is explained in detail in the subsequent description and is not further elaborated here.

[0147] Here, the hard read voltage may be an initial read voltage (the initial read voltage is a default read voltage preset by the memory system, which may be the same as a reference voltage in a read retry table (RRT), or may have a certain offset from the reference voltage. The offset is included in the RRT); or, the hard read voltage may be an optimal read voltage. The optimal read voltage may be obtained by, but is not limited to, determining an optimal read voltage based on the usage of the memory device and the RRT, the specific process comprising: traversing the RRT, determining a voltage offset in the RRT that results in the least error in reading the memory device under the usage condition, and then obtaining the optimal read voltage based on the reference voltage and the determined voltage offset.

[0148] It should be noted that the RRT is a table containing multiple voltage offsets, where each voltage offset is relative to a reference voltage. These voltage offsets can be implemented by the hardware circuits in the memory, for example, by setting these voltage offsets through registers contained in the memory. In other words, all read voltages are obtained by obtaining the required voltage offset according to this RRT table, and then superimposed with the reference voltage (including the superposition of the sign, that is, if the voltage offset is negative, the final read voltage is less than the reference voltage) to obtain the required voltage value, which is then applied to the corresponding word line.

[0149] For example, Table 1 shows the RRT corresponding to a TLC-type memory cell provided by an embodiment of the present disclosure. Each column in Table 1 represents a set of voltage offsets relative to a corresponding reference voltage for distinguishing adjacent programming states, namely, Rd1 to Rd7. It should be noted that since a TLC-type memory cell has eight data states, they can be distinguished using seven read voltages, which is why Table 1 has seven columns.

[0150] Among them, the set of voltage offsets described above can include a positive offset that increases in a direction greater than the reference voltage, and a negative offset that decreases in a direction less than the reference voltage. For example, for Rd7, +V1, +V2, +V3, and +V4 are positive offsets, wherein the values ​​of V1, V2, V3, and V4 increase in sequence; and -V5 to -V11 are negative offsets, wherein the values ​​of V5 to V11 decrease in sequence.

[0151] Table 1 RRT

[0152] Returning to the decoder shown in FIG7 , the soft data used in the decoder can be a type of probabilistic information used to measure the reliability of a particular read data (such as the hard read data in the disclosed embodiment). This information can be represented by a log-likelihood ratio (LLR). Thus, a read data is used as a benchmark, and the soft data is used to measure its reliability.

[0153] For soft data, see Figure 8. In Figure 8, assume that the hard read data read using the optimal read voltage is 1100; the data read using the first reread voltage is 1000, where the first reread voltage is to the left of the optimal read voltage and has a certain offset from the optimal read voltage, denoted as -Δ; and the data read using the second reread voltage is 1110, where the second reread voltage is to the right of the optimal read voltage and has a certain offset from the optimal read voltage, denoted as +Δ. Correspondingly, the soft data can be 0110. In this case, the soft data can be used to determine the reliability of the hard read data 1100 / 1000 / 1110. Specifically, the soft data is used to determine the reliability of the hard read data. A bit with a "0" in the soft data indicates that the reliability of that bit in the hard read data is relatively high; in other words, the bit is judged to be closer to the truth. A bit with a "1" in the soft data indicates that the reliability of that bit in the hard read data is relatively low. For example, in Figure 8, the reliability of hard read data 1100 is determined using soft data 0110. If the leftmost bit is "1" and the corresponding bit in the soft data is "0," the reliability of that bit is high, or a strong "1." Similarly, if the middle two bits in hard read data 1100 correspond to "1" in the soft data, their reliability is weak, or a weak "1" or "0." The rightmost bit in hard read data 1100 is a strong "0."

[0154] In some embodiments, the soft data may be obtained by directly reading the soft data from a NAND memory device, as shown in FIG8 . Specifically, a memory controller may send a command to the memory device to read the soft data, and the memory device may feed the soft data back to the memory controller. In other embodiments, the soft data may also be obtained based on an exclusive-or result of two consecutive hard-read data pre-cached in the memory of the memory controller.

[0155] The decoder provided by the embodiment of the present disclosure, when performing hard decision decoding on a codeword to be decoded, uses soft data related to the codeword to be decoded cached by a cache module in the decoder, and then uses the soft data to assist in determining the number of bits in the decoded codeword that do not meet the parity check, wherein the hard decision decoding can be LDPC bit flip decoding. In LDPC bit flip decoding, at least in the first flip iteration, fast-read soft data is used to assist in LDPC bit flip decoding, so as to greatly improve the correction capability of LDPC bit flip decoding. The use of soft data to assist bit flip judgment at least in the first flip iteration can mean that it is used only in the first flip iteration; or in the first flip iteration and the second flip iteration; or, by analogy, in multiple flip iterations.

[0156] Here, the "failure to satisfy the check check" may refer to the fact that, after a single check is performed on the codeword to be decoded using the check matrix, each non-zero element in the checksum vector generated corresponds to an equation in which a bit in the codeword to be decoded participates in the check check. The "number of bits in the codeword to be decoded that fail to satisfy the check check" may refer to the number of non-zero elements in the check check equation in which the bits in the codeword to be decoded participate.

[0157] For example, assume the codeword to be decoded is: C1C2C3C4C5C6C8C9C10C11C12; when it is checked once, the checksum vector satisfied is as follows:

[0158] In this case, the number of bits in the codeword to be decoded that do not meet the parity check is as follows: C1: 2; C2: 2; C3: 0; C4: 1; C5: 2; C6: 1; C7: 1; C8: 0; C9: 0; C10: 1; C11: 0; C12: 1.

[0159] In some embodiments, the flip indication module 702 may also be configured to:

[0160] Determining an initial error bit indicator vector corresponding to the codeword to be decoded;

[0161] The soft data is used to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not meet the parity check.

[0162] It should be noted that this step specifically describes how to use soft data to assist in determining the number of bits in the codeword to be decoded that fail the parity check. Specifically, an initial error bit indicator vector is first determined for the codeword to be decoded. This initial error bit indicator vector can indicate the number of bits in the codeword to be decoded that fail the parity check when only LDPC bit-flipping decoding is performed without soft data assistance. Soft data is then used to assist in determining the number of bits in the codeword to be decoded that fail the parity check based on this initial error bit indicator vector.

[0163] Specifically, in some embodiments, the flip indication module 702 is further configured to:

[0164] Determining a soft data vector corresponding to the soft data;

[0165] Performing an AND operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector;

[0166] determining, according to the target error bit indicator vector, the number of each bit in the to-be-decoded codeword that fails to meet the parity check;

[0167] Each element in the target error bit vector corresponds to the number of bits that do not meet the parity check.

[0168] It should be noted that here is how to use soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the parity check. Specifically, the soft data is first represented in the form of a soft data vector; then, the soft data vector is ANDed with the aforementioned initial error bit indicator vector to obtain a target error bit indicator vector, in which each element of the target error bit indicator vector corresponds to the number of bits that do not meet the parity check.

[0169] For example, assuming that the initial error bit vector is: {0, 1, 1, 0}; the soft data vector corresponding to the soft data is {0, 1, 1, 0}; then, the target error bit vector is: {0, 2, 2, 0}, where the number of check failures corresponding to the first bit in the codeword to be decoded is 0; the number of check failures corresponding to the second bit in the codeword to be decoded is 2; the number of check failures corresponding to the third bit in the codeword to be decoded is 2; and the number of check failures corresponding to the fourth bit in the codeword to be decoded is 0.

[0170] In the embodiments of the present disclosure, regarding the acquisition of the initial error bit indicator vector, in some embodiments, as shown in FIG9 , the decoder 700 further includes: a variable node module 703 and a check node module 704, wherein the variable node module and the check node module are connected according to a pre-constructed check matrix to form a variable-check connection network; wherein,

[0171] The variable node module 703 is configured to: receive hard read data and generate the codeword to be decoded according to the hard read data; send the codeword to be decoded to the check node module; send the codeword to be decoded and the hard read data to the flip indication module;

[0172] The check node module 704 is configured to: receive the codeword to be decoded; determine a checksum vector according to the codeword to be decoded and the check matrix; and send the checksum vector to the flip indication module;

[0173] The flip indication module 702 is further configured to: receive the codeword to be decoded and the hard-read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; and determine the initial error bit indication vector corresponding to the codeword to be decoded based on the hard-read data, the codeword to be decoded, the checksum vector and the check matrix.

[0174] It should be noted that the decoder shown in FIG7 only discloses the main structures related to the inventive concept of the disclosed embodiment. In LDPC bit-flipping decoding, the decoder may further include a variable node module and a check node module, and the variable node module may include multiple variable node units; the check node module may include multiple check node units; the multiple variable node units and the multiple check node units are connected according to a pre-constructed check matrix to form a variable-check connection network. Here, the pre-constructed check matrix may refer to an LDPC check matrix, also referred to as an H matrix.

[0175] In practical applications, the variable-check connection network formed above can also be called a Tanner graph, as specifically shown in Figure 10. In Figure 10, the Tanner graph includes check nodes 1001, variable nodes 1002, and edges 1003 connecting the check nodes to the variable nodes. The values ​​transferred from the check nodes to the variable nodes after check node processing are called check node information 1004A; the values ​​transferred from the variable nodes to the check nodes after variable node processing are called variable node information 1004B.

[0176] As an example, referring to FIG11 , a Tanner graph includes five check nodes 1001 of a parity check equation of an H matrix, ten variable nodes 1002 representing code symbols, and edges 1003 representing relationships between the check nodes and the variable nodes. Edges 1003 connect each check node to the variable node corresponding to the code symbol included in the parity check equation represented by the check node. FIG11 illustrates a Tanner graph formed by an H matrix, in which the number of variable nodes connected to each check node is fixed at 4, and the number of check nodes connected to each variable node is fixed at 2. The initial values ​​of the variable nodes can be hard read data.

[0177] Under the decoder structure shown in Figure 9, the variable node module can receive hard-read data and generate a codeword to be decoded based on the hard-read data; and send the codeword to be decoded to the check node module; send the codeword to be decoded and the hard-read data to the flip indication module; the check node module can receive the codeword to be decoded, and determine the check sum vector based on the codeword to be decoded and the aforementioned check matrix, and send the check sum vector to the flip indication module; the flip indication module can receive the aforementioned codeword to be decoded, hard-read data, check vector and, and obtain the check matrix, and then use the codeword to be decoded, hard-read data, check vector and the check matrix to obtain the initial error bit indication vector.

[0178] It should be noted that, based on the previous description, the decoder can be located in the decoding section of the memory controller. Therefore, the hard read data received by the variable node module can be read data fed back by the memory device via the memory I / F in response to a read command from the processor and transmitted directly to the variable node module via the bus. Alternatively, the read data fed back by the memory device via the memory I / F in response to a read command from the processor is temporarily stored in the memory, and the processor retrieves the hard read data from the memory and transmits it to the variable node module. Any other process that can obtain hard read data is also possible. In general, the decoder is internal to the memory controller and coupled to other components such as the processor via the bus. Therefore, the variable node module can receive hard read data from outside the decoder. After receiving the hard read data, the variable node module assigns the value of each bit of the hard read data to the corresponding variable node unit, generating a codeword to be decoded.

[0179] The checksum vector may be determined based on the codeword to be decoded and the check matrix, by multiplying the transposed product of the check matrix and the codeword to be decoded to obtain the checksum vector.

[0180] For the initial error bit indicator vector obtained by using the codeword to be decoded, the hard read data, the check vector and the check matrix, in some embodiments, the flip indication module 702 is further configured to:

[0181] Performing a sum operation on the hard read data and the codeword to be decoded and then performing a modulo operation to obtain a first bit vector;

[0182] multiplying the transpose of the checksum vector by the check matrix to obtain a second bit vector;

[0183] Perform an AND operation on the first bit vector and the second bit vector to obtain the initial error bit indication vector.

[0184] It should be noted that the steps described here are how to obtain the initial error bit indicator vector using the codeword to be decoded, the hard read data, the check vector, and the check matrix. Specifically, the hard read data (the codeword to be decoded in the first iterative flip) is first summed with the codeword to be decoded and then modulo-operated to obtain a first bit vector; the transpose of the check sum vector is then multiplied by the check matrix to obtain a second bit vector; and the first bit vector is then summed with the second bit vector to obtain the aforementioned initial error bit indicator vector. Here, the number of elements in the first and second bit vectors is the same as the number of bits in the codeword to be decoded.

[0185] Specifically, the calculation process described above can be described by the following formula: f1 = (y + y0) mod 2 + s′H

[0186] Wherein, f1 is the initial error bit indicator vector, each element of which corresponds to a bit in the codeword to be decoded; y is the codeword to be decoded; y0 is the hard read data; s' is the transpose of the checksum vector; and H is the check matrix.

[0187] It should be noted that in the first flip iteration, y=y0, that is, in the first flip iteration, the codeword to be decoded is the hard read data; in the remaining flip iterations, the codeword to be decoded is the hard read data after bit flipping.

[0188] Based on this, in the embodiment of the present disclosure, the target error bit indication vector can be expressed by the following formula: f2=(y+y0)mod2+s′H+R

[0189] Wherein, f2 is the target error bit indicator vector; R is the soft data.

[0190] In some embodiments, the flip indication module 702 is further configured to:

[0191] generating a flip indication vector according to the number of bits that do not meet the checksum and the flip criterion; wherein the flip indication vector includes the bits that need to be flipped in the codeword to be decoded;

[0192] The variable node module 703 is further configured to receive the flip indication vector and flip the bits to be flipped in the codeword to be decoded according to the flip indication vector.

[0193] The flipping criteria may include:

[0194] Flipping the largest number of bits that fail to meet the parity check in the codeword to be decoded;

[0195] Alternatively, bits in the codeword to be decoded, the number of which not meeting the parity check being greater than or equal to a preset threshold, are flipped.

[0196] It should be noted that after obtaining the target error bit indicator vector mentioned above, the number of bits that do not meet the checksum is obtained for each bit in the codeword to be decoded. Afterwards, the flip indication module obtains a flip indication vector based on the number of bits that meet the checksum and the flip criteria obtained for each bit; afterward, the variable node module flips the bits to be flipped in the codeword to be decoded according to the flip indication vector. Among them, the flip criteria here include but are not limited to flipping the bits with the largest number of bits that do not meet the checksum in the codeword to be decoded, and flipping the bits with the number of bits that do not meet the checksum greater than or equal to the preset threshold in the codeword to be decoded. The above description is that only the bits corresponding to the largest data in f2 are flipped; or, the bits in f2 with data greater than or equal to T (that is, the preset threshold) are flipped.

[0197] In some embodiments, as shown in FIG12 , the decoder 700 further includes: a counting module 704 and a termination decision module 705 , wherein:

[0198] The counting module 704 is configured to: count the number of iterations of performing hard decision on the codeword to be decoded;

[0199] The termination decision module 705 is configured to: determine whether the number of iterations reaches the maximum number of iterations and determine whether the checksum vector is a zero vector; when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, output a first stop decoding signal; the first stop decoding signal is configured to indicate a hard decision decoding failure of the codeword to be decoded.

[0200] It should be noted that in hard-decision decoding, the number of flipping iterations is limited. This number of flipping iterations can be counted by a counting module 704, that is, the counting module counts the number of iterations. Thereafter, a termination decision module 705 determines whether the counted number of iterations has reached a maximum number of iterations and whether the checksum vector is a zero vector. When the maximum number of iterations has been reached and the checksum vector is a non-zero vector, a first stop-decoding signal is output. This first stop-decoding signal is used to indicate that hard-decision decoding of the codeword to be decoded has failed.

[0201] In some embodiments, the decoder 700 further includes: a rearrangement module 706;

[0202] The termination decision module 705 is further configured to: output a second stop decoding signal when determining that the checksum vector is a zero vector; the second stop decoding signal is configured to indicate that the hard decision decoding of the codeword to be decoded is successful;

[0203] The rearrangement module 706 is configured to: in response to the second stop decoding signal, rearrange the codewords to be decoded; and output the codewords to be decoded in a correct order.

[0204] It should be noted that when the termination decision module 705 outputs the second stop decoding signal, the rearrangement module responds to the second stop decoding signal, rearranges the codewords to be decoded, and outputs the codewords to be decoded in the correct order, thereby completing the decoding of the hard read data.

[0205] In some embodiments, the termination decision module 705 is further configured to: output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the variable node module, the check node module and the flip indication module to continue to perform hard decision decoding operations on the codeword to be decoded.

[0206] It should be noted that the steps here may refer to the termination decision module outputting a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the aforementioned variable node module, check node module and flip indication module to continue to perform hard decision decoding operations on the codeword to be decoded, so as to determine whether the decoding of the codeword to be decoded is successful or unsuccessful.

[0207] Based on the above description, Figure 13 shows a schematic diagram of the decoder structure provided by one embodiment of the present disclosure. It should be noted that in Figure 13, d represents hard read data; v represents the codeword to be decoded; S represents the checksum vector; I represents the flip indicator vector; and Stop represents the stop decoding signal, including the first and second stop decoding signals described above. Here, the first and second sub-connection networks together constitute the variable-check node connection network.

[0208] Based on the decoder shown in FIG13 , the decoding workflow provided by the embodiment of the present disclosure may be as shown in FIG14 . Specifically, an achievable decoding workflow may be as follows:

[0209] S1401: Obtain hard read data y0 and soft data R; assign the hard read data to the codeword to be decoded y (y=y0); and cache the soft data; the number of iterations is 0; here, y0 is d in Figure 13; y is v in 13.

[0210] S1402: Generate a checksum vector using the check matrix and the codeword to be decoded; and determine whether the checksum vector is a zero vector (i.e., H*y T =0?); if so, execute S1403; if not, execute S1404;

[0211] S1403: Output the successfully decoded codeword to be decoded, and end the process;

[0212] S1404: Determine whether the number of iterations reaches the maximum number of iterations; if so, execute S1305; if not, execute S1406;

[0213] S1405: Output a decoding failure indication signal; for example, a first stop decoding signal.

[0214] S1406: Calculate the number of bits in the codeword to be decoded that do not meet the parity check using the f2 formula;

[0215] S1407: Determine the features to be flipped in the codeword to be decoded based on the number of codewords that do not meet the verification check and the flipping criterion;

[0216] S1408: The number of iterations is increased by 1, and the process proceeds to the next iteration, and S1402 to S1408 are executed in sequence until the decoding succeeds or fails, and the process ends.

[0217] It should be noted that the methods for obtaining hard read data and soft data in step S1401 have been described above. That is, the hard read data can be directly received as feedback from the memory device or obtained from the memory of the memory controller; the soft data can be cached in the cache module of the decoder and then obtained from the cache module. The above steps are only one implementation method of the decoding workflow. The execution order of each step can be adjusted according to actual conditions. For example, S1404 can first determine whether the maximum number of iterations has been reached before S1402. If the maximum number of iterations has not been reached, the check matrix and the codeword to be decoded are used to generate a checksum vector. Otherwise, a decoding failure indication signal is output, and the process ends.

[0218] The decoder provided in the embodiments of the present disclosure applies soft data to LDPC bit-flip (i.e., hard decision) decoding, and utilizes the strong error correction capability of soft data to speed up LDPC bit-flip decoding, thereby reducing the power consumed by LDPC bit-flip decoding and improving the error correction throughput of the decoder.

[0219] The present disclosure also provides a decoding method, as shown in FIG15 , including:

[0220] S1501: Acquire soft data corresponding to the codeword to be decoded;

[0221] S502: When performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check in at least a first flipping iteration.

[0222] In some embodiments, the using the soft data to assist in determining the number of bits in the to-be-decoded codeword that do not satisfy the parity check includes:

[0223] Determining an initial error bit indicator vector corresponding to the codeword to be decoded;

[0224] The soft data is used to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not meet the parity check.

[0225] In some embodiments, the step of using the soft data to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not satisfy a parity check comprises:

[0226] Determining a soft data vector corresponding to the soft data;

[0227] Performing an AND operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector;

[0228] determining, according to the target error bit vector, the number of each bit in the codeword to be decoded that fails to meet the parity check;

[0229] Each element in the target error bit vector corresponds to the number of bits that do not meet the parity check.

[0230] In some embodiments, determining the initial error bit indicator vector corresponding to the codeword to be decoded includes:

[0231] receiving hard read data, and generating the codeword to be decoded according to the hard read data;

[0232] Determining a checksum vector based on the codeword to be decoded and a pre-constructed check matrix;

[0233] An initial error bit indicator vector corresponding to the codeword to be decoded is determined according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix.

[0234] In some embodiments, determining the initial error bit indicator vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix includes:

[0235] Performing a sum operation on the hard read data and the codeword to be decoded and then performing a modulo operation to obtain a first bit vector;

[0236] multiplying the transpose of the checksum vector by the check matrix to obtain a second bit vector;

[0237] Perform an AND operation on the first bit vector and the second bit vector to obtain the initial error bit indication vector.

[0238] In some embodiments, the method further comprises:

[0239] generating a flip indication vector according to the number of bits that do not meet the checksum and the flip criterion; wherein the flip indication vector includes the bits that need to be flipped in the codeword to be decoded;

[0240] The bits to be flipped in the codeword to be decoded are flipped according to the flip indication vector.

[0241] In some embodiments, the flipping criteria include:

[0242] Flipping the largest number of bits that fail to meet the parity check in the codeword to be decoded;

[0243] Alternatively, bits in the codeword to be decoded, the number of which not meeting the parity check being greater than or equal to a preset threshold, are flipped.

[0244] In some embodiments, the method further comprises:

[0245] Counting the number of iterations of performing hard decision on the codeword to be decoded;

[0246] Determining whether the number of iterations reaches a maximum number of iterations and determining whether the checksum vector is a zero vector;

[0247] When the number of iterations reaches a maximum number of iterations and the checksum vector is a non-zero vector, a first stop-decoding signal is output; the first stop-decoding signal is configured to indicate that hard decision decoding of the codeword to be decoded has failed.

[0248] In some embodiments, the method further comprises:

[0249] Determining whether the checksum vector is a zero vector; outputting a second stop decoding signal when determining that the checksum vector is a zero vector;

[0250] In response to the second stop decoding signal, the code words to be decoded are rearranged, and the code words to be decoded in a correct order are output.

[0251] In some embodiments, the method further comprises:

[0252] When the checksum vector is not a zero vector and the number of iterations does not reach the maximum number of iterations, a continue decoding signal is output; the continue decoding signal is configured to instruct to perform a hard decision decoding operation on the codeword to be decoded.

[0253] It should be noted that the decoding method provided in the embodiment of the present disclosure is actually the workflow of the decoder provided above. The workflow of the decoder has been described in detail above. The terms and features appearing here can be found in the above description and will not be repeated here.

[0254] The present disclosure also provides a memory controller 1600, as shown in FIG16 , comprising: a processor 1601 and any one of the decoders 700 described above, wherein the processor 1601 is configured to: read soft data corresponding to a codeword to be decoded from the memory device;

[0255] The decoder is configured to: cache the soft data; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check in at least a first flipping iteration.

[0256] It should be noted that the memory controller provided in the embodiment of the present disclosure includes the aforementioned decoder. Therefore, the terms and features of the decoder have been described in detail above and will not be repeated here.

[0257] The present disclosure also provides a memory system, including:

[0258] a memory device configured to: store data;

[0259] A memory controller is coupled to the memory device and includes a processor and a decoder; wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device;

[0260] The decoder is configured to: cache the soft data; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the parity check in at least a first flipping iteration.

[0261] In some embodiments, the processor is further configured to: read hard read data from the memory device; send the hard read data to the decoder;

[0262] The decoder is further configured to: receive the hard read data; and generate the codeword to be decoded according to the hard read data.

[0263] In some embodiments, the decoder includes: a cache module, a variable node module, a check node module and a flip indication module, wherein;

[0264] The cache module is configured to: cache the soft data read by the processor;

[0265] The variable node module is configured to: receive the hard read data read by the processor; generate the codeword to be decoded according to the hard read data; and send the codeword to be decoded to the check node module;

[0266] The check node module is configured to: receive the codeword to be decoded sent by the variable node module; determine a checksum vector according to the codeword to be decoded and a pre-constructed check matrix; and send the checksum vector to the flip indication module;

[0267] The flip indication module is configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix; and use the soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check check.

[0268] It should be noted that the memory system provided by the embodiment of the present disclosure includes the memory controller described above and the decoder included in the memory controller. Therefore, the various related terms and features described here can be found in the above description and will not be repeated here.

[0269] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A decoder, comprising: A cache module and a flip indication module, wherein; The cache module is configured to: cache soft data related to the codeword to be decoded; The flip indication module is configured to: obtain the soft data from the cache module; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not satisfy the verification check at least in the first flip iteration.

2. The decoder according to claim 1, wherein: The flip indication module is further configured as follows: Determining an initial error bit indicator vector corresponding to the codeword to be decoded; The soft data is used to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not satisfy the parity check.

3. The decoder according to claim 2, wherein: The decoder further comprises: a variable node module and a check node module, wherein the variable node module and the check node module are connected according to a pre-constructed check matrix to form a variable-check connection network; wherein, The variable node module is configured to: receive hard read data, and generate the codeword to be decoded according to the hard read data; send the codeword to be decoded to the check node module; send the codeword to be decoded and the hard read data to the flip indication module; The check node module is configured to: receive the codeword to be decoded; determine a checksum vector according to the codeword to be decoded and the check matrix; and send the checksum vector to the flip indication module; The flip indication module is also configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; and determine the initial error bit indication vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix.

4. The decoder according to claim 2, wherein: The flip indication module is further configured as follows: Determining a soft data vector corresponding to the soft data; Performing an AND operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector; Determining, according to the target error bit vector, the number of each bit in the to-be-decoded codeword that does not satisfy the parity check; Each element in the target error bit vector corresponds to the number of bits that do not satisfy the parity check.

5. The decoder according to claim 3, wherein: The flip indication module is further configured as follows: Performing a sum operation on the hard read data and the codeword to be decoded and then performing a modulus operation to obtain a first bit vector; Multiplying the transpose of the checksum vector by the check matrix to obtain a second bit vector; Perform an AND operation on the first bit vector and the second bit vector to obtain the initial error bit indication vector.

6. The decoder according to claim 3, wherein: The flip indication module is further configured as follows: Generate a flip indication vector according to the number of bits that do not meet the verification check and the flip criterion; the flip indication vector includes the bits that need to be flipped in the codeword to be decoded; The variable node module is further configured to: receive the flip indication vector, and flip the bits to be flipped in the codeword to be decoded according to the flip indication vector.

7. The decoder according to claim 6, wherein: The flipping criteria include: Flipping the largest number of bits that do not satisfy the parity check in the codeword to be decoded; Or, the bits in the codeword to be decoded, the number of which not satisfying the verification check is greater than or equal to a preset threshold, are flipped.

8. The decoder according to claim 3, wherein: The decoder further includes: a counting module and a termination decision module, wherein: The counting module is configured to: count the number of iterations of performing hard decision on the codeword to be decoded; The termination decision module is configured to: determine whether the number of iterations reaches the maximum number of iterations and determine whether the checksum vector is a zero vector; when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, output a first stop decoding signal; the first stop decoding signal is configured to indicate that hard decision decoding of the codeword to be decoded has failed.

9. The decoder according to claim 8, wherein: The decoder further comprises: a rearrangement module; The termination decision module is further configured to: output a second stop decoding signal when determining that the checksum vector is a zero vector; The rearrangement module is configured to: in response to the second stop decoding signal, rearrange the codewords to be decoded; and output the codewords to be decoded in a correct order.

10. The decoder according to claim 9, wherein: The termination decision module is also configured to: output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the variable node module, the check node module and the flip indication module to continue to perform hard decision decoding operations on the codeword to be decoded.

11. A decoding method, comprising: Acquire soft data corresponding to the codeword to be decoded; When performing hard decision decoding on the codeword to be decoded, the soft data is used to assist in determining the number of bits in the codeword to be decoded that fail to satisfy a parity check in at least a first flipping iteration.

12. The decoding method according to claim 11, wherein: The using the soft data to assist in determining the number of bits in the to-be-decoded codeword that do not satisfy the check, comprises: Determining an initial error bit indicator vector corresponding to the codeword to be decoded; The soft data is used to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not satisfy the parity check.

13. The decoding method according to claim 12, wherein: The using the soft data to assist the initial error bit vector in determining the number of bits in the to-be-decoded codeword that do not satisfy the check, comprises: Determining a soft data vector corresponding to the soft data; Performing an AND operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector; Determining, according to the target error bit vector, the number of each bit in the to-be-decoded codeword that does not satisfy the parity check; Each element in the target error bit vector corresponds to the number of bits that do not satisfy the parity check.

14. The decoding method according to claim 12, wherein: The determining of the initial error bit indication vector corresponding to the codeword to be decoded includes: receiving hard read data, and generating the to-be-decoded codeword according to the hard read data; Determining a checksum vector according to the codeword to be decoded and a pre-constructed check matrix; An initial error bit indicator vector corresponding to the codeword to be decoded is determined according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix.

15. The decoding method according to claim 14, wherein: The step of determining the initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix comprises: Performing a sum operation on the hard read data and the codeword to be decoded and then performing a modulus operation to obtain a first bit vector; Multiplying the transpose of the checksum vector by the check matrix to obtain a second bit vector; Perform an AND operation on the first bit vector and the second bit vector to obtain the initial error bit indication vector.

16. The decoding method according to claim 11, wherein: The method further comprises: Generate a flip indication vector according to the number of bits that do not meet the verification check and the flip criterion; the flip indication vector includes the bits that need to be flipped in the codeword to be decoded; The bits to be flipped in the codeword to be decoded are flipped according to the flip indication vector.

17. The decoding method according to claim 16, wherein: The flipping criteria include: Flipping the largest number of bits that do not satisfy the parity check in the codeword to be decoded; Or, the bits in the codeword to be decoded, the number of which not satisfying the verification check is greater than or equal to a preset threshold, are flipped.

18. The decoding method according to claim 13, wherein: The method further comprises: Counting the number of iterations of performing hard decision on the codeword to be decoded; Determining whether the number of iterations reaches a maximum number of iterations and determining whether the checksum vector is a zero vector; When the number of iterations reaches a maximum number of iterations and the checksum vector is a non-zero vector, a first stop decoding signal is output; the first stop decoding signal is configured to indicate that hard decision decoding of the codeword to be decoded fails.

19. The decoding method according to claim 18, wherein: The method further comprises: Determining whether the checksum vector is a zero vector; if the checksum vector is determined to be a zero vector, outputting a second stop decoding signal; In response to the second stop decoding signal, the code words to be decoded are rearranged, and the code words to be decoded in a correct order are output.

20. The decoding method according to claim 19, wherein: The method further comprises: When the checksum vector is not a zero vector and the number of iterations does not reach the maximum number of iterations, a continue decoding signal is output; the continue decoding signal is configured to indicate to perform a hard decision decoding operation on the codeword to be decoded.

21. A memory controller comprising: A processor and a decoder according to any one of claims 1 to 10, wherein the processor is configured to: read soft data corresponding to the codeword to be decoded from the memory device; The decoder is configured to: cache the soft data; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not satisfy the parity check in at least the first flipping iteration.

22. A memory system comprising: A memory device configured to: store data; A memory controller, coupled to the memory device, comprises: a processor and a decoder; wherein the processor is configured to: read soft data corresponding to a codeword to be decoded from the memory device; The decoder is configured to: cache the soft data; and when performing hard decision decoding on the codeword to be decoded, use the soft data to assist in determining the number of bits in the codeword to be decoded that do not satisfy the parity check in at least the first flipping iteration.

23. The memory system according to claim 22, wherein: The processor is further configured to: read hard read data from the memory device; send the hard read data to the decoder; The decoder is further configured to: receive the hard read data; and generate the codeword to be decoded according to the hard read data.

24. The memory system of claim 23, wherein: The decoder comprises: a cache module, a variable node module, a check node module and a flip indication module, wherein; The cache module is configured to: cache the soft data read by the processor; The variable node module is configured to: receive the hard read data read by the processor; generate the codeword to be decoded according to the hard read data; and send the codeword to be decoded to the check node module; The check node module is configured to: receive the codeword to be decoded sent by the variable node module; determine a checksum vector according to the codeword to be decoded and a pre-constructed check matrix; and send the checksum vector to the flip indication module; The flip indication module is configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; determine the initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix; and use the soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check check.

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