Chip layout and training method, electronic device, storage medium, and chip system

Abstract

The present application relates to the technical field of chip design, and provides a chip layout and training method, an electronic device, a storage medium, and a chip system. According to the method, generalization of the layout method across different chip netlists can be improved. The method comprises: determining first relative position information, wherein the first relative position information is relative position information between different units among units laid-out in a sample chip; determining a first input of a graph neural network to be trained, wherein the first input is obtained on the basis of a first netlist corresponding to the sample chip; obtaining a first output by means of the graph neural network; performing encoding on the basis of the first output to obtain second relative position information; calculating a loss function value on the basis of the first relative position information and the second relative position information; and optimizing a trainable parameter in the graph neural network on the basis of the loss function value.

Description

Chip layout and training method, electronic device, storage medium and chip system

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on August 4, 2023, with application number 202310979735.2 and application name “Chip layout and training method, electronic device, storage medium and chip system”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip design technology, and in particular to a chip layout and training method, electronic equipment, storage medium and chip system. Background Art

[0003] Chip design and manufacturing can be broadly divided into three phases: front-end design (logic code design), back-end design (wiring process), and wafer production (chip manufacturing, testing, and packaging). Chip layout is a crucial step in the VLSI design process and can significantly impact the chip design iteration cycle. The chip layout problem can be described as solving the cell placement problem given the cell size and connectivity, constraints, and optimization objectives.

[0004] Nonlinear programming is one of the technical means used to solve chip layout problems. In one nonlinear programming scheme, the chip layout problem is formulated as a wire length optimization problem under layout density constraints and is solved. However, this scheme requires independent training on each chip, and its generalization needs to be improved.

[0005] Summary of the Invention

[0006] The present application provides a chip layout and training method, electronic device, storage medium and chip system, which can improve the generalization of the chip layout method between different chip netlists.

[0007] In a first aspect, an embodiment of the present application provides a chip layout training method, the method comprising: determining first relative position information; the first relative position information is the relative position information between different units in each laid out unit in a sample chip; determining a first input of a graph neural network to be trained; the first input is obtained based on a first netlist corresponding to the sample chip; obtaining a first output through the graph neural network; based on the first output, performing encoding to obtain second relative position information; calculating a loss function value based on the first relative position information and the second relative position information; and optimizing the trainable parameters in the graph neural network based on the loss function value.

[0008] By encoding the relative positional relationships between units and using them as the output and training target of the graph neural network model, the graph neural network model can migrate information from existing chip layouts to the chip to be laid out, improving the generalization of the layout method, increasing the efficiency of cross-chip reasoning, and solving the problem of difficulty in migrating large-scale netlist circuit layout knowledge. In addition, this solution is a self-supervised learning solution that automatically extracts labels (first relative position information) from the training data during the training process. There is no need to annotate the training data, and the existing netlist training dataset can be used as training data. There is no need to collect large amounts of sample data, which reduces the workload of data preparation.

[0009] In one feasible implementation, determining the first relative position information includes: obtaining absolute position information of each cell already laid out in the sample chip; and calculating relative position information between different cells based on the absolute position information. The absolute position information may be position information (e.g., coordinate information) of each cell included in the netlist. This is known and easily accessible data, so calculating the relative position information based on the absolute position information can directly utilize existing position data without the need for additional data annotation.

[0010] In one possible implementation, the absolute position information includes coordinate information; calculating relative position information between different units based on the absolute position information includes calculating the polar coordinate information of the jth unit relative to the ith unit based on the coordinate information corresponding to the jth unit and the ith unit, respectively; i and j are both integers greater than or equal to 1, and i ≠ j. Polar coordinates can accurately express relative positional relationships and facilitate precise positioning of unit positions.

[0011] In one feasible implementation, encoding is performed based on the first output to obtain the second relative position information, including: determining an independent variable based on the first output, executing an encoding function on the independent variable to obtain the second relative position information; the encoding function is used to map the independent variable to the second relative position information; and after calculating a loss function value, the method further includes: optimizing trainable parameters in the encoding function based on the loss function value. By performing relative position encoding using the encoding function, specific expressions of various encoding functions can be set, and trainable parameters can be set, so that the mapping process can also be optimized during training, thereby obtaining more accurate relative position information.

[0012] In a second aspect, an embodiment of the present application also provides a chip layout method, which includes: determining a second input of the graph neural network after training; obtaining the second input based on a second netlist corresponding to the chip to be laid out; obtaining a second output through the graph neural network; performing encoding based on the second output to obtain third relative position information; performing decoding based on at least the third relative position information to obtain absolute position information of each unit in the chip to be laid out.

[0013] Relative position encoding is used to encode the output features of the graph neural network to obtain the predicted relative position information, and then decoding is performed on this basis to obtain the absolute position information of each unit. Relative position encoding and decoding enable the graph neural network model to migrate the information of the chip that has been laid out to the chip to be laid out, thereby improving the generalization of the layout method and the efficiency of cross-chip reasoning layout.

[0014] In one feasible implementation, determining the second input of the trained graph neural network includes: obtaining at least multiple subgraphs based on a second netlist; nodes in the multiple subgraphs represent units or nets; obtaining input features based on the second netlist; the input features include unit features corresponding to each unit in the chip to be laid out; and determining at least the graph structure information and input features corresponding to the multiple subgraphs as the second input. Dividing the subgraphs into multiple subgraphs can alleviate the data processing pressure of the graph neural network and reduce the data processing difficulty caused by the size of the netlist.

[0015] In one feasible implementation, at least multiple subgraphs are obtained based on the second netlist, including: establishing a hypergraph based on the second netlist, wherein nodes in the hypergraph represent units and hyperedges represent wires; dividing the hypergraph into N blocks, obtaining N first subgraphs corresponding to the N blocks and a first global graph; wherein the first subgraph represents the connection relationship between different units within a block via wires; and the first global graph represents the connection relationship between different blocks within the N blocks via wires; N ≥ 2; respectively expanding the N first subgraphs and the first global graph to obtain corresponding N second subgraphs and a second global graph; wherein nodes in the second subgraphs and the second global graph represent units or wires and edges represent pins; and determining at least graph structure information and input features corresponding to the multiple subgraphs as second input, including: determining at least graph structure information and input features corresponding to the multiple second subgraphs and the second global graph as input. First, establishing a hypergraph. In a hypergraph, an edge can connect more nodes, facilitating rapid topological analysis and achieving higher graph construction efficiency compared to a conventional graph.

[0016] In a feasible implementation, after obtaining the corresponding N second subgraphs, the method further includes: establishing N unit flow graphs corresponding to the N second subgraphs based on the signal direction information contained in the second netlist; wherein, in the unit flow graph, nodes represent units, and the connecting edges between nodes are directed edges used to represent network cables, and the direction of the directed edges is determined according to the signal direction; at least the graph structure information and input features corresponding to multiple subgraphs are determined as the second input, including: at least the graph structure information and input features corresponding to multiple second subgraphs and one second global graph and multiple N unit flow graphs are determined as input. The unit flow graph contains the connection relationship information and signal flow direction information between units. The construction of the unit flow graph can provide important reference information for the encoding and decoding process.

[0017] In a feasible implementation method, N unit flow graphs corresponding to N second subgraphs are established based on the signal direction information contained in the netlist, including: in a second subgraph, a unit is regarded as a starting node; a unit connected to the starting node through a network line is searched as a first-order neighboring node corresponding to the starting node; according to the signal direction, a directed edge is generated between the starting node and each first-order neighboring node; a unit connected to the first-order neighboring node through a network line is searched as a second-order neighboring node corresponding to the starting node; according to the signal direction, a directed edge is generated between the first-order neighboring node and the second-order neighboring node; and the search for the next-order neighboring node is continued until all units in the same second subgraph are visited, thereby obtaining a unit flow graph.

[0018] In a feasible implementation, the input features also include the network features corresponding to each network line in the chip to be laid out; the second output includes the output features corresponding to each unit, or the second output also includes the output features corresponding to each network line; the graph neural network is a graph convolutional neural network, and the graph convolutional neural network includes a convolution layer; through the graph neural network, the second output is obtained, including: in the convolution layer, by executing at least one of the first convolution function, the second convolution function and the third convolution function, the feature transfer between nodes is performed; wherein the first convolution function is used to transfer the network features corresponding to each network line connected to the i-th unit to the i-th unit pair The corresponding node obtains the i-th first unit sub-feature; i ≥ 1 and is an integer; the second convolution function is used to transfer the unit features of each unit connected to the t-th network line to the node corresponding to the t-th network line, obtaining the network line feature corresponding to the t-th network line; t ≥ 1 and is an integer; the third convolution function is used to transfer the unit features of each unit connected to the i-th unit to the node corresponding to the i-th unit, obtaining the i-th second unit sub-feature; based on the i-th first unit sub-feature and the i-th second unit sub-feature, obtain the output feature corresponding to the i-th unit; or, based on the network line feature corresponding to the t-th network line, obtain the output feature corresponding to the t-th network line. Through the above operations of the convolution layer, the graph convolutional neural network can fuse node features with graph structure information. The features of each node are related to the features of the nodes to which it is connected, and the output features containing graph structure information are obtained, which helps to predict more accurate relative position information.

[0019] In a feasible implementation, encoding is performed based on the second output to obtain third relative position information, including: determining an independent variable based on the second output, executing an encoding function on the independent variable, and obtaining the third relative position information; wherein the encoding function is used to map the independent variable to the third relative position information.

[0020] In a feasible implementation, the encoding function includes a first encoding function and a second encoding function; the third relative position information is polar coordinate information; executing the encoding function to obtain the third relative position information includes: determining the first independent variable based on the second output, executing the first encoding function on the first independent variable, and obtaining the polar diameter; determining the second independent variable based on the second output, executing the second encoding function on the second independent variable, and obtaining the deflection angle; the deflection angle represents the relative value of the polar angle corresponding to different units.

[0021] In a feasible implementation, the output includes unit features corresponding to each unit and network features corresponding to each network line; based on the second output, the first independent variable is determined, including: based on the unit features corresponding to the i-th unit and the j-th unit in the second output, and the network features corresponding to the t-th directed edge, the first independent variable is obtained; wherein the t-th directed edge is a directed edge connecting the i-th unit and the j-th unit in the unit flow graph; based on the second output, the second independent variable is determined, including: searching for at least one path corresponding to the j-th unit in the unit flow graph, and selecting one as the first path; the path is a directed path starting from the starting node in the unit flow graph and ending at the node corresponding to the j-th unit, and formed by at least one directed edge; based on the unit features corresponding to each node passed by the first path in the second output and the network features corresponding to at least one directed edge, the second independent variable is obtained; wherein i, j and t are all integers greater than or equal to 1.

[0022] In a feasible implementation, decoding is performed at least based on the third relative position information to obtain the absolute position information of each unit in the chip to be laid out, including: determining a starting node in a subgraph and the absolute position information of the starting node; determining the absolute position information of the first-order neighboring node based on the third relative position information of the first-order neighboring node corresponding to the starting node and the absolute position information of the starting node; determining the absolute position information of the m+1 order neighboring node based on the absolute position information of the m-order neighboring node and the third relative position information of the m+1 order neighboring node; m≥1 and is an integer.

[0023] In a feasible implementation, decoding is performed based on at least the third relative position information to obtain absolute position information of each unit in the chip to be laid out, including: for the j-th unit, searching in the unit flow graph for at least one path with the j-th unit as the end node; based on the third relative position information corresponding to the starting node of one of the at least one paths and the third relative position information of each node passed by the path, obtaining a feasible solution corresponding to the path, and at least one path corresponding to at least one feasible solution; based on the at least one feasible solution, obtaining the absolute position information of the j-th unit.

[0024] In a feasible implementation, after obtaining the absolute position information of each unit in the chip to be laid out, the method further includes: using the absolute position information of each unit as an initial solution to calculate an objective function; the objective function uses at least one of line length, density, and anchor point as a constraint condition; the objective function includes at least one hyperparameter of a learning rate, a number of iterations, and a loss function weight; and gradient updating the absolute position information of each unit.

[0025] After obtaining the absolute position information of each unit through encoding and decoding, the absolute position information can be used as the initial solution for further adaptive fine-tuning. On the one hand, it can avoid the problem of cold start and significantly shorten the time required to optimize the unit position. On the other hand, fine-tuning can further meet constraints such as no overlap between components and the placement of components cannot exceed the set layout boundaries, thereby optimizing the layout.

[0026] In a third aspect, the technical solution of the present application also provides an electronic device for sending data through a data transmission interface, the electronic device comprising: one or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, enable the electronic device to execute a method as described in any one of the first or second aspects above.

[0027] In a fourth aspect, the technical solution of the present application also provides a storage medium comprising computer instructions, which, when executed on an electronic device, enables the electronic device to execute a method as described in any one of the first and second aspects above.

[0028] In the fifth aspect, the technical solution of the present application also provides a chip system, including: a communication interface for inputting and / or outputting data; a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any one of the first or second aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is an example diagram of the system architecture of the method provided in an embodiment of the present application during the training phase;

[0030] FIG2 is a flow chart of the method provided in the training phase of the embodiment of the present application;

[0031] FIG3 is an example diagram of the system architecture of the method provided in an embodiment of the present application in the application stage;

[0032] FIG4 is a schematic diagram of a method flow chart of the method provided in an embodiment of the present application in the application stage;

[0033] FIG5 is a schematic diagram of dividing sub-graphs during the composition process;

[0034] Figure 6 is a diagram of data processing in a convolutional layer of a graph convolutional neural network;

[0035] FIG7 is an example diagram of a processing flow architecture based on a graph structure during the training phase;

[0036] FIG8 is an example diagram of encoding relative positions based on absolute position information;

[0037] FIG9 is a schematic diagram of the main flow chart of the method provided in an embodiment of the present application;

[0038] FIG10 is a schematic diagram of chip layout based on a hierarchical netlist;

[0039] FIG11 is a schematic diagram of establishing a unit flow graph and obtaining unit flow graph edges and unit paths;

[0040] FIG12 is a diagram illustrating an example of a system architecture that uses a unit flow graph as one of its inputs to predict relative positions and perform training;

[0041] FIG13 is a diagram showing an example of the system architecture of a graph convolutional neural network;

[0042] Figure 14 is an example diagram of the data processing architecture of a graph neural network;

[0043] FIG15 is a schematic diagram of encoding based on unit flow graph edges and unit paths;

[0044] FIG16 is a schematic diagram of decoding based on a unit flow graph;

[0045] FIG17 is a schematic diagram of further fine-tuning and optimizing the chip layout after the inductive layout;

[0046] FIG18( a ) to FIG18 ( c ) respectively show the congestion distribution diagrams of the model, D***Place, and **Place proposed in the embodiment of the present application on the mgc_fft_2 netlist;

[0047] Figure 18(d) is an example graph of congestion levels;

[0048] FIG19( a ) to FIG19 ( c ) respectively show the congestion distribution diagrams of the model, D***Place, and **Place proposed in the embodiment of the present application on the mgc_matrix_mult_2 netlist;

[0049] Figures 20(a)-20(c) show the congestion distribution of each method on the mgc_superblue19 netlist;

[0050] FIG21 is a schematic diagram of the hardware structure of an electronic device. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0053] Chip design is divided into front-end design and back-end design. Front-end design generally includes specification formulation, RTL (Register Transfer Level) design, simulation verification, logic synthesis (Logic Synthesis), static timing analysis (STA), formal verification and other stages. Front-end design is the process of determining design requirements to outputting a netlist (generally a gate-level netlist circuit); back-end design includes design for test (DFT), physical implementation, clock tree synthesis (CTS), routing (Place & Route), parasitic parameter extraction, layout physical verification and other stages. The physical layout is handed over to the chip foundry in the GDS II file format, and the actual circuit is made on the silicon wafer, and then packaged and tested to obtain the chip.

[0054] The physical implementation phase of back-end design converts the logical design into actual chip layout and connectivity. Its primary task is floor planning, which determines the overall placement of various functional circuits, such as IP modules, RAM, and I / O pins. Floor planning directly impacts the final chip area. Considering IP modules, RAM, I / O pins, and other functional circuits as cells, the chip layout problem can be described as solving for cell locations given the size and connectivity of standard cells and macro cells, constraints (e.g., no component overlap), and optimization goals (e.g., minimizing total bus length).

[0055] The chip layout method provided in the embodiment of the present application can be applied to the physical implementation stage or layout planning stage in chip design application scenarios.

[0056] To facilitate understanding of the solutions proposed in the embodiments of this application, a brief description of the relevant technologies is first given:

[0057] For chip layout, modern VLSI design requires the ability to quickly generate high-quality layout plans on different chips to accelerate the design iteration cycle. Current technical research focuses on developing more efficient global layout algorithms. Some solutions cannot simultaneously take into account operational efficiency and generalization.

[0058] In related technologies, chip layout methods generally include iterative optimization, integer programming, nonlinear programming, and reinforcement learning. Iterative optimization methods, such as simulated annealing, genetic algorithms, and Monte Carlo simulation, rely on iteration to approximate the optimal solution. Integer programming restricts all or some of the variables in the planning process to integers, searching for the best solution that satisfies certain constraints among a finite number of available options. Nonlinear programming solves an optimization problem defined by a set of equations and inequalities (collectively referred to as constraints) consisting of a series of unknown real functions, accompanied by an objective function to be maximized or minimized. Some constraints or objective functions are nonlinear. Reinforcement learning methods, for example, treat the chip layout problem as a finite Markov decision process and use a reward function to guide layout. The following are several examples of related technologies to illustrate potential challenges.

[0059] Related technology 1: A nonlinear programming method that uses a GPU (graphics processing unit) acceleration algorithm enabled by the PyTorch framework to digitally calculate wire length and density gradients for modern VLSI (Very Large Scale Integration Circuit) layout. It uses a weighted objective function based on metrics such as wire length to optimize cell placement. This method can improve layout efficiency and save time to a certain extent, but it still faces the following challenges when faced with diverse chip netlists:

[0060] Independent training is required on each chip, that is, each chip requires targeted training, and there is no more universal layout method to adapt to more chips to be laid out. The generalization needs to be improved, which brings a bottleneck to the chip optimization layout time.

[0061] Secondly, layout has a significant impact on subsequent indicators such as congestion and timing, but this method makes it difficult to effectively optimize timing and congestion indicators during the layout phase.

[0062] Related Technology 2: For the first time, reinforcement learning is applied to the chip layout stage. This approach uses reinforcement learning to generalize the model across different chip netlists. This approach, based on a reinforcement learning architecture, treats the netlist, its associated features, and the locations of placed cells as states. The reward function is defined as the weighted sum of total line length and congestion, with total line length being weighted HPWL (Half-Perimeter Wire Length). Each action is defined as the probability distribution of the current macrocell in the current layout.

[0063] During training, each training session assumes that all macrocells are placed sequentially in the current layout. The order of macrocell placement is to arrange them from largest to smallest in area. When the areas of the macrocells are the same, the topological order of the macrocells in the netlist is introduced, with the topological order of the macrocells at the top. The reward generated for each placement in this sequential order is 0. After the last macrocell is placed, all standard cell clusters are placed in the center of the layout. A classic force-directed method is run to determine the positions of each standard cell cluster, and each cell is placed at the center of the corresponding cluster. This results in a layout plan, calculates HPWL and congestion, and obtains a reward. On the chip layout, the macrocell position is a continuous value. The probability distribution of each macrocell placement is the probability of placement at the center of each grid cell. Its possible placement positions are the centers of the corresponding cells, ultimately discretizing the probability distribution of the macrocells.

[0064] Among them, for the generation of the probability density of each macro unit, during the training process, after obtaining the initial macro unit probability distribution, the probability of illegal placement positions is first set to zero according to the density constraint, and the probability of legal positions is renormalized. The placement position of the macro unit in the current training round is obtained according to probability sampling, and the center of the cell with the maximum probability is taken as the placement position during the inference process. However, there is a density constraint in the placement process, that is, the density on each cell must be strictly less than the given maximum density. Therefore, if a macro unit block does not have a legal placement position during the placement process, the training data is abandoned and retrained from the beginning. The training process adopts the Proximal Policy Optimization (PPO) strategy for training.

[0065] The disadvantage of this reinforcement learning-based solution is that during the layout generation inference process, the number of network inferences is equivalent to the number of macro cells, and its time complexity is linearly related to the macro cells and standard cells in the netlist, which consumes a long time and has low layout efficiency.

[0066] Especially for large-scale netlists, the search space is huge, which makes the training time to converge longer. Current integrated circuit netlists are often large-scale netlists exceeding one million, which makes this method difficult to apply.

[0067] Related technology three: Obtain the logic diagram executed by the chip to be laid out and the device list corresponding to the chip to be laid out; use a pre-trained layout model to determine the layout diagram of the chip to be laid out based on the logic diagram and the device list. By using a pre-trained layout model to perform chip layout, the layout diagram of the chip to be laid out can be quickly obtained through the logic diagram and the device list. Compared with manual chip layout, the required time can be shortened and the efficiency of chip layout can be improved. Among them, when the layout model is trained, it is necessary to obtain K logic diagram samples and the device list samples corresponding to each logic diagram sample; for each of the logic diagram samples, the operation type of each type of operation sample in the logic diagram sample, the sub-device list sample corresponding to each type of operation sample, and the input or output of each operation sample are obtained.

[0068] In this solution, multiple layout samples are used to train the model. The initial chip layout data preparation is difficult, and the chip layout differences are too large. The model may be underfitting and have poor generalization ability.

[0069] Related Technology 4: Analyze the layout and configuration of functional units using deep learning methods to obtain the optimal chip layout and routing that meets the set constraints. First, determine the functional unit type that implements the chip to be designed; set attribute information corresponding to each functional unit type based on its characteristics; select target functional units corresponding to each functional unit type from the candidate functional units of each functional unit type and add them to the layout of the chip to be designed. Then, based on the set deep learning algorithm, all target functional units are laid out and routed according to the set constraints until the evaluation representation value of the layout and routing according to the constraints is maximized.

[0070] This method reduces the manual effort involved in chip design, particularly during chip layout and routing, improving chip design efficiency. However, this method is very slow, as each iteration requires evaluating and characterizing the routing results of the currently designed chip, including performance, energy consumption, layout density, and area settings. This results in low data utilization, long interactive iteration cycles, and weak model transferability.

[0071] In summary, Related Technology 1 requires calculating the layout individually for each chip, lacks generalizability, and may not achieve good results across different chips. Related Technology 2, on the other hand, uses reinforcement learning to learn layout knowledge and improve generalizability across different chips, but its efficiency is relatively low. Specifically, layout methods with relatively good time efficiency cannot achieve generalization, while reinforcement learning methods, which do have generalizability, are inefficient for large-scale chip netlists because their inference time is linearly correlated with the number of cells to be placed.

[0072] On the one hand, the preparation of training data for related technology three is difficult, and on the other hand, it also has the problem of poor generalization ability; on the other hand, related technology four also has problems such as low efficiency and weak transferability (i.e., poor generalization ability).

[0073] In view of this, an embodiment of the present application proposes a chip layout method, which encodes the relative position relationship between the units and uses it as the training target and prediction target of the graph neural network model, so that the graph neural network model can migrate the information of the chip that has been laid out to the chip to be laid out, which can at least solve the problem of model generalization in chip layout. That is, after the model is trained on a part of the chip netlist, it can directly generate a layout on other unlaid netlists without the need for additional training.

[0074] In the embodiments of the present application, cells include fixed cells and movable cells. Fixed cells are components that are fixed in position and cannot be moved, such as terminals or ports. Fixed cells generally occupy a larger area or volume than movable cells.

[0075] Removable cells typically include standard cells and macrocell modules. Macrocells primarily include memory cells and various custom IPs and are the primary functional modules of integrated circuits. For example, memory cells can be RAM or ROM. Standard cells are a collection of underlying electronic logic functions, such as AND / NOR gates, flip-flops, latches, and so on.

[0076] Fixed units such as ports are generally immovable, so the objects of chip layout are mostly movable units. When laying out movable units, the position information of fixed units can be referenced.

[0077] To avoid confusion, the solution provided in the embodiment of the present application is described below in two stages: a training stage and an application stage.

[0078] During the training phase, an embodiment of the present application provides a chip layout training method. FIG1 shows an example of a system architecture for executing the chip layout training method.

[0079] The embodiments of the present application employ self-supervised learning, using at least a graph neural network as the training target. First, sample chips that can serve as training examples are screened, and the netlists corresponding to the sample chips are used as training data. The sample chips are chips with a complete layout and all performance indicators meet expectations. For example, the training samples can be the four netlists mgc_fft_1, mgc_fft_2, mgc_fft_a, and mgc_fft_b from the ISPD2015 dataset.

[0080] A netlist file (hereafter referred to as a netlist) describes the logical structure of a circuit design. Generally, a netlist consists of cells, pins, terminals / ports, and networks. A network consists of multiple nets.

[0081] A netlist typically consists of an LEF (Library Exchange Format) file containing physical library information and a DEF (Design Exchange Format) file containing circuit physical information. The DEF file provides information such as cell location, pin location, signal direction, cell size, pin-to-net connections, and pin-to-cell connections.

[0082] After determining the training data, the input of the graph neural network is obtained based on the training data. Input features (initial features) and graph structure information are extracted from the netlist (first netlist) corresponding to the sample chip and input into the graph neural network. The input features include at least unit features and network features. For example, in some embodiments, the input features can be unit features and network features; in other embodiments, the input features can also include pin features.

[0083] Graph structure information, along with unit features, network features, and, optionally, pin features, are input into a graph neural network. The graph neural network then performs message passing, fusion, and updates of node features to obtain output features. The output features include at least unit features. For example, in some embodiments, the output features are only unit features, while in other embodiments, the output features include both unit features and network features.

[0084] Among them, graph neural networks can adopt one of the following: Graph Convolution Networks (GCN), Graph Attention Networks, Graph Autoencoders, Graph Generative Networks and Graph Spatial-temporal Networks, or a combination of two or more of them.

[0085] After obtaining the output, relative position encoding is performed based on the output features to obtain relative position information, which is the predicted value obtained based on the graph neural network.

[0086] The training method of the embodiment of the present application is implemented based on the idea of ​​self-supervised learning, and can complete training on unlabeled data, and requires mining its own supervisory information from the training data.

[0087] The netlist generally records the specific location information of each unit, so the location information of each unit can be obtained from the netlist. In the embodiments of the present application, the location information recorded in the netlist is defined as absolute location information. Generally speaking, absolute location information is the location information of each unit on the chip relative to a unified coordinate origin.

[0088] To address the difficulty of migration in other training methods, the embodiments of the present application propose relative position information and relative position encoding. During training, the output features of the graph neural network are mapped to relative position information through relative position encoding, the value of the loss function is calculated based on the relative position information, and the trainable parameters are updated by gradients. The relative position encoding is a variant encoding method such as SE(2) (Special Euclidean Group 2), which is insensitive to translation and rotation in two-dimensional space, to ensure that the layout learned by the graph neural network model can be generalized between different chip netlists. Self-supervised training is used to enable the graph neural network to learn layout knowledge from the already laid out chip netlist.

[0089] Different from the application phase, in the training phase, the relative position information of each unit in the sample chip can be obtained based on its absolute position information.

[0090] For example, based on the absolute position information of the i-th unit and the j-th unit, the relative position information of the j-th unit relative to the i-th unit can be calculated. In this way, based on the absolute position information of each unit, the relative position information between different units in the sample chip, that is, the relative position information between different units on the chip that has been laid out, can be obtained.

[0091] To prevent confusion, the relative position information obtained by encoding the features output by the graph neural network is defined as the second relative position information, and the relative position information calculated based on the absolute position information of the sample chip is defined as the first relative position information. The first relative position information can be understood as self-supervisory information extracted from the training samples, that is, labels, without the need for additional annotation.

[0092] Then, based on the first relative position information and the second relative position information, the value of the loss function is calculated, and based on the loss function value (Ltrain), the trainable parameters in the graph neural network are optimized. This iteration is repeated until the graph neural network converges and the training is completed.

[0093] It should be noted that, in some embodiments, encoding the output features may involve mapping the features into relative position information via an encoding function, wherein the encoding function may include trainable parameters. Therefore, in addition to the trainable parameters in the graph neural network, the training objectives may also include the trainable parameters in the encoding function. Of course, in other embodiments, the encoding function may not include trainable parameters but may only contain hyperparameters, i.e., non-independent parameters are all constants or pre-set and do not require gradient updates.

[0094] Specifically, the chip layout training method provided in the embodiments of the present application may include the following process:

[0095] S201: Determine first relative position information.

[0096] The first relative position information is the relative position information between different units in the sample chip. The first relative position information can be calculated based on the absolute position information of each unit in the sample chip. The absolute position information can be obtained from the netlist.

[0097] For example, the relative position information of the jth unit relative to the ith unit can be calculated based on the absolute position information (e.g., coordinate information) corresponding to the jth unit and the ith unit, respectively. Wherein, i and j are both integers greater than or equal to 1, and i≠j. In some embodiments, the relative position information is expressed in the form of polar coordinates, such as the polar coordinate information of the jth unit relative to the ith unit, including the polar diameter and the deflection angle. In other embodiments, other coordinates can also be used to record the relative position information between units, for example, using a plane rectangular coordinate system or a space rectangular coordinate system, a cylindrical coordinate system, a spherical coordinate system, etc.

[0098] Different from the polar diameter and polar angle in the ordinary polar coordinate system, in the relative position information proposed in the embodiment of the present application, the polar diameter is the modulus of the directed vector between the jth unit and the ith unit, rather than the polar diameter of the jth unit relative to the coordinate origin; the deflection angle is the polar angle corresponding to the vector from the ith unit to the jth unit, which is the deflection angle of the polar angle corresponding to the vector from the kth unit to the ith unit.

[0099] S202: Determine the first input of the graph neural network to be trained.

[0100] The input data obtained according to the first netlist is defined as the first input. In some embodiments, the input includes input features and graph structure information, where the input features include at least unit features. In some embodiments, the input features may include unit initial features, net initial features, and pin initial features. These initial features can be input into the graph neural network in the form of feature vectors or feature matrices.

[0101] For example, the netlist contains information such as the size and position (initial position) of each unit. By using the values ​​of this information as elements in a vector, the initial feature vector of the unit can be obtained; the netlist contains information such as the position, size, number, and spacing of the pins. By using the values ​​of this information as elements in a vector, the initial feature vector of the pins can be obtained. Similarly, based on the network cable related information contained in the netlist, the initial feature vector of the network cable can be obtained.

[0102] There is no restriction on the execution sequence of S202 - S204 and S201 , and S202 - S204 can be executed before S201 .

[0103] S203, obtain the first output through the graph neural network.

[0104] The first output can specifically be output features. Input features and graph structure information are fed into the graph neural network to be trained. The graph neural network then extracts features to obtain output features. The output features include at least unit features and, in some embodiments, may also include network features.

[0105] It should be noted that the word order limitations such as "first" and "second" are only used to distinguish different description objects to prevent confusion, and do not indicate the limitations of the execution sequence or priority of the description objects. "First" and "second" can be objects of the same type or different types.

[0106] S204: Perform encoding based on the first output to obtain second relative position information.

[0107] In some embodiments, an independent variable can be determined based on the first output, and then an encoding function can be applied to the independent variable to obtain the second relative position information. The process of applying the encoding function is equivalent to a mapping process, where the encoding function maps the independent variable to the second relative position information. The second relative position information is a predicted value obtained based on the graph neural network. The first relative position information is a label.

[0108] S205: Calculate a loss function value based on the first relative position information and the second relative position information; and optimize trainable parameters in the graph neural network based on the loss function value.

[0109] The loss function may be one or more of a cross entropy loss function (Cross Entropy Error Function), a mean squared error loss function (MSE), and a smooth_L1. In other embodiments, the HingeLoss0-1 loss function, a logarithmic loss function, etc. may be used, and this specification does not list them one by one.

[0110] The training phase is used to train the graph neural network, optimize the trainable parameters, and at least obtain a graph neural network with predictive performance that meets expectations. After training is complete, the application phase begins, using the trained graph neural network to layout the chips to be laid out.

[0111] In the application stage, an embodiment of the present application provides a chip layout method. FIG3 shows an example of a system architecture for executing the chip layout method.

[0112] To avoid confusion, the netlist corresponding to the sample chip is defined as the first netlist, and the netlist corresponding to the chip to be laid out in the application phase is defined as the second netlist.

[0113] Input features and graph structure information are extracted from the second netlist and input into the graph neural network. Output features are obtained through the graph neural network, and relative position encoding is performed on the output features to obtain relative position information (third relative position information). Unlike the training phase, after obtaining the third relative position information, the absolute position information of each unit is inferred from the relative position information in combination with the graph structure. This inference process is called decoding, and the layout is completed.

[0114] In the application stage, the chip layout method proposed in the embodiment of the present application, as shown in FIG3 and FIG4 , may include the following process:

[0115] S401, determining the second input of the graph neural network after training.

[0116] The input data obtained according to the second netlist is the second input. The data format of the input and output of the graph neural network in the training phase and the application phase is consistent. In the application phase, the input of the graph neural network also includes input features and graph structure information. The input features include at least the unit features (initial features) corresponding to each unit in the chip to be laid out. In other embodiments, the input features may include unit initial features, network cable initial features, or also include pin initial features.

[0117] Regarding graph structure information, in some embodiments, at least multiple subgraphs can be obtained based on the second netlist; then, graph structure information is extracted from the multiple subgraphs, and the graph structure information and input features corresponding to the multiple subgraphs are input as input data (second input) to the graph neural network. The graph structure information can specifically be an adjacency matrix. In other embodiments, it can also be other data formats that can digitally express graph structure information. For example, the graph structure information corresponding to the multiple subgraphs can be one or more of a connection list, a cross-link list, a connection multi-list, and an edge set array corresponding to the multiple subgraphs.

[0118] A netlist contains the connection relationships and geometric topology between cells, nets, and pins. Based on this netlist, a corresponding netlist graph can be constructed. Inputting a large-scale netlist into a graph neural network requires building a neural network with a large number of neurons and large-scale computing power, which reduces the feasibility of the solution.

[0119] In an embodiment of this application, it is proposed to divide the large-scale netlist corresponding to the chip into multiple blocks, and establish a corresponding subgraph for each block, so as to obtain multiple subgraphs. In this way, each subgraph can be input into the graph neural network and processed separately, thereby reducing the pressure of the graph neural network to process each subgraph at a time.

[0120] Specifically, referring to FIG5 , in some embodiments, the following method can be used to obtain multiple sub-images:

[0121] Based on the netlist file (second netlist) of the chip to be laid out, a hypergraph is created. In the hypergraph, nodes represent units and hyperedges represent network lines. A hyperedge can connect more than three nodes. The hypergraph is divided into N blocks, resulting in N corresponding first subgraphs and one first global graph.

[0122] The first subgraph represents the connections between different units within a block, which are connected by network cables. The first global graph represents the connections between blocks within N blocks, which are connected by network cables. Specifically, the connections within a block are represented by the first subgraph, while the connections between blocks are represented by the global graph. N ≥ 2. The first subgraph and the first global graph are still hypergraphs, where nodes still represent units and hyperedges represent network cables.

[0123] Expand N first subgraphs and one first global graph, respectively, to obtain corresponding N second subgraphs and one second global graph. This expansion process is the process of expanding a hypergraph into a normal graph. In a normal graph, an edge can only connect two nodes at most. Specifically, methods such as clique expansion, star expansion, line expansion (LE), and connected component expansion can be used. In the second subgraph and second global graph obtained after expansion, nodes represent units or network cables, and connecting edges represent pins, as shown in Figure 11, which shows an example of a second subgraph.

[0124] In some embodiments, after obtaining multiple second subgraphs and the second global graph, the graph structure information of the multiple second subgraphs and the second global graph can be extracted and used together with the input features as input to the graph neural network.

[0125] It should be noted that constructing a hypergraph is not a necessary process for obtaining multiple subgraphs. In other embodiments, the netlist graph can also be divided directly, that is, there is no need to establish a hypergraph first, but directly construct a large-scale netlist graph based on the netlist, and then divide it to obtain multiple subgraphs.

[0126] Cluster analysis can be used to partition both hypergraphs and netlists. Units with denser connections are grouped together as much as possible, while units with sparser connections are grouped into different blocks. The density of connectivity can be measured by the number of netlines between units.

[0127] In some embodiments, after obtaining the corresponding N second subgraphs, a corresponding unit flow graph may be established:

[0128] According to the signal direction information included in the second netlist, N unit flow graphs corresponding to the N second subgraphs are established.

[0129] In a unit flow graph, nodes represent units, and the edges connecting nodes are directed edges, representing network cables. The direction of the directed edges is determined by the signal direction, which can be obtained from the netlist. Optionally, in some embodiments, the second global graph can also establish a corresponding global flow graph. In other embodiments, a corresponding global flow graph for the second global graph may not be established.

[0130] Based on the unit flow graph, we can obtain multiple directed edges (unit flow graph edges) and unit paths. A unit path is a path that starts from the starting node and passes through at least one directed edge. For example, the unit path corresponding to the jth unit node is the path starting from the starting node and ending at the jth unit node. Except for the starting node, every node has at least one corresponding path.

[0131] After obtaining multiple unit flow graphs, at least multiple second subgraphs, one second global graph, and graph structure information corresponding to multiple N unit flow graphs are input into the graph neural network together with the input features.

[0132] Exemplarily, the unit flow graph can be established according to the second subgraph in the following manner:

[0133] In a second subgraph, a cell is considered the starting node. This cell can be a macrocell or other cell, but cells with larger areas are generally chosen as the starting node. In blocks containing ports, the ports are generally considered the starting nodes. The number of starting nodes in a block can be one or more.

[0134] After determining the starting node, the next step is to search and establish directed edges between other nodes and the starting node to obtain a unit flow graph. When searching, you can use depth-first search (DFS) or breadth-first search (BFS).

[0135] In other embodiments, a hierarchical search approach may also be used:

[0136] The search is for cells connected to the starting node via a network line, which serve as the starting node's first-order neighboring nodes. Based on the signal direction, directed edges are generated between the starting node and each first-order neighboring node. Next, the search is for cells connected to the first-order neighboring node via a network line, which serve as the starting node's second-order neighboring nodes. Based on the signal direction, directed edges are generated between the first-order and second-order neighboring nodes. The search continues for the next-order neighboring node until all cells in the same second subgraph have been visited, resulting in a cell flow graph.

[0137] In this way, after the above process, multiple second subgraphs, a second global graph and multiple unit flow graphs, as well as the initial features of each unit, the initial features of each network cable and the initial features of each pin (feature vectors) are obtained. These feature vectors and the adjacency matrices corresponding to the multiple graphs are input into the graph neural network together.

[0138] S402, obtain a second output through the graph neural network.

[0139] In some embodiments, the graph neural network is a graph convolutional neural network, which includes at least one convolutional layer.

[0140] Through the graph neural network, in the convolution layer, features are transferred between nodes by executing at least one of the first convolution function, the second convolution function and the third convolution function.

[0141] Referring to Figure 6, the first convolution function is used to transfer the network line features corresponding to each network line connected to the i-th unit to the node corresponding to the i-th unit based on the connection relationship information between the nodes and the network lines in the second subgraph (i.e., the graph structure information), to obtain the i-th first unit sub-feature, where i ≥ 1 and is an integer.

[0142] The second convolution function is used to transfer the unit features of each unit connected to the t-th network line to the node corresponding to the t-th network line based on the connection relationship information between the nodes and the network lines in the second subgraph, so as to obtain the network line features corresponding to the t-th network line, where t≥1 and is an integer.

[0143] The third convolution function is used to transfer the unit features of each unit connected to the i-th unit to the node corresponding to the i-th unit based on the graph structure information corresponding to the unit flow graph, so as to obtain the i-th second unit sub-feature.

[0144] Based on the i-th first unit sub-feature and the i-th second unit sub-feature, an output feature corresponding to the i-th unit is obtained. For example, the first unit sub-feature and the second unit sub-feature are weighted or directly summed to obtain the feature corresponding to the i-th unit. In other embodiments, the first unit sub-feature and the second unit sub-feature may be vector-concatenated, and the resulting vector may be used as the feature vector output by the i-th unit.

[0145] In some embodiments, the output features may only include the feature vector corresponding to the unit. In other embodiments, the network cable features corresponding to the t-th network cable obtained after the above message transmission may also be output as the feature vector corresponding to the t-th network cable.

[0146] It should be noted that, in some embodiments, in the second subgraph, the connecting edges between nodes represent pins. On the premise that the input features include pin features, when performing message passing in the convolution layer, the pin features of the pins connected to the unit node or the network cable node can be aggregated to the i-th unit node or the t-th network cable node through the convolution function, for example, through the first convolution function and / or the second convolution function, so that the output unit features or network cable features contain the pin feature information.

[0147] S403: Perform encoding based on the second output to obtain third relative position information.

[0148] The encoding performed on the output of the graph neural network is relative position encoding. Specifically, in some embodiments, an independent variable can be determined based on the second output (output feature), and an encoding function can be performed on the independent variable to obtain third relative position information. The role of the encoding function is to map the output feature to relative position information (third relative position information), and the output feature can be converted into an independent variable. The specific conversion method can be a cascade operation on the output feature vector, etc.

[0149] Specifically, in some embodiments, the encoding function may include a first encoding function and a second encoding function. The relative position encoding process may include determining a first independent variable based on the second output, executing the first encoding function on the first independent variable to obtain a polar diameter; determining a second independent variable based on the second output, executing the second encoding function on the second independent variable to obtain a deflection angle; the deflection angle represents the relative value of the polar angle corresponding to different units.

[0150] Exemplarily, the output includes unit features corresponding to each unit and network features corresponding to each network line. Based on the second output, the first independent variable can be determined as follows: the first independent variable is obtained based on the unit features corresponding to the i-th unit and the j-th unit in the second output, and the network features corresponding to the t-th directed edge. The t-th directed edge is a directed edge connecting the i-th unit and the j-th unit in the unit flow graph.

[0151] Similarly, based on the second output, the second independent variable can be determined in the following manner:

[0152] Search the cell flow graph for at least one path corresponding to the jth cell and select one of them as the first path. As mentioned above, a path is a directed path in the cell flow graph that starts from the starting node and ends at the node corresponding to the jth cell, formed by at least one directed edge.

[0153] A second independent variable is obtained based on the cell features corresponding to each node and the network features corresponding to at least one directed edge in the second output. For example, the features corresponding to each node and each edge along the path are concatenated into a feature vector, which serves as the second independent variable. Alternatively, a weighted sum of the node features and edge features is taken as the second independent variable. Here, i, j, and t are all integers greater than or equal to 1.

[0154] After determining the independent variable, the corresponding encoding function is executed to obtain the relative position information. The encoding function can include trainable parameters, which can be optimized through training during the training phase.

[0155] S404 , performing decoding based on at least the third relative position information to obtain absolute position information of each unit in the chip to be laid out.

[0156] In some embodiments, layer-by-layer decoding may be performed in the following manner:

[0157] Determine the starting node and the absolute position information of the starting node in a subgraph, determine the absolute position information of the first-order neighboring node based on the third relative position information of the first-order neighboring node corresponding to the starting node and the absolute position information of the starting node; determine the absolute position information of the m+1 order neighboring node based on the absolute position information of the m-order neighboring node and the third relative position information of the m+1 order neighboring node; m ≥ 1 and is an integer.

[0158] For the jth cell, there may be multiple cell paths ending at the jth cell. Therefore, when searching for at least one path ending at the jth cell in the cell flow graph, more than two cell paths may be obtained. The search may be performed using DFS or BFS.

[0159] In this case, based on the position information (absolute position information or relative position information) corresponding to the starting node of each path in at least one path and the relative position information of each other node passed by the path, a feasible solution of the j-th unit relative to the path is obtained, and then multiple unit paths can obtain multiple absolute position information, that is, multiple feasible solutions are obtained, and then based on the multiple feasible solutions, the absolute position information of the j-th unit is obtained. For example, the multiple feasible solutions are averaged. In other embodiments, one of the multiple unit paths with the j-th unit as the end node can be selected for decoding without the need for averaging. Or a weighted sum is performed on the multiple feasible solutions corresponding to the multiple paths, and so on. The specific implementation method is not unique.

[0160] Optionally, after obtaining the absolute position of the unit through decoding, you can also fine-tune it:

[0161] The absolute position information of each unit is used as the initial solution to calculate the objective function. The objective function uses at least one of line length, density, and anchor points as a constraint. The objective function also includes at least one hyperparameter: learning rate, number of iterations, and loss function weight. The absolute position information of each unit is updated using gradients. For example, gradient descent is used to iteratively update the unit position.

[0162] The present invention proposes a transferable, self-supervised learning chip layout framework that encodes the relative positional relationships between cells and uses them as the model's output and training target. This allows the model to transfer existing chip layout information to the chip to be laid out, saving resources required for iteration in chip design. Compared to other methods, the model provided by the present invention can generate competitive layout solutions on different chips, accelerating the iteration speed of chip design.

[0163] To further understand the method provided in the embodiments of the present application, a specific embodiment is listed below. This embodiment is only an illustrative example, and other embodiments can be adaptively derived based on this embodiment:

[0164] Unlike the application phase, in the training phase, the absolute position information of each cell in the sample chip needs to be encoded into relative position information. Taking the jth cell, the ith cell, and the kth cell as an example, the specific encoding method is as follows:

[0165] The jth unit is connected to the ith unit through a network cable, and the ith unit is connected to the kth unit through a network cable. The signal flow direction is from the kth unit to the ith unit, and from the ith unit to the jth unit. Assume that the kth unit is the starting node.

[0166] Then, the relative position information of the jth unit relative to the ith unit can be obtained as follows:

[0167] Among them, v i represents the i-th unit, v j represents the jth unit, p i For the i-th unit v i The absolute position, p j For the jth unit v j The absolute position of Represents the edge set in the constructed unit flow graph, (v i , v j )express A cell flow graph edge in ; vector The polar coordinates ρ i，j ,θ i，j In the form of i，j is a vector The modulus of θ i，j is a vector The polar angle, θ i，j for Angle with the horizontal direction;

[0168] Next, calculate the deflection angle Δθ i，j , as shown in formula (3): Δθ i，j =θ i，j -θ k，i Formula (3)

[0169] Among them, θ k，i is the polar angle corresponding to the vector from the kth unit to the ith unit, where(v k , v i )=f INCOME (v i )

[0170] f INCOME (v i ) represents the vector from the kth unit to the ith unit, that is, the unit flow graph edge from the kth unit to the ith unit.

[0171] (ρ i，j ,Δθ i，j ) is the relative position information of the j-th unit relative to the ith unit.

[0172] For example, referring to FIG8 , node 1 is the starting node, and the polar radius of the vector (unit flow graph edge) from node 1 to node 3 is ρ 1,3 =1.00, polar angle θ 1,3 = 0.0π, the polar radius ρ corresponding to the vector (unit flow graph edge) pointing from node 3 to node 43,4 =1.12, polar angle θ 3,4 =0.35π, then the relative position information of node 2 relative to node 1 is (ρ 1,3 =1.00, Δθ 1,3 =0.0π); the deflection angle Δθ of node 4 relative to node 3 3,4 =θ 1,3 -θ 3,4 =-0.35π, then the relative position information of node 4 relative to node 3 is (ρ 3,4 =1.12, Δθ 3,4 =-0.35π).

[0173] Where edge represents the vector pointing from one node to another (unit flow graph edge), ρ represents the polar radius, and Δθ is the deflection angle.

[0174] In this way, the first relative position information corresponding to the other multiple units can be obtained as labels.

[0175] In addition, based on the netlist corresponding to the sample chip, the input data of the graph neural network is determined, and the input data is input into the graph neural network to obtain output features, and then the output features are relatively position encoded and mapped to second relative position information.

[0176] The second relative position information is the predicted value, and the first relative position information is the label. The loss value is calculated through the loss function, and the gradient descent method is used to update the trainable parameters until the graph neural network model converges.

[0177] For example, referring to Figure 7, during the training phase, input features and graph structure information are fed into the graph neural network (GNN), and the GNN output is encoded to obtain a predicted relative position. Furthermore, the actual relative position is obtained based on the actual layout (absolute position) of the sample chip. The loss function is then calculated based on the actual relative position and the predicted relative position. Figure 7 is merely a schematic diagram, where the second subgraph can be understood as part of the input, not the entire input. The construction of the second subgraph will be elaborated in detail in the application phase. In this embodiment, the loss function is Smooth_L1.

[0178] In other embodiments, the loss function may be a cross entropy loss function or a mean squared error loss function (MSE), or other loss functions that can be adjusted to be suitable for calculating the relative error between positions. For example, the HingeLoss0-1 loss function, the logarithmic loss function, etc. may be used, and this application description does not list them one by one.

[0179] In this embodiment, both the graph neural network and the encoding function contain trainable parameters, and the objects of the gradient update include the trainable parameters in the graph neural network and the trainable parameters in the encoding function. In other embodiments, the encoding function may not contain trainable parameters, and the objects of the gradient update may only be the trainable parameters in the graph neural network.

[0180] Among them, the process of determining input based on the netlist and obtaining output features through the graph neural network will be explained in detail in the application stage.

[0181] It should be noted that there is no clear limitation on the execution sequence of the processes of obtaining the first relative position information based on the absolute position information and obtaining the second relative position information through prediction and encoding.

[0182] After the graph neural network, or the encoding function, is trained, it can enter the application stage.

[0183] During the application phase, the second relative position information is predicted based on the trained graph neural network, and is decoded based on the second relative position information to obtain the absolute position information of each unit.

[0184] In this embodiment, after obtaining the predicted absolute position information, the position information is fine-tuned. In other embodiments, fine-tuning may not be performed. Therefore, in this embodiment, referring to FIG9 , the application phase can be further divided into the following three phases: Part 1, the patterning phase; Part 2, the inductive layout generation phase; and Part 3, the netlist adaptive fine-tuning phase.

[0185] In the composition phase, netlist segmentation is performed and at least a unit flow graph is constructed:

[0186] After the netlist is segmented, a hierarchical netlist diagram is obtained, and a unit flow diagram can be established based on the hierarchical netlist diagram.

[0187] The chip netlist stores the topological information and geometric prior knowledge generated by the chip during the logic synthesis stage. A graph containing graph structure information can be constructed based on the netlist of the chip to be laid out.

[0188] Inductive layout generation phase:

[0189] Based on the netlist, initial unit features, initial mesh features, and initial pin features are generated. In other embodiments, pin features may not be generated. The initial unit features, initial mesh features, and initial pin features are then used as input features. The input features and the corresponding graph structure information, such as the hierarchical netlist and / or unit flow graph, are input into the graph neural network. The output features are encoded to generate the relative positions between units. Decoding is then performed based on the unit flow graph and the relative positions between units to obtain the absolute positions of each unit.

[0190] The inductive layout generation stage is the prediction stage, which predicts relative positions through graph neural networks.

[0191] Netlist adaptive fine-tuning stage:

[0192] During the netlist adaptive fine-tuning phase, the absolute positions of each cell, obtained from the inductive layout, are used as the initial solution. Based on the netlist information, hyperparameters such as the learning rate, number of iterations, and loss function weights are set. The objective function is calculated, and the cell positions are updated based on the gradients. The objective function is then recalculated, and this process is repeated to obtain the final cell positions.

[0193] In this embodiment, netlist adaptive fine-tuning may include adaptive adjustment of differentiable objective functions based on wire length, density, and anchor points, and / or density function weights. For example, by optimizing cell positions using gradient descent based on differentiable objective functions based on wire length, density, and anchor points, the density function weights may be adaptively updated during the iterative updating of cell positions.

[0194] The following describes in detail how each stage is implemented. In the graphing stage, specifically, in this embodiment, first, based on the netlist, a hypergraph is created with cells (including fixed cells and movable cells) as nodes and with the mesh lines between cells as edges.

[0195] An edge in a normal graph can only connect two nodes, while an edge in a hypergraph can connect multiple nodes (greater than or equal to 2 nodes). An edge in a hypergraph is equivalent to a face, and the points connected by the edge are the points contained in the face.

[0196] Building a hypergraph from a netlist can reduce the complexity of graph construction compared to building a regular graph from a netlist. This is because large-scale netlists have extremely complex logical structures and a large number of units. Building a regular graph would be difficult, time-consuming, or even impossible. By building a hypergraph from the netlist first, a single edge can connect more nodes, simplifying graph construction and facilitating rapid graph construction.

[0197] The netlist records the connection relationships between pins and units and the connection relationships between pins and nets. In this embodiment, a pin-to-unit mapping can be established based on the connection relationships between pins and units in the netlist. Combined with the connection relationships between pins and nets, the connection relationships between pins and nets are mapped to the connections between units and nets.

[0198] Then, the network cables are regarded as hyperedges, and the nodes connected by the hyperedges are the units connected by the network cables. A hypergraph is established with the units as nodes and the network cables as hyperedges.

[0199] In order to quantitatively express the complex properties of the netlist, the hypergraph (netlist graph) form is defined as follows:

[0200] in Represents a unit, where They represent terminal / port and movable cells respectively. Represents a network line, a hyperedge that is not connected to a unit in the hypergraph, and a pin Indicates the interaction between the unit and the network cable, They are and The corresponding feature matrix, Stored port The horizontal and vertical position information may be, for example, horizontal and vertical coordinate information.

[0201] Next, a partitioning procedure is performed on the hypergraph to divide the hypergraph into N blocks.

[0202] In this embodiment, during the execution of partitioning the hypergraph into N blocks, different macrocells cannot be simultaneously partitioned into the same block, i.e., the number of macrocells in each partitioned block is less than or equal to 1. Specifically, in this embodiment, different macrocells are partitioned into different blocks, and with a macrocell as the center, standard cells that have more connections to the macrocell are partitioned into the same block as much as possible. Fixed cells (e.g., ports) can be partitioned into a block individually or into the same block with adjacent macrocells.

[0203] The partitioning process can be implemented through a clustering algorithm, such as the K-means clustering algorithm, the K-Medoids algorithm, the CLARANS algorithm, or derivative or improved algorithms based on the above algorithms. During clustering, the macro cells and ports can be first divided into different blocks. Then, for standard cells, whether they are connected to the same macro cell is used as a clustering feature. The standard cells to be divided are grouped according to the similarity of their own characteristics. Standard cells connected to the same macro cell are grouped into a group. The more edges connecting to the macro cell, the higher the priority of being divided into the group. Multiple clusters can be obtained, and one cluster corresponds to one block.

[0204] It should be noted that there are various specific implementations of dividing into N blocks according to different division rules. For example, in some other embodiments, division can also be performed according to the number of units, and the maximum and minimum values ​​of the number of units in each block can be set.

[0205] Alternatively, in other embodiments, macrocells and ports can be first divided into different blocks. Ports and macrocells can be divided into the same block or into different blocks. Then, for standard cells, macrocells or ports can be used as cluster centers. Based on the Euclidean distance between standard cells and macrocells or ports, cluster analysis can be performed on the standard cells, and cells that are closer in distance can be grouped into the same block. There are many specific implementation methods, which are not listed in this application specification.

[0206] When the division is completed, multiple blocks are obtained, and each unit belongs to a unique block B i , for each block B i , build a hypergraph (First sub-image). The node is block B i Contained units, hyperedges are only connected to block B i Network cable for the inner unit.

[0207] Secondly, each block is regarded as a node and a hypergraph is built (First Global Graph), Hypergraph The nodes in the hypergraph are the blocks after division. The edges in are the lines connecting the units in different blocks. In this way, we get N+1 hypergraphs, which have N first subgraphs and 1 first global graph. in, It is used to indicate the connection relationship between blocks and does not contain the logical structure information within the block.

[0208] Then, the N+1 hypergraphs are expanded respectively, and for each hypergraph, a corresponding normal graph is established. In this embodiment, a star expansion method is used for the hypergraph. In other embodiments, one or more other expansion methods can be used.

[0209] After the hypergraph is expanded, N+1 ordinary graphs are obtained, among which N first subgraphs are expanded to obtain N second subgraphs, and the first global graph is expanded to obtain the second global graph. The second subgraph and the second global graph are both ordinary graphs, including two types of nodes, units and network cables. The edges in the graph are the connections between network cables and units, that is, the edges represent pins, and the nodes represent units or network cables. It should be noted that the subgraph obtained after division (the first subgraph or the second subgraph) is defined as a hierarchical netlist graph in the embodiment of the present application, and the hierarchical netlist graph can be the first subgraph or the second subgraph.

[0210] For example, referring to FIG10, the netlist diagram (hypergraph) Partition the set, where nodes 3 and 4 are divided into the same block B1, and nodes 5 and 6 are divided into the same block B2, to obtain a hypergraph and Hypergraph It should be noted that FIG10 is only a schematic diagram, wherein the netlist diagram Hypergraph and Hypergraph In the diagram, each edge only connects two nodes. In the actual netlist, each edge connects more than two nodes, not limited to two nodes.

[0211] As can be seen from Figure 10, after being divided into multiple blocks, hierarchical layout can be performed, that is, first determine the layout between blocks, and then reconstruct the layout within each block into the corresponding block to obtain a complete netlist layout.

[0212] The netlist (hypergraph) and its resulting subgraphs are undirected graphs, retaining only the chip's topological connectivity. Signal flow (i.e., direction) is also a crucial factor in determining chip layout in chip design. Next, based on the N subgraphs, we create N corresponding unit flow graphs. Unit flow graphs are directed graphs that carry signal flow information.

[0213] For example, the process of establishing a unit flow graph is shown in FIG11. In this embodiment, a corresponding unit flow graph is established for each common graph (second subgraph) in the hierarchical netlist graph. In other embodiments, a unit flow graph can be established based on the first subgraph, that is, without expanding the first subgraph, but directly establishing the corresponding unit flow graph based on the topological relationship expressed by the first subgraph.

[0214] In this embodiment, the specific method of establishing the unit flow graph is:

[0215] In each common graph (second subgraph), the starting point is first determined. The number of starting nodes can be one or more than two.

[0216] The principle for determining the starting point can be to consider the macrocell as the starting node. If there is no macrocell, the cell with the largest area can be used as the starting node. For example, if there is no macrocell, the port can be used as the starting point. If there is neither a macrocell nor a port, the cell with the largest area among the standard cells can be used as the starting point. In other embodiments, any cell can be selected as the starting point, or the cell with the largest area can be directly selected as the starting point.

[0217] Alternatively, two units can be selected as starting nodes. For example, when a subgraph contains more than two ports, both ports can be used as starting nodes; or when a subgraph includes a macro unit and at least one port, both the macro unit and one port can be used as starting nodes.

[0218] Place the starting point node in the queue, search for cells connected to the same network line as the starting point, and establish a directional edge connection between the starting point and the cell according to the signal flow direction. Place unvisited cells in the queue one by one until all cells have been visited, completing the construction of a cell flow graph.

[0219] More generally, when building a unit flow graph, an ordered traversal can be used. That is, when traversing, first traverse the first-order neighboring nodes of the starting node, establish directed edges between the starting node and the first-order neighboring nodes, then traverse the second-order neighboring nodes, establish directed edges between the first-order neighboring nodes and the second-order neighboring nodes, and so on, until all units in the same subgraph are visited and the construction of the unit flow graph is completed.

[0220] For example, in the first subgraph shown in Figure 11, nodes 0 and 1 are ports, nodes 2-6 represent movable units, and the edges connecting the nodes are network cables. In the second subgraph, nodes 0-6 represent units, nodes af represent network cables, and the edges connecting the units and network cables represent pins.

[0221] On the basis of the second subgraph, a unit flow graph is established. Among the nodes 0-6 representing the unit, node 0 and node 1 are selected as the starting nodes. From the first subgraph, we can know that node 0 and node 1 are both ports.

[0222] Then, traverse the other unit nodes connected to node 0 through the same network line. In the second subgraph, nodes connected through the same network line are represented as being connected to the same network node. For example, if both node 0 and node 2 are connected to network node a, that is, node 0 is connected to node 2 through network node a, then node 2 is a first-order neighbor node of node 0. Node 3 and node 0 are also connected to network node b, so node 3 is also a first-order neighbor node of node 0.

[0223] A directed edge is established between node 0 and node 2, and a directed edge is established between node 0 and node 3.

[0224] Next, among the first-order neighbor nodes, there is no other node connected to the same network node as node 2, so the traversal continues to the first-order neighbor node 3. Node 3 and node 4 are both connected to network node d, so node 4 is the second-order neighbor node of the starting node 0. A directed edge is established between the first-order neighbor node 3 and the second-order neighbor node 4. Similarly, through traversal, it can be determined that node 5 is the second-order neighbor node of the starting node.

[0225] Taking node 1 as the starting node, both node 1 and node 5 are connected to network node c. Node 5 is the first-order neighbor node of starting node 1, and there is no other first-order neighbor node. A directed edge is established between node 1 and node 5. Continuing the traversal, it is found that both node 6 and node 5 are connected to network node f, that is, node 5 is connected to node 1 through a network cable c, and node 6 is connected to node 5 through a network cable f. Then node 6 is the second-order neighbor node of starting node 1, and a directed edge is established between node 6 and node 5.

[0226] In this way, based on the unit flow graph, multiple directed edges are obtained, and the directed edges are defined as unit flow graph edges f INCOME .

[0227] In this embodiment, for each unit flow graph, continue to construct the unit path f path A unit path is a path within a unit flow graph that starts from the start node and passes through at least one unit flow graph edge. As shown in Figure 11, based on the unit flow graph, multiple unit paths are obtained: 0→2, 0→3, 0→3→4, 1→5, 0→3→5, and 1→5→6.

[0228] More generally, as shown in the following formula (5), where v i represents the unit, t represents the path length, (v0, v1, ..., v t ) P Represents a path. (v0, v1, ..., v t ) P =f PATH ((v t-1 , v t )), where f INCOME (v i )=(v i-1 , v i ), i∈{1, 2, ..., t-1} Formula (5)

[0229] It should be noted that, in the training phase, it is also necessary to execute the composition process. Unlike the application phase, the training phase is composed based on the netlist corresponding to the sample chip. In some embodiments, when encoding, it is necessary to use the directed edges in the unit flow graph to encode the absolute position into a relative position. For example, referring to FIG12 , in a specific embodiment, in the training phase, the input includes graph structure information and input features. The graph structure information includes a netlist graph and a unit flow graph. The netlist graph can be N hierarchical netlist graphs (second subgraphs) and 1 second global graph. The input features are the features of each node. For the netlist graph, they include the initial features of the network line and the initial features of the unit; for the unit flow graph, they only include the initial features of the unit.

[0230] Next, we will explain part 2 of the application phase: the inductive layout generation phase.

[0231] The inductive layout generation stage can be further divided into three sub-stages: graph neural network feature generation (output feature), relative position encoding, and relative position decoding.

[0232] Refer to Figure 13, which shows the hierarchical architecture of the graph neural network and the data processing flow at each level.

[0233] In the composition stage, multiple hierarchical netlist diagrams (second sub-diagrams) and unit flow diagrams corresponding to each hierarchical netlist diagram are obtained based on the netlist. In this embodiment, the input of the graph neural network includes input features and graph structure information, wherein the input features include unit initial features, network cable initial features and pin initial features, and the graph structure information includes graph structure information of N second subgraphs, 1 second global graph and N unit flow graphs.

[0234] The graph structure information can be input into the graph neural network in the form of an adjacency matrix, and the initial features of the units, the initial features of the network cables, and the initial features of the pins can be input into the graph neural network in the form of feature vectors or feature matrices. For example, the netlist contains information such as the size and position (initial position) of each unit. By using the values ​​of this information as elements in a vector, the initial feature vector of the unit can be obtained. The netlist contains information such as the position, size, number, and spacing of the pins. By using the values ​​of this information as elements in a vector, the initial feature vector of the pins can be obtained. Similarly, based on the network cable related information contained in the netlist, the initial feature vector of the network cable can be obtained.

[0235] In the adjacency matrix corresponding to the second subgraph, row elements and column elements can represent cells, pins, or pins and cables, respectively. If a cell or cable is connected to a pin, the element value at the corresponding row-column intersection is 1; if not, it is 0. In the corresponding adjacency matrix in the cell flow graph, row and column elements both represent cell nodes. If there is a connection between cells, the element value at the corresponding row-column intersection is 1; otherwise, it is 0.

[0236] Specifically, in this embodiment, a graph convolutional network based on a unit flow graph and a layered netlist graph is designed, that is, the graph neural network is a graph convolutional neural network.

[0237] Exemplarily, in this embodiment, the graph convolutional neural network may include a multilayer perceptron (MLP), a convolutional layer, and an attention mechanism layer (Attention layer); wherein, the MLP includes at least one fully connected layer, the convolutional layer includes at least one convolutional layer; the attention layer includes at least one attention mechanism layer and at least one hidden layer.

[0238] Refer to Figure 13 and x+6, in the convolution layer, three convolution functions are used and To transmit the message M, the hidden layer performs feature fusion and update, and finally obtains the output features of each unit and the output features of the network. The convolution function is the message passing function shown in Figure 14.

[0239] As shown in Figure 13, for example, after performing the following calculations on the MLP fully connected layer, we can obtain

[0240] in, They represent the initial feature vectors of unit v and network line u respectively; MLP represents the operation performed by the fully connected layer. Optionally, in this embodiment, the initial features of the pins may not participate in the fully connected operation. The H output by MLP P That is, the initial eigenvector of the pin.

[0241] In the convolutional layers, message passing is performed from unit to unit, from unit to wire, and from wire to unit.

[0242] Specifically, based on the graph structure information of the unit flow graph, the unit-to-unit (V→V) message passing is performed. In the application scenario of this application, the message is the feature, and the transmission of the message is the transmission of the feature. In the unit flow graph, only one type of node is included: the unit node. In this embodiment, as shown in the figure, the first-order neighborhood message passing can be performed, that is, the features of the first-order neighborhood nodes of each unit node are transferred to the unit node. The specific transmission can be the execution of the corresponding convolution function to map the features of multiple first-order neighborhood nodes to the features of the unit node. Here, the process of mapping the features of multiple nodes to one node can be understood as the process of feature aggregation.

[0243] In other embodiments, multi-order neighborhood message passing can be performed. For example, second-order neighborhood message passing can be performed: for each cell node, its first-order and second-order neighborhood nodes are first determined, the features of the second-order neighborhood nodes are first transferred to the first-order neighborhood nodes, and then the features of the first-order neighborhood nodes are transferred to the cell node. That is, the number of convolutional layers is 2, and two layers of message passing are performed. Wherein, cell represents a cell node, and edge represents a connecting edge (network cable).

[0244] Based on the graph structure of the hierarchical netlist, message passing is performed from nets to cells (U→V) and from cells to nets (V→U). Cell represents a cell node, net represents a net node, and edge represents a connection (pin).

[0245] The computational expressions involved in the message passing process performed through the convolutional layer are as follows:

[0246] in, Respectively represent the unit set and the network cable set; It is the adjacency matrix corresponding to the hierarchical netlist graph, which represents the connection between cells and net lines. Represents the adjacency matrix corresponding to the unit flow graph, indicating the connection between units Represents the feature representation of the lth hidden layer of the unit and the network line; l is the number of convolutional layers of the model; Indicates that the lth layer passes through the edge The message obtained after message passing.

[0247] For example, for Consider a single network cable u and fuse its adjacent unit set and the pin information connecting them, and finally The form can be shown as follows:

[0248] in, is the eigenvector of unit v, is the eigenvector of the pin connecting v,u, Represents the connection edge between the unit and the network line Represents the unit set and the network cable set respectively, is a learnable parameter matrix, i.e., a training parameter. ⊙ represents the Hadamard product operation. The unit features containing the pin information are already in collect.

[0249] For example, The form is as follows:

[0250] in is the eigenvector of the network cable u, is the characteristic vector of the pins connecting v and u, where v and u represent the unit and the network respectively. Represents the connection edge between the unit and the network line Represents the unit set and the network cable set respectively, is a learnable parameter matrix, i.e., a training parameter; ⊙ represents the Hadamard product operation, and η and shift are hyperparameters.

[0251] In the unit flow diagram Only the feature vectors of cells are used to perceive the topological information in the cell flow graph. As shown in the following formula:

[0252] in, is the eigenvector of unit v, Represents the connecting edges between units Represents the set of all units, v represents the unit, It is a learnable parameter matrix, i.e., a trainable parameter.

[0253] In this embodiment, an attention mechanism layer is set after the convolution layer, and the output of the convolution layer is fused and updated based on the attention mechanism. In other embodiments, the convolution layer may not be followed by an attention mechanism, but at least one hidden layer is set to achieve message fusion and update. The attention mechanism is not a necessary component of the graph neural network. After the convolution layer, any neural network layer that can perform the following operations can be used:

[0254] f update is the update function. For example, in this embodiment, the update function is: update (H, M) = H + Tanh (M) Formula (12)

[0255] Tanh represents the hyperbolic tangent function, and its expression is

[0256] In other embodiments, other update functions may be selected and are not limited to the hyperbolic tangent function. For example, it is not excluded that hyperbolic sine, hyperbolic cosine, hyperbolic cotangent, hyperbolic secant, hyperbolic cosecant, etc. may be used as update functions in other embodiments.

[0257] Thus, after the graph neural network generates features as described above, output features can be obtained. In this embodiment, the output features include feature vectors corresponding to unit nodes and feature vectors corresponding to network nodes. In other embodiments, only unit features can be output, that is, the output features only include feature vectors corresponding to unit nodes, and do not include feature vectors corresponding to network nodes.

[0258] Next, relative position encoding is performed based on the output features. For example, the specific process of relative position encoding is as follows:

[0259] After obtaining the feature representations of the cells and the mesh, they are converted into the relative distance ρ and deflection angle Δθ between cells through relative position encoding. Optionally, in this embodiment, relative position encoding is the process of mapping the output features into relative position information through an encoding function.

[0260] As shown in Figure 15, in this embodiment, the relative position encoding process requires reference to the unit flow graph, specifically the unit flow graph edges and unit paths. Optionally, the first independent variable can be obtained based on the unit flow graph edges (directed edges) and their associated node features and network features; the second independent variable can be obtained based on the unit path and its associated node features and network features.

[0261] For example, the relative position information of the jth unit relative to the ith unit is encoded as follows:

[0262] First, combine the unit flow graph edges to get the first independent variable; combine the unit paths to get the second independent variable: where u s =f NET ((v k , v i )) u t =f NET ((v i , v j )) (v k , v i )=f INCOME (v i ) Formula (13)

[0263] in, Represent the output features of the i-th, j-th, k-th unit and the t-th, s-th network line respectively; Represents the connection operation between vectors; Represents the unit set and the network cable set respectively, is the first independent variable, representing the unit flow graph The edge (v i , v j )The characteristic representation of its relative distance ρ; is the second independent variable, which is represented in the unit flow diagram The edge (v i , v j ) Characteristic representation of its deflection angle Δθ;

[0264] v k Representation unit v i The predecessor node in the unit flow graph, that is, the kth unit is connected to the i-th unit through a directed edge; f NET Indicates the network cable between two units, such as u s =f NET ((v k , v i )), indicating that the k-th unit and the i-th unit are connected via the s-th network cable; u t =f NET ((vi , v j )), indicating that the i-th unit and the j-th unit are connected through the t-th network cable.

[0265] Represents the feature vector (output feature) corresponding to the i-th unit, Represents the feature vector (output feature) corresponding to the t-th network line, Represents the feature vector (output feature) corresponding to the jth unit. In the unit flow graph, there is a directed edge (unit flow graph edge) from the i-th unit to the j-th unit.

[0266] After obtaining the output features through the graph neural network, the corresponding first independent variables are obtained by traversing the unit flow graph edges. For example, for the unit flow graph edge pointing from the i-th unit to the j-th unit, the first independent variable is obtained based on the output features of the i-th unit, the output features of the j-th unit, and the output features of the t-th network line.

[0267] As can be seen from the above calculation formula (8), in this embodiment, a vector concatenation operation can be performed on the output features of the i-th unit, the output features of the j-th unit, and the output features of the t-th network line, and the concatenated vector is the first independent variable. In other embodiments, other operations can be performed on the output features of the i-th unit, the output features of the j-th unit, and the output features of the t-th network line to obtain the first independent variable, such as weighted summation, normalization followed by concatenation, etc., and the method is not limited to performing vector concatenation.

[0268] The second independent variable is obtained based on the unit path. Referring to Figure 15, the unit path starts at the kth unit and passes through the sth network line, the ith unit, and the tth network line to reach the jth unit. The second independent variable is obtained based on the eigenvector corresponding to the kth unit, the eigenvector corresponding to the sth network line, the eigenvector corresponding to the ith unit, and the eigenvector corresponding to the jth unit. For example, a connection operation can be performed on the eigenvectors corresponding to the nodes and network lines on the path. In other embodiments, the eigenvectors corresponding to the nodes and network lines on the path can be weighted summed or normalized before being connected, etc., and are not limited to performing vector connection operations.

[0269] After obtaining the first independent variable (polar diameter feature) and the second independent variable (deflection angle feature), the first independent variable and the second independent variable are mapped to the polar diameter and deflection angle respectively through the encoding function:

[0270] ρ i，j , Δθ i，j Represents the polar diameter (relative distance between units) and the deflection angle, is the first encoding function, which is used to convert the first independent variable Mapped to the polar radius in relative position information; is the second encoding function, which is used to convert the second independent variable Mapped to the deflection angle in relative position information.

[0271] a ρ , a θ , b ρ , b θ is the learnable parameter vector, b ρ , b θ is a learnable parameter scalar. α and β are hyperparameters.

[0272] After the above steps, the mapping from output features to relative position information can be achieved.

[0273] After obtaining the relative position information, the third sub-stage, relative position decoding, begins. It should be noted that in other embodiments, after obtaining the relative position information, decoding may not be performed. Instead, the decoding operation may be performed by another service provider, or a decoding solution may be provided, allowing the user to perform the decoding themselves. Decoding is not a necessary step in this method.

[0274] Specifically, in this embodiment, after the relative position code is obtained, it is decoded to obtain the absolute position of the unit.

[0275] For a unit path (v0, v1, ..., v t-1 , v t ) P , with the unit flow graph edge (v t-1 , v t ) calculates the unit position vector

[0276] Where ρ0 is the polar radius of the first node relative to the starting node, ρ0 is the modulus of p0, and p0 is the vector of the first node relative to the starting node, and its relative coordinates are (x0, y0). Then θ0 is the angle between p0 and the positive direction of the x-axis, θ t-1，t is the vector between units t-1 and t The angle with the horizontal direction, For two units v t-1 , v t The vector formed by connecting the lines.

[0277] During decoding, N unit flow graphs may be decoded one by one, taking the unit flow graph as a unit.

[0278] For a unit flow graph, a layer-by-layer decoding method can be used: first determine the starting node and the absolute position information of the starting node, then determine the absolute position information of the first-order neighboring nodes based on the relative position information of the first-order neighboring nodes corresponding to the starting node and the absolute position information of the starting node. Next, based on the relative position information of the second-order neighboring nodes relative to the first-order neighboring nodes and the absolute position information of the first-order neighboring nodes, the absolute position information of the second-order neighboring nodes can be obtained. Similarly, based on the absolute position information of the m-th order neighboring nodes and the relative position information of the m+1 order neighboring nodes, the absolute position information of the m+1 order neighboring nodes can be determined; m ≥ 1 and is an integer.

[0279] For example, referring to Figure 16, in a unit flow graph, node 1 is the starting node. The nodes connected to the starting node via a directed edge (unit flow graph edge) are the starting node's first-order neighbor nodes. Nodes 2 and 3 in the graph are the starting node's first-order neighbor nodes. Based on the absolute position of node 1, the relative position information of node 2 relative to node 1, and the relative position information of node 3 relative to node 1, the absolute position information of nodes 2 and 3 can be obtained. According to the signal flow direction, the downstream nodes connected to the first-order neighbor nodes via a directed edge are the starting node's second-order neighbor nodes. Node 4 in the graph is the second-order neighbor node of node 1. Given the absolute position information of first-order neighbor nodes 2 and 3, the absolute position information of second-order neighbor node 4 can be obtained based on the relative position information of node 4 relative to node 3. For more complex unit flow graphs, this method can be used for layer-by-layer decoding. Thus, when decoding the deflection angle based on the unit path, by the time the last node on the path needs to be decoded, the predecessor nodes (upstream nodes) on the path have already been decoded.

[0280] It should be noted that, since each unit node may be a terminal node (end node) of multiple unit paths, during decoding, the same unit node may obtain different absolute positions according to different unit paths.

[0281] Optionally, in this embodiment, the average value of multiple absolute positions obtained based on multiple paths can be taken to obtain v t Final position p t .

[0282] Among them, p t；(t-1，t) To use the path (v0, v1, ..., v t ) P The decoded unit v t The absolute position of For two units v t-1 , v t The vector formed by the connecting line, p t For unit vt Final position, mean means the average value, Represents the connecting edges between cells Represents a collection of cells.

[0283] In other embodiments, during decoding, one path may be selected from multiple paths, for example, the shortest path. The longer the path, the greater the potential error, so selecting the shortest path can reduce the error to a certain extent. Alternatively, one absolute position information may be selected from the multiple absolute position information obtained as the decoding result. Furthermore, in other embodiments, a weighted summation may be performed on the multiple absolute position information obtained based on multiple paths, and implementation methods are not unique.

[0284] It should be noted that during the encoding phase, the same node may correspond to multiple paths. During encoding, one path may be selected from the multiple paths for encoding, for example, any one path or the shortest path. In other embodiments, the encoding results of multiple paths may be averaged, or weighted summed, with the sum of the weights being 1, etc., which are not listed in this application specification.

[0285] In this way, after the inductive layout generation phase, the absolute position information of each unit is obtained. In some embodiments, the absolute position information obtained in the inductive layout generation phase can be directly used as the chip layout result. In this embodiment, after obtaining the absolute position information through decoding, the chip layout is further optimized through fine-tuning. As shown in Figure 17, after the relative position encoding and decoding to obtain the layout, the layout position is further fine-tuned to obtain the optimized layout as the layout result.

[0286] In related technologies, each chip is trained separately, which is not generalizable and may not achieve good results in different chips, which also leads to bottlenecks in speed optimization. The embodiment of the present application adopts an inductive layout generation algorithm. The inductive layout generation mainly includes variant encoding methods such as SE (2), which ensures that the layout learned by the model can be generalized between different chip netlists. Self-supervised training is used to enable the graph neural network to learn layout knowledge from the laid out chip netlist. Based on the unit flow graph and the relative position decoding between units, the position of each unit is obtained, which improves the generalization of the layout method for different chips and eliminates the need for separate training for each chip.

[0287] In addition, a variety of layout samples are used to train the model, and the initial chip layout data preparation is difficult. In the solution provided in the embodiment of the present application, the inductive layout generation algorithm is based on the existing information of the chip netlist (the connection relationship between pins and wires, the mapping relationship between pins and units, pin positions, signal directions, unit sizes, and unit types). It constructs unit, wire, and pin features, and inputs them into the graph neural network together with the hierarchical netlist diagram and the unit flow diagram. The output is encoded to obtain the relative position between units, and finally the relative position is decoded to obtain the absolute position. This method significantly improves the efficiency of cross-chip training and reasoning with the help of relative position encoding and graph neural networks. In addition, this method reduces the difficulty of chip layout data preparation by learning layout knowledge on the laid out netlist and performing reasoning on the unlaid chip netlist.

[0288] Netlist adaptive fine-tuning uses the cell positions obtained from the inductive layout as the initial solution. During the adaptive fine-tuning phase, the objective function must be determined first. Then, based on the netlist information, hyperparameters such as the learning rate, number of iterations, and loss function weights are set. The objective function is calculated, cell positions are updated based on the gradients, and the objective function is recalculated. This process is repeated to obtain the final cell positions.

[0289] When using graph neural networks to generate chip layouts, the graph neural network model sometimes cannot fully meet the constraints of the chip layout, such as components cannot overlap and the placement of components cannot exceed the set layout boundaries. Further performing netlist adaptive fine-tuning based on inductive layout can solve this problem.

[0290] Furthermore, because the output of a graph neural network is a geometric layout based solely on the topology of the netlist, even similar topologies on different netlists can have significant geometric differences due to factors such as chip layout. These differences are beyond the reach of graph neural networks based solely on topology, necessitating further fine-tuning to improve layout quality and usability in subsequent design processes.

[0291] For example, the fine-tuning phase process is as follows:

[0292] Three optimization objectives are set: wire length, density, and anchor points. Wire length can be half-perimeter wire length (HPWL).

[0293] The line length takes the weighted average line length as the line length function, and the formula is shown in the following formula (11), where x v ,y v Represents the horizontal and vertical coordinates of unit v, and γ is a hyperparameter.

[0294] The density function is the same as that in the self-supervised training stage, and the unit is regarded as a charged body to solve the electric potential energy and the electric field intensity in the x and y directions.

[0295] The calculation formula is shown in formula 12 and formula 13 below, where N(v) is the cell density function, v represents the cell, x and y are spatial coordinates, ρ(x, y) and ψ(x, y) represent the spatial single point density function and potential distribution function, is a vector orthogonal to the boundary, is the spatial electric field intensity distribution function, Indicates the chip layout boundary.

[0296] The above electrostatic field can be solved using a method similar to the fast Fourier transform, with a time complexity of O(NlogN×MlogM). The time complexity of the final algorithm is

[0297] The purpose of the anchor function is to prevent the final fine-tuned layout from differing significantly from the output layout of the graph neural network during fine-tuning, which could disrupt the output layout of the graph neural network and slow down convergence. Therefore, the anchor function is used to limit excessive unit drift during optimization.

[0298] The anchor point function is shown in formula (14):

[0299] in is the unit position before fine-tuning, (X, Y) is the chip layout area, x v ,y v represents the horizontal and vertical coordinates of unit v, and the negative slope of LeakyReLU is fixed to 0.01. In the fine-tuning stage, the final chip layout is directly optimized. The loss function of the final fine-tuning stage is shown in the following formula (15), where λ D ,λ A is the weight coefficient.

[0300] The parameter γ in the weighted average line length is adjusted once every multiple rounds during the training process. For example, it is adjusted once every 5 rounds. The adjustment formula is shown in the following formula (16):

[0301] where γ init It is necessary to set an initial value. For example, in this embodiment, the initial value γ init It is set to 40960. In other embodiments, it can be set to other values, which are not listed one by one.

[0302] The overflow value of the layout is calculated as shown in the following formula (17): overflow = ∑N(v) - target density *Area(v) Formula (24)

[0303] Where N(v) is the cell density function, target density is a hyperparameter, and Area(v) is the area of ​​cell v.

[0304] When the congestion value of the layout is large, it means that the units are arranged too closely together, and the value of γ is increased in turn, which is actually equivalent to reducing The weight of , is equivalent to spreading out the layout units.

[0305] λ D It can be adjusted in each training round, and its initial value is calculated as follows:

[0306] After each round D The update formula is as follows:

[0307] Among them, the initial value density init is an adjustable hyperparameter, To calculate the weighted average function and density function of the layout and perform back propagation, the gradient at each unit position of the layout, epochs is the current training round, HPWL new is the HPWL of the current round, HPWL old is the HPWL of the previous round, and UPCOF is an adjustable hyperparameter.

[0308] It should be noted that the optimization in the fine-tuning phase is directly applied to the movable unit position P M , rather than the trainable parameters in the graph neural network. In the fine-tuning phase, the time complexity is where t f is the number of rounds of fine-tuning required on each netlist.

[0309] Adaptive fine-tuning can further optimize the layout position based on the chip layout result obtained by inductive generation, but some embodiments may not perform fine-tuning.

[0310] Some models in related technologies have poor training and inference times on large-scale netlists, resulting in low efficiency. This is partly due to the cold start problem associated with traditional methods that directly optimize cell positions, which requires a long training time. In the embodiments of the present application, netlist adaptive fine-tuning uses the cell positions obtained based on the inductive layout as the initial solution for adaptive fine-tuning, avoiding the cold start problem, significantly shortening the time required to optimize cell positions, and improving efficiency. Furthermore, netlist adaptive fine-tuning further optimizes the results generated by the inductive layout.

[0311] After testing, the solution proposed in the embodiment of this application can achieve the following technical effects:

[0312] See the following tables, where “Our” refers to the solution proposed in this application, D***Place refers to a solution in the related art, and **Place refers to another solution in the related art.

[0313] Tables 1-4 below show the results of the model proposed in this embodiment of the application compared with the D***Place[3] method and the **PlAce[4] method on the ISPD2015[1] and ISPD2019[2] datasets. The model proposed in this embodiment of the application was trained on the four netlists of ISPD2015, mgc_fft_1, mgc_fft_2, mgc_fft_a, and mgc_fft_b, while the other netlist designs were directly inferred to obtain the layout results.

[0314] Table 1 compares the HPWL results of the methods D***Place and **Place in related art and the method proposed in the embodiments of this application based on the netlists of the ISPD2015 dataset (the smaller the value, the better):

[0315] Table 1

[0316] Table 2 compares the running time of the methods in the related art and the method proposed in the embodiments of the present application based on the netlists of the ISPD2015 dataset (the smaller the value, the better):

[0317] Table 2

[0318] Table 3 compares the HPWL results of the methods in the related art and the method proposed in the embodiments of the present application on each netlist based on the ISPD2019 dataset (the smaller the value, the better):

[0319] Table 3

[0320] Table 4 compares the running time of the methods in the related art and the method proposed in the embodiments of the present application based on the netlists of the ISPD2019 dataset (the smaller the value, the better):

[0321] Table 4

[0322] As shown in Tables 1 and 2, on the training set netlists (mgc_fft_1, mgc_fft_2, mgc_fft_a, and mgc_fft_b), the proposed model achieves 13% and 46% improvements on HPWL compared to D***Place and **PlAce. Furthermore, in terms of running speed, the proposed model achieves an average improvement of 595% and 1929% compared to D***Place and **PlAce, respectively. This demonstrates that the proposed model is able to learn layout knowledge from the training set and quickly generate high-quality chip layouts.

[0323] In a test set of other chip netlists, the proposed model achieved a 5% and 79% improvement in HPWL compared to the D***Place and **PlAce methods. Furthermore, in terms of running speed, the proposed model achieved a 53% and 4974% improvement compared to D***Place and **PlAce, respectively. This demonstrates that the layout knowledge learned by the proposed model is generalizable.

[0324] As can be seen from Tables 3 and 4, compared with D***Place and **PlAce, the model proposed in this application achieved an improvement of 1% and 23% in HPWL, and an improvement of 138% and 857% in running speed, respectively.

[0325] From the perspective of the chip design process, simply achieving excellent HPWL is not enough. In order to further compare the layout quality, the OpenROAD flow routing tool is used to perform global routing according to the models in the relevant technology and the layout schemes generated by the method proposed in the embodiment of this application. The wire length and congestion are evaluated based on the results of global routing. The wire length determines the cost of etching in the subsequent chip manufacturing process, and the part of the chip with excessive congestion may be at risk of burning, making the design unusable. Moreover, the wire length and congestion calculated by the routing scheme obtained by global layout are more accurate than the HPWL and density of the global layout. The results of the global routing calculation are more accurate in estimating the results of the final solution.

[0326] Table 5 shows the results after routing of a portion of the netlist. Table 5 is a comparison of rWL and Overflow of D***Place and the method proposed in the embodiment of this application based on a portion of the ISPD2015 netlist (the smaller the value, the better):

[0327] Table 5

[0328] As can be seen from Table 5, even after global routing, the model method proposed in this embodiment of the application achieves a 7% improvement in line length compared to D***Place. Furthermore, Table 5 shows that compared to D***Place, the method proposed in this application demonstrates significant and superior routing optimization results.

[0329] Refer to Figures 18(a)-(d), 19(a)-(c), and 20(a)-(c), which show the visualization of congestion after routing on netlists of different architectures. The darker the grayscale in the figure, the more severe the congestion. Among them, Figures 18(a)-(c) respectively show the congestion distribution diagrams of the model, D***Place, and **Place proposed in the embodiment of this application on the mgc_fft_2 netlist. Figure 18(d) is an example diagram of the congestion level. Figures 19(a)-(c) respectively show the congestion distribution diagrams of the model, D***Place, and **Place proposed in the embodiment of this application on the mgc_matrix_mult_2 netlist; Figures 20(a)-(c) respectively show the congestion distribution diagrams of each method on the mgc_superblue19 netlist.

[0330] As can be seen from Figures 18-20, compared with D***Place and **Place on the netlists of three different architectures, the method proposed in the embodiment of the present application can obtain a chip layout with less congestion. This shows that the model proposed in the embodiment of the present application can be generalized on different heterogeneous netlists and achieve better layout quality.

[0331] In summary, the related art trains each chip separately, which is not generalizable, which causes a bottleneck in the speed optimization of chip layout. This application provides a complete and portable global layout generation framework (inductive layout generation and netlist adaptive fine-tuning) by learning layout knowledge from the laid out netlist and performing reasoning on the unlaid chip netlist, generating a usable global layout solution in a relatively short period of time, and providing a good estimate for the subsequent calculation of congestion, line length and timing. Through this framework, a global layout solution for a usable high-quality chip netlist can be quickly generated, which greatly improves the layout efficiency, and realizes the portability of the layout method through inductive layout generation based on relative position encoding and decoding.

[0332] Optionally, adaptive netlist fine-tuning further optimizes the results of inductive placement generation. Related methods that directly optimize cell positions suffer from the cold start problem and require a long training time. In this application, by using the results of inductive placement generation as the initial solution, the cold start problem is avoided and the time required to optimize cell positions is significantly shortened.

[0333] Overall, the proposed portable chip layout solution can provide higher-quality layout results in a shorter timeframe than traditional techniques. This portable layout is achieved through inductive layout generation, and with the help of netlist adaptive fine-tuning, the inductive layout generation results can be optimized in a shorter timeframe, further improving layout quality. This improves generalizability while also ensuring the timeliness of chip layout to a certain extent.

[0334] An embodiment of the present application also provides an electronic device, which includes: one or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, enable the electronic device to execute a method as described in any of the above embodiments.

[0335] Specifically, the electronic device may be a server or server cluster that provides chip layout services. Referring to FIG18 , the hardware structure of the electronic device may include: a processor, a memory, and a chipset.

[0336] Processor, the core that handles all computing tasks and requests, including at least the CPU.

[0337] Storage: This includes memory and hard disk. The larger the capacity, the more requests and files can be processed simultaneously.

[0338] Chipset: Includes the northbridge chip and the southbridge chip, which connect various I / O devices. The northbridge chip connects to the CPU, memory, and PCI bus, while the southbridge chip connects to hard drives, network devices, and other I / O devices.

[0339] I / O bus: connects various I / O devices, such as network cards, graphics cards, sound cards, USB, etc. The larger the I / O bus bandwidth of the server, the more requests it can handle.

[0340] I / O devices: including network cards, graphics cards, sound cards, USB, etc. The network card is the main device connecting the server to the external network. Its speed and performance directly affect the server's response speed and transmission speed.

[0341] Power supply: Provides stable power to the server to ensure normal operation of the server.

[0342] Chassis (not shown in Figure 18): The outer shell of the server hardware that protects the hardware from dust, vibration, and temperature.

[0343] Exemplarily, a processor may include one or more processing units, for example, a neural-network processing unit (NPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a digital signal processor (DSP), a baseband processor, etc. The different processing units may be independent devices or integrated into one or more processors. The controller may generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0344] The memory can be used to store computer executable program code, which includes instructions. The internal memory may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, at least one application required for a function, etc. The data storage area can store data (such as input data, output data) created during the use of the electronic device. In addition, the internal memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory and / or instructions stored in a memory provided in the processor.

[0345] Alternatively, the electronic device may be a terminal device with certain computing capabilities, such as a mobile phone, a personal computer (PC) (e.g., a laptop), a tablet PC, a wearable electronic device, etc. The terminal device may include a processor, an external memory interface, an internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, etc.

[0346] It should be understood that the structure illustrated in the embodiment of the present invention is merely an example and does not limit the electronic device. The electronic device in the embodiment of the present application may include more or fewer components than shown, or combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0347] An embodiment of the present application further provides a storage medium including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the method described in any of the above embodiments.

[0348] An embodiment of the present application also provides a chip system, including a communication interface for inputting and / or outputting data; and a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any of the above embodiments.

[0349] It should be noted that the solutions provided in the embodiments of the present application include any one or more of chip layout and training methods, electronic devices, storage media and chip systems, or may also be other forms of software products, hardware products or virtual service products obtained based on the technical concepts of the methods described in the specification of this application.

[0350] In the description of the device in the embodiment of the present application, various modules for implementing the method process functions are constructed in the device. The division of modules is merely a division of logical functions. When implementing the embodiment of the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0351] Specifically, in actual implementation, each functional module can be fully or partially integrated into one physical entity, or physically separated. Moreover, these modules can all be implemented in the form of software called through processing elements; or all can be implemented in the form of hardware; or some modules can be implemented in the form of software called through processing elements, and some modules can be implemented in the form of hardware. For example, the detection module can be a separately established processing element, or it can be integrated into a chip of an electronic device. The implementation of other modules is similar. In addition, these modules can all or partly be integrated together, or they can be implemented independently. During the implementation process, each step of the above method or each of the above modules can be completed by the hardware integrated logic circuit in the processor element or by instructions in the form of software.

[0352] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs). For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0353] Specifically, in one embodiment of the present application, the above-mentioned one or more computer programs are stored in the above-mentioned memory, and the above-mentioned one or more computer programs include instructions. When the above-mentioned instructions are executed by the above-mentioned device, the above-mentioned device executes the method steps described in the embodiment of the present application.

[0354] Specifically, in one embodiment of the present application, the processor of the electronic device may be a SOC, which may include a central processing unit (CPU) and may further include other types of processors, such as a graphics processing unit (GPU). Specifically, in one embodiment of the present application, the processor of the electronic device may be a PWM control chip.

[0355] Specifically, in one embodiment of the present application, the processor involved may include, for example, a CPU, a DSP, a microcontroller, or a digital signal processor, and may also include a GPU, an embedded neural network processor (NPU), and an image signal processor (ISP). The processor may also include necessary hardware accelerators or logic processing hardware circuits, such as ASICs, or one or more integrated circuits for controlling the execution of the program of the technical solution of the present application. In addition, the processor may have the function of operating one or more software programs, and the software programs may be stored in a storage medium.

[0356] Specifically, in one embodiment of the present application, the memory of the electronic device may be a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any computer-readable medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer.

[0357] Specifically, in one embodiment of the present application, the processor and the memory may be combined into a processing device, or more commonly, they may be independent components, with the processor being configured to execute program code stored in the memory to implement the method described in the embodiment of the present application. In a specific implementation, the memory may also be integrated into the processor or independent of the processor.

[0358] Furthermore, the devices, apparatuses, and modules described in the embodiments of the present application may be implemented by computer chips or entities, or by products having certain functions.

[0359] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, apparatus, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0360] In the several embodiments provided in this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of this application.

[0361] The embodiment description in this application is described with reference to the flow chart and / or block diagram according to the method, equipment (device) and computer program product of embodiment of the present application.It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of general-purpose computer, special-purpose computer, embedded processing machine or other programmable data processing equipment to produce a machine, so that the instruction executed by the processor of computer or other programmable data processing equipment produces the device for realizing the function specified in one flow chart flow chart or multiple flow charts and / or one block or multiple blocks of block diagram.

[0362] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0363] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0364] It should also be noted that, in the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can represent: a, b, c, a and b, a and c, b and c or a and b and c, where a, b, c can be single or multiple.

[0365] In the embodiments of the present application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus comprising the element.

[0366] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communications network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0367] The various embodiments in this application are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the partial description of the method embodiments.

[0368] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments of the present application can be implemented using a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0369] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices, apparatuses and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0370] The above description is merely a specific embodiment of the present application. Any person skilled in the art may easily conceive of variations or substitutions within the technical scope disclosed in this application, and such variations or substitutions shall be within the scope of protection of this application. The scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A chip layout training method, characterized in that: The method comprises: Determine first relative position information; the first relative position information is relative position information between different units in each unit that has been laid out in the sample chip; Determine a first input of a graph neural network to be trained; the first input is obtained based on a first netlist corresponding to the sample chip; Obtaining a first output through the graph neural network; Based on the first output, perform encoding to obtain second relative position information; Calculate a loss function value based on the first relative position information and the second relative position information; and optimize trainable parameters in the graph neural network based on the loss function value.

2. The method according to claim 1, characterized in that Determining first relative position information includes: Obtaining absolute position information of each laid out unit in the sample chip; The relative position information between different units is calculated based on the absolute position information.

3. The method according to claim 2, characterized in that The absolute position information includes coordinate information; Calculating relative position information between different units according to the absolute position information includes: According to the coordinate information corresponding to the j-th unit and the i-th unit respectively, the polar coordinate information of the j-th unit relative to the i-th unit is calculated; both i and j are integers greater than or equal to 1, and i≠j.

4. The method according to claim 1, characterized in that Based on the first output, encoding is performed to obtain second relative position information, including: Determine an independent variable based on the first output, and execute an encoding function on the independent variable to obtain second relative position information; the encoding function is used to map the independent variable to the second relative position information; After calculating the loss function value, the method further includes: According to the loss function value, the trainable parameters in the encoding function are optimized.

5. A chip layout method, characterized in that: The method comprises: Determine a second input of the graph neural network after training; the second input is obtained based on a second netlist corresponding to the chip to be laid out; Obtaining a second output through the graph neural network; Based on the second output, performing encoding to obtain third relative position information; Decoding is performed at least according to the third relative position information to obtain absolute position information of each unit in the chip to be laid out.

6. The method according to claim 5, characterized in that Determine the second input of the graph neural network after training, including: Based on the second netlist, at least a plurality of subgraphs are obtained; in the plurality of subgraphs, nodes represent units or netlines; Based on the second netlist, an input feature is obtained; the input feature includes a cell feature corresponding to each cell in the chip to be laid out; At least the graph structure information corresponding to the multiple sub-graphs and the input features are determined as the second input.

7. The method according to claim 6, characterized in that Based on the second netlist, at least a plurality of subgraphs are obtained, including: Based on the second netlist, a hypergraph is established; wherein, in the hypergraph, nodes represent units and hyperedges represent network lines; Divide the hypergraph into N blocks, and obtain N first subgraphs and 1 first global graph corresponding to the N blocks; wherein the first subgraph is used to represent the connection relationship between different units in a block through network connection; the first global graph is used to represent the connection relationship between different blocks in the N blocks through network connection; N≥2; Expand the N first subgraphs and the 1 first global graph respectively to obtain corresponding N second subgraphs and 1 second global graph; wherein in the second subgraphs and the second global graph, nodes represent units or network cables, and connecting edges represent pins; Determining at least the graph structure information corresponding to the plurality of sub-graphs and the input features as the second input includes: At least the graph structure information corresponding to the plurality of second subgraphs and the one second global graph and the input features are determined as the input.

8. The method according to claim 7, characterized in that After obtaining the corresponding N second sub-images, the method further includes: According to the signal direction information contained in the second netlist, N unit flow graphs corresponding to the N second subgraphs are established; wherein, in the unit flow graphs, nodes represent units, and the connecting edges between nodes are directed edges, which are used to represent network cables, and the directions of the directed edges are determined according to the signal directions; Determining at least the graph structure information corresponding to the plurality of sub-graphs and the input features as the second input includes: At least the graph structure information corresponding to the multiple second subgraphs, the one second global graph, and the multiple N unit flow graphs, and the input features are determined as the input.

9. The method according to claim 8, characterized in that According to the signal direction information included in the netlist, N unit flow graphs corresponding to the N second subgraphs are established, including: In a second subgraph, a cell is considered as the starting node; Searching for a unit connected to the starting node via a network cable as a first-order neighboring node corresponding to the starting node; Generate directed edges between the starting node and each first-order neighboring node according to the signal direction; Searching for a unit connected to the first-order neighboring node via a network cable as a second-order neighboring node corresponding to the starting node; Generate a directed edge between the first-order neighboring node and the second-order neighboring node according to the signal direction; Continue searching for the next-order neighboring nodes until all cells in the same second subgraph are visited, and obtain a cell flow graph.

10. The method according to any one of claims 6 to 9, characterized in that The input features also include network features corresponding to each network in the chip to be laid out; the second output includes output features corresponding to each unit, or the second output also includes output features corresponding to each network; The graph neural network is a graph convolutional neural network, and the graph convolutional neural network includes a convolutional layer; Through the graph neural network, a second output is obtained, including: In the convolution layer, feature transfer between nodes is performed by executing at least one of a first convolution function, a second convolution function, and a third convolution function; The first convolution function is used to transfer the network cable features corresponding to each network cable connected to the i-th unit to the node corresponding to the i-th unit to obtain the i-th first unit sub-feature; i≥1 and is an integer; The second convolution function is used to transfer the unit features of each unit connected to the t-th network line to the node corresponding to the t-th network line to obtain the network line features corresponding to the t-th network line; t≥1 and is an integer; The third convolution function is used to transfer the unit features of each unit connected to the i-th unit to the node corresponding to the i-th unit to obtain the i-th second unit sub-feature; Based on the i-th first unit sub-feature and the i-th second unit sub-feature, an output feature corresponding to the i-th unit is obtained; or, based on the network cable feature corresponding to the t-th network cable, an output feature corresponding to the t-th network cable is obtained.

11. The method according to any one of claims 8 to 10, characterized in that: Based on the second output, encoding is performed to obtain third relative position information, including: An independent variable is determined based on the second output, and an encoding function is executed on the independent variable to obtain third relative position information; wherein the encoding function is used to map the independent variable to the third relative position information.

12. The method according to claim 11, characterized in that The encoding function includes a first encoding function and a second encoding function; the third relative position information is polar coordinate information; Execute the encoding function to obtain the third relative position information, including: Based on the second output, determining a first independent variable, and performing a first encoding function on the first independent variable to obtain a polar diameter; Based on the second output, a second independent variable is determined, and a second encoding function is performed on the second independent variable to obtain a deflection angle; the deflection angle represents the relative value of the polar angle corresponding to different units.

13. The method according to claim 12, characterized in that The output includes unit features corresponding to each unit and network line features corresponding to each network line; Based on the second output, determining a first independent variable includes: Based on the unit features corresponding to the i-th unit and the j-th unit in the second output, and the network line features corresponding to the t-th directed edge, a first independent variable is obtained; wherein the t-th directed edge is a line connecting the i-th unit and the j-th unit in the unit flow graph. Directed edges of cells; Based on the second output, determining a second independent variable includes: Searching for at least one path corresponding to the j-th unit in the unit flow graph, and selecting one of the paths as a first path; the path is a directed path formed by at least one directed edge starting from a start node in the unit flow graph and ending at a node corresponding to the j-th unit; Based on the unit features corresponding to each node passed by the first path in the second output and the network features corresponding to at least one directed edge, a second independent variable is obtained; wherein i, j and t are all integers greater than or equal to 1.

14. The method according to any one of claims 6 to 13, characterized in that Performing decoding at least according to the third relative position information to obtain absolute position information of each unit in the chip to be laid out includes: Determine a starting node in a subgraph and absolute position information of the starting node; Determine the absolute position information of the first-order neighboring node according to the third relative position information of the first-order neighboring node corresponding to the starting node and the absolute position information of the starting node; The absolute position information of the m+1 order neighbor node is determined according to the absolute position information of the m-order neighbor node and the third relative position information of the m+1 order neighbor node; m≥1 and is an integer.

15. The method according to claim 13, characterized in that Performing decoding at least according to the third relative position information to obtain absolute position information of each unit in the chip to be laid out includes: For the j-th unit, searching the unit flow graph for at least one path with the j-th unit as an end node; Obtaining a feasible solution corresponding to a path according to the third relative position information corresponding to a starting node of the at least one path and the third relative position information of each node passed by the path, wherein the at least one path corresponds to at least one feasible solution; Based on the at least one feasible solution, the absolute position information of the j-th unit is obtained.

16. The method according to any one of claims 5 to 15, characterized in that After obtaining the absolute position information of each unit in the chip to be laid out, the method further includes: The absolute position information of each unit is used as an initial solution to calculate an objective function; the objective function uses at least one of line length, density, and anchor point as a constraint condition; the objective function includes at least one hyperparameter of a learning rate, a number of iterations, and a loss function weight; The gradient updates the absolute position information of each unit.

17. An electronic device, characterized in that: The electronic device comprises: One or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the electronic device, cause the electronic device to perform a method as described in any one of claims 1-16.

18. A storage medium, characterized in that: The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method as claimed in any one of claims 1 to 16.

19. A chip system, characterized in that: include: A communication interface for inputting and / or outputting data; A processor, configured to execute a computer executable program so that a device equipped with the chip system executes a method as described in any one of claims 1 to 16.

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