Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of sub-pixels, each sub-pixel comprises a pixel driving circuit, and the pixel driving circuit is separately connected to data signal lines and a compensation signal line. The pixel driving circuit at least comprises a storage capacitor, the storage capacitor at least comprises two stacked capacitor plates, and the two capacitor plates are arranged between the data signal lines and the compensation signal line. For at least one capacitor electrode in at least one sub-pixel, a first distance is reserved between the edge of the side of the capacitor plate close to the compensation signal line and the edge of the side of the compensation signal line close to the capacitor plate, a second distance is reserved between the edge of the side of the capacitor plate close to the data signal line and the edge of the side of the data signal line close to the capacitor plate, and the first distance is smaller than the second distance. The present disclosure can reduce the impact of a data voltage transition on the data signal line on the storage capacitor, and prevent a data voltage transition from affecting normal operation of the pixel driving circuit.

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202311018194.3, filed on August 10, 2023, and entitled "Display substrate, preparation method thereof and display device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0004] SUMMARY

[0005] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0006] In one aspect, the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being connected with a data signal line and a compensation signal line extending along a pixel column direction respectively, the data signal line being configured to provide a data signal to the pixel driving circuit, the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least two capacitor plates stacked, the two capacitor plates being disposed between the data signal line and the compensation signal line; at least one capacitor plate in at least one sub-pixel, an edge of the capacitor plate close to a side of the compensation signal line having a first distance from an edge of the compensation signal line close to the capacitor plate, an edge of the capacitor plate close to a side of the data signal line having a second distance from an edge of the data signal line close to the capacitor plate, the first distance being smaller than the second distance, the first distance and the second distance being a dimension in a pixel row direction.

[0007] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.35 to 0.75.

[0008] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.6 to 0.7.

[0009] In an exemplary embodiment, the first distance is 5.5 μm to 6.5 μm, and the second distance is 8.5 μm to 9.5 μm.

[0010] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.4 to 0.5.

[0011] In an exemplary embodiment, the first distance is 5.5 μm to 6.5 μm, and the second distance is 12.5 μm to 13.5 μm.

[0012] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.65 to 0.75.

[0013] In an exemplary embodiment, the first distance is 8.5 μm to 9.5 μm, and the second distance is 12.5 μm to 13.5 μm.

[0014] In an exemplary embodiment, the two capacitor plates include a first plate and a second plate, the pixel driving circuit further includes a first transistor, a second transistor and a third transistor, a first electrode of the first transistor is connected with the data signal line, a second electrode of the first transistor is connected with the first plate and a gate electrode of the second transistor respectively, a first electrode of the third transistor is connected with the compensation signal line, a second electrode of the third transistor is connected with the second plate and a second electrode of the second transistor respectively, the second plate has a first distance between an edge close to a side of the compensation signal line close to the second plate and an edge close to a side of the data signal line close to the second plate.

[0015] In an exemplary embodiment, the first transistor includes at least a first active layer, the first active layer and the second plate are an integrated structure.

[0016] In an exemplary embodiment, the pixel driving circuit is further connected with a first power supply line extending along the pixel column direction; at least one repeating unit includes one compensation signal line, two first power supply lines and four data signal lines, the compensation signal line is located in the middle of the pixel row direction of the repeating unit, the two first power supply lines are located on both sides of the pixel row direction of the repeating unit, two of the four data signal lines are located on a side of one first power supply line close to the compensation signal line, and the other two of the four data signal lines are located on a side of the other first power supply line close to the compensation signal line.

[0017] In an example embodiment, the two first power lines include a first first power line and a second first power line arranged in sequence along the pixel row direction, and the four data signal lines include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line arranged in sequence along the pixel row direction; the first data signal line is located on a side of the first first power line close to the compensation signal line, the second data signal line is located on a side of the first data signal line close to the compensation signal line, the two capacitor plates are arranged between the second data signal line and the compensation signal line, an edge of the capacitor plate close to the compensation signal line has a first distance from an edge of the compensation signal line close to the capacitor plate, and an edge of the capacitor plate close to the second data signal line has a second distance from an edge of the second data signal line close to the capacitor plate; the fourth data signal line is located on a side of the second first power line close to the compensation signal line, the third data signal line is located on a side of the fourth data signal line close to the compensation signal line, the two capacitor plates are arranged between the third data signal line and the compensation signal line, an edge of the capacitor plate close to the compensation signal line has a first distance from an edge of the compensation signal line close to the capacitor plate, and an edge of the capacitor plate close to the third data signal line has a second distance from an edge of the third data signal line close to the capacitor plate.

[0018] In an example embodiment, the pixel driving circuit is further connected with a first power line extending along the pixel column direction; at least one repeating unit includes two compensation signal lines, two first power lines, and four data signal lines, the four data signal lines are located in the middle of the pixel row direction of the repeating unit, the two compensation signal lines are located on both sides of the pixel row direction of the repeating unit, and the two first power lines are respectively located on a side of the four data signal lines close to the compensation signal line.

[0019] In an exemplary embodiment, the two compensation signal lines include a first compensation signal line and a second compensation signal line arranged in sequence along the pixel row direction, the two first power supply lines include a first first power supply line and a second first power supply line arranged in sequence along the pixel row direction, and the four data signal lines include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line arranged in sequence along the pixel row direction; the first first power supply line is located on a side of the first data signal line close to the first compensation signal line, and the two capacitor plates are arranged between the first compensation signal line and the first first power supply line; the second first power supply line is located on a side of the fourth data signal line close to the second compensation signal line, and the two capacitor plates are arranged between the second compensation signal line and the second first power supply line.

[0020] In another aspect, the present disclosure also provides a display device including the aforementioned display substrate.

[0021] In yet another aspect, the present disclosure also provides a method for manufacturing a display substrate including a plurality of repeating units, at least one repeating unit including a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the method including:

[0022] forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit being connected to a data signal line and a compensation signal line extending along a pixel column direction, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; the pixel driving circuit including at least a storage capacitor, the storage capacitor including at least two capacitor plates stacked, the two capacitor plates being arranged between the data signal line and the compensation signal line; at least one capacitor plate in at least one sub-pixel, an edge of the capacitor plate close to the compensation signal line having a first distance from an edge of the compensation signal line close to the capacitor plate, and an edge of the capacitor plate close to the data signal line having a second distance from an edge of the data signal line close to the capacitor plate, the first distance being smaller than the second distance, and the first distance and the second distance being dimensions in the pixel row direction.

[0023] Other aspects can become apparent after reading the following detailed description and viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0025] FIG. 1 is a structural schematic diagram of a display device;

[0026] FIG. 2 is a planar structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0027] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in a repeat unit according to an exemplary embodiment of the present disclosure;

[0028] FIG. 4 is a structural schematic diagram of a driving circuit layer in a display substrate according to an embodiment of the present disclosure;

[0029] FIG. 5 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0030] FIGS. 6A and 6B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0031] FIGS. 7A, 7B and 7C are schematic diagrams of a display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0032] FIG. 8 is a schematic diagram of a display substrate after forming a second insulating layer pattern according to the present disclosure;

[0033] FIGS. 9A and 9B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0034] FIG. 10 is a schematic diagram of a display substrate after forming a third insulating layer and a planarization layer pattern according to the present disclosure;

[0035] FIGS. 11A and 11B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0036] FIG. 12 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0037] FIG. 13 is a structural schematic diagram of a driving circuit layer in another display substrate according to an embodiment of the present disclosure.

[0038] Reference numerals are explained as follows: 11-first connection electrode; 12-second connection electrode; 13-third connection electrode; 14-fourth connection electrode; 15-fifth connection electrode; 16-sixth connection electrode; 17-seventh connection electrode; 18-eighth connection electrode; 19-ninth connection electrode; 20-tenth connection electrode; 21-first active layer; 22-second active layer; 23-third active layer; 30-scanning signal line; 31-first gate electrode; 32-second gate electrode; 33-third gate electrode; 51-first power supply line; 52-data signal line; 53-compensation signal line; 54-pixel driving circuit; 61-first plate; 62-second plate; 63-first electrode; 100-repeating unit. DETAILED DESCRIPTION

[0039] For the purpose of making the object, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments can be implemented in multiple different forms. One of ordinary skill in the art can easily understand that the manners and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0040] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and interval of each film layer, and the width and interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0041] The ordinal numbers "first", "second", "third", and the like in the present specification are set to avoid confusion of the components, and are not intended to be limited in terms of quantity.

[0042] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0043] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0044] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0045] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other, and "source terminal" and "drain terminal" can be exchanged with each other.

[0046] In this specification, "electrically connected" includes the case where the components are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the connected components. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0047] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where an angle of 85° or more and 95° or less is also included.

[0048] In this specification, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be sometimes interchanged with "conductive film". Similarly, "insulating film" can be sometimes interchanged with "insulating layer".

[0049] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and the like are not strictly so, and can be an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, and deformation, and the like.

[0050] In this specification, "about" means not strictly limited to a boundary, and allows a range of values within a process and measurement error.

[0051] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the OLED display device can include a timing controller, a data driver, a scan driver, and a pixel array, the timing controller is connected to the data driver and the scan driver respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively, and the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively. The pixel array can include a plurality of sub-pixels Pxij, each sub-pixel Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, i and j can be natural numbers. At least one sub-pixel Pxij can include at least a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line and the data signal line respectively, the light emitting unit can include at least a light emitting device, the light emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel Pxij can refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, and can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixels, n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, etc. from the timing controller. For example, the scan driver can sequentially provide the scan signal having a turn-on level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner of sequentially transmitting the scan start signal provided in the form of a turn-on level pulse to the next stage circuit under the control of the clock signal, m can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0052] The exemplary embodiments of the present disclosure provide a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being connected with a data signal line and a compensation signal line extending along a pixel column direction respectively, the data signal line being configured to provide a data signal to the pixel driving circuit, the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least two capacitor plates stacked, the two capacitor plates being disposed between the data signal line and the compensation signal line; at least one capacitor plate in at least one sub-pixel, an edge of the capacitor plate close to a side of the compensation signal line having a first distance from an edge of the compensation signal line close to the capacitor plate, an edge of the capacitor plate close to a side of the data signal line having a second distance from an edge of the data signal line close to the capacitor plate, the first distance being smaller than the second distance, the first distance and the second distance being a dimension in a pixel row direction.

[0053] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.35 to 0.75.

[0054] In an exemplary embodiment, the ratio of the first distance to the second distance is 0.6 to 0.7.

[0055] In another exemplary embodiment, the ratio of the first distance to the second distance is 0.4 to 0.5.

[0056] In yet another exemplary embodiment, the ratio of the first distance to the second distance is 0.65 to 0.75.

[0057] In an exemplary embodiment, the pixel driving circuit is further connected with a first power supply line extending along the second direction; at least one repeating unit comprises one compensation signal line, two first power supply lines and four data signal lines, one compensation signal line being located in the middle of the repeating unit in the first direction, two first power supply lines being located on both sides of the repeating unit in the first direction, two of the four data signal lines being located on one side of one first power supply line close to the compensation signal line, and the other two of the four data signal lines being located on one side of the other first power supply line close to the compensation signal line.

[0058] In an example embodiment, the two first power lines include a first first power line and a second first power line arranged in sequence along the first direction, and the four data signal lines include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line arranged in sequence along the first direction; the first data signal line is located on a side of the first first power line close to the compensation signal line, the second data signal line is located on a side of the first data signal line close to the compensation signal line, the two capacitor plates are arranged between the second data signal line and the compensation signal line, an edge of the capacitor plate close to the compensation signal line has a first distance from an edge of the compensation signal line close to the capacitor plate, and an edge of the capacitor plate close to the second data signal line has a second distance from an edge of the second data signal line close to the capacitor plate; the fourth data signal line is located on a side of the second first power line close to the compensation signal line, the third data signal line is located on a side of the fourth data signal line close to the compensation signal line, the two capacitor plates are arranged between the third data signal line and the compensation signal line, an edge of the capacitor plate close to the compensation signal line has the first distance from an edge of the compensation signal line close to the capacitor plate, and an edge of the capacitor plate close to the third data signal line has the second distance from an edge of the third data signal line close to the capacitor plate.

[0059] In an example embodiment, the pixel driving circuit is further connected with a first power line extending along the second direction; and at least one repeating unit includes two compensation signal lines, two first power lines, and four data signal lines, the four data signal lines are located in the middle of the first direction of the repeating unit, the two compensation signal lines are located on both sides of the first direction of the repeating unit, and the two first power lines are respectively located on a side of the four data signal lines close to the compensation signal line.

[0060] In an example embodiment, the two compensation signal lines include a first compensation signal line and a second compensation signal line arranged in sequence along the first direction, the two first power supply lines include a first first power supply line and a second first power supply line arranged in sequence along the first direction, and the four data signal lines include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line arranged in sequence along the first direction; the first first power supply line is located on a side of the first data signal line close to the first compensation signal line, and the two capacitor plates are arranged between the first compensation signal line and the first first power supply line; the second first power supply line is located on a side of the fourth data signal line close to the second compensation signal line, and the two capacitor plates are arranged between the second compensation signal line and the second first power supply line.

[0061] The display substrate of the present disclosure is illustrated below through some example embodiments.

[0062] FIG. 2 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure. As shown in FIG. 2, in an example embodiment, in a direction parallel to the display substrate, the display substrate can include a plurality of repeating units 100, and at least one repeating unit 100 can include a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns. In an example embodiment, a repeating unit is a basic unit constituting the display substrate, and the display substrate is formed by repeating and continuously arranging the repeating units in at least one direction, i.e., the display substrate is formed by splicing a plurality of repeating units.

[0063] In an example embodiment, one repeating unit 100 can include four sub-pixels, and the four sub-pixels can include a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, a third sub-pixel P3 emitting third color light, and a fourth sub-pixel P4 emitting fourth color light. The four sub-pixels can be arranged in a square manner, which can effectively increase the aperture ratio and the light transmission area.

[0064] In an example embodiment, in at least one repeating unit 100, the second sub-pixel P2 can be arranged on one side of the first sub-pixel P1 in a first direction X, the third sub-pixel P3 can be arranged on one side of the first sub-pixel P1 in a second direction Y, and the fourth sub-pixel P4 can be arranged on one side of the third sub-pixel P3 in the first direction X. A plurality of sub-pixels arranged in sequence along the first direction X can be referred to as a pixel row, a plurality of sub-pixels arranged in sequence along the second direction Y can be referred to as a pixel column, the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array, and the first direction X and the second direction Y intersect.

[0065] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 can be a white sub-pixel (W) emitting white light, and the fourth sub-pixel P4 can be a green sub-pixel (G) emitting green light. In some possible embodiments, the arrangement of RBWG can be adjusted according to actual needs, which is not specifically limited in the present disclosure.

[0066] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate can include at least a driving circuit layer disposed on a base, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. In at least one repeating unit, the driving circuit layer can include a plurality of circuit units, and each circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line and a data signal line, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to a light-emitting device. The light-emitting structure layer can include a plurality of light-emitting units, and each light-emitting unit can include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit of the sub-pixel where the light-emitting device is located, and is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0067] In another example embodiment, in a direction perpendicular to the display substrate, the display substrate can include at least a driving circuit layer disposed on a base, a color film structure layer disposed on a side of the driving circuit layer away from the base, and a light-emitting structure layer disposed on a side of the color film structure layer away from the base. In at least one repeating unit, the color film structure layer can include a plurality of color film units, and each color film unit can include at least a color filter layer. The color filter layer is configured to make the corresponding sub-pixel emit light with a required color.

[0068] In an example embodiment, the circuit unit in the present disclosure refers to an area divided according to the pixel driving circuit. The color film unit in the present disclosure refers to an area divided according to the color filter layer. The light-emitting unit in the present disclosure refers to an area divided according to the light-emitting device. The positions of the orthographic projection of the circuit unit on the base, the orthographic projection of the color filter layer on the base, and the orthographic projection of the light-emitting unit on the base can be corresponding or non-corresponding.

[0069] In an example embodiment of the present disclosure, the positions of the orthographic projection of the circuit unit on the base, the orthographic projection of the color filter layer on the base, and the orthographic projection of the light-emitting unit on the base are one-to-one corresponding. The circuit unit, the color film unit, and the light-emitting unit constitute a sub-pixel. Therefore, in the following content, the sub-pixel is used to refer to the circuit unit, the color film unit, and the light-emitting unit.

[0070] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in one repeat unit according to an exemplary embodiment of the present disclosure. As shown in FIG. 3, at least one repeat unit can include four pixel driving circuits, and the four pixel driving circuits can be arranged in a square manner. The pixel driving circuit can be a 3T1C structure.

[0071] In an exemplary embodiment, at least one pixel driving circuit can include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to a scan signal line 30, a first power supply line 51, a data signal line 52, and a compensation signal line 53, respectively.

[0072] In an exemplary embodiment, each pixel driving circuit can include a first node N1 and a second node N2. The first node N1 is connected to a second electrode of the first transistor T1, a gate electrode of the second transistor T2, and a first terminal of the storage capacitor C, respectively. The second node N2 is connected to a second electrode of the second transistor T2, a second electrode of the third transistor T3, and a second terminal of the storage capacitor C, respectively.

[0073] In an exemplary embodiment, the first terminal of the storage capacitor C is connected to the first node N1, and the second terminal of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store a potential of the gate electrode of the second transistor T2.

[0074] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0075] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 30, a first electrode of the first transistor T1 is connected to the data signal line 52, and a second electrode of the first transistor T1 is connected to the first node N1. When a conduction signal is applied to the scan signal line 30, the first transistor T1 inputs a data signal of the data signal line 52 to the gate electrode of the second transistor T2.

[0076] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power supply line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0077] In an example embodiment, the gate electrode of the third transistor T3 is connected with the scan signal line 30, the first electrode of the third transistor T3 is connected with the compensation signal line 53, and the second electrode of the third transistor T3 is connected with the second node N2. When a driving signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth.

[0078] In an example embodiment, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the pixel driving circuit of the at least one sub-pixel are connected with the same scan signal line 30.

[0079] In an example embodiment, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 in the plurality of pixel driving circuits of the at least one pixel row are connected with the same scan signal line 30.

[0080] In an example embodiment, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 in the plurality of pixel driving circuits of the at least one repeating unit are connected with the same scan signal line 30.

[0081] In an example embodiment, the light emitting device EL can be an OLED including a first electrode, an organic light emitting layer and a second electrode stacked, or can be a QLED including a first electrode, a quantum dot light emitting layer and a second electrode stacked. The first electrode of the light emitting device EL is connected with the second node N2, and the second electrode of the light emitting device EL is connected with the second power supply line VSS. The light emitting device EL emits light of a corresponding brightness in response to the current of the second electrode of the second transistor T2. In an example embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0082] In an example embodiment, the signal of the first power supply line 51 is a high level signal continuously provided, and the signal of the second power supply line VSS is a low level signal continuously provided.

[0083] In an example embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the third transistor T3 can include P-type transistors and N-type transistors.

[0084] In the example embodiment, the first transistor T1 to the third transistor T3 can adopt a low temperature poly-silicon thin film transistor, or can adopt an oxide thin film transistor, or can adopt a low temperature poly-silicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate, i.e., an LTPS+Oxide (LTPO for short) display substrate, can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0085] FIG. 4 is a structural schematic diagram of a driving circuit layer in a display substrate according to an example embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in one repeat unit (four sub-pixels) of a bottom emission display substrate. In the example embodiment, at least one repeat unit can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged in a square manner, each of which includes a pixel driving circuit.

[0086] In the example embodiment, at least one repeat unit can include one scan signal line 30, two first power supply lines 51, four data signal lines 52, and one compensation signal line 53, which are respectively connected to the pixel driving circuits in the corresponding sub-pixels. The scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power supply line 51 is configured to provide a power supply signal to the pixel driving circuit, the data signal line 52 is configured to provide a data signal to the pixel driving circuit, and the compensation signal line 53 is configured to provide a compensation signal to the pixel driving circuit.

[0087] In the example embodiment, the scan signal line 30 can be in a linear shape with a main body extending along the first direction X (pixel row direction), the first power supply line 51, the data signal line 52, and the compensation signal line 53 can be in a linear shape with a main body extending along the second direction Y (pixel column direction), and the first direction X and the second direction Y can be perpendicular to each other. In the example embodiment, the scan signal line 30 can be disposed in the middle of the second direction Y of the repeating unit, one compensation signal line 53 can be disposed in the middle of the first direction X of the repeating unit, two first power supply lines 51 can be disposed on both sides of the first direction X of the repeating unit, four data signal lines 52 and the compensation signal line 53 can be disposed between the two first power supply lines 51, two of the four data signal lines 52 can be disposed on the side of one of the first power supply lines 51 close to the compensation signal line 53, and the other two of the four data signal lines 52 can be disposed on the side of the other of the first power supply lines 51 close to the compensation signal line 53. In this way, one scan signal line 30 extending along the first direction X can define two pixel rows, one compensation signal line 53 extending along the second direction Y can define two pixel columns, and the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 of one repeating unit can be formed.

[0088] In the example embodiment, in at least one repeating unit, the first sub-pixel P1 and the third sub-pixel P3 can be mirror-symmetrical with respect to the scan signal line 30, the second sub-pixel P2 and the fourth sub-pixel P4 can be mirror-symmetrical with respect to the scan signal line 30, the first sub-pixel P1 and the second sub-pixel P2 can be mirror-symmetrical with respect to the compensation signal line 53, and the third sub-pixel P3 and the fourth sub-pixel P4 can be mirror-symmetrical with respect to the compensation signal line 53.

[0089] In the example embodiment, the pixel driving circuit of at least one sub-pixel can include a first transistor, a second transistor, a third transistor, and a storage capacitor, each transistor can include an active layer, a gate electrode, a first electrode, and a second electrode, and the storage capacitor can include a first plate 61 and a second plate 62 as capacitor plates. In the example embodiment, the first electrode of the first transistor is connected to the data signal line 52, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the second plate 62 of the storage capacitor, respectively, the first electrode of the second transistor is connected to the first power supply line, the first electrode of the third transistor is connected to the compensation signal line 53, and the second electrode of the third transistor is connected to the second electrode of the second transistor and the first plate 61 of the storage capacitor, respectively.

[0090] In the example embodiment, in at least one sub-pixel, the first plate 61 and the second plate 62 can be disposed between the data signal line 52 and the compensation signal line 53.

[0091] In an exemplary embodiment, the two first power supply lines 51 in the at least one repeating unit can include a first first power supply line 51-1 and a second first power supply line 51-2 arranged in sequence along the first direction X, the first first power supply line 51-1 can be arranged on the side opposite to the first direction X of the repeating unit, and the second first power supply line 51-2 can be arranged on the side of the first direction X of the repeating unit. The four data signal lines 52 in the at least one repeating unit can include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3, and a fourth data signal line 52-4 arranged in sequence along the first direction X, the first data signal line 52-1 and the second data signal line 52-2 can be arranged between the first first power supply line 51-1 and the compensation signal line 53, and the third data signal line 52-3 and the fourth data signal line 52-4 can be arranged between the second first power supply line 51-2 and the compensation signal line 53.

[0092] In an exemplary embodiment, the first data signal line 52-1 can be located on the side of the first first power supply line 51-1 close to the compensation signal line 53, the second data signal line 52-2 is located on the side of the first data signal line 52-1 close to the compensation signal line 53, and the first plate 61 and the second plate 62 can be arranged between the second data signal line 52-2 and the compensation signal line 53. The fourth data signal line 52-4 can be located on the side of the second first power supply line 51-2 close to the compensation signal line 53, and the third data signal line 52-3 can be located on the side of the fourth data signal line 52-4 close to the compensation signal line 53, and the first plate 61 and the second plate 62 can be arranged between the third data signal line 52-3 and the compensation signal line 53.

[0093] In an exemplary embodiment, in the at least one sub-pixel, for at least one of the first plate 61 and the second plate 62, a first distance L1 between an edge of the at least one of the first plate 61 and the second plate 62 close to the compensation signal line 53 and an edge of the compensation signal line 53 close to the at least one of the first plate 61 and the second plate 62, and a second distance L2 between an edge of the at least one of the first plate 61 and the second plate 62 close to the data signal line 52 and an edge of the data signal line 52 close to the at least one of the first plate 61 and the second plate 62, the first distance L1 can be less than the second distance L2, and the first distance L1 and the second distance L2 can be dimensions of the first direction X.

[0094] In an exemplary embodiment, in the at least one sub-pixel, a ratio of the first distance L1 to the second distance L2 can be 0.35 to 0.75.

[0095] As shown in FIG. 4, for the second plate 62 in the first sub-pixel P1, the second plate 62 has a first distance L1 between the edge close to the compensation signal line 53 and the edge close to the second plate 62 of the compensation signal line 53, and has a second distance L2 between the edge close to the second data signal line 52-2 and the edge close to the second plate 62 of the second data signal line 52-2, and the ratio of the first distance L1 to the second distance L2 can be 0.6 to 0.7.

[0096] In an exemplary embodiment, the first distance L1 in the first sub-pixel P1 can be about 5.5 μm to 6.5 μm, and the second distance L2 can be about 8.5 μm to 9.5 μm. For example, the first distance L1 can be about 6 μm or so, and the second distance L2 can be about 9 μm or so.

[0097] As shown in FIG. 4, for the second plate 62 in the second sub-pixel P2, the second plate 62 has a first distance L1 between the edge close to the compensation signal line 53 and the edge close to the second plate 62 of the compensation signal line 53, and has a second distance L2 between the edge close to the third data signal line 52-3 and the edge close to the second plate 62 of the third data signal line 52-3, and the ratio of the first distance L1 to the second distance L2 can be 0.4 to 0.5.

[0098] In an exemplary embodiment, the first distance L1 in the second sub-pixel P2 can be about 5.5 μm to 6.5 μm, and the second distance L2 can be about 12.5 μm to 13.5 μm. For example, the first distance L1 can be about 6 μm or so, and the second distance L2 can be about 13 μm or so.

[0099] As shown in FIG. 4, for the second plate 62 in the third sub-pixel P3, the second plate 62 has a first distance L1 between the edge close to the compensation signal line 53 and the edge close to the second plate 62 of the compensation signal line 53, and has a second distance L2 between the edge close to the second data signal line 52-2 and the edge close to the second plate 62 of the second data signal line 52-2, and the ratio of the first distance L1 to the second distance L2 can be 0.65 to 0.75.

[0100] In an exemplary embodiment, the first distance L1 in the third sub-pixel P3 can be about 8.5 μm to 9.5, and the second distance L2 can be about 12.5 μm to 13.5 μm. For example, the first distance L1 can be about 9 μm or so, and the second distance L2 can be about 13 μm or so.

[0101] In an exemplary embodiment, the first transistor of each sub-pixel can at least include a first active layer 21, and the first active layer 21 and the second plate 62 can be an integrated structure connected to each other.

[0102] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material made on a substrate by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0103] In an exemplary embodiment, taking four sub-pixels (the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4) of one repeating unit as an example, the preparation process of the display substrate can include the following operations.

[0104] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern includes: depositing a first conductive thin film on a substrate, patterning the first conductive thin film by a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG. 5.

[0105] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate can at least include a first connection electrode 11, a second connection electrode 12 and a first plate 61 of a storage capacitor.

[0106] In an exemplary embodiment, the first plate 61 can be rectangular in shape, and the corners of the rectangular shape can be chamfered. The first plate 61 can serve as one transparent plate of a transparent storage capacitor, and the first plate 61 can be configured to form the transparent storage capacitor with a second plate formed later.

[0107] In an exemplary embodiment, the first connection electrode 11 and the second connection electrode 12 can be located on both sides of the first plate 61 in the second direction Y, respectively.

[0108] In an exemplary embodiment, in the first sub-pixel P1 and the second sub-pixel P2, the first connection electrode 11 can be disposed on the side opposite to the second direction Y of the first plate 61, and the second connection electrode 12 can be disposed on the side of the second direction Y of the first plate 61. In the third sub-pixel P3 and the fourth sub-pixel P4, the first connection electrode 11 can be disposed on the side of the second direction Y of the first plate 61, and the second connection electrode 12 can be disposed on the side opposite to the second direction Y of the first plate 61.

[0109] In an exemplary embodiment, the first connection electrode 11 can be in a bar shape in which a main body portion extends in the second direction Y, a first end of the first connection electrode 11 can be connected to the first plate 61, and a second end of the first connection electrode 11 can extend in a direction away from the second connection electrode 12. The first connection electrode 11 can be configured to be connected to a third connection electrode formed later.

[0110] In an exemplary embodiment, the second connection electrode 12 can be in a bar shape in which a main body portion extends in the second direction Y, a first end of the second connection electrode 12 can be connected to the first plate 61, and a second end of the second connection electrode 12 can extend in a direction away from the first connection electrode 11. The second connection electrode 12 can be configured to be connected to a fourth connection electrode formed later.

[0111] In an exemplary embodiment, in the first pixel column, an edge of the first connection electrode 11 near the side of the second pixel column can be substantially flush with an edge of the first plate 61 near the side of the second pixel column. In the second pixel column, an edge of the first connection electrode 11 near the side of the first pixel column can be substantially flush with an edge of the first plate 61 near the side of the first pixel column.

[0112] In an exemplary embodiment, the first connection electrode 11, the second connection electrode 12, and the first plate 61 of each sub-pixel can be an integrated structure connected to each other.

[0113] In an exemplary embodiment, the positions of each pattern in the first conductive layer in the first sub-pixel P1 and the positions of each pattern in the first conductive layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of each pattern in the first conductive layer in the second sub-pixel P2 and the positions of each pattern in the first conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the horizontal reference line, the positions of each pattern in the first conductive layer in the first sub-pixel P1 and the positions of each pattern in the first conductive layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to a vertical reference line, and the positions of each pattern in the first conductive layer in the third sub-pixel P3 and the positions of each pattern in the first conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the vertical reference line. The horizontal reference line can be a straight line extending along the first direction X and bisecting the repeating unit in the second direction Y, and the vertical reference line can be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0114] In an exemplary embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO, etc.

[0115] (2) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: depositing a second conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the second conductive thin film by a patterning process to form a second conductive layer, as shown in FIGS. 6A and 6B, FIG. 6B is a schematic view of the second conductive layer in FIG. 6A. In an exemplary embodiment, the second conductive layer can be referred to as a SHIELD layer.

[0116] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate can include at least a third connection electrode 13 and a fourth connection electrode 14.

[0117] In an exemplary embodiment, the third connection electrode 13 can have a block shape (such as a rectangular shape), can be located on the side of the first plate 61 away from the second connection electrode 12, the orthographic projection of the third connection electrode 13 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 11 on the substrate, and the third connection electrode 13 directly overlaps the first connection electrode 11. In an exemplary embodiment, the third connection electrode 13 is configured to connect with the fifth connection electrode formed subsequently, and is configured to shield light from the second transistor, reduce the light intensity incident on the second transistor, reduce the leakage current of the second transistor, and thus reduce the influence of light on the characteristics of the second transistor.

[0118] In the example embodiment, the fourth connection electrode 14 can have a block shape (e.g., a rectangular shape), can be located on the side of the first electrode plate 61 away from the first connection electrode 11, the orthographic projection of the fourth connection electrode 14 on the substrate at least partially overlaps the orthographic projection of the second connection electrode 12 on the substrate, and the fourth connection electrode 14 directly overlaps the second connection electrode 12, and the fourth connection electrode 14 is configured to be connected to the sixth connection electrode to be formed later.

[0119] In the example embodiment, the second conductive layer of each repeating unit in the display substrate can include at least two first power lines 51, four data signal lines 52, and one compensation signal line 53.

[0120] In the example embodiment, the first power line 51, the data signal line 52, and the compensation signal line 53 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, the compensation signal line 53 can be located at the middle of the first direction X of the repeating unit, the first first power line 51 can be located on the side of the first direction X of the repeating unit in the opposite direction, the second first power line 51 can be located on the side of the first direction X of the repeating unit, two of the four data signal lines 52 can be located between the first first power line 51 and the compensation signal line 53, and the other two of the four data signal lines 52 can be located between the second first power line 51 and the compensation signal line 53.

[0121] In the example embodiment, the first first power line 51 and the compensation signal line 53 can define a first pixel column, and two of the data signal lines 52 are arranged in the first pixel column. The second first power line 51 and the compensation signal line 53 can define a second pixel column, and two of the data signal lines 52 are arranged in the second pixel column.

[0122] In the example embodiment, the positions of the two first power lines 51 can be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the two data signal lines 52 on the side of the first direction X of the compensation signal line 53 and the positions of the two data signal lines 52 on the side of the first direction X of the compensation signal line 53 can be substantially mirror-symmetrical with respect to a vertical reference line. The positions of the third connection electrode 13 and the fourth connection electrode 14 in the first sub-pixel P1 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the third sub-pixel P3 can be substantially mirror-symmetrical with respect to a horizontal reference line, and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the second sub-pixel P2 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to a horizontal reference line.

[0123] In the example embodiment, the first power line 51, the data signal line 52 and the compensation signal line 53 can be non-equal-width meandering lines, and the use of the variable-width meandering lines can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance.

[0124] (3) Forming a semiconductor layer pattern. In the example embodiment, forming the semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor thin film through a patterning process, forming a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIGS. 7A and 7B, FIG. 7B being a schematic view of the semiconductor layer in FIG. 7A.

[0125] In the example embodiment, the semiconductor layer of each sub-pixel in the display substrate can at least include a first active layer 21, a second active layer 22, a third active layer 23 and a second plate 62 of a storage capacitor, the first active layer 21 can serve as an active layer of the first transistor T1, the second active layer 22 can serve as an active layer of the second transistor T2, the third active layer 23 can serve as an active layer of the third transistor T3, and the second plate 62 can serve as another transparent plate of the transparent storage capacitor, and the second plate 62 is configured to form the transparent storage capacitor with the first plate 61.

[0126] In the example embodiment, for the first sub-pixel P1 and the second sub-pixel P2, the first active layer 21 and the third active layer 23 can be disposed on one side of the first sub-pixel in the second direction Y of the first plate 61, and the second active layer 22 can be disposed on the side of the first sub-pixel opposite to the second direction Y of the first plate 61.

[0127] In the example embodiment, for the first sub-pixel P1, the first active layer 21 can be disposed on the side of the first sub-pixel away from the second sub-pixel P2, and the third active layer 23 can be disposed on the side of the first sub-pixel close to the second sub-pixel P2. For the second sub-pixel P2, the first active layer 21 can be disposed on the side of the second sub-pixel away from the first sub-pixel P1, and the third active layer 23 can be disposed on the side of the second sub-pixel close to the first sub-pixel P1.

[0128] In the example embodiment, for the third sub-pixel P3 and the fourth sub-pixel P4, the first active layer 21 and the third active layer 23 can be disposed on the side of the third sub-pixel opposite to the second direction Y of the first plate 61, and the second active layer 22 can be disposed on the side of the third sub-pixel in the second direction Y of the first plate 61.

[0129] In the exemplary embodiments, for the third sub-pixel P3, the first active layer 21 can be disposed on the side of the sub-pixel away from the fourth sub-pixel P4, and the third active layer 23 can be disposed on the side of the sub-pixel close to the fourth sub-pixel P4. For the fourth sub-pixel P4, the first active layer 21 can be disposed on the side of the sub-pixel away from the third sub-pixel P3, and the third active layer 23 can be disposed on the side of the sub-pixel close to the third sub-pixel P3.

[0130] In the exemplary embodiments, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region.

[0131] In the exemplary embodiments, the first region of the first active layer 21 of each sub-pixel has a projection on the substrate that at least partially overlaps with a projection of the corresponding data signal line 52 on the substrate, and the second region of the first active layer 21 is connected to the second plate 62.

[0132] In the exemplary embodiments, the first region of the second active layer 22 of each sub-pixel has a projection on the substrate that does not overlap with a projection of the third connection electrode 13 of the sub-pixel on the substrate, and the second region and the channel region of the second active layer 22 have projections on the substrate that at least partially overlap with a projection of the third connection electrode 13 on the substrate, so that the third connection electrode 13 as a shielding layer can shield the channel region of the second transistor T2, avoid the influence of light on the channel, and ensure the electrical performance of the second transistor T2.

[0133] In the exemplary embodiments, the first region of the third active layer 23 of each sub-pixel has a projection on the substrate that at least partially overlaps with a projection of the compensation signal line 53 on the substrate, and the second region of the third active layer 23 has a projection on the substrate that at least partially overlaps with a projection of the fourth connection electrode 14 of the sub-pixel on the substrate.

[0134] In the exemplary embodiments, the first region of the third active layer 23 in the first sub-pixel P1 and the first region of the third active layer 23 in the second sub-pixel P2 can be connected to each other, and the first region of the third active layer 23 in the third sub-pixel P3 and the first region of the third active layer 23 in the fourth sub-pixel P4 can be connected to each other.

[0135] In the example embodiment, the third active layer 23 in the first sub-pixel P1 and the third active layer 23 in the second sub-pixel P2 can be an integrated structure connected to each other, and the third active layer 23 in the third sub-pixel P3 and the third active layer 23 in the fourth sub-pixel P4 can be an integrated structure connected to each other. By arranging the first region of the third active layer shared by the third transistors of the two adjacent sub-pixels in one pixel row, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the resolution can be improved, the via connection structure can be reduced, and the manufacturing process can be simplified.

[0136] In the example embodiment, the second plate 62 can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The second plate 62 can be arranged between the second active layer 22 and the third active layer 23 in the sub-pixel. The orthographic projection of the second plate 62 on the substrate at least partially overlaps the orthographic projection of the first plate 61 on the substrate. The second plate 62 can serve as a transparent intermediate plate of a transparent storage capacitor, and the first plate 61 and the second plate 62 form the transparent storage capacitor.

[0137] In the example embodiment, the second plate 62 and the first active layer 21 of each sub-pixel can be an integrated structure connected to each other.

[0138] In the example embodiment, in each sub-pixel, the area of the overlapping region in the orthographic projection of the first plate 61 on the substrate and the orthographic projection of the second plate 62 on the substrate can be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0139] In the example embodiment, the semiconductor layer can be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0140] In the example embodiment, the positions of the various patterns in the semiconductor layer in the first sub-pixel P1 and the positions of the various patterns in the semiconductor layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the various patterns in the semiconductor layer in the second sub-pixel P2 and the positions of the various patterns in the semiconductor layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the various patterns in the semiconductor layer in the first sub-pixel P1 and the positions of the various patterns in the semiconductor layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to a vertical reference line, and the positions of the various patterns in the semiconductor layer in the third sub-pixel P3 and the positions of the various patterns in the semiconductor layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a vertical reference line.

[0141] FIG. 7C is a schematic diagram of storing capacitance positions in an exemplary embodiment of the present disclosure. As shown in FIG. 7C, in at least one of the first and second plates 61 and 62 of each sub-pixel, a first distance L1 is between an edge of the capacitance plate close to the compensation signal line 53 and an edge of the compensation signal line 53 close to the capacitance plate, and a second distance L2 is between an edge of the capacitance plate close to the data signal line 52 and an edge of the data signal line 52 close to the capacitance plate, the first and second distances L1 and L2 being dimensions in the first direction X. In at least one sub-pixel, the first distance L1 can be less than the second distance L2.

[0142] In an exemplary implementation, the second plate 62 is taken as an example. A first distance L1 is between an edge of the second plate 62 close to the compensation signal line 53 and an edge of the compensation signal line 53 close to the second plate 62, and a second distance L2 is between an edge of the second plate 62 close to the data signal line 52 and an edge of the data signal line 52 close to the second plate 62.

[0143] In an exemplary implementation, in at least one sub-pixel, L1 / L2 = 0.35-0.75.

[0144] In an exemplary implementation, in the first sub-pixel P1, L1 / L2 = 0.6-0.7. For example, L1 / L2 = 0.67.

[0145] In an exemplary implementation, in the first sub-pixel P1, L1 = 5.5-6.5 μm, and L2 = 8.5-9.5 μm. For example, L1 = 6 μm, and L2 = 9 μm.

[0146] In an exemplary implementation, in the second sub-pixel P2, L1 / L2 = 0.4-0.5. For example, L1 / L2 = 0.46.

[0147] In an exemplary implementation, in the second sub-pixel P2, L1 = 5.5-6.5 μm, and L2 = 12.5-13.5 μm. For example, L1 = 6 μm, and L2 = 13 μm.

[0148] In an exemplary implementation, in the third sub-pixel P3, L1 / L2 = 0.65-0.75. For example, L1 / L2 = 0.7.

[0149] In an exemplary implementation, in the third sub-pixel P3, L1 = 8.5-9.5 μm, and L2 = 12.5-13.5 μm. For example, L1 = 9 μm, and L2 = 13 μm.

[0150] In an exemplary implementation, the first and second distances L1 and L2 can be minimum distances, or can be average distances, which are not limited in the present disclosure.

[0151] In the example embodiment, the first distance L1 can be the distance between the first plate 61 and the compensation signal line 53, and the second distance L2 can be the distance between the first plate 61 and the data signal line 52.

[0152] (4) Forming a second insulating layer pattern. In the example embodiment, forming the second insulating layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a second insulating thin film, patterning the second insulating thin film through a patterning process, forming a second insulating layer pattern covering the semiconductor layer, and the second insulating layer being provided with a plurality of vias, as shown in FIG. 8.

[0153] In the example embodiment, the plurality of vias of each sub-pixel in the display substrate at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0154] In the example embodiment, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first region of the first active layer 21 and the data signal line 52 on the substrate. The first via V1 is a via of the switching structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away, exposing the surface of the first region of the first active layer 21, and the first insulating layer and the second insulating layer in the deep half-hole are etched away, exposing the surface of the data signal line 52, so that the via of the switching structure composed of the two half-holes simultaneously exposes the first region of the first active layer 21 and the data signal line 52, and the first via V1 is configured to allow the seventh connection electrode formed subsequently to pass through the via and simultaneously connect with the first region of the first active layer 21 and the data signal line 52.

[0155] In the example embodiment, the orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the first region of the second active layer 22 on the substrate, and the second insulating layer in the second via V2 is etched away, exposing the surface of the first region of the second active layer 22, and the second via V2 is configured to allow the eighth connection electrode formed subsequently to pass through the via and connect with the first region of the second active layer 22.

[0156] In the example embodiment, the third via V3 has a projection on the substrate within the range of the second region of the second active layer 22 and the projection on the substrate of the third connection electrode 13. The third via V3 is a via of a transfer structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away to expose the surface of the second region of the second active layer 22, and the first insulating layer and the second insulating layer in the deep half-hole are etched away to expose the surface of the third connection electrode 13, so that the via of the transfer structure composed of the two half-holes simultaneously exposes the second region of the second active layer 22 and the third connection electrode 13, and the third via V3 is configured to enable the fifth connection electrode formed subsequently to connect with the second region of the second active layer 22 and the third connection electrode 13 through the via.

[0157] In the example embodiment, the fourth via V4 has a projection on the substrate within the range of the first region of the third active layer 23 and the projection on the substrate of the compensation signal line 53. The fourth via V4 is a via of a transfer structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the third active layer 23, and the first insulating layer and the second insulating layer in the deep half-hole are etched away to expose the surface of the compensation signal line 53, so that the via of the transfer structure composed of the two half-holes simultaneously exposes the first region of the third active layer 23 and the compensation signal line 53, and the fourth via V4 is configured to enable the ninth connection electrode formed subsequently to connect with the first region of the third active layer 23 and the compensation signal line 53 through the via.

[0158] In the example embodiment, since the first regions of the third active layers in the first sub-pixel P1 and the second sub-pixel P2 are connected with each other, and the first regions of the third active layers in the third sub-pixel P3 and the fourth sub-pixel P4 are connected with each other, the first sub-pixel P1 and the second sub-pixel P2 share one fourth via V4, and the third sub-pixel P3 and the fourth sub-pixel P4 share one fourth via V4. By setting the adjacent sub-pixels to share one fourth via V4, the number of vias can be effectively reduced, the occupied area of the pixel driving circuit can be reduced, the resolution can be improved, the via connection structure can be reduced, and the manufacturing process can be simplified.

[0159] In the exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is within the range of the orthographic projection of the second region of the third active layer 23 and the fourth connection electrode 14 on the substrate. The fifth via V5 is a via of the transfer structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the third active layer 23, the first insulating layer and the second insulating layer in the deep half-hole are etched away, exposing the surface of the fourth connection electrode 14, so that the two half-holes of the via of the transfer structure simultaneously expose the second region of the third active layer 23 and the fourth connection electrode 14, and the fifth via V5 is configured to allow the sixth connection electrode formed subsequently to pass through the via and be connected to the second region of the third active layer 23 and the fourth connection electrode 14.

[0160] In the exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is within the range of the orthographic projection of the second plate 62 on the substrate, and the second insulating layer in the sixth via V6 is etched away, exposing the surface of the second plate 62, and the sixth via V6 is configured to allow the second gate electrode formed subsequently to pass through the via and be connected to the second plate 62.

[0161] In the exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the first power line 51 on the substrate, and the first insulating layer and the second insulating layer in the seventh via V7 are etched away, exposing the surface of the first power line 51, and the seventh via V7 is configured to allow the eighth connection electrode formed subsequently to pass through the via and be connected to the first power line 51.

[0162] In the exemplary embodiment, in the process of forming the second insulating layer pattern, a dry etching process is used to form a plurality of vias, and at the same time, a first conductorization treatment is performed on the semiconductor layer exposed in the vias, so that the semiconductor layer exposed in the vias forms a first conductorization region. In the first conductorization treatment, the edge portion of the semiconductor layer covered by the second insulating layer near the via is also conductorized, i.e., the first conductorized semiconductor layer extends away from the via.

[0163] (5) Forming a third conductive layer pattern. In the exemplary embodiment, forming the third conductive layer pattern can include: depositing a third conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern on the second insulating layer, as shown in FIGS. 9A and 9B, FIG. 9B is a schematic diagram of the third conductive layer in FIG. 9A. In the exemplary embodiment, the third conductive layer can be referred to as a gate metal (GT) layer.

[0164] In the exemplary embodiment, the third conductive layer of each sub-pixel in the display substrate can at least include the fifth connection electrode 15, the sixth connection electrode 16, the seventh connection electrode 17, the eighth connection electrode 18, the ninth connection electrode 19, the scan signal line 30, the first gate electrode 31, the second gate electrode 32, and the third gate electrode 33.

[0165] In the exemplary embodiment, the shape of the scan signal line 30 can be a linear shape with a main body portion extending along the first direction X, and the scan signal line 30 can be arranged at the middle of the second direction Y of the repeating unit, i.e., between the first sub-pixel P1 and the second sub-pixel P2 and between the third sub-pixel P3 and the fourth sub-pixel P4, and the scan signal line 30 is configured to simultaneously control the turn-on or turn-off of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0166] In the exemplary embodiment, the orthogonal projection of the scan signal line 30 on the substrate does not overlap with the orthogonal projection of the first active layer 21 and the third active layer 23 on the substrate.

[0167] In the exemplary embodiment, the shape of the first gate electrode 31 can be a strip shape extending along the second direction Y, the first gate electrode 31 can be arranged on the side of the scan signal line 30 close to the first active layer 21, the first end of the first gate electrode 31 is connected with the scan signal line 30, the second end of the first gate electrode 31 extends toward the first active layer 21, and the orthogonal projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthogonal projection of the first active layer 21 on the substrate. In the exemplary embodiment, the first gate electrode 31 can serve as the gate electrode of the first transistor T1, so that the scan signal line 30 can control the turn-on or turn-off of the first transistor T1.

[0168] In the exemplary embodiment, the shape of the second gate electrode 32 can be a strip shape extending along the second direction Y, the first end of the second gate electrode 32 is connected with the second plate 62 through the sixth via hole V6, the second end of the second gate electrode 32 extends toward the second active layer 22, and the orthogonal projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthogonal projection of the second active layer 22 on the substrate. In the exemplary embodiment, the second gate electrode 32 can serve as the gate electrode of the second transistor T2, and can control the turn-on or turn-off of the second transistor T2.

[0169] In the exemplary embodiment, since the second gate electrode 32 is connected with the second plate 62, and the second plate 62 is connected with the second region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate 62 (the first end of the storage capacitor) have the same potential, forming a first node in the pixel driving circuit, and the second plate 62 has the potential of the first node in the pixel driving circuit.

[0170] In an example embodiment, the third gate electrode 33 can have a strip shape extending along the second direction Y, can be disposed on a side of the scan signal line 30 close to the third active layer 23, a first end of the third gate electrode 33 can be connected to the scan signal line 30, a second end of the third gate electrode 33 can extend toward the third active layer 23, and a projection of the third gate electrode 33 on the substrate can at least partially overlap a projection of the third active layer 23 on the substrate. In an example embodiment, the third gate electrode 33 can serve as a gate electrode of the third transistor T3, so that the scan signal line 30 can control the third transistor T3 to be turned on or off.

[0171] In an example embodiment, in one sub-pixel, one scan signal line 30 can be connected to the first gate electrode 31 and the third gate electrode 33 at the same time, so that the scan signal line 30 can control the first transistor T1 and the third transistor T3 in one sub-pixel to be turned on or off.

[0172] In an example embodiment, in one pixel row, one scan signal line 30 can be connected to all the first gate electrodes 31 and all the third gate electrodes 33 in multiple sub-pixels at the same time, so that the scan signal line 30 can control all the first transistors T1 and all the third transistors T3 in one pixel row to be turned on or off.

[0173] In an example embodiment, in one repeating unit, one scan signal line 30 can be connected to all the first gate electrodes 31 and all the third gate electrodes 33 in multiple sub-pixels at the same time, so that the scan signal line 30 can control all the first transistors T1 and all the third transistors T3 in the repeating unit to be turned on or off at the same time.

[0174] In an example embodiment, the fifth connection electrode 15 can have a block shape (e.g., a rectangular shape), can be disposed on a side of the second plate 62 away from the scan signal line 30, and can be connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time through the third via hole V3.

[0175] In an example embodiment, since the fifth connection electrode 15 is connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first plate 61, the fifth connection electrode 15 makes the second plate 61 and the second electrode of the second transistor have the same potential. In an example embodiment, the fifth connection electrode 15 is configured to be connected to a tenth connection electrode formed subsequently.

[0176] In the example embodiment, the sixth connection electrode 16 can be in a block shape (e.g., a rectangular shape) and can be disposed on the side of the second plate 62 close to the scan signal line 30. The sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14 through the fifth via V5.

[0177] In the example embodiment, since the sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14, the fourth connection electrode 14 is connected to the second connection electrode 12, and the second connection electrode 12 is connected to the first plate 61, the sixth connection electrode 16 makes the second electrode of the third transistor and the first plate 61 have the same potential.

[0178] In the example embodiment, the fifth connection electrode 15 and the sixth connection electrode 16 realize the connection between the second electrode of the second transistor, the second electrode of the third transistor, and the first plate 61 (the second terminal of the storage capacitor), form the second node in the pixel driving circuit, and thus the first plate 61 has the potential of the second node in the pixel driving circuit.

[0179] In the example embodiment, since the first plate 61 has the potential of the second node in the pixel driving circuit and the second plate 62 has the potential of the first node in the pixel driving circuit, the first plate 61 with the potential of the second node and the second plate 62 with the potential of the first node form the storage capacitor.

[0180] In the example embodiment, since the first plate 61 is made of a transparent conductive material and the second plate 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0181] In the example embodiment, the seventh connection electrode 17 can be in a block shape (e.g., a rectangular shape) and can be disposed between the first gate electrode 31 and the first power supply line 51. The seventh connection electrode 17 is connected to the first region of the first active layer 21 and the data signal line 52 through the first via V1, thus realizing that the data signal line 52 writes the data signal to the first electrode of the first transistor T1. In the example embodiment, each data signal line 52 can be connected to the first region of the first active layer in one sub-pixel through the first via V1, thus realizing that four data signal lines 52 write data signals to the first electrodes of four first transistors T1 in one repeating unit, respectively.

[0182] In the example embodiment, the four data signal lines 52 can include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. The first data signal line can be located on one side of the first power supply line 51 in the first direction X in the first pixel column, and can be connected to the first region of the first active layer in the first sub-pixel P1 through the seventh connection electrode 17. The second data signal line can be located on one side of the first data signal line in the first direction X, and can be connected to the first region of the first active layer in the third sub-pixel P3 through the seventh connection electrode 17. The third data signal line can be located on one side of the compensation signal line 53 in the first direction X, and can be connected to the first region of the first active layer in the second sub-pixel P2 through the seventh connection electrode 17. The fourth data signal line can be located on one side of the third data signal line in the first direction X, and can be connected to the first region of the first active layer in the fourth sub-pixel P4 through the seventh connection electrode 17.

[0183] In the example embodiment, the eighth connection electrode 18 can have a strip shape extending in the first direction X, and can be arranged on the side of the second plate 62 away from the scan signal line 30. The first end of the eighth connection electrode 18 is connected to the first power supply line 51 through the seventh via hole V7, and the second end of the eighth connection electrode 18 is connected to the first region of the second active layer 22 through the second via hole V2, thereby realizing that the first power supply line 51 writes the first power supply signal to the first electrode of the second transistor T2.

[0184] In the example embodiment, the first power supply line 51 in the first pixel column can simultaneously provide the first power supply signal to the pixel driving circuit in the first sub-pixel P1 and the third sub-pixel P3, and the first power supply line 51 in the second pixel column can simultaneously provide the first power supply signal to the pixel driving circuit in the second sub-pixel P2 and the fourth sub-pixel P4, thereby realizing a one-to-two structure of the first power supply line 51 in one repeating unit. The present disclosure shows that by designing the first power supply line as a one-to-two structure, the number of signal lines is saved, the occupied space is reduced, the structure is simple, the layout is reasonable, the layout space is fully utilized, the space utilization rate is improved, and the resolution is improved.

[0185] In the example embodiment, the two first power supply lines 51 in one repeating unit are symmetrically arranged with respect to the compensation signal line 53, and the second transistor T2 in the first pixel column and the second transistor T2 in the second pixel column are symmetrically arranged with respect to the compensation signal line 53. The symmetric structure of the present disclosure can ensure that the voltage drop of the first power supply line writing the second transistor T2 is substantially the same, and the display uniformity is guaranteed.

[0186] In the example embodiment, the ninth connection electrode 19 can be in a block shape (e.g., a rectangular shape) and can be disposed between the third gate electrodes 33 of two adjacent sub-pixels in the first direction X. The ninth connection electrode 19 is connected to the first region of the third active layer 23 and the compensation signal line 53 through the fourth via V4, so that the compensation signal line 53 writes the compensation signal to the first electrode of the third transistor T3.

[0187] In the example embodiment, the first region of the third active layer in the first sub-pixel P1 and the second sub-pixel P2 is connected to each other, the first sub-pixel P1 and the second sub-pixel P2 share one fourth via V4, and thus the first sub-pixel P1 and the second sub-pixel P2 share one ninth connection electrode 19. The first region of the third active layer in the third sub-pixel P3 and the fourth sub-pixel P4 is connected to each other, the third sub-pixel P3 and the fourth sub-pixel P4 share one fourth via V4, and thus the third sub-pixel P3 and the fourth sub-pixel P4 share one ninth connection electrode 19.

[0188] In the example embodiment, the compensation signal line 53 can provide the compensation signal to the pixel driving circuit in four sub-pixels at the same time, so that the four pixel driving circuits in one repeating unit can share one compensation signal line 53, that is, the compensation signal line 53 in one repeating unit is in a one-to-four structure. The present disclosure shows that by designing the compensation signal line in a one-to-four structure, the number of signal lines is saved, the occupied space is reduced, the structure is simple, the layout is reasonable, the layout space is fully utilized, the space utilization rate is improved, and the resolution is improved.

[0189] In the example embodiment, the compensation signal line 53 is disposed between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically disposed with respect to the compensation signal line 53. The symmetric structure of the present disclosure can ensure that the RC delay of the compensation signal written into the third transistor T3 is substantially the same, and the display uniformity is ensured.

[0190] In the example embodiment, the positions of the patterns in the third conductive layer in the first sub-pixel P1 and the positions of the patterns in the third conductive layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns in the third conductive layer in the second sub-pixel P2 and the positions of the patterns in the third conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns in the third conductive layer in the first sub-pixel P1 and the positions of the patterns in the third conductive layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to a vertical reference line, and the positions of the patterns in the third conductive layer in the third sub-pixel P3 and the positions of the patterns in the third conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a vertical reference line.

[0191] In the exemplary embodiment, in the process of forming the third conductive layer pattern, the wet etching process is used to form the third conductive layer pattern, so that the at least one connecting electrode is connected to the second conductive layer and the semiconductor layer through the via of the transfer structure. The via of the transfer structure can include at least two half-holes: a shallow half-hole and a deep half-hole. In the shallow half-hole, the second insulating layer is removed to expose the surface of the semiconductor layer. In the deep half-hole, the second insulating layer and the first insulating layer are removed to expose the surface of the second conductive layer. Thus, the connecting electrode is connected to the semiconductor layer and the second conductive layer through the shallow half-hole and the deep half-hole. In the exemplary embodiment, a distance is provided between the end of the connecting electrode located in the shallow half-hole region and the edge of the shallow half-hole, i.e., the connecting electrode does not cover the shallow half-hole completely.

[0192] In the exemplary embodiment, after the wet etching process forms the third conductive layer pattern, a self-alignment process using the third conductive layer as a mask is used to etch the second insulating layer in the area outside the third conductive layer by using a dry etching process. The second insulating layer is etched away, and the exposed semiconductor layer is secondarily conductive at the same time, forming a secondarily conductive area.

[0193] In the exemplary embodiment, in the secondarily conductive process, the edge portion of the semiconductor layer covered by the third conductive layer is also conductive, i.e., the secondarily conductive semiconductor layer extends to the first conductive area. The twice conductive area is formed in the overlapping area of the first conductive area and the second conductive area, which can ensure the reliable connection between the third conductive layer and the semiconductor layer.

[0194] (6) Forming the third insulating layer and the planar layer pattern. In the exemplary embodiment, forming the third insulating layer and the planar layer pattern can include: depositing a third insulating film on the substrate on which the aforementioned patterns are formed, then coating a planar film, and patterning the planar film and the third insulating film by a patterning process to form the third insulating layer covering the third conductive layer and the planar layer pattern disposed on the third insulating layer. The planar layer is provided with a plurality of vias, as shown in FIG. 10.

[0195] In the exemplary embodiment, the via of each sub-pixel in the display substrate includes at least an eleventh via V11.

[0196] In the exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is within the orthographic projection range of the fifth connecting electrode 15 on the substrate. The third insulating layer and the planar layer in the eleventh via V11 are etched away to expose the surface of the fifth connecting electrode 15. The eleventh via V11 is configured to connect the tenth connecting electrode formed subsequently to the fifth connecting electrode 15 through the via.

[0197] In the example embodiment, the present process adopts one patterning process to form the via hole on the third insulating layer and the planar layer at the same time, i.e., the third insulating layer and the planar layer share one half-tone or gray-tone mask process, effectively reducing the number of patterning processes.

[0198] (7) Forming the fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the fourth conductive thin film through a patterning process, and forming the fourth conductive layer pattern on the color film layer, as shown in FIG. 11A and FIG. 11B, which is a schematic diagram of the fourth conductive layer in FIG. 11A.

[0199] In the example embodiment, the fourth conductive layer of each sub-pixel in the display substrate can at least include the tenth connecting electrode 20 and the first electrode 63.

[0200] In the example embodiment, the shape of the first electrode 63 can be rectangular, and the corner of the rectangular shape can be provided with a chamfer, a groove or a protrusion. The orthographic projection of the first electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 62 on the substrate.

[0201] In the example embodiment, the shape of the tenth connecting electrode 20 can be block-shaped (e.g., rectangular), which can be located on the side of the first electrode 63 away from the scan signal line 30. The first end of the tenth connecting electrode 20 is connected with the first electrode 63, and the second end of the tenth connecting electrode 20 extends away from the scan signal line 30 and is connected with the fifth connecting electrode 15 through the eleventh via hole V11.

[0202] In the example embodiment, in at least one sub-pixel, the tenth connecting electrode 20 and the first electrode 63 can be an integrated structure connected with each other.

[0203] In the example embodiment, the four first electrodes 63 in one repeating unit are arranged in a square shape. The first electrode in the upper left is connected with the pixel driving circuit in the first sub-pixel P1, the first electrode in the upper right is connected with the pixel driving circuit in the second sub-pixel P2, the first electrode in the lower left is connected with the pixel driving circuit in the third sub-pixel P3, and the first electrode in the lower right is connected with the pixel driving circuit in the fourth sub-pixel P4. In some possible implementations, the first electrode can serve as an anode of the light-emitting device, and the arrangement of the first electrode can be adjusted according to actual needs, which is not limited in the present disclosure.

[0204] In the example embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0205] In the example embodiment, the first electrode 63 can also serve as an auxiliary capacitor of the storage capacitor. Since the first electrode 63 is connected with the tenth connecting electrode 20, the tenth connecting electrode 20 is connected with the first plate 61 through the fifth connecting electrode 15, the third connecting electrode 13 and the first connecting electrode 11, the first electrode 63 has the potential of the second node in the pixel driving circuit, so that the first electrode 63 with the potential of the second node forms an auxiliary capacitor with the second plate 62 with the potential of the first node, and the auxiliary capacitor and the storage capacitor are in parallel. The present disclosure forms an auxiliary capacitor by using the first electrode, and the auxiliary capacitor and the storage capacitor are in parallel, which can effectively increase the capacitance value of the storage capacitor on the one hand, and can reduce the plate area while ensuring the capacitance value of the storage capacitor, effectively reducing the occupied area.

[0206] (8) Forming a pixel definition layer. In the example embodiment, forming the pixel definition layer pattern can include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition film by a patterning process to form a pixel definition layer covering the fourth conductive layer, as shown in FIG. 12.

[0207] In the example embodiment, a pixel opening K is formed on the pixel definition layer of each sub-pixel in the display substrate, the pixel definition film in the pixel opening K is removed, and part of the surface of the first electrode 63 is exposed, and the orthographic projection of the pixel opening K on the substrate is within the orthographic projection of the first electrode 63 on the substrate.

[0208] In the example embodiment, the shape of the pixel opening K can be similar to the shape of the first electrode 63 in a plane parallel to the substrate, and the cross-sectional shape of the pixel opening K can be rectangular or trapezoidal, etc. in a plane perpendicular to the substrate.

[0209] In the example embodiment, the shape of the pixel opening can include any one or more of the following: triangular, rectangular, trapezoidal, parallelogram, pentagon, hexagon, circular and elliptical.

[0210] In the example embodiment, the shapes of the pixel openings of the four sub-pixels can be the same or different. The areas of the pixel openings of the four sub-pixels can be the same or different.

[0211] In the example embodiment, the shapes and areas of the pixel openings of the four sub-pixels can be different to adapt to the transmittance of different sub-pixel filters, so that the light emitting devices of the four sub-pixels can emit the same brightness at different currents, maximizing the life of the light emitting devices of the four sub-pixels and ensuring the product life.

[0212] In the example embodiment, at least one partition groove M can also be arranged on the pixel definition layer of each repeating unit in the display substrate. The partition groove M can have a strip shape with a main body extending along the second direction Y, and can be arranged between the pixel openings K of the first direction X adjacent pixels. For example, the partition groove M can be arranged between the pixel opening K of the first sub-pixel P1 and the pixel opening K of the second sub-pixel P2. For another example, the partition groove M can be arranged between the pixel opening K of the third sub-pixel P3 and the pixel opening K of the fourth sub-pixel P4. In the example embodiment, the partition groove M is configured to cut off the subsequently formed organic light-emitting layer, block the lateral propagation path of the hole-type carriers, eliminate lateral leakage, and eliminate lateral cross talk of the sub-pixels.

[0213] In the example embodiment, the pixel definition layer can be made of polyimide, acrylic, polyethylene terephthalate, or the like.

[0214] (9) Forming an organic light-emitting layer and a cathode pattern. In the example embodiment, forming the organic light-emitting layer and the cathode pattern can include: first forming an organic light-emitting layer pattern, the organic light-emitting layer being connected to the first electrode 63 through the pixel opening K. Then forming a second electrode, the second electrode being connected to the organic light-emitting layer. In the example embodiment, the second electrode can serve as the cathode of the light-emitting device.

[0215] In the example embodiment, the organic light-emitting layer can include a light-emitting layer (EML), and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In the example embodiment, the organic light-emitting layer can be formed by fine metal mask (FMM) or open mask evaporation, or by an inkjet process.

[0216] (10) Forming an encapsulation structure layer pattern. In the example embodiment, forming the encapsulation structure layer pattern can include: first depositing a first inorganic thin film using an open mask to form a first encapsulation layer. Then, using an inkjet printing process to inkjet print an organic material on the first encapsulation layer, and after curing the film to form a second encapsulation layer. Then, depositing a second inorganic thin film using an open mask to form a third encapsulation layer, the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer forming the encapsulation structure layer. The first encapsulation layer and the third encapsulation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbon nitride (SiCN), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The second encapsulation layer can be made of a resin material, forming a stacked structure of inorganic material / organic material / inorganic material, with the organic material layer being arranged between the two inorganic material layers, so as to prevent external water vapor from entering the light-emitting structure layer.

[0217] So far, the preparation of the display substrate of the exemplary embodiment of the present disclosure is completed. The display substrate can include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on the light-emitting structure layer away from the substrate. In a direction perpendicular to the substrate, the driving circuit layer can include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a planar layer disposed on the substrate in sequence, the light-emitting structure layer can include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, and the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked.

[0218] In the exemplary embodiment, for the display substrate including the color film structure layer, the third insulating layer can be formed after the third conductive layer is formed, and then the red color film layer, the green color film layer, and the blue color film layer can be formed in sequence, and then the planar layer is formed, which will not be described here.

[0219] In the exemplary embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can be one or more of, but not limited to, glass, quartz, and the flexible substrate can be one or more of, but not limited to, polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In the exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, the materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0220] In the exemplary embodiment, the second conductive layer and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, and the second insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which can be a single layer, a multi-layer, or a composite layer. The planar layer can be made of an organic material, such as resin, etc.

[0221] At present, the existing display substrate has problems such as signal interference. The present inventor found that, because the four data signal lines in a repeat unit are arranged on both sides of the repeat unit in the first direction X, there is a cross-line connection, so the data signal lines will interfere with the second electrode of the first transistor and the storage capacitor. Taking the first data signal line and the second data signal line as an example, the first data signal line is connected to the first electrode of the first transistor T1 in the first sub-pixel P1, and the second data signal line is connected to the first electrode of the first transistor T1 in the third sub-pixel P3. Since the second data signal line is located on one side of the first data signal line in the first direction X, the first transistor T1 is located on one side of the second data signal line in the first direction X, so the first electrode of the first transistor T1 in the first sub-pixel P1 needs to cross the second data signal line to connect with the first data signal line. The present disclosure sets the position of the storage capacitor so that the storage capacitor is close to the compensation signal line and away from the data signal line. Since the second plate of the storage capacitor and the second electrode of the first transistor T1 are an integral structure connected to each other, the first transistor T1 is away from the data signal line, so the influence of the data voltage jump on the second electrode of the first transistor T1 and the storage capacitor can be reduced, avoiding the influence of the data voltage jump on the normal work of the pixel driving circuit, and improving the display effect and display quality.

[0222] At present, the existing display substrate has problems such as complex production process and high production cost. For example, the preparation process of the driving structure layer in a display substrate needs nine times of patterning (MASK) process, which not only reduces the production efficiency and increases the production cost, but also affects the product yield. The display substrate with a bottom emission structure provided by the embodiments of the present disclosure sets the first power line, the data signal line and the compensation signal line and other structures in the SHIELD layer on the side of the semiconductor layer close to the substrate, and sets the scan signal line and the gate electrode of the plurality of transistors and other structures in the GT layer on the side of the semiconductor layer away from the substrate, which not only reduces one conductive layer, but also reduces the patterning process of the transfer via hole and the patterning process of the transfer conductive layer, so that the preparation process of the driving structure layer only needs six times of patterning process, reduces the number of patterning processes, effectively improves the production efficiency, effectively reduces the production cost, and maximizes the product yield.

[0223] The display substrate of the embodiment of the present disclosure adopts a 3T1C pixel driving circuit with one scan signal line, and the scan signal line is connected with the first transistor and the third transistor in the pixel driving circuit. By reducing the number of scan signal lines, the structure of the pixel driving circuit can be simplified, the occupied area of the pixel driving circuit is reduced, and high resolution display is facilitated. In addition, since one repeat unit only needs one scan signal line for driving, the number of corresponding gate driving circuit (GOA) and clock signal line (CLK) can be reduced by several times, effectively reducing the occupied area of the gate driving circuit and the clock signal line, facilitating narrow frame and improving product advantages.

[0224] The display substrate of the exemplary embodiment of the present disclosure comprises a transparent storage capacitor composed of a transparent conductive layer and a transparent semiconductor layer, so that light can be emitted through the transparent storage capacitor. Therefore, the storage capacitor can be arranged in the pixel opening, which can effectively increase the capacitance of the storage capacitor and effectively increase the pixel aperture ratio.

[0225] The pixels of the embodiment of the present disclosure are arranged in a square manner. By adopting the first power line structure of non-network structure, the pixel aperture ratio can be effectively increased, the display effect is improved, and the display is more suitable for display type.

[0226] The preparation process of the present disclosure can be well compatible with the existing preparation process, and the process is simple to implement, high in production efficiency, low in production cost and high in yield.

[0227] The structure and preparation process of the present disclosure are only an exemplary illustration. In the exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or reduced, which is not limited in the present disclosure.

[0228] FIG. 13 is a schematic structural diagram of a driving circuit layer in another display substrate according to an exemplary embodiment of the present disclosure, which illustrates the structure of signal line arrangement in a repeat unit (four sub-pixels) of a bottom emission display substrate. In the exemplary embodiment, at least one repeat unit can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 arranged in a square manner, and each sub-pixel includes a pixel driving circuit 54.

[0229] In the exemplary embodiment, at least one repeat unit can include one scan signal line 30, two first power lines 51, two compensation signal lines 53 and four data signal lines 52, and the above-mentioned signal lines are connected with the pixel driving circuit 54 in the corresponding sub-pixel.

[0230] In the example embodiment, the scan signal line 30 can be in a linear shape with a main body extending along the first direction X, and the first power supply line 51, the data signal line 52, and the compensation signal line 53 can be in a linear shape with a main body extending along the second direction Y. In the example embodiment, the scan signal line 30 can be disposed in a middle region of the second direction Y of the repeating unit, the two first power supply lines 51 and the four data signal lines 52 can be disposed in a middle region of the first direction X of the repeating unit, and the two compensation signal lines 53 can be disposed on both sides of the first direction X of the repeating unit. One of the two first power supply lines 51 can be disposed between the data signal line 52 and one of the compensation signal lines 53, and the other of the two first power supply lines 51 can be disposed between the data signal line 52 and the other of the compensation signal lines 53.

[0231] In the example embodiment, the pixel driving circuit of the at least one sub-pixel can include a first transistor, a second transistor, a third transistor, and a storage capacitor, and the relevant connection structure is substantially the same as that of the foregoing embodiments, which will not be described herein again.

[0232] In the example embodiment, the storage capacitor can include at least a first plate and a second plate as capacitor plates. In the at least one sub-pixel, the first plate and the second plate can be disposed between the first power supply line 51 and the compensation signal line 53.

[0233] In the example embodiment, in the at least one repeating unit, the two compensation signal lines 53 can include a first compensation signal line 53-1 and a second compensation signal line 53-2 disposed in sequence along the first direction X, the first compensation signal line 53-1 can be disposed on the side opposite to the first direction X of the repeating unit, and the second compensation signal line 53-2 can be disposed on the side of the first direction X of the repeating unit. The two first power supply lines 51 can include a first first power supply line 51-1 and a second first power supply line 51-2 disposed in sequence along the first direction X, and the four data signal lines 52 can include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3, and a fourth data signal line 52-4 disposed in sequence along the first direction X, and the four data signal lines 52 can be disposed between the first first power supply line 51-1 and the second first power supply line 51-2.

[0234] The present disclosure can effectively shield the influence of the data voltage jump on the second plate of the first transistor T1 and the storage capacitor on the data signal line by disposing the storage capacitor between the first power supply line and the compensation signal line and disposing the four data signal lines between the two first power supply lines, thereby avoiding the influence of the data voltage jump on the normal operation of the pixel driving circuit and improving the display effect.

[0235] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (Micro LED or Mini LED), or a quantum dot light-emitting diode display (QDLED), etc., which are not limited herein.

[0236] The exemplary embodiments of the present disclosure also provide a preparation method of a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of repeating units, at least one repeating unit including a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the preparation method can include:

[0237] forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit being connected to a data signal line and a compensation signal line extending along a pixel column direction, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; the pixel driving circuit including at least a storage capacitor, the storage capacitor including at least two capacitor plates stacked, the two capacitor plates being disposed between the data signal line and the compensation signal line; at least one capacitor plate in at least one sub-pixel, an edge of the capacitor plate close to the compensation signal line having a first distance from an edge of the compensation signal line close to the capacitor plate, and an edge of the capacitor plate close to the data signal line having a second distance from an edge of the data signal line close to the capacitor plate, the first distance being smaller than the second distance, and the first distance and the second distance being a dimension in a pixel row direction.

[0238] The present disclosure also provides a display device including the display substrate of the aforementioned embodiments. The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc.

[0239] Although the embodiments disclosed by the present disclosure are as described above, it should be noted that the above-described embodiments are merely exemplary and not limiting. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

A display substrate includes a plurality of repeating units, at least one of the repeating units includes a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one of the sub-pixels includes a pixel driving circuit, the pixel driving circuit is connected with a data signal line and a compensation signal line extending along a pixel column direction respectively, the data signal line is configured to provide a data signal to the pixel driving circuit, and the compensation signal line is configured to provide a compensation signal to the pixel driving circuit; the pixel driving circuit includes at least a storage capacitor, the storage capacitor includes at least two capacitor plates stacked, and the two capacitor plates are arranged between the data signal line and the compensation signal line; at least one of the capacitor plates in at least one of the sub-pixels has a first distance between an edge of the capacitor plate close to a side of the compensation signal line and an edge of the compensation signal line close to the capacitor plate, and has a second distance between an edge of the capacitor plate close to a side of the data signal line and an edge of the data signal line close to the capacitor plate, the first distance is smaller than the second distance, and the first distance and the second distance are dimensions in a pixel row direction. The display substrate according to claim 1, wherein The ratio of the first distance to the second distance is 0.35 to 0.

75. The display substrate according to claim 1, wherein The ratio of the first distance to the second distance is 0.6 to 0.

7. The display substrate according to claim 3, wherein The first distance is 5.5 μm to 6.5 μm, and the second distance is 8.5 μm to 9.5 μm. The display substrate according to claim 1, wherein The ratio of the first distance to the second distance is 0.4 to 0.

5. The display substrate according to claim 5, wherein The first distance is 5.5 μm to 6.5 μm, and the second distance is 12.5 μm to 13.5 μm. The display substrate according to claim 1, wherein The ratio of the first distance to the second distance is 0.65 to 0.

75. The display substrate according to claim 7, wherein The first distance is 8.5 μm to 9.5 μm, and the second distance is 12.5 μm to 13.5 μm. The display substrate according to any one of claims 1 to 8, wherein The two capacitor plates include a first plate and a second plate, the pixel driving circuit further includes a first transistor, a second transistor and a third transistor, a first electrode of the first transistor is connected with the data signal line, a second electrode of the first transistor is connected with the first plate and a gate electrode of the second transistor respectively, a first electrode of the third transistor is connected with the compensation signal line, a second electrode of the third transistor is connected with the second plate and a second electrode of the second transistor respectively, the second plate has a first distance between an edge of the second plate close to a side of the compensation signal line and an edge of the compensation signal line close to the second plate, and has a second distance between an edge of the second plate close to a side of the data signal line and an edge of the data signal line close to the second plate. The display substrate according to claim 9, wherein The first transistor includes at least a first active layer, and the first active layer and the second plate are an integrated structure connected with each other. The display substrate according to any one of claims 1 to 8, wherein The pixel driving circuit is further connected with a first power line extending along the pixel column direction; at least one repeating unit comprises one compensation signal line, two first power lines and four data signal lines, the compensation signal line is located in the middle of the pixel row direction of the repeating unit, the two first power lines are located on both sides of the pixel row direction of the repeating unit, and two of the four data signal lines are located on one side of the first power line close to the compensation signal line, and the other two of the four data signal lines are located on one side of the other first power line close to the compensation signal line. The display substrate according to claim 11, wherein The two first power lines comprise a first first power line and a second first power line arranged in sequence along the pixel row direction, and the four data signal lines comprise a first data signal line, a second data signal line, a third data signal line and a fourth data signal line arranged in sequence along the pixel row direction; the first data signal line is located on one side of the first first power line close to the compensation signal line, the second data signal line is located on one side of the first data signal line close to the compensation signal line, the two capacitor plates are arranged between the second data signal line and the compensation signal line, the edge of the capacitor plate close to one side of the compensation signal line has a first distance from the edge of the compensation signal line close to the capacitor plate, and the edge of the capacitor plate close to one side of the second data signal line has a second distance from the edge of the second data signal line close to the capacitor plate; the fourth data signal line is located on one side of the second first power line close to the compensation signal line, the third data signal line is located on one side of the fourth data signal line close to the compensation signal line, the two capacitor plates are arranged between the third data signal line and the compensation signal line, the edge of the capacitor plate close to one side of the compensation signal line has a first distance from the edge of the compensation signal line close to the capacitor plate, and the edge of the capacitor plate close to one side of the third data signal line has a second distance from the edge of the third data signal line close to the capacitor plate. The pixel driving circuit is further connected with a first power line extending along the pixel column direction; at least one repeating unit comprises two compensation signal lines, two first power lines and four data signal lines, the four data signal lines are located in the middle of the pixel row direction of the repeating unit, the two compensation signal lines are located on both sides of the pixel row direction of the repeating unit, and the two first power lines are respectively located on one side of the four data signal lines close to the compensation signal line. The display substrate according to any one of claims 1 to 8, wherein ​ The display substrate according to claim 13, wherein The two compensation signal lines include a first compensation signal line and a second compensation signal line arranged in sequence along the pixel row direction, the two first power supply lines include a first first power supply line and a second first power supply line arranged in sequence along the pixel row direction, and the four data signal lines include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line arranged in sequence along the pixel row direction; the first first power supply line is located on one side of the first data signal line close to the first compensation signal line, and the two capacitor plates are arranged between the first compensation signal line and the first first power supply line; the second first power supply line is located on one side of the fourth data signal line close to the second compensation signal line, and the two capacitor plates are arranged between the second compensation signal line and the second first power supply line. A display device includes the display substrate of any one of claims 1 to 14. A method for manufacturing a display substrate, the display substrate including a plurality of repeating units, at least one repeating unit including a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the method including: forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit being connected to a data signal line and a compensation signal line extending along a pixel column direction, the data signal line being configured to provide a data signal to the pixel driving circuit, and the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; the pixel driving circuit including at least a storage capacitor, the storage capacitor including at least two capacitor plates stacked, the two capacitor plates being arranged between the data signal line and the compensation signal line; at least one capacitor plate in at least one sub-pixel, an edge of the capacitor plate close to the compensation signal line having a first distance from an edge of the compensation signal line close to the capacitor plate, and an edge of the capacitor plate close to the data signal line having a second distance from an edge of the data signal line close to the capacitor plate, the first distance being smaller than the second distance, and the first distance and the second distance being dimensions in a pixel row direction.

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