Random number generation method and apparatus

Abstract

The present application discloses a random number generation method and apparatus. The method comprises: dividing 64-byte information to be encrypted into 16 blocks, each block representing four bytes, and every four blocks being used as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; on the basis of the basic blocks and 256-bit registers, completing a one-time basic operation of performing a hybrid operation on a block in a stream symmetric encryption algorithm; using a block as a unit, circularly shifting the second basic block leftward by one block, circularly shifting the third basic block leftward by two blocks, and circularly shifting the fourth basic block leftward by three blocks; and on the basis of the basic blocks and the 256-bit registers, completing a one-time basic operation of performing a hybrid operation on a rearranged block in a stream symmetric encryption algorithm.

Description

A Random Number Generation Method and Device Technical Field This application relates to, but is not limited to, information security technology, and particularly refers to a random number generation method and device. Background Art Zero-Knowledge Proof (ZKP) was proposed by S. Goldwasser, S. Micali, and C. Rackoff in the early 1980s. Zero-Knowledge Proof means that the prover can make the verifier believe that a certain assertion is correct without providing any useful information to the verifier. Zero-Knowledge Proof is essentially a protocol involving two or more parties. In other words, it is a series of steps that two or more parties need to take to complete a task. In Zero-Knowledge Proof, the prover proves to the verifier and makes it believe that it knows or has a certain message, but the proof process cannot disclose any information about the message being proved to the verifier. The stream symmetric encryption algorithm, as a random number generator in the ZKP system, can ensure that the prover and the verifier generate the same random number, and at the same time, the random number cannot be predicted in advance. In the related art, when the stream symmetric encryption algorithm is implemented by software, its operation data volume is large, and it will frequently call memory, thus increasing the burden on the CPU; moreover, during the execution of the ZKP encryption process, it will also cause the encryption time to be too long. Summary of the Invention This application provides a random number generation method and device, which can reduce the amount of computation, improve the random number generation speed, and thus shorten the duration of the ZKP encryption process. An embodiment of this application provides a random number generation method, including: Dividing 64-byte information to be encrypted into 16 blocks, each block representing 4 bytes, and taking every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; storing the four basic blocks into four 256-bit registers respectively; Based on the four basic blocks and the four 256-bit registers, complete a basic operation of mixing the blocks in the stream symmetric encryption algorithm; Taking the blocks as units, circularly shift the second basic block left by one block, the third basic block left by two blocks, and the fourth basic block left by three blocks; Based on the four basic blocks and the four 256-bit registers, complete a basic operation of mixing the rearranged blocks in the stream symmetric encryption algorithm. In an exemplary example, it further includes: Increment the preset number of rounds by one, and return to the step of performing a basic operation of mixing the blocks until the number of rounds reaches the preset round threshold; Perform an addition operation on the result after iteratively operating for a preset number of rounds threshold and the information to be encrypted before update, and use the operation result as a random number. In an exemplary instance, the hybrid operation includes: a 256-bit single instruction multiple data (SIMD) addition instruction for implementing an addition operation on two 256-bit SIMD registers; a 256-bit SIMD exclusive OR for implementing an exclusive OR operation on two 256-bit SIMD registers, where one 256-bit register represents the result of the addition operation; and, a first SIMD circular left shift instruction for implementing a first circular left shift of N1 bits on a 256-bit SIMD register representing the result of the exclusive OR operation in units of 32 bits. In an exemplary instance, the first basic block includes block0, block1, block2, and block3 among the 16 blocks; the second basic block includes block4, block5, block6, and block7 among the 16 blocks; the third basic block includes block8, block9, block10, and block11 among the 16 blocks; the fourth basic block includes block12, block13, block14, and block15 among the 16 blocks; The circular left shift of the second basic block by one block, the circular left shift of the third basic block by two blocks, and the circular left shift of the fourth basic block by three blocks include: For the result after a single basic operation of performing a hybrid operation on the block, circularly shift block5 of the second basic block to block4, circularly shift block10 of the third basic block to block8, and circularly shift block15 of the fourth basic block to block12. In an exemplary instance, the circular left shift is a second SIMD circular left shift; the second SIMD circular left shift is implemented by the SIMD128_ROL instruction; The format of the SIMD128_ROL instruction includes: SIMD128_ROL(S, N2, R), which is used to implement a circular left shift of N2 bits on S for 128 bits to obtain R; where S represents a 256-bit SIMD register for performing the circular left shift operation, N2 represents the number of bits of the circular left shift, and N2 is an integer multiple of 32. The embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions for executing the random number generation method described in any one of the above. Another embodiment of the present application provides a computer device, including a memory and a processor. Among them, the following instructions that can be executed by the processor are stored in the memory: the steps for executing the random number generation method described in any one of the above. Another embodiment of the present application provides a random number generation device, including: a control unit, a preprocessing unit, a 256-bit register bank, an iterative processing unit, and a tail processing unit; among them, A preprocessing module, configured to, under the control of the control unit, read data from the memory, perform the following preprocessing on the read data and store it in the 256-bit register bank. Among them, two preprocessed results are stored in the 256-bit register bank: divide 64 bytes of information to be encrypted into 16 blocks, each block represents 4 bytes, and take every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; the four basic blocks are respectively stored in four 256-bit registers; A core processing unit, configured to perform the following preset number of rounds of iterative operations: read the information to be encrypted from the 256-bit register bank, and complete a basic operation of mixing the blocks in the stream symmetric encryption algorithm based on the four basic blocks and the four 256-bit registers; take the blocks as units, circularly shift the second basic block to the left by one block, circularly shift the third basic block to the left by two blocks, circularly shift the fourth basic block to the left by three blocks, and update the 16 blocks corresponding to the information to be encrypted in the 256-bit register bank; based on the updated four basic blocks and the four 256-bit registers, complete a basic operation of mixing the rearranged blocks in the stream symmetric encryption algorithm; A tail processing unit, configured to, under the control of the control unit, perform an addition operation on the result after the preset number of rounds of threshold iterative operations and the information to be encrypted before update, and write the result as the obtained random number into the memory. In an exemplary example, the 256-bit register bank includes eight 256-bit registers SIMD_reg0 to SIMD_reg7; among them, SIMD_reg0 is used to save the first basic block, SIMD_reg1 is used to save the second basic block, SIMD_reg2 is used to save the third basic block, and SIMD_reg3 is used to save the fourth basic block; SIMD_reg4 is used to save the first basic block, SIMD_reg5 is used to save the second basic block, SIMD_reg6 is used to save the third basic block, and SIMD_reg7 is used to save the fourth basic block. In an exemplary example, the information to be encrypted before update read by the tail processing unit is the data read from SIMD_reg4 to SIMD_reg7 in the 256-bit register bank. In an exemplary instance, the core processing unit may include: an iteration control module, a first processing module, a rearrangement module, and a second processing module; wherein, The first processing module is configured to, under the control of the iteration processing module, read the information to be encrypted from SIMD_reg0 to SIMD_reg3 in the 256-bit register bank, and complete a basic operation of performing a mixing operation on the block in the stream symmetric encryption algorithm based on the basic block and the 256-bit register; in one embodiment, reading the information to be encrypted from the 256-bit register bank is from; The rearrangement module is configured to cyclically shift the second basic block to the left by one block, the third basic block to the left by two blocks, and the fourth basic block to the left by three blocks in units of blocks, and update 16 blocks in the preprocessing module; The second processing module is configured to complete a basic operation of performing a mixing operation on the rearranged block in the stream symmetric encryption algorithm based on the updated basic block and the 256-bit register. In an exemplary instance, the control of the iteration processing module is used to: increment the preset number of rounds by one, and notify the first processing module to perform a basic operation until the number of rounds reaches the preset round threshold, and use the operation result as a random number. An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions for executing the random number generation method described in any one of the above. An embodiment of the present application further provides a computer device including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for executing the random number generation method described in any one of the above. Other features and advantages of the present invention will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the specification, claims, and drawings. And obtained. BRIEF DESCRIPTION OF THE DRAWINGS The drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application. FIG. 1 is a schematic diagram of the division of blocks in the related art; FIG. 2 is a schematic flowchart of the random number generation method in an embodiment of the present application; FIG. 3 is a schematic diagram of the division of blocks in an embodiment of the present application; FIG. 4 is a schematic diagram of rearranging blocks in an embodiment of the present application; FIG. 5 is a schematic structural diagram of the random number generation device in the embodiment of the present application; FIG. 6 is a schematic diagram of the process of a basic operation in the first processing module in the embodiment of the present application; FIG. 7 is a schematic diagram of the addition process of the tail processing module in the embodiment of the present application. Detailed description To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other. To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. Embodiments of the present application are shown in the drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. When the stream symmetric encryption algorithm in the related art encrypts 64 bytes (byte), first, the 64-byte information to be encrypted input is divided into 16 blocks (block), and the arrangement index of each block is shown in FIG. 1. Each block represents 4 bytes. In the stream symmetric encryption algorithm, a basic operation includes performing a mixing operation on 4 blocks, and the following 8 basic operations need to be performed in each round: The first basic operation: performing a mixing operation on block0, block4, block8, and block12; The second basic operation: performing a mixing operation on block1, block5, block9, and block13; The third basic operation: performing a mixing operation on block2, block6, block10, and block14; The fourth basic operation: performing a mixing operation on block3, block7, block11, and block15; The fifth basic operation: performing a mixing operation on block0, block5, block10, and block15; The sixth basic operation: performing a mixing operation on block1, block6, block11, and block12; The seventh basic operation: perform a mixed operation on block2, block7, block8, and block13; The eighth basic operation: perform a mixed operation on block3, block4, block9, and block14. In this way, after running multiple rounds (the number of rounds can be preset in advance), a 64-byte random number is obtained. Each round can be regarded as two segments of operations. The first segment of operations includes the first basic operation to the fourth basic operation, and the second segment of operations includes the fifth basic operation to the eighth basic operation. Taking the first basic operation as an example, a mixed operation of 4 blocks at a time can include the following operations: block[0] = block[0] + block[4]; block

[0012] = ROL(block

[0012] ^ block[0], 16), where ROL represents the cyclic left shift operator and ^ represents the exclusive OR operator; block[8] = block[8] + block

[0012] ; block[4] = ROL(block[4] ^ block[8], 12); block[0] = block[0] + block[4]; block

[0012] = ROL(block

[0012] ^ block[0], 8); block[8] = block[8] + block

[0012] ; block[4] = ROL(block[4] ^ block[8], 7). During the process of performing the mixed operation on the blocks, since the stream symmetric encryption algorithm does not need to consider the carry operation when performing the block operation, therefore, the first basic operation to the fourth basic operation can be carried out simultaneously. During the process of simultaneously performing the first basic operation, that is, the addition operation, the stream will cause the encryption time to be too long when performing the ZKP encryption process. In order to reduce the amount of computation, improve the random number generation speed, and thus shorten the duration of the ZKP encryption process, the embodiment of the present application proposes a random number generation method. Figure 2 is a schematic flowchart of the random number generation method in the embodiment of the present application. As shown in Figure 2, it includes: Step 200: Divide the 64-byte information to be encrypted into 16 blocks, each block represents 4 bytes, and take every 4 blocks as a basic block to obtain the first basic block, the second basic block, the third basic block, and the fourth basic block; the four basic blocks are respectively stored in four 256-bit registers. In an exemplary instance, if the information to be encrypted to be processed is 64 bytes, then in step 200, the 64-byte information to be encrypted can be divided into 16 blocks; if the information to be encrypted to be processed is 128 bytes, then the 128-byte information to be encrypted will first be divided into two 64-byte information to be encrypted, and then each time the 64-byte information is processed according to the random number generation method provided in the embodiments of the present application, and then the other 64-byte information to be encrypted is processed. That is to say, the information to be encrypted in the embodiments of the present application will first be divided into one or more 64-byte information to be encrypted, and then processed one by one in units of 64 bytes. In an exemplary instance, as shown in FIG. 3, block0, block1, block2, and block3 are used as the first basic block (shown as diagonal shading in FIG. 3), block4, block5, block6, and block7 are used as the second basic block (shown as vertical shading in FIG. 3), block8, block9, block10, and block11 are used as the third basic block (shown as diamond grid shading in FIG. 3), and block12, block13, block14, and block15 are used as the fourth basic block (shown as horizontal shading in FIG. 3). Based on the scenario of a 256-bit register, taking the RISC-V instruction set architecture as an example, in the first 256-bit single-instruction multiple-data (SIMD) register (SIMD_reg1), the first basic block, namely block0, block1, block2, and block3 data, is stored. The first operand is block0, which is included in bits [31:0] of the 256-bit SIMD_reg1. The second operand is block1, which is included in bits [63:32] of the 256-bit SIMD_reg1. The third operand is block2, which is included in bits [95:64] of the 256-bit SIMD_reg1. The fourth operand is block3, which is included in bits [127:96] of SIMD_reg1. In the second 256-bit SIMD register (SIMD_reg2), the second basic block, namely block4, block5, block6, and block7 data, is stored. The first operand is block4, which is included in bits [31:0] of the 256-bit SIMD_reg2. The second operand is block5, In the bits [63:32] of the 256-bit SIMD_reg2, the third operand is block6; in the bits [95:64] of the 256-bit SIMD_reg2, the fourth operand is block7; in the bits [127:96] of the 256-bit SIMD_reg2. In the third 256-bit SIMD register (SIMD_reg3), the third basic block, namely block8, block9, block10, and block11 data, is saved. The first operand is block8, included in the bits [31:0] of the 256-bit SIMD_reg3; the second operand is block9, included in the bits [63:32] of the 256-bit SIMD_reg3; the third operand is block10, included in the bits [95:64] of the 256-bit SIMD_reg3; the fourth operand is block11, included in the bits [127:96] of the 256-bit SIMD_reg3. In the fourth 256-bit SIMD register (SIMD_reg4), the fourth basic block, namely block12, block13, block14, and block15 data, is saved. The first operand is block12, included in the bits [31:0] of the 256-bit SIMD_reg4; the second operand is block13, included in the bits [63:32] of the 256-bit SIMD_reg4; the third operand is block14, included in the bits [95:64] of the 256-bit SIMD_reg4; the fourth operand is block15, included in the bits [127:96] of the 256-bit SIMD_reg4. Among them, RISC-V is an open-source instruction set architecture (ISA) based on the reduced instruction set (RISC) principle. Step 201: Based on four basic blocks and four 256-bit registers, complete a basic operation of block mixing in the stream symmetric encryption algorithm. In the embodiments of the present application, since every 4 blocks form a basic block, as shown in Figure 3, therefore, based on the 256-bit register, the first to fourth basic operations of block mixing only require one basic operation to complete, which reduces the amount of computation, improves the random number generation speed, and thus shortens the execution duration of the ZKP encryption process. Taking the first basic operation, i.e., the addition operation, in the basic operation as an example, in the 256-bit register in the embodiments of the present application, as follows, only one addition is required: SIMD_reg1_block0 = SIMD_reg1_block0 + SIMD_reg2_block4, SIMD_reg1_block1 = SIMD_reg1_block1 + SIMD_reg2_block5, SIMD_reg1_block2 = SIMD_reg1_block2 + SIMD_reg2_block6, SIMD_reg1_block3 = SIMD_reg1_block3 + SIMD_reg2_block7. As can be seen more intuitively from FIGS. 1 and 3, in the related art, as shown in FIG. 1, based on a 32-bit register, the first basic operation is performed on the first column, the second basic operation is performed on the second column, the third basic operation is performed on the third column, and the fourth basic operation is performed on the fourth column. The four basic operations are independent of each other. In the embodiment of the present application, as shown in FIG. 3, based on a 256-bit register, the four blocks in the first row are regarded as one element in the same column, that is, the four blocks in the first row are a basic block, namely the first basic block. Similarly, the four blocks in the second row are a basic block, namely the second basic block, the four blocks in the third row are a basic block, namely the third basic block, and the four blocks in the fourth row are a basic block, namely the fourth basic block. In this way, a column is composed of four basic blocks. Therefore, in the embodiment of the present application, only one basic operation on the column composed of the four basic blocks can include the four basic operations in the related art. That is to say, in the embodiment of the present application, when performing addition, exclusive OR, or the first circular left shift operation, only one basic operation is required based on a 256-bit register. In an exemplary example, in order to implement the mixed operation based on a 256-bit register, the instructions for mixed operation are set as follows in the embodiment of the present application: 256-bit SIMD addition (SIMD256_ADD) instruction, which is used to implement the addition operation on two 256-bit SIMD registers. Its format includes: SIMD256_ADD(S1, S2, R1), where S1 represents the first 256-bit SIMD register participating in the addition operation, and S2 is the second 256-bit SIMD register participating in the addition operation. SIMD256_ADD(S1, S2, R1) is used to implement R1 = S1 + S2. In one embodiment, taking the addition operation of 256-bit SIMD_reg1 and 256-bit SIMD_reg2 as an example, S1 is SIMD_reg1(block0, block1, block2, block3), S2 is SIMD_reg2(block4, block5, block6, block7), then, R1 = (S1_Block0 + S2_Block4, S1_Block1 + S2_Block5, S1_Block2 + S2_Block6, S1_Block3 + S2_Block7). 256-bit SIMD Exclusive OR (SIMD256_XOR) instruction, used to implement the exclusive OR operation on two 256-bit SIMD registers. Its format includes: SIMD256_XOR(S1, S2, R1), where S1 represents the first 256-bit SIMD register participating in the exclusive OR operation, and S2 is the second 256-bit SIMD register participating in the exclusive OR operation. SIMD256_XOR(S1, S2, R1) is used to implement R1 = S1 ^ S2. In one embodiment, taking the exclusive OR operation of 256-bit SIMD_reg1 and 256-bit SIMD_reg2 as an example, S1 is SIMD_reg1(block0, block1, block2, block3), S2 is SIMD_reg2(block4, block5, block6, block7), then, R1 = (S1_Block0 ^ S2_Block4, S1_Block1 ^ S2_Block5, S1_Block2 ^ S2_Block6, S1_Block3 ^ S2_Block7). First SIMD Rotate Left (SIMD256_32_ROL) instruction, its format includes: SIMD256_32_ROL(S, N1, R), where S represents the 256-bit SIMD register for performing the rotate left operation, N1 represents the number of bits for rotate left, and SIMD256_32_ROL(S, N1, R) is used to implement rotating S left by N1 bits with 32 bits as an independent unit to obtain R. In the embodiments of the present application, N1 = 7, 8, 12, 16. Taking the rotate left operation on 256-bit SIMD_reg1 as an example, S is SIMD_reg1(block0, block1, block2, block3), then, R = (S1_Block0_ROL(N1), S1_Block1_ROL(N1), S1_Block2_ROL(N1), S1_Block3_ROL(N1)). In an exemplary instance, the execution of step 201 may include: the processor executes the SIMD256_ADD instruction, the result of the SIMD256_ADD instruction is used to execute the SIMD256_XOR instruction, and the result of the SIMD256_XOR instruction is used to execute SIMD256_32_ROL. In this way, for the 256-bit register, by performing the above algorithm on each row block (i.e., the basic block) of the input information to be encrypted in the stream symmetric encryption algorithm, the result after the operation of step 201 can be obtained. Step 202: Taking blocks as units, rotate the second basic block left by one block, rotate the third basic block left by two blocks, and rotate the fourth basic block left by three blocks. In an exemplary instance, as shown in FIG. 4, this step may include: Based on the result of the operation in step 201, step 202 performs the following rearrangement operation to achieve the rearrangement of the blocks: Keep the first basic block unchanged, circularly shift block 5 of the second basic block to block 4, circularly shift block 10 of the third basic block to block 8, and circularly shift block 15 of the fourth basic block to block 12. In an exemplary instance, in order to achieve the rearrangement of the blocks based on 256-bit registers, the instructions for block rearrangement are set in the embodiments of the present application as follows: The second SIMD circular left shift (SIMD128_ROL) instruction, the format of which includes: SIMD128_ROL(S, N2, R), where S represents the 256-bit SIMD register for performing the circular left shift operation, N2 represents the number of bits of the circular left shift, and SIMD128_ROL(S, N2, R) is used to achieve a 128-bit N2-bit circular left shift of S to obtain R. In the embodiments of the present application, N2 = 32, 64, 96. In one embodiment, as shown in FIG. 4, the implementation of step 202 using the SIMD128_ROL instruction may include: SIMD128_ROL(SIMD_reg2, 32, R2), which represents performing a 128-bit 32-bit circular left shift operation on the 256-bit SIMD_reg2 above FIG. 4 to obtain the 256-bit SIMD_reg2 below FIG. 4; SIMD128_ROL(SIMD_reg3, 64, R3), which represents performing a 128-bit 64-bit circular left shift operation on the 256-bit SIMD_reg3 above FIG. 4 to obtain the 256-bit SIMD_reg3 below FIG. 4; SIMD128_ROL(SIMD_reg4, 96, R4), which represents performing a 128-bit 96-bit circular left shift operation on the 256-bit SIMD_reg4 above FIG. 4 to obtain the 256-bit SIMD_reg4 below FIG. 4. Step 203: Based on the four basic blocks and the four 256-bit registers, complete a basic operation of the mixing operation on the rearranged blocks in the stream symmetric encryption algorithm. In an exemplary instance, the specific implementation of this step is as described in step 201, which will not be elaborated here. It should be noted that after the rearrangement operation in step 202, in the related art, based on 32-bit registers, the corresponding form of the block in the fifth to eighth basic operations in the stream symmetric encryption algorithm has changed to the corresponding form of the block in the first to fourth basic operations. Therefore, step 203 can be like step 201, and performing one basic operation on a column composed of four basic blocks can include the fifth to eighth basic operations in the related art. In this way, the amount of computation is reduced, the random number generation speed is increased, and thus the duration of the ZKP encryption process is shortened. After step 203, the random number in the stream symmetric encryption algorithm, that is, the encryption result of the information to be encrypted, can be obtained. In an exemplary instance, the mixed operation on the block in step 201 and step 203 in the embodiments of the present application may include: 256-bit single instruction multiple data (SIMD) addition instruction, used to implement the addition operation on two 256-bit registers; 256-bit SIMD exclusive OR, used to implement the exclusive OR operation on two 256-bit registers, where one 256-bit register represents the result of the addition operation; and, the first SIMD circular left shift instruction, used to implement a first circular left shift of N1 bits on the 256-bit SIMD register representing the result of the exclusive OR operation with 32 bits as an independent unit. The random number generation method provided by the embodiments of the present application is based on 256-bit registers, and cleverly rearranges the blocks during the random number generation process, which not only ensures the successful generation of random numbers, but also reduces the amount of computation of the mixed operation on the blocks in the stream symmetric encryption algorithm, improves the random number generation speed, and thus shortens the duration of the ZKP encryption process. In an exemplary instance, according to the needs of encryption, the number of encryption rounds can also be preset That is, the round number threshold. In this way, it may further include: Step 204: Increment the preset number of rounds by one, and return to step 201 until the number of rounds reaches the preset number of round thresholds; perform an addition operation on the result after the iterative operation of the preset number of round thresholds and the information to be encrypted before update, and use the operation result as the random number. The embodiments of the present application also provide a computer-readable storage medium storing computer-executable instructions, and the computer-executable instructions are used to execute the random number generation method described in any one of the above. Another computer device in the embodiments of the present application includes a memory and a processor. Among them, the memory stores the following instructions executable by the processor: used to execute the steps of the random number generation method described in any one of the above. FIG. 5 is a schematic structural diagram of a random number generation device according to an embodiment of the present application. As shown in FIG. 5, it at least includes: a control unit, a preprocessing unit, a 256-bit register bank, an iterative processing unit, and a tail processing unit; wherein, The preprocessing module is configured to read data from the memory under the control of the control unit, perform the following preprocessing on the read data and store it in the 256-bit register bank. Among them, two preprocessed results are stored in the 256-bit register bank: divide the 64-byte information to be encrypted into 16 blocks, each block represents 4 bytes, and take every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; the four basic blocks are respectively stored in four 256-bit registers; The core processing unit is configured to perform the following preset number of rounds of iterative operations under the control of the iterative processing module: read the information to be encrypted from the 256-bit register bank, and complete a basic operation of mixing the blocks in the stream symmetric encryption algorithm based on the four basic blocks and the four 256-bit registers; take the blocks as units, circularly shift the second basic block to the left by one block, circularly shift the third basic block to the left by two blocks, circularly shift the fourth basic block to the left by three blocks, and update the 16 blocks corresponding to the information to be encrypted in the 256-bit register bank; based on the updated four basic blocks and the four 256-bit registers, complete a basic operation of mixing the rearranged blocks in the stream symmetric encryption algorithm; The tail processing unit is configured to perform an addition operation on the result after the preset number of rounds of threshold iterative operations and the information to be encrypted before update under the control of the control unit, and write the result as a random number into the memory as the obtained random number. In the embodiment of the present application, during the calculation process, the core processing unit directly retrieves data from the 256-bit register bank without accessing the memory operation. In an exemplary instance, SIMD_reg0 to SIMD_reg7 in the 256-bit register file are all 256-bit registers. Among them, SIMD_reg0 to SIMD_reg3 and SIMD_reg4 to SIMD_reg7 store the same data. That is to say, the preprocessed information to be encrypted will be stored twice in the 256-bit register file. Taking Figure 3 as an example, SIMD_reg0 stores the first basic block, namely block0, block1, block2, and block3; SIMD_reg1 stores the second basic block, namely block4, block5, block6, and block7; SIMD_reg2 stores the third basic block, namely block8, block9, block10, and block11; SIMD_reg3 stores the fourth basic block, namely block12, block13, block14, and block15; SIMD_reg4 stores the first basic block, SIMD_reg5 stores the second basic block, SIMD_reg6 stores the third basic block, and SIMD_reg7 stores the fourth basic block. In an exemplary instance, the core processing unit may include: an iteration control module, a first processing module, a rearrangement module, and a second processing module; among them, The first processing module is used to read the information to be encrypted from the 256-bit register file under the control of the iteration processing module, and complete a basic operation of performing a mixing operation on the block in the stream symmetric encryption algorithm based on the basic block and the 256-bit register; in an embodiment, reading the information to be encrypted from the 256-bit register file is the data read from SIMD_reg0 to SIMD_reg3 in the 256-bit register file; The rearrangement module is used to cyclically shift the second basic block left by one block, the third basic block left by two blocks, and the fourth basic block left by three blocks in units of blocks, and update the 16 blocks in the preprocessing module; The second processing module is used to complete a basic operation of performing a mixing operation on the rearranged block in the stream symmetric encryption algorithm based on the updated basic block and the 256-bit register. In an exemplary instance, the control of the iteration processing module is used to: increment the preset number of rounds by one, and notify the first processing module to execute a basic operation until the number of rounds reaches the preset number of round thresholds, and use the operation result as a random number. In an exemplary instance, the information to be encrypted read by the tail processing unit before update is the data read from SIMD_reg4 to SIMD_reg7 in the 256-bit register file. The random number generation device provided by the embodiment of the present application is based on a 256-bit register, and cleverly rearranges blocks during the random number generation process, which not only ensures the successful generation of random numbers, but also reduces the computational complexity of the block mixing operation in the stream symmetric encryption algorithm, improves the random number generation speed, and thus shortens the execution time of the ZKP encryption process. In an exemplary instance, FIG. 6 shows a schematic diagram of the process implementation of a basic operation in the first processing module. In FIG. 6, a represents the first basic block, b represents the second basic block, c represents the third basic block, and d represents the fourth basic block. As shown in FIG. 6, the mixing operation of a basic operation may include: block[a] = block[a] + block[b]; where + represents the 256-bit SIMD addition (SIMD256_ADD) instruction; block[d] = ROL(block[d] ^ block[a], 16), where ROL represents the first SIMD circular left shift (SIMD256_32_ROL) instruction, and ^ represents the 256-bit SIMD exclusive OR (SIMD256_XOR) instruction; block[c] = block[c] + block

[0012] ; block[b] = ROL(block[b] ^ block[8], 12); block[a] = block[a] + block[b]; block[d] = ROL(block[d] ^ block[a], 8); block[c] = block[c] + block[d]; block[b] = ROL(block[b] ^ block[c], 7). In an exemplary instance, FIG. 7 shows a schematic diagram of the addition process of the tail processing module. In FIG. 7, a represents the original first basic block, b represents the original second basic block, c represents the original third basic block, and d represents the original fourth basic block; a' represents the first basic block after iterating through the preset number of rounds threshold of the core processing unit, b' represents the second basic block after iterating through the preset number of rounds threshold of the core processing unit, c' represents the third basic block after iterating through the preset number of rounds threshold of the core processing unit, and d' represents the fourth basic block after iterating through the preset number of rounds threshold of the core processing unit. As shown in FIG. 7, the result after the iterative operation through the preset number of rounds threshold is added to the original (i.e., before update) information to be encrypted, and the obtained result is used as the random number, such as the result first basic block, result second basic block, result third basic block, and result fourth basic block in FIG. 7. Although the embodiments disclosed in this application are as above, the content described is only an embodiment adopted for the convenience of understanding this application and is not intended to limit this application. Any person skilled in the art within the scope of this application may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of patent protection of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A random number generation method, comprising: Dividing 64 bytes of information to be encrypted into 16 blocks, each block representing 4 bytes, and taking every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; storing the four basic blocks into four 256-bit registers respectively; Based on the four basic blocks and the four 256-bit registers, completing a basic operation of mixing blocks in a stream symmetric encryption algorithm; Taking blocks as units, circularly shifting the second basic block left by one block, the third basic block left by two blocks, and the fourth basic block left by three blocks; Based on the four basic blocks and the four 256-bit registers, completing a basic operation of mixing the rearranged blocks in a stream symmetric encryption algorithm.

2. The random number generation method according to claim 1, further comprising: Incrementing the preset number of rounds by one, and returning to the step of performing a basic operation of mixing blocks until the number of rounds reaches a preset round threshold; Performing an addition operation on the result after iterative operations with the preset round threshold and the information to be encrypted before update, and taking the operation result as a random number.

3. The random number generation method according to claim 1 or 2, wherein, The mixing operation includes: a 256-bit single instruction multiple data (SIMD) addition instruction for implementing an addition operation on two 256-bit registers; a 256-bit SIMD exclusive OR for implementing an exclusive OR operation on two 256-bit registers, where one 256-bit register represents the result of the addition operation; and, a first SIMD circular left shift instruction for implementing a first circular left shift of N1 bits on a 256-bit SIMD register representing the result of the exclusive OR operation with 32 bits as an independent unit.

4. The random number generation method according to claim 1 or 2, wherein, The first basic block includes blocks block0, block1, block2, and block3 among the 16 blocks; the second basic block includes blocks block4, block5, block6, and block7 among the 16 blocks; the third basic block includes blocks block8, block9, block10, and block11 among the 16 blocks; the fourth basic block includes blocks block12, block13, block14, and block15 among the 16 blocks; The circularly shifting the second basic block left by one block, the third basic block left by two blocks, and the fourth basic block left by three blocks includes: For the result after a basic operation of mixing blocks, circularly shifting block5 of the second basic block to block4, circularly shifting block10 of the third basic block to block8, and circularly shifting block15 of the fourth basic block to block12.

5. The random number generation method according to claim 4, wherein, The circular left shift is a second SIMD circular left shift; The second SIMD circular left shift is implemented by the SIMD128_ROL instruction; The format of the SIMD128_ROL instruction includes: SIMD128_ROL(S, N2, R), which is used to perform a 128-bit circular left shift on S to obtain R; where S represents a 256-bit SIMD register for performing the circular left shift operation, and N2 represents the number of bits for the circular left shift, and N2 is an integer multiple of 32.

6. A computer-readable storage medium storing computer-executable instructions for executing the random number generation method according to any one of claims 1 to 5.

7. A computer device, comprising a memory and a processor, wherein, The memory stores the following instructions executable by a processor: steps for executing the random number generation method according to any one of claims 1 to 5.

8. A random number generation device, comprising: A control unit, a preprocessing unit, a 256-bit register bank, an iterative processing unit, and a tail processing unit; where A preprocessing module, which is used to read data from the memory under the control of the control unit, perform the following preprocessing on the read data and store it in the 256-bit register bank. Among them, two preprocessed results are stored in the 256-bit register bank: divide the 64-byte information to be encrypted into 16 blocks, each block representing 4 bytes, and take every 4 blocks as a basic block to obtain a first basic block, a second basic block, a third basic block, and a fourth basic block; A core processing unit for performing the following preset number of rounds of iterative operations: read the information to be encrypted from the 256-bit register bank, and complete a basic operation of mixing the blocks in the stream symmetric encryption algorithm based on the basic block and the 256-bit register; take the blocks as units, circularly shift the second basic block by one block, the third basic block by two blocks, and the fourth basic block by three blocks, and update the 16 blocks corresponding to the information to be encrypted in the 256-bit register bank; based on the updated basic block and the 256-bit register, complete a basic operation of mixing the rearranged blocks in the stream symmetric encryption algorithm. A tail processing unit, which is used to perform an addition operation on the result after the preset number of rounds of threshold iterative operations and the information to be encrypted before update under the control of the control unit, and write the result as the obtained random number into the memory.

9. The random number generation device according to claim 8, wherein, The 256-bit register bank includes eight 256-bit registers SIMD_reg0 to SIMD_reg7; where SIMD_reg0 is used to store the first basic block, SIMD_reg1 is used to store the second basic block, SIMD_reg2 is used to store the third basic block, and SIMD_reg3 is used to store the fourth basic block; SIMD_reg4 is used to store the first basic block, SIMD_reg5 is used to store the second basic block, SIMD_reg6 is used to store the third basic block, and SIMD_reg7 is used to store the fourth basic block.

10. The random number generation device according to claim 8, wherein, The information to be encrypted before update read by the tail processing unit is the data read from SIMD_reg4 to SIMD_reg7 in the 256-bit register bank.

11. The random number generation device according to claim 8, wherein, The core processing unit may include: an iterative control module, a first processing module, a rearrangement module, and a second processing module; where The first processing module is used to, under the control of the iterative processing module, read the information to be encrypted from SIMD_reg0 to SIMD_reg3 in the 256-bit register file, and complete a basic operation of performing a mixing operation on the block in the stream symmetric encryption algorithm based on the basic block and the 256-bit register; in one embodiment, reading the information to be encrypted from the 256-bit register file is from; The rearrangement module is used to, in units of blocks, circularly shift the second basic block to the left by one block, circularly shift the third basic block to the left by two blocks, circularly shift the fourth basic block to the left by three blocks, and update 16 blocks in the preprocessing module; The second processing module is used to, based on the updated basic block and the 256-bit register, complete a basic operation of performing a mixing operation on the rearranged block in the stream symmetric encryption algorithm.

12. The random number generation device according to claim 10, wherein The control of the iterative processing module is used to: increment the preset number of rounds by one, and notify the first processing module to perform a basic operation until the number of rounds reaches the preset number of round threshold, and use the operation result as a random number.

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