Matrix operation apparatus based on flexible RRAM memory-computing array

Abstract

The present application relates to the technical field of integrated circuits and relates to a matrix operation apparatus based on a flexible RRAM memory-computing array, and solves the problem in the prior art of the inability to reduce the area of the memory-computing array without affecting the precision. The apparatus comprises: the flexible RRAM memory-computing array for outputting cumulative currents of columns of memory-computing units to a multiplexer (MUX) on the basis of multiple rows of inputs; the MUX for selecting the cumulative current of one column of memory-computing units from among the columns of memory-computing units and sending said cumulative current to an analog-to-digital converter (ADC); the ADC for converting the received cumulative current into a digital signal and sending said digital signal to a subtractor; a popcount module for receiving the multiple rows of inputs, obtaining the number of 1 in the multiple rows of inputs, and outputting the number of 1 to a multiplier; the multiplier for multiplying the number of 1 by a fixed value β and sending a product result to the subtractor; and the subtractor for subtracting the product result from the digital signal to obtain a multiply-accumulate result of the matrix. The present application realizes high-precision memory-computing based on a small-area memory-computing array, further enhances energy efficiency, and can be applied to flexible computing chips to create electronic skin.

Description

A matrix operation device based on flexible RRAM storage and computing array Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a matrix operation device based on a flexible RRAM storage and computing array. Background Art

[0002] The current trend in AI perception research is to make machines more human-like. Electronic skin, by endowing intelligent robots with tactile perception, is expected to revolutionize robotics. The development direction for electronic skin tactile perception is to integrate sensing, storage, and computing into a sensor-storage-computing architecture. This will address the power consumption bottleneck of data transfer in the von Neumann architecture and, combined with sensing, improve overall efficiency. The traditional von Neumann architecture is constrained by the "memory wall bottleneck," resulting in high power consumption and slow speed. In-memory computing technology, however, enables more efficient computing systems and reduces power consumption. Since convolution operations involving numerous multiplications and additions are a core component of deep learning algorithms, in-memory computing and logic are well-suited for deep neural network applications in AI and AI-based big data technologies. The BNN (Binarized Neural Network) algorithm can reduce memory usage, power consumption, and area overhead while maintaining a certain level of computational accuracy, while also increasing computational speed, making it ideal for edge computing. As a new type of non-volatile storage, RRAM (Resistive Random Access Memory) has been considered to be the new device most likely to break through the limitations of traditional devices due to its simple structure, high integration, and low power consumption. It is used in in-memory computing.

[0003] While flexible pressure sensor design has achieved significant success, flexible computing chips, which are essential for creating truly flexible electronic skin, are still in the exploratory stage. Currently, RRAM-based in-memory computing chips implement BNN algorithms through XNOR operations based on a 2T2R (two RRAMs and two MOS transistors form a memory and computing unit). Therefore, to further improve energy efficiency and apply flexible computing chips to create electronic skin, a matrix operation device based on a flexible memory and computing array with a 1T1R structure using flexible RRAM and IGZO TFTs is urgently needed.

[0004] Summary of the Invention

[0005] In view of the above analysis, the embodiments of the present application aim to provide a matrix operation device based on a flexible RRAM storage and computing array to solve the problem in the prior art that the storage and computing array is large in size and cannot be applied to electronic skin.

[0006] On the one hand, an embodiment of the present application provides a matrix operation device based on a flexible RRAM storage and computing array, the device comprising: a flexible RRAM storage and computing array, a multiplexer MUX, an analog-to-digital converter ADC, a popcount module, a multiplier, and a subtractor;

[0007] The flexible RRAM storage and computing array outputs the accumulated current of each column of storage and computing units to the multiplexer MUX according to the multiple rows of inputs;

[0008] The multiplexer MUX selects one column from each column of storage and calculation units, and sends the accumulated current of the column of storage and calculation units to the analog-to-digital converter ADC;

[0009] The analog-to-digital converter ADC converts the accumulated current output by the RRAM storage array into a digital signal and sends it to the subtractor;

[0010] The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier;

[0011] The multiplier multiplies the number of 1s by a fixed value β and sends the product to the subtractor;

[0012] The subtractor subtracts the product result from the digital signal to obtain the matrix multiplication and addition result.

[0013] Furthermore, the flexible RRAM storage and computing array includes n×m storage and computing units;

[0014] The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence. The bit lines BL are used to output the calculation results of the storage and calculation units in this column.

[0015] Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

[0016] Furthermore, the transistor is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the memristor is an RRAM;

[0017] The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage unit, the drain is connected to the bit line BL of the storage unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage and computing unit.

[0018] Furthermore, the operating modes of the flexible RRAM storage and computing array include a write weight mode and an inference operating mode.

[0019] Furthermore, in the write weight working mode, the connection voltage of the word line WL, the bit line BL and the source line SL is controlled to change the resistance state of the memristor RRAM, thereby achieving weight writing.

[0020] Furthermore, when the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low resistance state LRS, and its weight is assigned to β+1;

[0021] When the word line WL is connected to a high level, the bit line BL is grounded, and the source line SL is connected to a write voltage Vw, the conductance state of the memristor RRAM is a high resistance state HRS, and its weight is assigned to β-1;

[0022] When the word line WL is connected to a low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.

[0023] Furthermore, the write weight mode adopts a half voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the state of the unselected memristor RRAM remains unchanged.

[0024] Furthermore, in the inference working mode, the bit line BL is connected to the read voltage Vr and the source line SL is grounded. The input of the storage unit is determined according to whether the bit line WL is connected to a high level or a low level. The current value output by the storage unit is used as the product of the storage unit input and the memristor RRAM weight. The current output by each storage unit in each column of storage units is merged in the bit line corresponding to the storage unit in the column, so that the bit line output is the sum of the products of each unit in the column of storage units.

[0025] Furthermore, when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the memory computing unit is 1 and the output is a low current I L , low current I L The value of is β-1;

[0026] When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the memory computing unit is 1 and the output is a high current I H , high current I H The value of is β+1;

[0027] When the word line WL is connected to a low level, the indium gallium zinc oxide thin film transistor IGZO TFT is disconnected, the storage and calculation unit is not connected, the input of the storage and calculation unit is 0, and the output current of the storage and calculation unit is 0.

[0028] Furthermore, the β>1.

[0029] Compared with the prior art, this application can achieve at least one of the following beneficial effects:

[0030] 1. This application uses a flexible RRAM memory and computing array with a 1T1R unit structure. The indium gallium zinc oxide thin-film transistor (IGZO TFT) and memristor in the 1T1R unit structure are both flexible structures. Compared with the traditional 2T2R structure, this application halves the memory and computing array area without affecting the computing accuracy, further improving energy efficiency. Its flexible characteristics make it more suitable for application in the creation of electronic skin.

[0031] 2. The design of peripheral circuits such as analog-to-digital converter ADC, popcount module, multiplier and subtractor improves the calculation accuracy of the matrix operation.

[0032] In this application, the above-mentioned technical solutions can be combined with each other to achieve more preferred combination solutions. Other features and advantages of this application will be described in the subsequent description, and some advantages will become apparent from the description or be understood by practicing this application. The objectives and other advantages of this application can be achieved and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered as limiting the present application. Like reference symbols denote like components throughout the drawings.

[0034] Figure 1 is a circuit diagram of a flexible RRAM storage and computing array;

[0035] Figure 2 is a calculation coding table of the RRAM storage and calculation array based on the 1T1R structure;

[0036] Figure 3 is the overall circuit block diagram of the RRAM storage and computing array. DETAILED DESCRIPTION

[0037] The preferred embodiments of the present application are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present application and are used together with the embodiments of the present application to illustrate the principles of the present application, and are not used to limit the scope of the present application.

[0038] A specific embodiment of the present application discloses a matrix operation device based on a flexible RRAM storage and computing array, as shown in Figure 1. The device includes: a flexible RRAM storage and computing array, a multiplexer MUX, an analog-to-digital converter ADC, a popcount module, a multiplier, and a subtractor;

[0039] The flexible RRAM storage and computing array outputs the accumulated current of each column of storage and computing units to the multiplexer MUX according to the multiple rows of inputs;

[0040] The multiplexer MUX selects one column from each column of storage and calculation units, and sends the accumulated current of the column of storage and calculation units to the analog-to-digital converter ADC;

[0041] The analog-to-digital converter ADC converts the accumulated current output by the RRAM storage array into a digital signal and sends it to the subtractor;

[0042] The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier;

[0043] The multiplier multiplies the number of 1s by a fixed value β and sends the product to the subtractor;

[0044] The subtractor subtracts the product result from the digital signal to obtain the matrix multiplication and addition result.

[0045] Specifically, the function of the multiplier is to multiply the input by a fixed β value, where the β value is determined by the performance of the RRAM storage array.

[0046] For example, when the matrix multiplication is [1,0,1,0,1]*[+1,+1,-1,-1,-1], that is, the multiple rows of input are [1,0,1,0,1], the weight of a column of the RRAM storage array is [+1,+1,-1,-1,-1], the multiplication and addition result is -1, the corresponding multiple rows of input of the RRAM storage array are 10101, and the resistance states of the input corresponding RRAM units are β+1, β+1, β-1, β-1, β-1, respectively. Then, the accumulated current output by the RRAM storage array in this column is input to the multiplexer, and the multiplexer selects the accumulated current of the column of the storage array and outputs it to the analog-to-digital converter ADC. After analog-to-digital conversion, it outputs a current digital signal of 3β-1 to the subtractor. The popcount module output is 3, the multiplier output is 3β, and the subtractor output is -1. It can be seen that this scheme is completely consistent with the original multiplication and addition result.

[0047] Furthermore, the flexible RRAM storage and computing array includes n×m storage and computing units;

[0048] The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence. The bit lines BL are used to output the calculation results of the storage and calculation units in this column.

[0049] Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

[0050] Furthermore, the transistor is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the memristor is an RRAM;

[0051] The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage unit, the drain is connected to the bit line BL of the storage unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage and computing unit.

[0052] Furthermore, the operating modes of the flexible RRAM storage and computing array include a write weight mode and an inference operating mode.

[0053] Specifically, when the bit line BL or the source line SL is connected to the write voltage Vw, the working mode of the flexible RRAM memory computing array is the write weight mode; when the bit line BL is connected to the read voltage Vr, the working mode of the flexible RRAM memory computing array is the inference working mode.

[0054] Specifically, the input voltages of the word lines, bit lines, and source lines connected to the array are controlled by the peripheral FPGA, that is, the word line WL is connected to a high level or a low level to control the on and off of the transistor, thereby selecting whether the current storage unit is selected; when the word line WL is connected to a high level, the transistor is turned on, that is, the storage unit is selected; when the word line WL is connected to a low level, the transistor is not turned on, that is, the storage unit is not selected.

[0055] Furthermore, in the write weight working mode, the connection voltage of the word line WL, the bit line BL and the source line SL is controlled to change the resistance state of the memristor RRAM, thereby achieving weight writing.

[0056] Furthermore, when the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low resistance state LRS, and its weight is assigned to β+1;

[0057] When the word line WL is connected to a high level, the bit line BL is grounded, and the source line SL is connected to a write voltage Vw, the conductance state of the memristor RRAM is a high resistance state HRS, and its weight is assigned to β-1;

[0058] When the word line WL is connected to a low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.

[0059] In the write weight mode, the high and low resistance states of the RRAM are set by controlling the write voltage Vw of the storage and calculation unit and the on and off of the transistor, thereby completing the deployment of the weight in the RRAM array; the output of the source line SL and the bit line BL is grounded or connected to the write voltage, and the word line WL controls the on and off of the transistor to control the weight writing of the RRAM in the storage and calculation unit. For example, when the word line WL <0> When the source line SL is connected to the ground, and the bit line BL is connected to the write voltage, the RRAM is programmed to a low resistance state.

[0060] Specifically, in the write weight mode and inference working mode, because the memristor RRAM is a non-volatile device, after the write weight mode completes the resistance state setting of the RRAM, the resistance state of the memristor RRAM is fixed and will not change unless a new programming voltage is applied to the word line WL, the bit line BL and the source line SL.

[0061] Furthermore, the write weight mode adopts a half voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the state of the unselected memristor RRAM remains unchanged.

[0062] Furthermore, in the inference working mode, the bit line BL is connected to the read voltage Vr and the source line SL is grounded. The input of the storage unit is determined according to whether the bit line WL is connected to a high level or a low level. The current value output by the storage unit is used as the product of the storage unit input and the memristor RRAM weight. The current output by each storage unit in each column of storage units is merged in the bit line corresponding to the storage unit in the column, so that the bit line output is the sum of the products of each unit in the column of storage units.

[0063] Furthermore, as shown in FIG2 , when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the memory computing unit is 1 and the output is a low current I L , low current I L The value of is β-1;

[0064] When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the memory computing unit is 1 and the output is a high current I H , high current I H The value of is β+1;

[0065] When the word line WL is connected to a low level, the indium gallium zinc oxide thin film transistor IGZO TFT is disconnected, the storage and calculation unit is not connected, the input of the storage and calculation unit is 0, and the output current of the storage and calculation unit is 0.

[0066] In the inference working mode, the entire RRAM array can realize the calculation function of multiplication and addition; the word line WL is used to control the on and off of the TFT transistor to realize the input: when the word line WL is connected to a high level, the TFT transistor is turned on, that is, the storage unit is selected, indicating that the input is 1; when the word line WL is connected to a low level, the transistor is turned off, that is, the unit is not connected, indicating that the input is 0. The source line SL is connected to the ground terminal, and the bit line BL is connected to the read voltage Vr to obtain the corresponding accumulated current, which is the multiplication and addition result. The high and low resistance states of RRAM after programming represent the weight distribution. When a bit line BL of the RRAM array is selected, a current I will be generated according to different high resistance or low resistance states. H or I LFor example, when the word line WL <0> When the RRAM is in a high-resistance state, the memory unit generates a reference current I L , indicating that the calculation result of this cell is β-1 (β>1). This is repeated for an entire column of memory-calculation cells. The accumulated current obtained at the output bit line BL is the multiplication and addition result of the entire column of memory-calculation cells. This allows the use of only one TFT transistor and one RRAM as a memory-calculation cell, thus forming a memory-calculation array.

[0067] This solution halves the area of ​​the memory and computation array without compromising computational accuracy. Combined with peripheral circuitry, it improves the overall energy efficiency of the computing chip. Furthermore, this solution uses flexible IGZO TFTs and flexible RRAM as basic components to construct a fully flexible memory and computation array. Combined with peripheral circuitry, this solution builds a matrix operation device based on the flexible RRAM memory and computation array, providing a solid foundation for the subsequent fabrication of complete electronic skin. Furthermore, a binary multiplication-accumulation method based on this RRAM memory and computation array provides a strong foundation for the subsequent hardware circuit implementation of intelligent algorithms.

[0068] Furthermore, the β>1.

[0069] Specifically, the present application is equivalent to a deformed binary calculation. The input of the word line WL controls whether the transistor is turned on or not. In the write weight mode, the high resistance state and low resistance state of the memristor RRAM are determined by controlling the voltage connected to the bit line BL and the source line SL. Since the high resistance state and the low resistance state are actually positive values, the low resistance state and the high resistance state are encoded as β+1 and β-1 respectively. In the inference working mode, the output also changes accordingly, and the output is also a binary high current and low current.

[0070] Furthermore, the flexible RRAM storage and computing array has a size of 64*64 and a total capacity of 4Kb.

[0071] Compared with the prior art, this embodiment provides a matrix operation device based on a flexible RRAM memory array. By selecting a flexible RRAM memory array with a 1T1R unit structure, the indium gallium zinc oxide thin-film transistor (IGZO TFT) and memristor in the 1T1R unit structure are both flexible RRAM structures. Compared with the traditional 2T2R structure, this application halves the memory array area without affecting calculation accuracy. Energy efficiency is further improved by combining with peripheral circuits, making its flexibility more suitable for application in electronic skin. The design of peripheral circuits such as the analog-to-digital converter (ADC), popcount module, multiplier, and subtractor improves the calculation accuracy of the matrix operation. This application provides a binary multiplication and accumulation calculation method based on the RRAM memory array, providing a good foundation for the subsequent hardware circuit implementation of intelligent algorithms.

[0072] Those skilled in the art will appreciate that all or part of the process steps of the above-described embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a magnetic disk, an optical disk, a read-only memory, or a random access memory.

[0073] The above is only a preferred specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in this application should be covered by the scope of protection of the present application.

Claims

1. A matrix operation device based on a flexible RRAM storage and computing array, characterized in that: The device comprises: a flexible RRAM storage array, a multiplexer mux, an analog-to-digital converter ADC, a popcount module, a multiplier and a subtractor; The flexible RRAM storage and computing array outputs the accumulated current of each column of storage and computing units to the multiplexer MUX according to the multiple row inputs; The multiplexer MUX selects one column from each column of storage and calculation units, and sends the accumulated current of the column of storage and calculation units to the analog-to-digital converter ADC; The analog-to-digital converter ADC converts the accumulated current output by the RRAM storage array into a digital signal and sends it to the subtractor; The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier; The multiplier multiplies the number of 1s by a fixed value β and sends the product to the subtractor; The subtractor subtracts the product result from the digital signal to obtain the matrix multiplication and addition result.

2. A matrix operation device based on a flexible RRAM storage and computing array according to claim 1, characterized in that: The flexible RRAM storage and computing array contains n×m storage and computing units; The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence, and the bit lines BL are used to output the calculation results of the storage and calculation units in this column; Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

3. A matrix operation device based on a flexible RRAM storage and computing array according to claim 2, characterized in that: The transistor is an indium gallium zinc oxide thin film transistor IGZO TFT, and the memristor is RRAM; The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage unit, the drain is connected to the bit line BL of the storage unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage unit.

4. A matrix operation device based on a flexible RRAM storage and computing array according to claim 3, characterized in that: The working modes of the flexible RRAM storage and computing array include a write weight mode and an inference working mode.

5. A matrix operation device based on a flexible RRAM storage and computing array according to claim 4, characterized in that: In the write weight working mode, the connection voltage of the word line WL, the bit line BL and the source line SL is controlled to change the resistance state of the memristor RRAM, thereby achieving weight writing.

6. A matrix operation device based on a flexible RRAM storage and computing array according to claim 5, characterized in that: When the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low resistance state LRS, and its weight is assigned to β+1; When the word line WL is connected to a high level, the bit line BL is grounded, and the source line SL is connected to a write voltage Vw, the conductance state of the memristor RRAM is a high resistance state HRS, and its weight is assigned to β-1; When the word line WL is connected to a low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.

7. A matrix operation device based on a flexible RRAM storage and computing array according to claim 6, characterized in that: The write weight mode adopts a half voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the state of the unselected memristor RRAM remains unchanged.

8. The matrix operation device based on the flexible RRAM storage and computing array according to claim 7, characterized in that: In the inference working mode, the bit line BL is connected to the read voltage Vr and the source line SL is grounded. The input of the storage unit is determined according to whether the bit line WL is connected to a high level or a low level. The current value output by the storage unit is taken as the product of the input of the storage unit and the weight of the memristor RRAM. The currents output by each storage unit in each column of storage units are combined in the bit line corresponding to the storage unit in the column, so that the bit line output is the sum of the products of each unit in the column of storage units.

9. A matrix operation device based on a flexible RRAM storage and computing array according to claim 8, characterized in that: When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the storage unit is 1 and the output is a low current I L , low current I L The value of is β-1; When the word line WL is connected to a high level, the resistance state of the memristor RRAM is a low resistance state LRS. The input of the calculation unit is 1, and the output high current I H , high current I H The value of is β+1; When the word line WL is connected to a low level, the indium gallium zinc oxide thin film transistor IGZO TFT is disconnected, the storage unit is not connected, the input of the storage unit is 0, and the output current of the storage unit is 0.

10. The matrix operation device based on the flexible RRAM storage and computing array according to claim 9, characterized in that: The β>1.

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