Laterally-diffused metal-oxide semiconductor device and preparation method therefor

Abstract

The present application relates to a laterally-diffused metal-oxide semiconductor device and a preparation method therefor. The laterally-diffused metal-oxide semiconductor device comprises: a substrate 10; a first doped region 111, which is arranged in the substrate 10; a second doped region 123, which is arranged in the substrate 10 and is located on the side of the first doped region 111 close to a surface of the substrate 10; a first trench 13, which is arranged in the substrate 10 and is open from the surface of the substrate 10 and extends to the first doped region 111 to expose part of the first doped region 111; a drain region 121, which is arranged in the exposed part of the first doped region 111; a source region 122, which is arranged in the substrate 10; a gate 20, which is arranged on the side of the source region 122 away from the drain region 121; and a well region 124, which is arranged in the substrate 10, wherein the well region 124 extends towards the first doped region 111 from the surface of the substrate 10 and is adjacent to the second doped region 123, and the well region 124 is located between the gate 20 and the drain region 121.

Description

Laterally diffused metal oxide semiconductor device and preparation method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2023110401619, filed on August 17, 2023, entitled “Laterally Diffused Metal Oxide Semiconductor Device and Method for Making the Same,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal oxide semiconductor device and a method for preparing the same. Background Art

[0004] With the continuous development of semiconductor technology, the application of Lateral Double-Diffuse MOS (LDMOS) devices has become increasingly widespread, and at the same time, higher performance requirements have been placed on LDMOS devices. The FOM value is a key indicator for measuring device performance. The smaller the FOM value, the better the device performance. Among them, FOM = Cgd * Rsp, which is determined by the Cgd capacitance and Rsp on-resistance of the LDMOS. In related LDMOS technology, while increasing the device's withstand voltage, the Rsp on-resistance and Cgd capacitance are usually increased, causing the device's FOM value to deteriorate with the increase in withstand voltage. How to improve the device's withstand voltage while reducing the adverse effects on the FOM value has become the direction of designers' efforts.

[0005] Summary of the Invention

[0006] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor device and a method for preparing the same to address the above problems.

[0007] To achieve the above objectives, in a first aspect, the present application provides a laterally diffused metal oxide semiconductor device, comprising:

[0008] substrate;

[0009] A first doped region is provided in the substrate;

[0010] a second doping region disposed in the substrate and located on a side of the first doping region close to the surface of the substrate;

[0011] a first trench, disposed in the substrate, opening from a surface of the substrate and extending to the first doped region to expose a portion of the first doped region;

[0012] a drain region, disposed in the exposed portion of the first doped region;

[0013] a source region disposed in the substrate;

[0014] a gate, disposed on a side of the source region away from the drain region;

[0015] A well region is provided in the substrate; the well region extends from the surface of the substrate toward the first doping region and is adjacent to the second doping region; the well region is located between the gate and the drain region.

[0016] In one embodiment, the doping concentration of the well region gradually decreases from an end close to the source region to an end close to the drain region.

[0017] In one embodiment, the width of the well region gradually decreases from an end close to the source region to an end close to the drain region; the width is the dimension from a side of the well region close to the drain region to a side of the well region close to the gate.

[0018] In one embodiment, a gate trench is provided in the substrate, and the gate trench extends from the surface of the substrate toward the second doping region; the gate is located in the gate trench.

[0019] In one embodiment, the LDMOS device further includes a split gate, the gate trench extends into the second doped region, and the split gate is disposed in the gate trench and adjacent to the second doped region.

[0020] In one embodiment, the source region is located at least on both sides of the gate along a first direction; the first trench is located at least on both sides of the gate along the first direction; the drain region is located at least on both sides of the gate along the first direction; and the first direction is perpendicular to the thickness direction of the substrate.

[0021] In one embodiment, the source region is disposed around the gate.

[0022] In one embodiment, the source region is located on both sides of the gate along the first direction.

[0023] In one embodiment, there are multiple gates, and the multiple gates are arranged at intervals along the first direction;

[0024] The source region is provided on both sides of each gate along the first direction, and the first trench and the drain region are provided on both sides of each gate along the first direction;

[0025] Two source regions, one first trench and one drain region are arranged between two adjacent gates; one first trench and one drain region are arranged between the two source regions.

[0026] In one embodiment, the laterally diffused metal oxide semiconductor device further includes an isolation structure, wherein the isolation structure is disposed on the substrate and encloses a device region;

[0027] The first doping region, the second doping region, the first trench, the drain region, the source region, the gate, and the well region are all located in the device region.

[0028] In one embodiment, the first doped region is a buried layer, and the second doped region is a drift region;

[0029] The laterally diffused metal oxide semiconductor device also includes a body region, which is arranged in the substrate and extends from the surface of the substrate to the second doped region; the body region is located on a side of the gate close to the drain region and is adjacent to the gate; the source region is located in the body region; the orthographic projection of the body region on the first doped region covers the orthographic projection of the well region on the first doped region.

[0030] In one embodiment, the laterally diffused metal oxide semiconductor device further comprises:

[0031] a conductive layer disposed in the first trench, wherein one end of the conductive layer is in electrical contact with the drain region and the other end is located on the surface of the substrate;

[0032] a first dielectric layer filling the first trench;

[0033] a second dielectric layer covering the surface of the substrate;

[0034] a drain region lead-out structure, electrically connected to the conductive layer and extending through the surface of the second dielectric layer;

[0035] a source region lead-out structure, electrically connected to the source region and extending through the surface of the second dielectric layer;

[0036] A gate lead-out structure is electrically connected to the gate and penetrates to the surface of the second dielectric layer.

[0037] In a second aspect, an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device, specifically comprising:

[0038] Providing a substrate having a first doping region, a second doping region, and a well region; wherein the second doping region is located on a side of the first doping region close to a surface of the substrate; and the well region is located on a side of the first doping region close to the surface of the substrate and is adjacent to the second doping region;

[0039] forming a gate and a source region; the source region is located in the substrate;

[0040] forming a first trench in the substrate, wherein the first trench opens from a surface of the substrate and extends to the first doped region to expose a portion of the first doped region;

[0041] A drain region is formed in the first doped region, and the drain region is located in the exposed portion of the first doped region; wherein the gate is located on a side of the source region away from the drain region, and the well region is located between the gate and the drain region.

[0042] In one embodiment, the step of providing a substrate having a first doped region, a second doped region, and a well region includes:

[0043] providing a base layer having a first doping region;

[0044] forming an epitaxial layer on the base layer;

[0045] The second doped region and the well region are sequentially formed in the epitaxial layer.

[0046] In one embodiment, the step of forming the gate and the source region includes:

[0047] forming a gate trench in the substrate, wherein the gate trench extends from the surface of the substrate to the second doped region;

[0048] forming a split gate and the gate in sequence in the gate trench; the split gate is adjacent to the second doped region;

[0049] The source region is formed in the substrate.

[0050] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0052] FIG1A is a schematic diagram of a cross-sectional structure of a laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0053] FIG1B is a schematic diagram of the cross-sectional structure of another laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0054] FIG1C is a schematic diagram of the cross-sectional structure of another laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0055] FIG2 is a flow chart of a method for preparing a laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0056] FIG3 is a preparation flow chart of S100 in the preparation method shown in FIG2 .

[0057] FIG4 is a preparation flow chart of S200 in the preparation method shown in FIG2 .

[0058] 5 to 15 are schematic cross-sectional views of the device structure during the preparation method shown in FIG. 2 .

[0059] Explanation of the accompanying drawings: 1. Laterally diffused metal oxide semiconductor device; 10. Substrate; 11. Base layer; 111. First doped region; 12. Epitaxial layer; 121. Drain region; 122. Source region; 123. Second doped region; 124. Well region; 125. Body region; 126. Body lead-out region; 13. First trench; 14. Gate trench; 20. Gate; 21. Gate dielectric layer; 22. Gate conductive layer; 30. Split gate; 31. Split gate dielectric layer; 32. Split gate conductive layer; 40. Conductive layer; 51. First dielectric layer; 52. Second dielectric layer; 61. Drain lead-out structure; 62. Source lead-out structure; 63. Gate lead-out structure; 71. First mask layer; 72. First gate dielectric material layer; 73. First gate conductive material layer; 74. Second gate dielectric material layer; 75. Second mask layer. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0062] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0063] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0064] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] Embodiments of the application are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0066] As described in the background art, in the relevant LDMOS technology, LDMOS usually adopts a lateral drift region structure. In order to improve the withstand voltage of the device, the length of the drift region and the Poly field plate is usually increased. However, the applicant's research found that the increase in the length of the drift region will increase the Rsp on-resistance. Since the increase in the length of the drift region will increase the device area, the Rsp on-resistance will be further increased. At the same time, the Poly field plate increases the parasitic capacitance between the gate and the drain, resulting in an increase in the Cgd capacitance. Therefore, the superposition of the above factors causes the device FOM value to deteriorate sharply with the increase in withstand voltage. How to reduce the adverse effects on the FOM value while improving the withstand voltage of the device has become the direction of the designers' efforts.

[0067] In view of this, embodiments of the present application provide a laterally diffused metal oxide semiconductor device and a method for fabricating the same. A first trench is provided in a substrate, a drain region is disposed within a first doped region at the bottom of the first trench, and a well region is provided between the drain region and the gate, adjacent to the second doped region. This allows, on the one hand, the well region to provide a depletion layer, achieving charge balance with the second doped region and improving the device's withstand voltage. On the other hand, the structure of the source region and the well region can both shield the Cgd capacitance between the drain region and the gate, thereby effectively reducing the Cgd capacitance between the drain region and the gate and increasing the device's operating frequency. In summary, embodiments of the present application can simultaneously reduce the Cgd capacitance while improving the device's withstand voltage, thereby reducing the adverse effects on the FOM value.

[0068] In a first aspect, as shown in FIG1A , the present application provides a laterally diffused metal oxide semiconductor (LDMOS) device 1. Taking an N-type LDMOS device 1 as an example, the LDMOS device 1 has a first doping type of P-type and a second doping type of N-type. In other embodiments, the LDMOS device 1 may also be a P-type LDMOS device 1, with the first doping type of N-type and the second doping type of P-type.

[0069] Specifically, the LDMOS device 1 includes a substrate 10, a first doped region 111, a second doped region 123, a first trench 13, a drain region 121, a source region 122, a gate 20, and a well region 124. The first doped region 111 is disposed within the substrate 10. The second doped region 123 is disposed within the substrate 10 and is located on a side of the first doped region 111 that is close to the surface of the substrate 10. The first trench 13 is disposed within the substrate 10 and extends from the surface of the substrate 10 to the first doped region 111, exposing a portion of the first doped region 111. The drain region 121 is disposed within the exposed portion of the first doped region 111. The source region 122 is disposed within the substrate 10. The gate 20 is disposed on a side of the source region 122 that is away from the drain region 121. The well region 124 is disposed within the substrate 10 and is located on a side of the first doped region 111 that is close to the surface of the substrate 10 and is adjacent to the second doped region 123. The well region 124 is located between the gate 20 and the drain region 121 .

[0070] Here, the drain region 121 being disposed in the exposed portion of the first doping region 111 can be understood as: the drain region 121 being located in the first doping region 111 at the bottom of the first trench 13 .

[0071] In one example, the substrate 10 includes a base layer 11 and an epitaxial layer 12, which are stacked together. The first doped region 111 is disposed in the base layer 11. The second doped region 123 is disposed in the epitaxial layer 12. Specifically, the base layer 11 and the well region 124 are of the first doping type, and the first doped region 111, the second doped region 123, the drain region 121, and the source region 122 are of the second doping type.

[0072] It should be noted that the material of the base layer 11 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium-silicon compounds, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), or other materials known to those skilled in the art. The base layer 11 can provide a supporting foundation for the structural layers on the base layer 11. In the embodiment of the present application, the drain region 121 is a drain terminal, and the source region 122 is a source terminal.

[0073] It is understandable that the cross-sectional shape of the first groove 13 may be an inverted trapezoid, a rectangle, a semicircle, etc., and the embodiment of the present application does not limit the shape of the first groove 13 .

[0074] The laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application is characterized by providing a first trench 13 on the substrate 10, disposing a drain region 121 within the first doped region 111 at the bottom of the first trench 13, and providing a well region 124 adjacent to the second doped region 123 between the drain region 121 and the gate 20. Thus, on the one hand, the well region 124 can provide a depletion layer, achieving charge balance with the second doped region 123, thereby improving the device's withstand voltage. On the other hand, the embodiment of the present application adopts a Drain / Source / Gate port arrangement, and the structure of the source region 122 and the well region 124 can both shield the Cgd capacitance between the drain region 121 and the gate 20, thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20 and improving the device's operating frequency. In summary, the embodiment of the present application can reduce the Cgd capacitance while improving the device's withstand voltage, thereby reducing the adverse impact on the FOM value.

[0075] Further, referring to FIG1A , the dotted arrow in the figure indicates the path of current flowing from the source region 122 to the drain region 121. As can be seen from the figure, on the one hand, the second doped region 123 in the embodiment of the present application adopts a vertical structure. When increasing the device's withstand voltage, it is only necessary to increase the size of the second doped region 123 in the vertical direction. In this way, the device area will not be increased. On the other hand, the path of current flowing through the first doped region 111 is shorter, thereby reducing the on-resistance (Rsp) of the device. On the other hand, the drain region 121 is closer to the center of the first doped region 111, which is conducive to the potential conduction of the drain region 121 and facilitates more uniform opening of the body diode, thereby improving the device's ability to discharge current.

[0076] In one embodiment, the first trench 13 is a deep trench.

[0077] In one embodiment, as shown in Figure 14, the dimension H of the first trench 13 along the thickness direction of the substrate 10 is greater than or equal to 0.5μm. In one example, the dimension H of the first trench 13 along the thickness direction of the substrate 10 is between 0.5μm and 20μm. Exemplarily, the dimension H can be 0.5μm, 1μm, 5μm, 7.5μm, 9μm, 12μm, 16μm, 19μm or 20μm. Here, the dimension H can be understood as the depth of the first trench 13. By making the depth of the first trench 13 within the above range, it can be ensured that the device has a lower Cgd capacitance under the premise of stable operation.

[0078] In one embodiment, the doping concentration of the well region 124 gradually decreases from an end close to the source region 122 to an end close to the drain region 121 .

[0079] In this way, linear ion doping can be formed from the source region 122 to the drain region 121 , which is beneficial to optimizing the electric field distribution of the second doping region 123 , thereby improving the breakdown voltage of the device.

[0080] 1B and 1C , the width W of the well region 124 gradually decreases from the end near the source region 122 to the end near the drain region 121. The width W is the dimension from the side of the well region 124 near the drain region 121 to the side of the well region 124 near the gate 20.

[0081] In this way, linear ion doping can be formed from the source region 122 to the drain region 121 , which is beneficial to optimizing the electric field distribution of the second doping region 123 , thereby improving the breakdown voltage of the device.

[0082] In one example, the well region 124 is a deep well, which is beneficial for optimizing the electric field distribution of the second doping region 123 and thus improving the breakdown voltage of the device.

[0083] In one embodiment, a gate trench 14 is provided in the substrate 10, extending from the surface of the substrate 10 toward the second doped region 123. The gate 20 is located in the gate trench 14. This helps to assist in depletion of the second doped region 123, thereby improving the device's withstand voltage.

[0084] It is understandable that the gate 20 includes a gate dielectric layer 21 and a gate conductive layer 22 . The gate dielectric layer 21 is disposed on the sidewall of the gate trench 14 , and the gate conductive layer 22 is disposed on a side of the gate dielectric layer 21 away from the sidewall.

[0085] In one example, the gate dielectric layer 21 is a gate oxide layer, and the material of the gate dielectric layer 21 may be silicon dioxide. The material of the gate conductive layer 22 may be polysilicon or metal.

[0086] In one embodiment, the LDMOS device 1 further includes a split gate 30. The gate trench 14 extends into the second doped region 123. The split gate 30 is disposed within the gate trench 14 and adjacent to the second doped region 123. Furthermore, the split gate 30 is located on a side of the gate 20 that is adjacent to the first doped region 111.

[0087] In this way, the device in the embodiment of the present application utilizes the structure of the source region 122 and the well region 124 to shield the capacitance Cgd between the drain region 121 and the gate 20, thereby effectively reducing the parasitic capacitance Cgd between the drain region 121 and the gate 20. By adopting a trench split gate structure at the gate 20 end, on the one hand, the Cgd capacitance can be further shielded; on the other hand, the second doped region 123 can be assisted to be depleted, thereby further improving the device's withstand voltage.

[0088] It is understandable that the split gate 30 includes a split gate dielectric layer 31 and a split gate conductive layer 32 . The split gate dielectric layer 31 is disposed on the sidewall of the gate trench 14 , and the split gate conductive layer 32 is disposed on a side of the split gate dielectric layer 31 away from the sidewall.

[0089] In one example, the split gate dielectric layer 31 is a split gate oxide layer, and the material of the split gate oxide layer can be silicon dioxide. The material of the split gate conductive layer 32 can be polysilicon or metal.

[0090] In one embodiment, the source region 122 is located at least on both sides of the gate 20 along the first direction X. The first trench 13 is located at least on both sides of the gate 20 along the first direction X. The drain region 121 is located at least on both sides of the gate 20 along the first direction X. The first direction X is perpendicular to the thickness direction of the substrate 10. In this way, the device structure can be more diverse, and different device structure types can be realized.

[0091] In one example, the source region 122 is disposed around the periphery of the gate 20. This can also be understood as follows: the source region 122 is disposed around the periphery of the orthographic projection of the gate 20 on the substrate 10. The drain region 121 is disposed around the periphery of the source region 122. This can also be understood as follows: the drain region 121 is disposed around the periphery of the orthographic projection of the gate 20 on the substrate 10. The first trench 13 is disposed around the periphery of the source region 122. This can also be understood as follows: the first trench 13 is disposed around the periphery of the orthographic projection of the gate 20 on the substrate 10.

[0092] In this way, the source region 122 and the drain region 121 are arranged in a ring shape, and this structure is beneficial to improving the withstand voltage of the device.

[0093] In another example, the source region 122 is located on both sides of the gate 20 along the first direction X. The drain region 121 is located on both sides of the gate 20 along the first direction X. The source region 122 is located between the drain region 121 and the gate 20. This is equivalent to arranging the source region 122 and the drain region 121 in a strip shape. In this structure, two cells share the same gate 20.

[0094] In one embodiment, there are multiple gates 20, and the multiple gates 20 are arranged at intervals along the first direction X. Each gate 20 is provided with a source region 122 on both sides along the first direction X, and each gate 20 is provided with a first trench 13 and a drain region 121 on both sides along the first direction X. Two source regions 122, one first trench 13, and one drain region 121 are provided between two adjacent gates 20. One first trench 13 and one drain region 121 are provided between two source regions 122.

[0095] Thus, the laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application includes at least one cell, and each cell includes at least a drain region 121 , a source region 122 and a gate 20 .

[0096] In one embodiment, the LDMOS device 1 further includes an isolation structure (not shown), which is disposed on the substrate 10 and encloses a device region (not shown). The first doped region 111, the second doped region 123, the first trench 13, the drain region 121, the source region 122, the gate 20, and the well region 124 are all located in the device region.

[0097] The embodiment of the present application sets the first trench 13 in the device area. On the one hand, it avoids setting the first trench 13 on the isolation structure, reduces the adverse effects of the first trench 13 on the setting and performance of the isolation structure, makes the setting of the isolation structure more flexible, and thus reduces the difficulty of manufacturing the device; on the other hand, compared with the method of setting the first trench 13 on the isolation structure, the embodiment of the present application does not increase the area of ​​the cell, which is conducive to reducing the on-resistance.

[0098] In one embodiment, the first doped region 111 is a buried layer, and the second doped region 123 is a drift region. The laterally diffused metal oxide semiconductor device 1 further includes a body region 125, which is disposed within the substrate 10 and extends from the surface of the substrate 10 to the second doped region 123. The body region 125 is located on a side of the gate 20 near the drain region 121 and is adjacent to the gate 20. The source region 122 is located within the body region 125. The orthographic projection of the body region 125 on the first doped region 111 overlaps the orthographic projection of the well region 124 on the first doped region 111. Specifically, the body region 125 is of the first doping type.

[0099] It is understandable that the body region 125 can also shield the Cgd capacitance between the drain region 121 and the gate 20 , thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20 and improving the operating frequency of the device.

[0100] In the embodiment of the present application, on the one hand, the well region 124 can provide a depletion layer to achieve charge balance with the drift region and improve the device's withstand voltage; on the other hand, the drift region adopts a vertical structure. When increasing the device's withstand voltage, it is only necessary to increase the drift region size in the vertical direction. In this way, the device area will not be increased.

[0101] In one embodiment, the LDMOS device 1 further includes: a conductive layer 40 , a first dielectric layer 51 , a second dielectric layer 52 , a drain lead-out structure 61 , a source lead-out structure 62 , and a gate lead-out structure 63 .

[0102] The conductive layer 40 is disposed within the first trench 13. One end of the conductive layer 40 is in electrical contact with the drain region 121, and the other end is located on the surface of the substrate 10. A first dielectric layer 51 fills the first trench 13. A second dielectric layer 52 covers the surface of the substrate 10. A drain lead structure 61 is electrically connected to the conductive layer 40 and extends through the surface of the second dielectric layer 52. A source lead structure 62 is electrically connected to the source region 122 and extends through the surface of the second dielectric layer 52. A gate lead structure 63 is electrically connected to the gate 20 and extends through the surface of the second dielectric layer 52.

[0103] In this way, the first dielectric layer 51 acts as an insulator, reducing the electrical interference of the conductive layer 40 on other structures. The second dielectric layer 52 protects the cellular structure of the device. The drain lead structure 61, source lead structure 62, and gate lead structure 63 electrically connect the source region 122, drain region 121, and gate 20 of the device to external circuits. Furthermore, the source lead structure 62 is located between the drain region 121 and the gate 20. The source lead structure 62 can shield the Cgd capacitance between the drain region 121 and the gate 20, thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20 and improving the operating frequency of the device.

[0104] In one example, the first conductive layer 40 and the second conductive layer 40 are made of silicon dioxide, polysilicon or metal.

[0105] In one example, a body lead-out region 126 is further provided in the body region 125 , and the body lead-out region 126 is of the first doping type and can be led out through the source region lead-out structure 62 .

[0106] In a second aspect, referring to FIG. 2 and in combination with FIG. 5 to FIG. 15 , an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device 1 , specifically comprising:

[0107] S100: A substrate 10 is provided having a first doping region 111, a second doping region 123, and a well region 124. The second doping region 123 is located on a side of the first doping region 111 close to the surface of the substrate 10. The well region 124 is located on a side of the first doping region 111 close to the surface of the substrate 10 and is adjacent to the second doping region 123.

[0108] In one embodiment, as shown in FIG. 3 , S100 specifically includes the following steps:

[0109] S110: providing a base layer 11 having a first doping region 111. Specifically, as shown in FIG5 , the base layer 11 is a P-type semiconductor, and N-type ions are implanted into the base layer 11 by ion implantation to form the first doping region 111.

[0110] Exemplarily, the material of the base layer 11 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium-silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.

[0111] S120: forming an epitaxial layer 12 on the base layer 11. Specifically, the epitaxial layer 12 can be grown on the base layer 11 by vapor phase epitaxy or molecular beam epitaxy.

[0112] S130: A second doped region 123 and a well region 124 are sequentially formed in the epitaxial layer 12. Specifically, referring to FIG6 and FIG7 , first, N-type ions are implanted in the epitaxial layer 12 to form the second doped region 123, which is adjacent to the first doped region 111. Second, P-type ions are implanted in the epitaxial layer 12 to form the well region 124.

[0113] After the well region 124 is formed, the following steps are performed:

[0114] S200: forming the gate 20 and the source region 122. The source region 122 is located in the substrate 10. The source region 122 may be formed by implanting N-type ions through ion implantation.

[0115] S300 : forming a first trench 13 in the substrate 10 . The first trench 13 opens from the surface of the substrate 10 and extends to the first doped region 111 to expose a portion of the first doped region 111 .

[0116] S400: A drain region 121 is formed in the first doped region 111. The drain region 121 is located in the exposed portion of the first doped region 111. The gate 20 is located on a side of the source region 122 away from the drain region 121, and the well region 124 is located between the gate 20 and the drain region 121. Specifically, N-type ions can be implanted into the substrate 10 by ion implantation to form the drain region 121.

[0117] It should be noted that ion implantation damages the substrate 10, significantly reducing the mobility and lifetime of electron-hole pairs. Furthermore, most implanted ions are not located in substitutional positions at the lattice. To activate the ions and restore their original mobility, the substrate 10 must be annealed at an appropriate temperature. Annealing can repair lattice defects and allow impurity atoms to move to lattice sites, activating the impurities. Generally, repairing lattice defects requires approximately 450-550°C, while activating impurities requires 900-1000°C. Impurity activation is time- and temperature-dependent: the longer the time and the higher the temperature, the more fully the impurities are activated. Commonly used annealing methods for the substrate 10 include high-temperature thermal annealing and rapid thermal annealing (RTA). In one example, a high-temperature thermal annealing process can be used for annealing. Specifically, a high-temperature furnace is used to heat the silicon wafer to 800-1000°C and maintain the temperature for 20-40 minutes. In another example, a rapid thermal annealing process can be used for annealing. Compared with a high-temperature thermal annealing process, the rapid thermal annealing process has a shorter annealing time, can avoid the diffusion of doped ions caused by long-term high temperature, and reduce the instantaneous enhanced diffusion of doped ions.

[0118] The method for preparing a laterally diffused metal oxide semiconductor device 1 provided in an embodiment of the present application comprises providing a first trench 13 on a substrate 10, disposing a drain region 121 within a first doped region 111 at the bottom of the first trench 13, and providing a well region 124 adjacent to a second doped region 123 between the drain region 121 and the gate 20. Thus, on the one hand, the well region 124 can provide a depletion layer, achieving charge balance with the drift region (second doped region 123), thereby improving the device's withstand voltage. On the other hand, the structure of the source region 122 and the well region 124 can both shield the Cgd capacitance between the drain region 121 and the gate 20, thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20 and improving the device's operating frequency. In summary, the embodiments of the present application can reduce the Cgd capacitance while improving the device's withstand voltage, thereby reducing the adverse effects on the FOM value.

[0119] It should be noted that before performing S200, the following steps are also included:

[0120] S140: forming a body region 125 in the substrate 10. Specifically, referring to FIG8 , P-type ions are implanted into the substrate 10 by ion implantation to form the body region 125.

[0121] In one embodiment, as shown in FIG4 , S200 specifically includes the following steps:

[0122] S210 : forming a gate trench 14 in the substrate 10 , wherein the gate trench 14 extends from the surface of the substrate 10 to the second doped region 123 .

[0123] In one example, referring to FIG9 and FIG10 , S210 specifically includes the following steps:

[0124] S211: Form a first mask layer 71 on the substrate 10. Specifically, the first mask layer 71 may be made of silicon dioxide. Exemplarily, the first mask layer 71 may be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), or other processes.

[0125] S212 : etching the first mask layer 71 and the substrate 10 to form a gate trench 14 .

[0126] After the gate trench 14 is formed, the following steps are performed:

[0127] S220 : forming a split gate 30 and a gate 20 in sequence in the gate trench 14 . The split gate 30 is adjacent to the second doped region 123 .

[0128] In one example, referring to FIG. 10 , FIG. 11 , and FIG. 12 , S220 specifically includes the following steps:

[0129] S221: Form a first gate dielectric material layer 72 in the gate trench 14. The first gate dielectric material layer 72 covers the sidewalls and bottom wall of the gate trench 14. For example, the first gate dielectric material layer 72 can be formed by a process such as magnetron sputtering, chemical vapor deposition (CVD), electroplating, or atomic layer deposition (ALD). In one example, the first gate dielectric material layer 72 is made of an oxide. Furthermore, the first gate dielectric material layer 72 can be made of silicon dioxide.

[0130] S222: Fill the gate trench 14 with a first gate conductive material layer 73. Exemplarily, the first gate conductive material layer 73 can be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), or other processes. In one example, the first gate conductive material layer 73 is made of polysilicon or metal.

[0131] S223 : etching back the first gate conductive material layer 73 , and leaving a portion of the first gate conductive material layer 73 in the gate trench 14 .

[0132] S224 : removing the first gate dielectric material layer 72 located above the remaining first gate conductive material layer 73 and on the sidewalls of the gate trench 14 .

[0133] S225: Fill the gate trench 14 with a second gate dielectric material layer 74 to cover the surface of the first gate conductive material layer 73. In one example, the second gate dielectric material layer 74 is made of oxide, and further, the second gate dielectric material layer 74 may be made of silicon dioxide.

[0134] S226 : removing the second gate dielectric material layer 74 on the sidewalls of the gate trench 14 to form a split gate 30 .

[0135] S227: forming a gate dielectric layer 21 in the gate trench 14. In one example, the gate dielectric layer 21 is made of oxide. Furthermore, the gate dielectric layer 21 may be made of silicon dioxide.

[0136] S228: forming a gate conductive layer 22 in the gate trench 14 to form a gate 20. In one example, the gate conductive layer 22 may be made of polysilicon or metal.

[0137] Next, as shown in FIG13 , perform the following steps:

[0138] S230 : forming a source region 122 in the substrate 10 . Specifically, N-type ions are implanted into the body region 125 by ion implantation to form the source region 122 , and P-type ions are implanted into the body region 125 to form the body extraction region 126 .

[0139] In one embodiment, referring to FIG. 14 and FIG. 15 , S300 specifically includes the following steps:

[0140] S310: A second mask layer 75 is formed on the substrate 10 and patterned to define the shape and position of the first trench 13. Specifically, the patterning of the second mask layer 75 includes photolithography and etching. For example, the second mask layer 75 can be made of silicon dioxide or silicon nitride.

[0141] S320 : etching the substrate 10 based on the patterned second mask layer 75 to form a first trench 13 .

[0142] In one embodiment, after S400, the following steps are further included:

[0143] S500: forming a first dielectric material layer in the first trench 13. In one example, the first dielectric material layer may be formed by a chemical vapor deposition (CVD) process. The material of the first dielectric material layer may be silicon dioxide.

[0144] S600 : removing a portion of the first dielectric material layer to expose a portion of the first doped region 111 at the bottom of the first trench 13 .

[0145] S700: Fill the first trench 13 with a conductive material layer to form a conductive layer 40. For example, the conductive material layer can be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), or other processes. The conductive material layer can be made of copper, tungsten, aluminum, or the like.

[0146] S800 : forming a second dielectric layer 52 on the substrate 10 .

[0147] S900: A drain lead-out structure 61, a source lead-out structure 62, and a gate lead-out structure 63 are formed on the substrate 10. The drain lead-out structure 61 is electrically connected to the conductive layer 40 and extends through the surface of the second dielectric layer 52. The source lead-out structure 62 is electrically connected to the source region 122 and extends through the surface of the second dielectric layer 52. The gate lead-out structure 63 is electrically connected to the gate 20 and extends through the surface of the second dielectric layer 52.

[0148] It should be understood that, in the embodiments of the present application, although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0149] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0150] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A laterally diffused metal oxide semiconductor device, wherein: include: substrate; A first doped region, disposed in the substrate; A second doping region is disposed in the substrate and is located on a side of the first doping region close to the surface of the substrate; A first trench is provided in the substrate and opens from a surface of the substrate and extends to the first doped region to expose a portion of the first doped region; A drain region, disposed in the exposed portion of the first doped region; A source region, disposed in the substrate; A gate, disposed on a side of the source region away from the drain region; A well region is provided in the substrate; the well region is located on a side of the first doping region close to the surface of the substrate and is adjacent to the second doping region; the well region is located between the gate and the drain region.

2. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: The doping concentration of the well region gradually decreases from an end close to the source region to an end close to the drain region.

3. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: The width of the well region gradually decreases from one end close to the source region to one end close to the drain region; the width is the dimension from one side of the well region close to the drain region to one side of the well region close to the gate.

4. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: A gate trench is arranged in the substrate, and the gate trench extends from the surface of the substrate toward the second doping region; the gate is located in the gate trench.

5. The laterally diffused metal oxide semiconductor device according to claim 4, wherein: The LDMOS device further includes a split gate. The gate trench extends into the second doping region. The split gate is disposed in the gate trench and is adjacent to the second doping region.

6. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: The source region is at least located on both sides of the gate along a first direction; the first trench is at least located on both sides of the gate along the first direction; the drain region is at least located on both sides of the gate along the first direction; and the first direction is perpendicular to the thickness direction of the substrate.

7. The laterally diffused metal oxide semiconductor device according to claim 6, wherein: The source region is arranged around the periphery of the gate.

8. The laterally diffused metal oxide semiconductor device according to claim 6, wherein: The source region is located at two sides of the gate along the first direction.

9. The laterally diffused metal oxide semiconductor device according to claim 6, wherein: There are multiple gates, and the multiple gates are arranged at intervals along the first direction; The source region is disposed on both sides of each gate along the first direction, and the first trench and the drain region are disposed on both sides of each gate along the first direction; Two source regions, one first trench and one drain region are arranged between two adjacent gates; one first trench and one drain region are arranged between the two source regions.

10. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: The laterally diffused metal oxide semiconductor device further comprises an isolation structure, which is disposed on the substrate and surrounds a device region; The first doped region, the second doped region, the first trench, the drain region, the source region, the gate and the well region are all located in the device region.

11. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: The first doped region is a buried layer, and the second doped region is a drift region; The laterally diffused metal oxide semiconductor device also includes a body region, which is arranged in the substrate and extends from the surface of the substrate to the second doped region; the body region is located on the side of the gate close to the drain region and is adjacent to the gate; the source region is located in the body region; the orthographic projection of the body region on the first doped region covers the orthographic projection of the well region on the first doped region.

12. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: The laterally diffused metal oxide semiconductor device further comprises: A conductive layer is disposed in the first trench, one end of the conductive layer is in electrical contact with the drain region, and the other end of the conductive layer is located on the surface of the substrate; A first dielectric layer filled in the first trench; A second dielectric layer covering the surface of the substrate; a drain region lead-out structure, electrically connected to the conductive layer and penetrating to the surface of the second dielectric layer; A source region lead-out structure, electrically connected to the source region and extending through the surface of the second dielectric layer; A gate lead-out structure is electrically connected to the gate and penetrates to the surface of the second dielectric layer.

13. A method for preparing a laterally diffused metal oxide semiconductor device, wherein: include: Providing a substrate having a first doping region, a second doping region and a well region; wherein the second doping region is located on a side of the first doping region close to a surface of the substrate; The well region is located on a side of the first doping region close to the surface of the substrate and is adjacent to the second doping region; forming a gate and a source region; the source region is located in the substrate; forming a first trench in the substrate, wherein the first trench opens from a surface of the substrate and extends to the first doped region to expose a portion of the first doped region; A drain region is formed in the first doped region, and the drain region is located in the exposed portion of the first doped region; wherein the gate is located on a side of the source region away from the drain region, and the well region is located between the gate and the drain region.

14. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 13, wherein: The step of providing a substrate having a first doping region, a second doping region and a well region comprises: Providing a base layer having a first doping region; forming an epitaxial layer on the base layer; The second doped region and the well region are sequentially formed in the epitaxial layer.

15. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 13, wherein: The step of forming the gate and the source region comprises: forming a gate trench in the substrate, wherein the gate trench extends from the surface of the substrate to the second doped region; forming a split gate and the gate in sequence in the gate trench; the split gate is adjacent to the second doped region; The source region is formed in the substrate.

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